Interrupt processing method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides an interrupt processing method and device, electronic equipment and a readable storage medium. The method comprises the steps that a virtual processor thread is notified of to-be-processed interrupt triggered by a virtual equipment thread by setting the value of a first register as a first numerical value; obtaining a state parameter of the current execution code block, and judging whether the current execution code block meets a first response condition or not according to the state parameter; the state parameters comprise an address of a current execution instruction in the current execution code block, whether a first response flag bit exists in the current execution code block, and an address of the first response flag bit; if the current execution code block meets the first response condition, exiting the current execution code block through a first outlet to enter an interrupt processing program; and if the current execution code block does not meet the first response condition, quitting the current execution code block through a second outlet to enter an interrupt processing program. According to the method, the translated code operation performance and the interrupt response speed can be balanced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an interrupt processing method, device, electronic device and readable storage medium. Background Art

[0002] The interrupt mechanism is an important way for effective communication between peripheral devices (such as hard disk, network card, keyboard, mouse, etc.) and the processor (Central Processing Unit, CPU).

[0003] System-level Dynamic Binary Translation (DBT) is a technology that translates and converts binary code in real time when a computer system is running. It is usually used to convert a binary program of one instruction set architecture (ISA) into a program of another instruction set architecture, or to adapt code between different execution environments so that the program can run correctly in the target environment without recompiling the source code.

[0004] Device simulation in system-level DBT is usually implemented by software. The vDEV (Virtual Device) thread is responsible for simulating the behavior of peripheral devices (such as disks, network cards, etc.) and triggering interrupts; the vCPU (Virtual CPU) thread is responsible for simulating the behavior of the processor (such as instruction translation, execution, and interrupt processing). During the translation and execution of the vCPU, the interrupt may not be responded to for a long time due to the long length of the basic block. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide an interrupt processing method that overcomes the above problems or at least partially solves the above problems, so that interrupts can be responded to in time at a better time point in different situations, and the performance of the translated code running and the interrupt response speed can be more balanced.

[0006] Correspondingly, an embodiment of the present invention further provides an interrupt processing device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses an interrupt processing method, which is applied to a binary translation system, wherein a virtual device thread and a virtual processor thread are running in the binary translation system, and the method comprises: Notifying the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of the first register to a first value; Obtaining state parameters of a currently executed code block, and judging whether the currently executed code block satisfies a first response condition according to the state parameters; the state parameters include: an address of a currently executed instruction in the currently executed code block, whether a first response flag exists in the currently executed code block, and an address of the first response flag; wherein the first response flag is used to indicate whether the total number of instructions contained in the currently executed code block exceeds a preset number; If the currently executed code block meets the first response condition, the virtual processor thread exits the currently executed code block through a first exit and enters an interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executed code block; If the currently executed code block does not meet the first response condition, the virtual processor thread exits the currently executed code block through a second exit and enters an interrupt handler; the second exit is located at the end position of the currently executed code block.

[0008] In a second aspect, an embodiment of the present invention discloses an interrupt processing device, which is applied to a binary translation system, wherein a virtual device thread and a virtual processor thread are running in the binary translation system, and the device comprises: An interrupt detection module, configured to notify the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of the first register to a first value; A conditional judgment module, used to obtain state parameters of a currently executed code block, and judge whether the currently executed code block satisfies a first response condition according to the state parameters; the state parameters include: the address of a currently executed instruction in the currently executed code block, whether a first response flag exists in the currently executed code block, and the address of the first response flag; wherein the first response flag is used to indicate whether the total number of instructions contained in the currently executed code block exceeds a preset number; A first response module, configured to exit the currently executed code block through a first exit and enter an interrupt processing program if the currently executed code block satisfies the first response condition; the first exit is located at the end position of a preset number of instructions in the currently executed code block; The second response module is used to exit the current execution code block through a second exit and enter the interrupt processing program if the current execution code block does not meet the first response condition; the second exit is located at the end position of the current execution code block.

[0009] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of any of the interrupt handling methods described above.

[0010] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, it can implement any of the interrupt processing methods described above.

[0011] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the interrupt processing methods described above.

[0012] In other aspects, the present application also provides a binary translation system and a system-state binary translation device.

[0013] The embodiments of the present invention include the following advantages: In the translation process of the dynamic binary translator of the embodiment of the present invention, if an interrupt to be processed is detected, the state parameter of the current execution code block is obtained, and it is determined whether the current execution code block meets the first response condition according to the state parameter; and it is determined whether to respond to the interrupt through the first exit or the second exit according to whether the current execution code block meets the first response condition. The first response condition is used to determine whether the current execution code block meets the condition of exiting the current execution code block in advance. The first exit is used to exit the current execution code block in advance to respond to the interrupt before the execution of the current execution code block ends. The second exit is used to exit the current execution code block again at the end of the execution of the current execution code block to respond to the interrupt. According to the state parameter of the current execution code block, the embodiment of the present invention selects a better interrupt response time (the first exit or the second exit), so that the interrupt can be responded to in time at a better time point in different situations; it can avoid switching context too frequently when a large number of frequent interrupts are generated; and it can achieve a more balanced performance of the translated code running and the interrupt response speed.

[0014] In addition, the embodiment of the present invention utilizes a new method to implement the simulation of interrupt detection, which can separate the interrupt detection operation from the TB code. The interrupt detection operation no longer depends on the vCPU thread, so that the interrupt detection no longer affects the running performance of the translated code, and the performance of the vCPU thread can be further improved.

[0015] Furthermore, the embodiment of the present invention does not limit the length of the code block and will not affect the optimization effect of the translator on the code. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram of active interrupt detection in QEMU; Figure 2 is a flowchart of steps of an interrupt processing method embodiment of the present invention; Figure 3 Schematic diagram of communication between qINT thread and vCPU thread in an embodiment of the present invention; Figure 4 1 is a schematic diagram of an interrupt processing flow in case 1 of an embodiment of the present invention; Figure 5 Schematic diagram of interrupt processing flow in scenario 2 of an embodiment of the present invention; Figure 6 Schematic diagram of interrupt processing flow in scenario 3 of an embodiment of the present invention; Figure 7 is a structural block diagram of an interrupt processing device embodiment of the present invention; Figure 8 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0019] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0020] Dynamic Binary Translation (DBT) is widely used for program simulation, instrumentation, debugging, and other purposes. The instruction set architecture (ISA) of the guest is simulated, and DBT follows the ISA of the host. DBT achieves cross-ISA translation by translating guest binaries into host binaries. For example, it can translate ARM binaries into x86 binaries and run them on x86 platforms.

[0021] The translation process is organized in the form of code blocks. A series of consecutive guest instructions form a single-entry / single-exit block. This guest block is translated into a host binary block. The guest block can be represented by "basic block" and the translated host block can be represented by "translation block (TB)". In the following, depending on the different stages of DBT, the translation block TB may also be called code block, translation code block, and execution code block. Blocks usually end with control flow changing instructions (such as branch instructions, function calls, return instructions, etc.), such as Figure 1 as well as Figures 3 to 6 The jump exit in .

[0022] DBT runs in a loop of a find-translate phase (translate state) and an execute phase (execute state). In the find-translate phase, DBT searches the code cache for existing translation blocks to find the next block to execute. If the search fails, DBT fetches the guest binary and generates a translation block. In the execute phase, DBT simply executes the translation block. DBT switches between these two phases using context switch code.

[0023] There are two modes of dynamic binary translation. The first is user-mode DBT, which executes user-space programs. The second is full-system DBT, which can run a complete operating system. With the help of hardware emulation, the operating system can be arbitrary.

[0024] Full-system DBT can run a complete operating system. To achieve this, the hardware environment must be simulated. Full-system DBT includes software implementations of many hardware devices. Just like real hardware, simulated hardware also needs to be managed through interrupts. Simulating interrupt delivery is an important part of system DBT.

[0025] System DBTs typically utilize multiple threads to help simulate hardware, and the simulation of devices is separated from the simulation of the CPU. The vCPU thread is responsible for CPU simulation and manages translation blocks. It executes blocks, searches or finds blocks (in the code cache), and generates blocks through binary translation. It is also responsible for handling interrupts that may change the control flow. Another thread, called the "I / O thread" in QEMU, is responsible for simulating hardware devices. In the following, this thread is also called the vDEV virtual device thread.

[0026] When the simulated hardware needs to send an interrupt to the CPU, the I / O thread will set an interrupt pending flag. Once the interrupt check code of the vCPU thread sees this flag, it will simulate interrupt injection on the vCPU.

[0027] DBT runs in a loop of a lookup-translation phase (translation state) and an execution phase (execution state). Interrupts are detected in the execution state of DBT and, in some embodiments, are processed in the execution state. When a pending interrupt occurs, DBT needs to exit from the execution phase through a context switch code. The context switch code includes, for example, Figure 1 as well as Figures 4 to 6 See the "Exit - Context Switching" section in .

[0028] The interrupt handler in the guest operating system (such as the code pointed to by the IDT table entry of x86) is part of the guest instructions and needs to be dynamically translated into host instructions by DBT like other guest code. The first execution triggers the translation. When the guest executes the interrupt handler for the first time, DBT searches for an existing translation block in the search-translation phase. If it is not found, it translates and generates the corresponding host code block, such as Figure 1 as well as Figures 4 to 6 As shown in "Code Block Search" and "Code Block Translation".

[0029] In the specific implementation, QEMU uses an active detection interrupt mechanism. Specifically, it actively detects and finds an interrupt at the beginning of each TB and immediately exits the TB, such as Figure 1 As shown in the figure, it is a schematic diagram of active interrupt detection in QEMU. When there is an interrupt waiting to be processed, QEMU will set a flag for the vCPU thread to indicate the arrival of the interrupt signal. The vCPU thread will continuously detect the flag during the execution of the TB. When it is found that it is set, it will exit the TB and go to the interrupt processing. QEMU generates a dynamic detection code for identifying the flag at the beginning of each TB, which is an active detection interrupt mechanism. In order to avoid the interrupt signal being unresponsive for a long time, QEMU limits the length of each TB so that the interrupt signal can be detected in time. However, adding detection code at the beginning of each TB introduces additional overhead to the operation of the vCPU thread, affecting the running performance of the translated code. In addition, limiting the length of each code block may result in a smaller translated code block, further affecting performance, and may also affect the optimization effect of the translator on the code.

[0030] Reference Figure 2, shows a flowchart of an interrupt processing method embodiment of the present invention, the method is applied to a binary translation system, in which a virtual device thread (vDEV thread) and a virtual processor thread (vCPU thread) are running, and the method comprises the following steps: Step 101: Notify the virtual processor thread of a pending interrupt triggered by a virtual device thread by setting the value of a first register to a first value; Step 102: Obtain state parameters of the currently executed code block, and determine whether the currently executed code block meets the first response condition according to the state parameters; the state parameters include: the address of the currently executed instruction in the currently executed code block, whether there is a first response flag in the currently executed code block, and the address of the first response flag; wherein the first response flag is used to indicate whether the total number of instructions contained in the currently executed code block exceeds a preset number; Step 103: If the currently executed code block meets the first response condition, the virtual processor thread exits the currently executed code block through a first exit and enters an interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executed code block; Step 104: If the currently executed code block does not meet the first response condition, the virtual processor thread exits the currently executed code block through a second exit and enters an interrupt handler; the second exit is located at the end position of the currently executed code block.

[0031] The interrupt handling method provided in the embodiment of the present invention can be applied to a dynamic binary translator (DBT) to optimize the interrupt handling process in the binary translation process so as to achieve a balance between the performance of the translated code and the interrupt response speed.

[0032] In the translation process of the dynamic binary translator, the embodiment of the present invention detects the size of the code block; in the execution process, according to the total number of instructions contained in the current execution code block and the position of the current execution instruction in the current execution code block, it is determined when to respond to the interrupt. The current execution code block refers to the code block that is currently in the execution state.

[0033] According to different situations, the embodiment of the present invention can set the first exit or the second exit as two opportunities to respond to the interrupt. The first exit and the second exit are set in different ways, and the positions of the first exit and the second exit in the current execution code block are also different. Therefore, the execution process of the current execution code block is exited through the first exit and the second exit to respond to the interrupt at different times.

[0034] For example, if the total number of instructions contained in the currently executed code block is large, such as exceeding a preset number, and an interruption occurs when the currently executed code block just begins to execute, if the interruption is responded to after all the instructions in the currently executed code block have been executed, the interruption will not be responded to for a long time. If the interruption is responded to immediately when it arrives, when a large number of frequent interruptions occur, the context will be switched too frequently, affecting system performance.

[0035] To solve this problem, during the execution of the dynamic binary translator, if an interrupt to be processed is detected, the embodiment of the present invention obtains the status parameters of the current execution code block, and determines whether the current execution code block satisfies the first response condition based on the status parameters; based on whether the current execution code block satisfies the first response condition, it is determined whether the interrupt should be responded to through the first exit or the second exit. The first response condition is used to determine whether the current execution code block satisfies the condition for exiting the execution state of the current execution code block in advance, thereby responding to the interrupt in advance. The first exit is used to exit the execution state of the current execution code block in advance, so as to respond to the interrupt after the Mth instruction in the current execution code block is executed (corresponding to the attached Figure 5 The second exit is used to exit the execution state of the current execution code block when the current execution code block is finished, so as to respond to the interrupt after all instructions in the current execution code block are finished (corresponding to the attached Figure 4 or the jump exit in 6 - exit - context switch).

[0036] The state parameters may include: the address of the currently executed instruction in the currently executed code block, whether there is a first response flag in the currently executed code block, and the address of the first response flag. The first response flag is inserted into the block after DBT translates the Mth instruction in the translation phase.

[0037] Among them, the first response flag is used to indicate whether the total number of instructions contained in the current execution code block exceeds the preset number M, where M is a positive integer. For example, the variable b is used to indicate whether there is a first response flag in the code block. If b=1, it means that the current execution code block has a first response flag, and the total number of instructions contained exceeds the preset number, indicating that the total number of instructions contained in the current execution code block is relatively large. If b=0, it means that the total number of instructions contained in the current execution code block does not exceed the preset number, indicating that the total number of instructions contained in the current execution code block is not too many. The value of the preset number M can be determined according to the actual scenario, and the embodiment of the present invention does not limit it.

[0038] In the translation stage, when it is detected that the total number of instructions contained in the current translation code block exceeds the preset number M, an interrupt response code is inserted, that is, a response flag is set after the Mth instruction is translated. Thus, according to the address of the currently executed instruction in the currently executed code block and the address of the first response flag, it can be known whether the position of the currently executed instruction in the currently executed code block is before or after the Mth instruction.

[0039] For example, in the execution phase, assuming that the total number of instructions contained in the current execution code block exceeds a preset number M, and an interrupt arrives before the Mth instruction is executed, if the interrupt is responded to after the remaining instructions are executed, the number of remaining instructions is still large, which will cause the interrupt to wait for a long time and cannot be responded to in time. To solve this problem, in this case, the embodiment of the present invention can exit the current execution code block through the first exit, enter the interrupt handler, and respond to the interrupt in time; the first exit is located at the end position of the preset number of instructions in the current execution code block. That is, when the Mth instruction is executed, the first exit is entered. At this time, the current execution code block can be exited through the first exit and the interrupt handler can be entered without waiting until all instructions are executed to exit, so that the interrupt can be responded to in time.

[0040] For another example, assuming that the total number of instructions contained in the currently executed code block exceeds a preset number M, after executing the Mth instruction, an interrupt to be processed arrives. Since there are not many instructions left at this time, in this case, the currently executed code block can be exited through the second exit and the interrupt handler can be entered; the second exit is located at the end position of the currently executed code block.

[0041] Furthermore, in the case where the total number of instructions contained in the currently executed code block is relatively large (such as b=1), the embodiment of the present invention can decide whether to exit the currently executed code block through the first exit or the second exit according to the state parameters of the currently executed code block and enter the interrupt handling program, which can not only ensure the boundary integrity of the translated code, but also enable timely response to interrupts in different situations, and achieve a balance between the loss of synchronous interrupt detection on the running performance of the translated code and the impact of asynchronous interrupt detection on the interrupt response speed.

[0042] In an optional embodiment of the present invention, the method may further include: In the process of translating the binary program of the source platform, if it is identified that the total number of instructions contained in the current translation code block exceeds M, where M is a preset number, then after the Mth instruction and before the M+1th instruction, the first response flag and the first exit code (interrupt response code, for example Figure 5"Interrupt Response 2" in the code of the first exit); the code of the first exit is used to directly exit the current execution code block when the current execution code block detects that the value of the first register is the first value, and jump to the entry address of the interrupt handler, that is, go to the context switching code of "Exit" at the end, exit the execution stage, switch to the translation stage, and perform interrupt processing.

[0043] In order to avoid the problem that the vCPU thread cannot exit the execution process of the current execution code block for a long time after receiving an interrupt due to too much code in the current execution code block, resulting in the interrupt not being responded to in time, the embodiment of the present invention detects the size of the current translation code block during the process of the dynamic binary translator translating the binary program of the source platform. The current translation code block refers to the code block that is currently in the translation state. For example, after the translation of the Mth instruction is completed, if there are still untranslated instructions in the current translation code block, it is recognized that the total number of instructions contained in the current translation code block exceeds M, and the first response flag (such as setting b=1) can be set after the Mth instruction and before the M+1th instruction, and the code of the first exit is added to the position after b=1, for example, Figure 5 "Interrupt Response 2" in.

[0044] The position of the first exit is located at the end position of the preset number of instructions in the current translation code block, that is, at the end position of the Mth instruction. After the current translation code block is translated, it is called the translated code block and stored in the code cache. After entering the execution stage or execution state, the translated code block is called the current execution code block. The code of the first exit is used to directly exit the execution state of the current execution code block when the value of the first register is detected to be the first numerical value by the current execution code block, and jump to the entry address of the interrupt handling program. Thus, in the case of detecting an interrupt to be processed, if the current execution code block meets the first response condition, then when the dynamic binary translator executes to the code of the first exit, if the value of the first register is detected to be the first numerical value, such as the value of register R1 is detected to be 1, it means that there is an interrupt to be processed at present, and at this time, the current execution code block can be directly exited here, jump to the entry address of the interrupt handling program, and enter the interrupt handling program without waiting for the current execution code block to be executed.

[0045] For ease of description, in the embodiment of the present invention, variable a is used to represent the address of the currently executed instruction in the currently executed code block, variable b is used to represent whether there is a first response flag in the currently executed code block (b=0 indicates that there is no first response flag, b=1 indicates that there is a first response flag), and variable c is used to represent the address of the first response flag. It should be noted that the address of the currently executed instruction in the currently executed code block and the address of the first response flag refer to the value of the program counter (PC) of the client platform (source platform).

[0046] In an optional embodiment of the present invention, judging whether the currently executed code block satisfies the first response condition according to the state parameter may include: If there is a first response flag in the currently executed code block, and the address of the currently executed instruction in the currently executed code block is less than the address of the first response flag, it is determined that the currently executed code block meets the first response condition.

[0047] When a pending interrupt is detected, the status parameters of the currently executing code block in the vCPU thread can be obtained, including variable a (the address of the currently executing instruction in the currently executing code block), variable b (whether the first response flag exists in the currently executing code block), and variable c (the address of the first response flag). The status parameters of the currently executing code block are used to determine whether the currently executing code block meets the first response condition.

[0048] Variables b and c are attributes of the currently executed code block, are assigned values ​​during binary translation, and can be stored in a structure that can be obtained by DBT. Variable a is an attribute of the vCPU thread. The values ​​of variables a, b, and c can be obtained through shared memory.

[0049] If the first response flag exists in the currently executed code block, and the address of the currently executed instruction is less than the address of the first response flag, it is determined that the currently executed code block meets the first response condition. Expressed in variables: if variable b=1 and variable a<variable c, it is determined that the currently executed code block meets the first response condition.

[0050] When the currently executed code block meets the first response condition, the currently executed code block can be exited through the first exit and the interrupt handler can be entered. Therefore, there is no need to set the second exit. When the dynamic binary translator executes the code at the first exit, if it detects that the value of register R1 is 1, the currently executed code block is directly exited, and the entry address of the interrupt handler is jumped to enter the interrupt handler without waiting for the execution of the currently executed code block to end, that is, the currently executed code block is exited in advance.

[0051] In an optional embodiment of the present invention, the method may further include: If the currently executed code block does not meet the first response condition, the link between the currently executed code block and the next code block is disconnected, and the code of the second exit is set at the end position of the currently executed code block, and the code of the second exit indicates that the jump target address is the entry address of the interrupt handler.

[0052] If the currently executed code block does not meet the first response condition, it is represented by a variable: if variable b=0 or variable a≥variable c, it is determined that the currently executed code block does not meet the first response condition.

[0053] The currently executed code block does not meet the first response condition, including two situations. One situation is: the total number of instructions contained in the currently executed code block is small, such as not exceeding the preset number M. In this case, even if you wait until the currently executed code block is executed before responding to the interrupt, you will not wait for a long time. Another situation is: the total number of instructions contained in the currently executed code block is large, such as exceeding the preset number M, but most of the instructions have been executed, and the number of remaining unexecuted instructions is small, such as variable a≥variable c. In this case, even if you wait until all the remaining instructions in the currently executed code block are executed before responding to the interrupt, you will not wait for a long time. In addition, since variable a≥variable c, and the first exit is between the Mth instruction and the M+1th instruction, it means that the currently executed instruction is already after the first exit, and it is impossible to exit the currently executed code block through the first exit.

[0054] Therefore, when the currently executed code block does not meet the first response condition, a second exit can be set to exit the currently executed code block and enter the interruption processing program; the second exit is located at the end of the currently executed code block. That is, after the currently executed code block is executed, the currently executed code block is exited through the second exit and the interruption processing program is entered.

[0055] The method for setting the second exit is: disconnect the link between the current execution code block and the next code block, and set the second exit code at the end position of the current execution code block, the second exit code indicates that the jump target address is the entry address of the interrupt handler.

[0056] Disconnecting the link between the current executing code block and the next code block can be achieved by modifying the TB_LINK parameter of the current executing code block. TB_LINK is a variable or data structure used to describe the link relationship between TBs. During the binary translation process, the original binary code will be divided into multiple TBs, each TB is a continuous sequence of machine instructions, which can be converted into code that can be executed by the target platform after translation. TB_LINK is responsible for recording the jumps, execution order and other related information between these TBs. When a TB is executed, the information recorded in the TB_LINK of the TB can be used to know which TB should be jumped to next to continue execution, thereby ensuring the continuity and correctness of the program.

[0057] The TB_LINK parameter may include a jump exit, which is used to indicate the address of the next TB to be jumped to. The embodiment of the present invention can disconnect the link between the current execution code block and the next code block by modifying the TB_LINK parameter of the current execution code block, such as setting the jump exit to a null value.

[0058] In an embodiment of the present invention, when an interrupt to be processed is detected, the state parameter of the currently executed code block is obtained, and if it is determined that the currently executed code block does not meet the first response condition, the link between the currently executed code block and the next code block is disconnected, and a second exit is set at the end position of the currently executed code block, and the jump target address is set to the entry address of the interrupt handler. Thus, when the dynamic binary translator executes to the second exit, the currently executed code block can be exited through the second exit, jump to the entry address of the interrupt handler, and enter the interrupt handler.

[0059] It should be noted that when exiting the current executing code block through the first exit or the second exit, before entering the interrupt handling program, the context needs to be saved, such as saving the register state and related information of the current executing code block, such as recording the starting address and execution progress of the current executing code block, so that it can be determined from which position to continue execution when resuming execution. After the interrupt handling is completed, the context needs to be restored to continue executing the client program.

[0060] Furthermore, in the case of exiting through the first exit, it is a case of exiting early before the current execution code block is executed. Therefore, after the interrupt processing is completed and the context is restored, the remaining unexecuted instructions in the current execution code block continue to be executed. After all instructions in the current execution code block are executed, jump to the next code block for continued execution. In the case of exiting through the second exit, it is a case of exiting after the current execution code block has been executed. Therefore, after the interrupt processing is completed and the context is restored, jump directly to the next code block for continued execution.

[0061] The embodiment of the present invention does not limit the specific method of detecting whether there is a pending interrupt triggered by a virtual device thread.

[0062] Mode 1: The binary translation system also runs an interrupt detection thread, and the step of detecting whether there is an interrupt to be processed may include: The interrupt detection thread queries whether the global interrupt flag in the shared memory is set according to a preset frequency. If the global interrupt flag is set, it is determined that an interrupt to be processed is detected; the global interrupt flag is set by the virtual device thread when an interrupt is triggered.

[0063] In the related art, interrupt detection code is set in each TB header, which adds additional processing overhead and affects the running performance of the translated code. To solve this problem, the embodiment of the present invention proposes a method of executing the interrupt detection thread (qINT thread) in parallel with the virtual processor thread (vCPU thread). The interrupt detection work is separated from the TB code, so that the interrupt detection operation no longer depends on the vCPU thread, avoiding interference with the simulation performance of the vCPU thread. The two threads run independently, and the interrupt detection work is completed by the qINT thread without affecting the normal translation and execution operation of the vCPU thread.

[0064] In a system-level dynamic binary translation (DBT) environment, interrupt sending and response are simulated by software. Specifically, the vDEV thread (responsible for device simulation) and the vCPU thread (responsible for processor simulation) can collaborate to complete interrupt sending and response through a global interrupt flag.

[0065] When the state of a simulated peripheral device (such as a disk, network card, timer, etc.) changes, or when the simulated device requires processor intervention (for example, the processor needs to read data or handle an exception), the vDEV thread may trigger an interrupt. Specifically, the vDEV thread notifies the vCPU thread that an interrupt is pending by setting a global interrupt flag (such as a Boolean variable or register). The vDEV thread can also write interrupt-related information (such as interrupt type, interrupt number, etc.) to shared memory for the vCPU thread to read.

[0066] The embodiment of the present invention periodically queries the global interrupt flag bit through the qINT thread running in parallel with the vCPU thread, and no longer relies on the vCPU thread, thereby improving the execution efficiency of the vCPU thread.

[0067] In method 1, when the vDEV thread triggers an interrupt, it only needs to set the global interrupt flag and record the relevant information of the interrupt (such as the interrupt type, interrupt number, etc.). The qINT thread queries whether the global interrupt flag in the shared memory is set according to the preset frequency to detect whether there is an interrupt to be processed; if the qINT thread detects that the global interrupt flag is set, it is determined that an interrupt to be processed is detected, and the value of the first register R1 can be set to the first value (such as setting the value of R1 to 1) to notify the vCPU thread that there is an interrupt to be processed.

[0068] Furthermore, the preset frequency (such as f1) can be comprehensively determined based on the frequency of the processor querying the interrupt request flag in the simulated real machine (such as the host machine), the running time of the translated binary program in the target platform, and the running time of the binary program of the source platform in the source platform, so as to ensure that the vCPU thread will not exit the status parameters due to frequent interruptions, and the interruption will not be undetected for a long time, resulting in untimely processing.

[0069] Exemplarily, the preset frequency f1 can be calculated by the following formula: (1) Among them, f1 represents the preset frequency, and f2 represents the frequency at which the processor in the host machine queries the interrupt request flag. The difference between f1 and f2 is that f2 is the frequency of interrupt detection by the real host hardware, while f1 is the frequency of interrupt detection simulated by software. t1 represents the running time of the translated binary program in the target platform, and t2 represents the running time of the binary program of the source platform in the source platform.

[0070] It should be noted that, in a specific implementation, the preset frequency f1 may be a preset fixed frequency, such as every second or every 2 seconds, etc. Alternatively, the preset frequency f1 may be adaptively changed according to different scenarios, such as calculated by the above formula (1), so that the interrupt detection frequency in the simulation environment is as consistent as possible with the actual situation.

[0071] In the embodiment of the present invention, the interrupt detection thread (qINT thread) and the virtual processor thread (vCPU thread) run in parallel in the binary translation system. The qINT thread and the vCPU thread can communicate through shared memory and registers. Figure 3 , shows a schematic diagram of communication between the qINT thread and the vCPU thread in an embodiment of the present invention. Figure 3 Taking the first method of detecting interrupts as an example, when the qINT thread detects an interrupt to be processed, the qINT thread sets the value of the first register to the first value to notify the vCPU thread of the interrupt to be processed.

[0072] like Figure 3 As shown, the qINT thread queries the global interrupt flag in the shared memory at a preset frequency to see if it is set. The global interrupt flag is set by the virtual device thread when the interrupt is triggered. When the qINT thread detects that the global interrupt flag is set, it determines that an interrupt signal has arrived, that is, an interrupt to be processed is detected. Once the global interrupt flag is detected to be set, the qINT thread can perform the following operations to notify the vCPU thread: set the value of the first register R1 to 1. During execution, the vCPU thread can determine whether there is an interrupt to be processed by checking the value of R1.

[0073] In addition, the qINT thread can read the status parameters of the current TB in the vCPU thread from the shared memory, including variable a (the number of instructions executed by the current TB), variable b (whether there is a first response flag in the current TB), and variable c (the instruction position for determining the first response flag). The qINT thread can determine whether the current TB meets the first response condition based on the values ​​of variables a, b, and c obtained.

[0074] If the current TB meets the first response condition, the qINT thread does not need to modify the code block link related variables (such as TB_LINK parameters) of the current TB block in the vCPU thread. During the running process, when the vCPU thread executes to the code of the first exit, it will check the value of the first register R1. If R1 = 1, while ensuring the integrity of the translated code boundary, the vCPU thread will exit the state parameters of the current TB in advance and respond to and process the interrupt.

[0075] If it is determined that the current TB does not meet the first response condition, the qINT thread actively modifies the code block link related variables (such as TB_LINK parameters) of the current TB block in the vCPU thread. During the running process, the vCPU thread exits the state parameters of the current TB by eliminating the code block link (through the second exit) and performs interrupt response and processing.

[0076] The embodiment of the present invention realizes effective and timely processing of the system when an interrupt occurs through the communication method between the qINT thread and the vCPU thread, and the processing of interrupt responses under different conditions, ensuring that after the system receives the interrupt signal, the vCPU thread can correctly respond to the interrupt according to different situations, complete the interrupt processing process, and ensure the balance between interrupt response speed and code execution performance.

[0077] Method 2: Steps for detecting whether there is an interrupt to be processed may include: When the virtual device thread triggers an interrupt, it sends an interrupt signal to the virtual processor thread through the signal mechanism of the host operating system; the host operating system intercepts the interrupt signal and transmits it to the virtual processor thread; when the virtual processor thread receives the interrupt signal, it determines that an interrupt to be processed is detected.

[0078] In the second method, the vDEV thread can actively notify the vCPU thread through the signal mechanism, informing it that there is an interrupt that needs to be processed, and pass the relevant information of the interrupt (such as interrupt type, interrupt number, etc.) to the vCPU thread through the signal processing function.

[0079] In the embodiment of the present invention, the first method is a mechanism for actively detecting interruption, and the second method is a mechanism for passively detecting interruption.

[0080] The second method is to use the signal mechanism of the host operating system (such as Linux / Unix) to realize the transmission and processing of interrupts. When the vDEV thread detects a change in the device status or needs to trigger an interrupt, it sends an interrupt signal to the vCPU thread through the signal mechanism of the operating system. After the vDEV thread sends the interrupt signal, the host operating system intercepts the interrupt signal and passes it to the vCPU thread. After receiving the interrupt signal, the vCPU thread executes the pre-registered signal processing function. In the signal processing function, the vCPU thread reads the global interrupt flag and related shared data structures, obtains relevant information about the interrupt, and calls the corresponding interrupt processing logic.

[0081] In a specific implementation, a mechanism of actively detecting interrupts in parallel with the qINT thread and the vCPU thread (method one) may be adopted, or a mechanism of passively detecting interrupts based on signals (method two) may be adopted, and the embodiment of the present invention does not impose any limitation thereto.

[0082] In the second method, the qINT thread does not need to actively query the global interrupt flag, but the host operating system (host operating system) intercepts the interrupt signal sent by vDEV. The host operating system passes the interrupt related information to the vCPU thread by calling the signal processing function, so that the vCPU thread can perform corresponding processing later.

[0083] In the second method, the qINT thread can still communicate with the vCPU thread by modifying the register, but in the second method, the operation of modifying the first register R1 is completed in the signal processing function. How to respond to the interrupt is determined based on the state parameters of the currently executed code block and the value of the first register R1, which is consistent with the first method.

[0084] In the second approach, although interrupt detection is passive, the frequency of interrupt interference with DBT operation can still be achieved by controlling the frequency of sending inter-core interrupts (causing the translator to actively trap) to achieve a balance between the performance of the translated code and the interrupt response speed.

[0085] In an optional embodiment of the present invention, the method may further include: After the interrupt processing is completed, the value of the first register is set to a second value.

[0086] In an embodiment of the present invention, the first register R1 may be used to transmit interrupt signals between an interrupt detection thread (qINT thread) and a virtual processor thread (vCPU thread), coordinate interrupt response operations of the vCPU thread, and ensure that the system can handle interrupts promptly and correctly.

[0087] The first register R1 is used as a flag for the interrupt signal. When an interrupt to be processed is detected, it is set to the first value (such as set to 1) to notify the vCPU thread that there is an interrupt to be processed. After the vCPU thread completes the interrupt processing process, if R1 is not set to the second value (such as set to 0 or other values), the vCPU thread may detect that the value of R1 is 1 again, thereby mistakenly thinking that a new interrupt has arrived, resulting in repeated processing of the same interrupt. Therefore, after the interrupt processing is completed, the value of the first register is set to the second value to ensure the correct processing of the interrupt. Furthermore, after the interrupt processing is completed, the global interrupt flag should also be cleared.

[0088] In a specific implementation, when an interrupt to be processed is detected, the state parameters of the currently executed code block (such as the values ​​of variables a, b, and c) are obtained, and it is determined whether the currently executed code block meets the first response condition based on the state parameters. Based on whether the currently executed code block meets the first response condition, when the currently executed code block is in the state parameter, the response process of the vCPU thread to the interrupt can be divided into the following three situations (taking method one as an example): Case 1: The variable b of the currently executed code block is 0, that is, there is no first response flag in the currently executed code block, and the total number of instructions contained in the currently executed code block does not exceed M. Case 1 is a case where the currently executed code block does not meet the first response condition, and it is necessary to exit the currently executed code block through the second exit and enter the interrupt handler.

[0089] Reference Figure 4 , shows a schematic diagram of the interrupt processing flow of situation 1. Figure 4 As shown, the currently executed code block is TB2, the last executed code block is TB1, and the next code block to be executed is TB3. In the system-level DBT environment, TB2 starts to execute, and its variable b=0, indicating that there is no first response flag in TB2. During the execution process, if the qINT thread detects an interrupt to be processed, it sets the value of the first register R1 to 1 and obtains the status parameters of TB2 (such as the values ​​of variables a, b, and c). At this time, the variable b=0, indicating that there is no first response flag in TB2, and the total number of instructions contained in TB2 does not exceed the preset number M. Therefore, the vCPU thread does not need to exit TB2 early, and can disconnect the link between TB2 and the next code block (TB3) (corresponding to Figure 4In the interrupt response 1, set the second exit. After all the instructions of TB2 are executed in sequence, the vCPU thread exits the state parameters of TB2 through the second exit and prepares to perform context switching to handle the interrupt. The vCPU thread saves the information related to the current state parameters, such as the value of the register, the memory mapping relationship, the execution progress of TB2, and the TB_LINK parameter, to complete the context saving. After that, the system performs a context switch and transfers the execution right to the interrupt handler for corresponding processing. After the interrupt processing is completed, the value of the first register R1 is set to 0, and the system starts to restore the context. According to the saved information, the register value, memory mapping relationship, TB_LINK parameter, etc. are restored to the state before the interrupt occurs. After completing the context recovery, the vCPU thread can determine that the next TB to be executed is TB3 by looking up the TB_LINK parameter. Finally, the vCPU thread jumps to TB3 and continues to execute the subsequent program code to ensure the continuity and correctness of the program.

[0090] Scenario 2: Variable b of the currently executed code block = 1 and variable a < variable c, that is, there is a first response flag in the currently executed code block, the total number of instructions contained in the currently executed code block exceeds M, and the address of the currently executed instruction in the currently executed code block is less than the address of the first response flag, that is, the first exit has not yet been executed. Scenario 2 is a situation where the currently executed code block meets the first response condition, and the currently executed code block can be exited in advance through the first exit to enter the interrupt handler.

[0091] Reference Figure 5 , shows a schematic diagram of the interrupt processing flow of situation 2. Figure 5 As shown, the currently executed code block is TB2, the last executed code block is TB1, and the next code block to be executed is TB3. In the system-level DBT environment, TB2 starts to execute. During the execution process, if the qINT thread detects an interrupt to be processed, it sets the value of the first register R1 to 1, and obtains the status parameters of TB2 (such as the values ​​of variables a, b, and c). At this time, variable b=1, indicating that there is a first response flag in TB2, and the total number of instructions contained in TB2 exceeds the preset number M. At the same time, variable a (the number of instructions executed in TB2) is less than variable c (the instruction position of the first response flag). TB2 meets the first response condition and can exit the execution process of TB2 through the first exit. When the code of the first exit is executed (corresponding to Figure 5When the interrupt response 2 in the program is received, since R1=1, the execution flow of TB2 is directly exited and the interrupt handler is entered. Since the first exit is executed after the execution of the Mth instruction, the boundary integrity of the translated code can be guaranteed. The context needs to be saved before exiting, and the context needs to be restored after the interrupt processing is completed. This process is similar to that in case 1 and will not be repeated here. Finally, the vCPU thread continues to execute the remaining instructions of TB2 and then jumps to TB3 to continue executing the subsequent program code.

[0092] Case 3: Variable b of the currently executed code block = 1 and variable a ≥ variable c, that is, there is a first response flag in the currently executed code block, the total number of instructions contained in the currently executed code block exceeds M, and the address of the currently executed instruction in the currently executed code block is greater than or equal to the address of the first response flag, that is, the position of the currently executed instruction has exceeded the position of the first exit.

[0093] Situation 3 is the case where the currently executed code block does not meet the first response condition. It is necessary to exit the currently executed code block through the second exit and enter the interrupt handler. Figure 6 , shows a schematic diagram of the interrupt processing flow of situation 3. Figure 6 As shown, the currently executed code block is TB2, the last executed code block is TB1, and the next code block to be executed is TB3. In the system-level DBT environment, TB2 starts to execute. During the execution process, if the qINT thread detects an interrupt to be processed, the value of the first register R1 is set to 1, and the state parameters of TB2 (such as the values ​​of variables a, b and c) are obtained. At this time, variable b=1, indicating that there is a first response flag in TB2, the total number of instructions contained in TB2 exceeds the preset number M, and variable a≥variable c. TB2 does not meet the first response condition and can exit the execution process of TB2 through the second exit. Specifically, the second exit is set by disconnecting the link between TB2 and the next code block (TB3). After all instructions of TB2 are executed in sequence, the vCPU thread exits the execution state of TB2 through the second exit and prepares to perform context switching to handle the interrupt. The context is subsequently saved, and the context needs to be restored after the interrupt processing is completed. This process is similar to situation 1 and will not be repeated here. Finally, the vCPU thread jumps to TB3 and continues to execute subsequent program codes to ensure the continuity and correctness of the program.

[0094] In the embodiment of the present invention, when a pending interrupt is detected, the state parameters of the currently executed code block (such as the values ​​of variables a, b and c) are obtained, and the interrupt response mode and execution flow of the vCPU thread are determined according to the state parameters of the currently executed code block.

[0095] Function of variable b: variable b is an identifier of whether there is a first response flag in the basic block. When b = 1, it indicates that the current TB has the conditions to respond to interrupts in advance, otherwise the vCPU thread needs to wait for the current TB to complete execution before responding to interrupts. For example, in case 1, since b = 0, the vCPU thread will not exit until the current TB is executed; while in cases 2 and 3, since b = 1, the vCPU thread may respond to interrupts in advance, which requires further judgment.

[0096] Function of variable a: Variable a is the address of the currently executed instruction in the currently executed code block, which can be used to record the number of instructions that have been executed in the current TB, and to accurately determine the timing of the interrupt response. Variable a works with variables b and c to determine the interrupt response method of the vCPU thread. For example, in situation 2, the vCPU thread will only use the early exit method when variable b=1 and variable a<variable c; if variable a≥variable c, even if variable b=1, the processing flow is the same as situation 1, and it will exit after the current TB is executed, ensuring the balance between the interrupt response speed and the code execution progress.

[0097] Function of variable c: variable c indicates the position of the instruction for judging the first response flag, and provides a specific code position reference for the interrupt response. Variable c cooperates with variables a and b to determine when to trigger the interrupt response. For example, when variable b=1 and variable a<variable c, it means that before the current TB executes the instruction for judging the first response flag, that is, before the first exit, if an interrupt is detected (such as the value of the first register R1 is 1), the vCPU thread can exit in advance when executing to the first exit to respond to the interrupt; when variable b=1 and variable a≥variable c, it means that the best advance position for the interrupt response has passed, and it is necessary to exit through the second exit at this time, so that the interrupt response can be accurately located in the code execution, and the balance between the interrupt response speed and the code execution progress is guaranteed.

[0098] The embodiment of the present invention judges the first response condition through the state parameters (variables a, b and c) of the currently executed code block, determines the interrupt response mode and execution flow of the vCPU thread, and can ensure that interrupt processing can be carried out accurately and efficiently, thereby maintaining the stable operation of the system.

[0099] In summary, in the translation process of the dynamic binary translator of the embodiment of the present invention, if an interrupt to be processed is detected, the state parameters of the current execution code block are obtained, and it is determined whether the current execution code block meets the first response condition according to the state parameters; according to whether the current execution code block meets the first response condition, it is determined whether to respond to the interrupt through the first exit or the second exit. The first response condition is used to determine whether the current execution code block meets the condition for exiting the current execution code block in advance. The first exit is used to exit the current execution code block in advance and respond to the interrupt. The second exit is used to exit the current execution code block again at the end of the execution of the current execution code block and respond to the interrupt. The embodiment of the present invention selects a better interrupt response time (first exit or second exit) according to the state parameters of the current execution code block, so that the interrupt can be responded to in time at a better time point in different situations; it can avoid switching context too frequently when a large number of frequent interrupts are generated; it can achieve a more balanced performance of the translated code running and the interrupt response speed.

[0100] In addition, the embodiment of the present invention utilizes a new method to implement interrupt detection, which can separate the interrupt detection operation from the TB code. The interrupt detection operation no longer depends on the vCPU thread, so that the interrupt detection no longer affects the running performance of the translated code, and the performance of the vCPU thread can be further improved.

[0101] Furthermore, the embodiment of the present invention does not limit the length of the basic block and will not affect the optimization effect of the translator on the code.

[0102] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0103] The method in the above embodiment can be implemented as a binary translation system, including: a virtual device module, an interrupt detection module and a virtual processor module, which are respectively used to control the virtual device thread, the interrupt detection thread, and the virtual processor thread; wherein the interrupt detection thread is used to detect the interrupt triggered by the virtual device thread; the virtual processor thread is used to: in the translation stage, insert the interrupt response code after translating a preset number M instructions of the code block; in the execution stage, in response to the interrupt to be processed, determine whether the code block has been executed to the interrupt response code position; if the interrupt response code position has not been executed, after executing the Mth instruction, exit the execution stage via the interrupt response code and switch the context for interrupt processing; otherwise, exit the execution stage after executing the entire code block.

[0104] The interrupt detection thread can query whether the global interrupt flag in the shared memory is set according to a preset frequency. If the global interrupt flag is set, it is determined that an interrupt to be processed is detected; the global interrupt flag is set by the virtual device thread when the interrupt is triggered. The interrupt detection thread can notify the virtual processor thread of the interrupt to be processed by setting the value of the first register R1.

[0105] In combination Figure 4 In the embodiment described in or 6, when the virtual processor exits the execution phase after executing the entire code block, the interrupt detection thread disconnects the link between the current code block and the next code block in the virtual processor thread.

[0106] In combination Figure 5 In the described embodiment, after the virtual processor thread handles the interrupt, it switches back to the execution stage to execute the remaining unexecuted code i+1...m in the code block.

[0107] On the other hand, the above embodiment can also be implemented as a system-level binary translation device, including a context switching unit, which can enable the device to switch between a translation state for translating client code and an execution state for executing the translated host code; in the translation state, after translating a preset number M of host machine instructions for a code block, an interrupt response code is inserted; in the execution state, if an interrupt to be processed is found before the interrupt response code is executed, the binary translation device enters a context switch at the interrupt response code, exits the execution state, enters the translation state, and searches and translates the interrupt handler in the translation state; after executing the interrupt handler, it switches back to the execution state and executes the remaining unexecuted code in the code block.

[0108] Reference Figure 7 , shows a structural block diagram of an interrupt processing device embodiment of the present invention, which is applied to a binary translation system, in which a virtual device thread and a virtual processor thread are running, and the interrupt processing device may include: An interrupt detection module 801 is used to notify the virtual processor thread of a pending interrupt triggered by a virtual device thread by setting the value of a first register to a first value; The condition judgment module 802 is used to obtain the state parameters of the currently executed code block, and judge whether the currently executed code block meets the first response condition according to the state parameters; the state parameters include: the address of the currently executed instruction in the currently executed code block, whether there is a first response flag in the currently executed code block, and the address of the first response flag; wherein the first response flag is used to indicate whether the total number of instructions contained in the currently executed code block exceeds a preset number; A first response module 803 is used to exit the current execution code block through a first exit and enter an interrupt processing program if the current execution code block meets the first response condition; the first exit is located at the end position of a preset number of instructions in the current execution code block; The second response module 804 is used to exit the current execution code block through a second exit and enter the interrupt processing program if the current execution code block does not meet the first response condition; the second exit is located at the end position of the current execution code block.

[0109] Optionally, the device further comprises: The first exit setting module is used to set the first response flag and the first exit code after the Mth instruction and before the M+1th instruction if it is identified that the total number of instructions contained in the current translation code block exceeds M during the translation of the binary program of the source platform, where M is a preset number; the first exit code is used to directly exit the current execution code block and jump to the entry address of the interrupt handler when the current execution code block detects that the value of the first register is a first numerical value.

[0110] Optionally, the condition judgment module is specifically used to: If there is a first response flag in the currently executed code block, and the address of the currently executed instruction in the currently executed code block is less than the address of the first response flag, it is determined that the currently executed code block meets the first response condition.

[0111] Optionally, the device further comprises: The second exit setting module is used to disconnect the link between the current execution code block and the next code block if the current execution code block does not meet the first response condition, and set the second exit code at the end position of the current execution code block, and the second exit code indicates that the jump target address is the entry address of the interrupt handler.

[0112] Optionally, an interrupt detection thread is also run in the binary translation system, and the interrupt detection module is specifically used to: The interrupt detection thread queries whether the global interrupt flag in the shared memory is set according to a preset frequency. If the global interrupt flag is set, it is determined that an interrupt to be processed is detected; the global interrupt flag is set by the virtual device thread when an interrupt is triggered; and the value of the first register is set to a first value by the interrupt detection thread.

[0113] Optionally, the preset frequency is calculated based on the frequency of the processor in the host machine querying the interrupt request flag, the running time of the translated binary program in the target platform, and the running time of the binary program of the source platform in the source platform.

[0114] Optionally, the interrupt detection module is specifically used to: When an interrupt is triggered by the virtual device thread, an interrupt signal is sent to the virtual processor thread through the signal mechanism of the host operating system; the interrupt signal is intercepted by the host operating system and passed to the virtual processor thread; when the virtual processor thread receives the interrupt signal, it is determined that an interrupt to be processed is detected; after receiving the interrupt signal, the virtual processor thread executes a pre-registered signal processing function, and the value of a first register in the signal processing function is set to a first value.

[0115] Optionally, the device further comprises: A register recovery module is used to set the value of the first register to a second value after the interrupt processing is completed.

[0116] The interrupt processing device of the embodiment of the present invention, during the translation process of the dynamic binary translator, if an interrupt to be processed is detected, obtains the state parameters of the current execution code block, and determines whether the current execution code block meets the first response condition according to the state parameters; and determines whether to respond to the interrupt through the first exit or the second exit according to whether the current execution code block meets the first response condition. The first response condition is used to determine whether the current execution code block meets the condition of exiting the current execution code block in advance. The first exit is used to exit the current execution code block in advance and respond to the interrupt. The second exit is used to exit the current execution code block again at the end of the execution of the current execution code block and respond to the interrupt. The embodiment of the present invention selects a better interrupt response time (first exit or second exit) according to the state parameters of the current execution code block, so that the interrupt can be responded to in time at a better time point in different situations; it can avoid switching context too frequently when a large number of frequent interrupts are generated; and it can achieve a more balanced performance of the translated code running and the interrupt response speed.

[0117] In addition, the interrupt processing device of the embodiment of the present invention uses a new method to implement the simulation work of interrupt detection, which can separate the interrupt detection operation from the TB code. The interrupt detection operation no longer depends on the vCPU thread, so that the interrupt detection no longer affects the running performance of the translated code, and the performance of the vCPU thread can be further improved.

[0118] Furthermore, the embodiment of the present invention does not limit the length of the basic block and will not affect the optimization effect of the translator on the code.

[0119] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0120] Reference Figure 8 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the interrupt processing method of the aforementioned embodiment.

[0121] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to execute the steps of the interrupt processing method of the aforementioned embodiment. The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0122] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0123] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable terminal device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0126] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0127] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. An interrupt processing method, characterized in that: Applied to a binary translation system, in which a virtual device thread and a virtual processor thread are running, the method comprises: Notifying the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of the first register to a first value; Obtaining state parameters of a currently executed code block, and judging whether the currently executed code block satisfies a first response condition according to the state parameters; the state parameters include: an address of a currently executed instruction in the currently executed code block, whether a first response flag exists in the currently executed code block, and an address of the first response flag; wherein the first response flag is used to indicate whether the total number of instructions contained in the currently executed code block exceeds a preset number; If the currently executed code block meets the first response condition, the virtual processor thread exits the currently executed code block through a first exit and enters an interrupt handler; the first exit is located at the end position of a preset number of instructions in the currently executed code block; If the currently executed code block does not meet the first response condition, the virtual processor thread exits the currently executed code block through a second exit and enters an interrupt handler; the second exit is located at the end position of the currently executed code block.

2. The method according to claim 1, characterized in that The method further comprises: In the process of translating a binary program of a client platform, if it is identified that the total number of instructions contained in the current translation code block exceeds M, where M is the preset number, the virtual processor thread sets the first response flag and the first exit code after the Mth instruction and before the M+1th instruction; the first exit code is used to directly exit the current execution code block and jump to the entry address of the interrupt handler when the virtual processor thread reads that the value of the first register is a first numerical value.

3. The method according to claim 1, characterized in that The determining, according to the state parameter, whether the currently executed code block satisfies the first response condition includes: If there is a first response flag in the currently executed code block, and the address of the currently executed instruction in the currently executed code block is less than the address of the first response flag, it is determined that the currently executed code block meets the first response condition.

4. The method according to claim 1, characterized in that: The method further comprises: If the currently executed code block does not meet the first response condition, the link between the currently executed code block and the next code block is disconnected, and the code of the second exit is set at the end position of the currently executed code block, and the code of the second exit indicates that the jump target address is the entry address of the interrupt handler.

5. The method according to claim 1, characterized in that The binary translation system also runs an interrupt detection thread, and the steps of detecting pending interrupts triggered by the virtual device thread include: The interrupt detection thread queries whether a global interrupt flag in the shared memory is set according to a preset frequency, and if it is found that the global interrupt flag is set, it is determined that an interrupt to be processed is detected; the global interrupt flag is set by the virtual device thread when an interrupt is triggered; The step of setting the value of the first register to a first value includes: The interrupt detection thread sets the value of the first register to a first value.

6. The method according to claim 5, characterized in that The preset frequency is calculated based on the frequency of the processor in the host machine querying the interrupt request flag, the running time of the translated binary program in the target platform, and the running time of the binary program of the source platform in the source platform.

7. The method according to claim 1, characterized in that The steps of detecting a pending interrupt triggered by a virtual device thread include: When the virtual device thread triggers an interrupt, the virtual processor thread sends an interrupt signal through the signal mechanism of the host operating system; The host operating system intercepts the interrupt signal and transmits it to the virtual processor thread; When receiving the interrupt signal, the virtual processor thread determines that an interrupt to be processed is detected; and setting the value of the first register to a first value includes: After receiving the interrupt signal, the virtual processor thread executes a pre-registered signal processing function, in which the value of the first register is set to a first value.

8. The method according to claim 1, characterized in that The method further comprises: After the interrupt processing is completed, the value of the first register is set to a second value.

9. An interrupt processing method, applied to a binary translation system, wherein a virtual device thread, an interrupt detection thread, and a virtual processor thread are running in the binary translation system, the method comprising: The interrupt detection thread detects interrupts triggered by the virtual device thread; In the translation phase, after the virtual processor thread translates a preset number M of instructions of the code block, it inserts the interrupt response code; In the execution phase, in response to a pending interrupt, the virtual processor thread determines whether the code block has been executed to the interrupt response code location; In the case where the interrupt response code position is not executed, the virtual processor thread will exit the execution phase through the interrupt response code after executing the Mth instruction, and switch the context to perform interrupt processing; Otherwise, the virtual processor thread exits the execution phase after executing the entire code block.

10. The method according to claim 9, wherein: The interrupt detection thread queries whether the global interrupt flag in the shared memory is set according to a preset frequency. If the global interrupt flag is set, it is determined that an interrupt to be processed is detected; the global interrupt flag is set by the virtual device thread when an interrupt is triggered.

11. The method according to claim 9, wherein: The interrupt detection thread notifies the virtual processor thread of the pending interrupt by setting the value of the first register.

12. The method according to claim 9, wherein: When the virtual processor exits the execution phase after executing the entire code block, the interrupt detection thread disconnects the link between the current code block and the next code block in the virtual processor thread.

13. The method according to claim 9, wherein: After the virtual processor thread handles the interrupt, it switches back to the execution stage and executes the remaining unexecuted code in the code block.

14. A binary translation system comprising: The virtual device module, the interrupt detection module and the virtual processor module are used to control the virtual device thread, the interrupt detection thread and the virtual processor thread respectively; The interrupt detection thread is used to detect the interrupt triggered by the virtual device thread; Virtual processor threads are used to: In the translation phase, after translating a preset number M of instructions of the code block, an interrupt response code is inserted; In the execution phase, in response to the pending interrupt, determining whether the code block has been executed to the interrupt response code position; If the interrupt response code position is not executed, the execution phase will be exited through the interrupt response code after the Mth instruction is executed, and the context will be switched for interrupt processing; Otherwise, the execution phase is exited after the entire code block is executed.

15. A system-level binary translation device, comprising a context switching unit, which switches the device between a translation state for translating client code and an execution state for executing translated host code; In the translation state, after translating a preset number M of host machine instructions into the code block, an interrupt response code is inserted; In the execution state, if an interrupt to be processed is found before the interrupt response code is executed, the binary translation device enters a context switch at the interrupt response code, exits the execution state, enters the translation state, and searches and translates the interrupt handler in the translation state; After executing the interrupt handler, switch back to the execution state and execute the remaining unexecuted code in the code block.

16. An interrupt processing device, characterized in that: Applied to a binary translation system, in which a virtual device thread and a virtual processor thread are running, the apparatus comprises: An interrupt detection module, configured to notify the virtual processor thread of a pending interrupt triggered by the virtual device thread by setting the value of the first register to a first value; A conditional judgment module, used to obtain state parameters of a currently executed code block, and judge whether the currently executed code block satisfies a first response condition according to the state parameters; the state parameters include: the address of a currently executed instruction in the currently executed code block, whether a first response flag exists in the currently executed code block, and the address of the first response flag; wherein the first response flag is used to indicate whether the total number of instructions contained in the currently executed code block exceeds a preset number; A first response module, configured to exit the currently executed code block through a first exit and enter an interrupt processing program if the currently executed code block satisfies the first response condition; the first exit is located at the end position of a preset number of instructions in the currently executed code block; The second response module is used to exit the current execution code block through a second exit and enter the interrupt processing program if the current execution code block does not meet the first response condition; the second exit is located at the end position of the current execution code block.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the interrupt processing method according to any one of claims 1 to 13.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the interrupt processing method according to any one of claims 1 to 13 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the interrupt processing method according to any one of claims 1 to 13 are implemented.

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