A design method and system for nested DSR priorities

Abstract

The present invention discloses a design method and system for nested DSR priorities. The method includes adding a preset first number of interrupt sources to the original number of interrupt sources in the chip design; prioritizing the preset first number of interrupt sources; and simulating a DSR program with the preset first number of interrupt sources to replace the original DSR program and execute DSR tasks, thereby enabling an interrupt controller that supports priority order to execute the DSR program according to the preset priority. The solution provided by the present invention can more stably address real-time performance and hardware blocking issues in FreeRTOS systems.

Description

Technical Field

[0001] The present invention relates to the technical field of interrupt processing, and in particular to a design method and system for nested DSR priorities. Background Art

[0002] Interrupt Service Routine (ISR) and Deferred Service Routine (DSR) are two important concepts in interrupt handling, especially in the FreeRTOS real-time operating system. ISR and DSR are part of interrupt handling and they work together to handle interrupts efficiently.

[0003] An ISR, or interrupt service routine, is responsible for quickly responding to interrupt requests. Its primary function is to perform fast hardware-related operations, such as reading data or clearing interrupt flags, as quickly as possible. Because ISRs need to execute quickly, they typically contain only essential, fast code and avoid complex processing logic to minimize interrupt latency.

[0004] A Deferred Service Routine (DSR) handles tasks that were not completed by an ISR. After the ISR completes, if there are tasks requiring further processing, these tasks are deferred to the DSR. The DSR typically executes after the ISR, allowing the system to continue processing other tasks after the ISR completes its urgent tasks, thereby improving overall system efficiency and responsiveness.

[0005] The ISR and DSR work as follows: ‌When an interrupt occurs‌: The hardware generates an interrupt signal, calling the ISR. The ISR quickly performs the necessary hardware operations, such as reading data or clearing the interrupt flag. If the task is complex, the ISR marks the remaining tasks as pending. At the appropriate time, the DSR is called to complete the tasks left unfinished by the ISR. The DSR can execute when the system is idle or wait until a certain condition is met.

[0006] In FreeRTOS systems, a timer daemon task is typically used to execute DSRs. However, in FreeRTOS, all DSRs must be queued for execution. That is, regardless of the priority of the ISR, DSRs are executed sequentially with the same priority. This can cause DSRs for low-priority interrupts to take a long time to execute, delaying the execution of DSRs for higher-priority interrupts and affecting the real-time performance of the entire system.

[0007] If the DSR of an interrupt is abnormally blocked, the DSRs queued in the queue cannot be executed, and the ISR corresponding to the queued DSR cannot be executed (because the unmask work corresponding to the interrupt is completed in the DSR), which eventually causes the entire application to be unable to run. Summary of the Invention

[0008] To solve the above technical problems, an embodiment of the present invention provides a design method and system for nested DSR priorities.

[0009] The technical solution of the embodiment of the present invention is achieved as follows:

[0010] An embodiment of the present invention provides a design method for nested DSR priorities, the method comprising:

[0011] Based on the original number of interrupt sources in the chip design, a first number of interrupt sources are added;

[0012] Setting priorities for the preset first number of interrupt sources;

[0013] The preset first number of interrupt sources are used to simulate the DSR program to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority sequence executes the DSR program according to the set priority.

[0014] In one embodiment, when the interrupt controller executes the DSR program according to the set priority, the process of executing each DSR program is independent of each other, and the DSR program with a higher priority is executed first.

[0015] In one embodiment, after an ISR task is completed, a DSR program is triggered to execute the DSR task.

[0016] In one embodiment, one ISR program executes one ISR task, and the priority of any ISR program is higher than the priority of all DSR programs.

[0017] In one embodiment, the interrupt controller first executes the ISR program according to the set priority at any time, and then executes the DSR program according to the set priority after all ISR programs are executed.

[0018] An embodiment of the present invention also provides a DSR priority nestable design system, comprising: a processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, it executes the steps of the above-mentioned method.

[0019] The embodiments of the present invention have the following beneficial effects:

[0020] (1) High real-time performance: The execution of high-priority ISR is real-time and is not affected by any delay in processing of low-priority interrupts, which is used to ensure the real-time processing of high-priority interrupts.

[0021] (2) The DSR program is triggered directly by the interrupt without the intervention of the scheduler.

[0022] (3) Preemptible delay processing to avoid DSR priority flipping. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of a flow chart of a design method for nested DSR priorities according to an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of a processing flow in a scenario according to an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of a processing flow in a scenario using the prior art;

[0026] Figure 4 This is a diagram of the internal structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0028] The embodiment of the present invention provides a design method for nesting DSR priorities, such as Figure 1 As shown, the method includes:

[0029] Step 101: adding a preset first number of interrupt sources based on the original number of interrupt sources in the chip design;

[0030] Step 102: Setting priorities for the preset first number of interrupt sources;

[0031] Step 103: Use the preset first number of interrupt sources to simulate the DSR program to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority order executes the DSR program according to the set priority.

[0032] In previous technologies, traditional DSRs are pure software, and all interrupt delay handlers need to be queued in chronological order. Regardless of the priority of the interrupt itself, the corresponding DSRs have the same priority and are executed in the order they enter the queue.

[0033] This application utilizes the nested nature of ISR and uses ISR to simulate DSR, so that DSR also has priority, and the ISR of high-priority interrupt can be executed first, and the high-priority DSR can also be executed first.

[0034] This embodiment reserves N IRQ numbers (i.e., interrupt sources) when configuring the NVIC in the CPU to simulate DSRs. These N reserved IRQ numbers do not have hardware interrupt connections and are used only as simulated DSRs in the FreeRTOS system. For example, if the product requires 100 interrupt sources during chip design, this embodiment adds 32 additional reserved interrupt sources during chip design. These are not connected to peripherals and are considered idle IRQs. When the FreeRTOS system is running, the ISR programs corresponding to these reserved IRQs simulate DSR programs, enabling nested DSR programs (nesting means that the higher-priority interrupt is executed first).

[0035] That is, in the prior art, the DSR program corresponding to the ISR program is a pure software queue and is executed in chronological order. However, in this embodiment, the ISR simulates the DSR so that the DSR can have a priority and be executed according to the priority.

[0036] Specifically, the method provided in this embodiment mainly includes the following contents:

[0037] 1. When designing the chip architecture, reserve N IRQs to simulate DSR interrupt numbers;

[0038] 2. Set the priority of N IRQs, where N is the highest priority and 0 is the lowest priority. High-priority interrupts can nest low-priority interrupts; replace the DSR program with the interrupt ISR program corresponding to N IRQs, so that the DSR program has priority.

[0039] 3. The interrupt controller NVIC of ARM-M CPU supports interrupt nesting function.

[0040] 4. After the normal ISR is executed, the DSR is triggered. DSRs have different priorities. DSRs of different priorities will not affect each other, and high-priority DSRs can preempt low-priority DSRs.

[0041] In this embodiment, ISR0 can correspond to an independent DSR0. The execution time and real-time performance of ISR0 and DSR0 of this interrupt are not affected by DSR1 (and other lower-priority DSRs). DSRs can also be prioritized. A high-priority ISR0 corresponds to a higher-priority DSR0, and a DSR0 can nest a lower-priority DSR1. High-priority ISRs can ensure real-time performance.

[0042] For ease of understanding, the present embodiment is described below using a specific scenario.

[0043] See also Figure 2 In this embodiment, the scenario where the low-priority DSR1 is nested is as follows:

[0044] 1. At time t1, ISR1 is executing.

[0045] 2. At time T2, ISR1 is completed and DSR1 begins to execute.

[0046] 3. At time T3, DSR1 is not completed and the high-priority interrupt ISR0 is executed.

[0047] 4. At T4, ISR0 is completed and DSR0 begins to execute.

[0048] 5. At T5, DSR0 is executed (ISR0 can be triggered again at this time) and DSR1 is executed again.

[0049] 6. At T6, DSR1 is completed and the thread execution returns to normal.

[0050] Real-time requirement: T3~T5 is the execution time of 0 priority interrupt. After T5, ISR0 can be triggered again. Figure 2 Middle red arrow.

[0051] The processing flow chart of the same scenario without adopting the solution of this embodiment is as follows Figure 3 Shown, including:

[0052] 1. At time t1, ISR1 is executing.

[0053] 2. At time T2, ISR1 is completed and DSR1 begins to execute.

[0054] 3. At time T3, DSR1 is not completed and the high-priority interrupt ISR0 is executed.

[0055] 4. At time T4, ISR0 is completed and DSR1 continues to be executed.

[0056] 5. At T5, after DSR1 is executed, DSR0 is executed (because ISR1 is executed first, DSR1 enters the queue first, and ISR0 is executed later, and DSR0 enters the queue later).

[0057] 6. At T6, DSR0 is executed and the thread starts to execute. T6 can trigger ISR0, such as Figure 3 Indicated by the red line.

[0058] Real-time issue: The re-triggering of ISR0 depends on the execution time of DSR1, that is, the time from T4 to T5, which affects the real-time performance of ISR0.

[0059] In summary, because this embodiment uses ISR to simulate DSR, the real-time execution of high-priority ISR is not affected by any delay in processing of low-priority interrupts, which is used to ensure the real-time processing of high-priority interrupts and can more stably solve the real-time problems and hardware blocking problems in the FreeRTOS system.

[0060] In order to implement the method of an embodiment of the present invention, an embodiment of the present invention also provides a DSR priority nested design system, including: a processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, it executes the steps of the above-mentioned method.

[0061] The above-mentioned system provided in this embodiment and the above-mentioned method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0062] To implement the method of an embodiment of the present invention, an embodiment of the present invention further provides a computer program product. The computer program product includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of the above method.

[0063] Based on the hardware implementation of the above program modules and in order to implement the method of the embodiment of the present invention, the embodiment of the present invention further provides an electronic device (computer device). Specifically, in one embodiment, the computer device can be a terminal, and its internal structure diagram can be as follows: Figure 4 As shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05, and a memory (not shown in the figure) connected via a system bus. The processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor A01, the method of any of the above embodiments is implemented. The display screen A04 of the computer device can be a liquid crystal display or an electronic ink display. The input device A05 of the computer device can be a touch layer covering the display screen, or it can be a key, trackball, or touchpad provided on the computer device housing, or it can be an external keyboard, touchpad, or mouse.

[0064] Those skilled in the art will understand that Figure 4The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0065] The device provided by an embodiment of the present invention includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the method of any one of the above embodiments is implemented.

[0066] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0068] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1A step that specifies a function in one or more boxes.

[0070] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0071] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0072] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0073] It is understood that the memory of the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disk, or compact disc read-only memory (CD-ROM); magnetic surface memory may be magnetic disk or tape memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0074] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0075] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A design method for nested DSR priorities, characterized in that: The method comprises: Based on the original number of interrupt sources in the chip design, a first number of interrupt sources are added; Setting priorities for the preset first number of interrupt sources; Simulating a DSR program with the preset first number of interrupt sources to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority order executes the DSR program according to the set priority; The step of setting priorities for the preset first number of interrupt sources includes: Sort the preset first number of interrupt sources from 0 to N, with N being the highest priority and 0 being the lowest priority; Among them, the interrupt controller first executes the ISR program according to the set priority at any time, and then executes the DSR program according to the set priority after all ISR programs are executed; When the interrupt controller executes the DSR program according to the set priority, the process of executing each DSR program is independent of each other, and the DSR program with a higher priority is executed first.

2. The design method for nested DSR priorities according to claim 1, characterized in that: After an ISR task is completed, a DSR program is triggered to execute the DSR task.

3. The design method for nested DSR priorities according to claim 2, characterized in that: An ISR program executes an ISR task, and the priority of any ISR program is higher than the priority of all DSR programs.

4. A design system with nested DSR priorities, characterized in that: include: A processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, the steps of the method according to any one of claims 1 to 3 are performed.

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