Task processing method and device, electronic equipment and storage medium

Abstract

The invention provides a task processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a to-be-processed calculation task in a many-core system which comprises a plurality of processing cores; the calculation task is obtained in real time through calculation by a previous task processing layer of a current task processing layer in a target calculation scene, and the target calculation scene comprises a plurality of task processing layers with a data connection relationship; according to the time delay requirement and the first data size of the calculation task, the calculation task is split into multiple calculation instructions from the time dimension, a processing core set distributed for the calculation task is determined from the space dimension, and the multiple calculation instructions are used for indicating the execution logic of the calculation task; according to the calculation instruction, the calculation task is mapped to the processing core group, so that the processing core group processes the calculation task, in this way, calculation tasks of different sizes can be efficiently adapted, and the utilization rate of calculation resources is increased.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a task processing method and device, an electronic device, and a storage medium. Background Art

[0002] With the development of artificial intelligence and deep learning technologies, large models have been widely used in many fields such as natural language processing and computer vision. Large models usually have complex structures and large-scale parameters, and have high demands on computing resources. In related technologies, computing tasks of large models can be processed based on many-core systems. Many-core systems have multiple heterogeneous processing cores and can process computing tasks in parallel. However, the amount of computing data for computing tasks is usually uncertain, and fixed computing resource allocation may not match the computing tasks, resulting in problems such as computing resource allocation not meeting requirements or resource waste. Summary of the invention

[0003] The present invention provides a task processing method and device, an electronic device, and a storage medium.

[0004] In a first aspect, the present disclosure provides a task processing method, the task processing method comprising:

[0005] Obtaining a computing task to be processed in a many-core system, the many-core system including a plurality of processing cores; the computing task is obtained in real time by computing a task processing layer above a current task processing layer in a target computing scenario, the target computing scenario including a plurality of task processing layers having a data connection relationship;

[0006] According to the latency requirement of the computing task and the first data volume, splitting the computing task into a plurality of computing instructions from a time dimension, and determining a processing core group allocated to the computing task from a space dimension, wherein the plurality of computing instructions are used to indicate the execution logic of the computing task;

[0007] According to the computing instruction, the computing task is mapped to the processing core group so that the processing core group processes the computing task.

[0008] In a second aspect, the present disclosure provides a task processing device, the task processing device comprising:

[0009] an acquisition module, used for acquiring a computing task to be processed in a many-core system, the many-core system including a plurality of processing cores; the computing task is obtained in real time by calculation at a task processing layer above a current task processing layer in a target computing scenario, the target computing scenario including a plurality of task processing layers having a data connection relationship;

[0010] a determination module, configured to split the computing task into a plurality of computing instructions from a time dimension according to a latency requirement of the computing task and a first data volume, and to determine a processing core group allocated to the computing task from a space dimension, wherein the plurality of computing instructions are used to indicate an execution logic of the computing task;

[0011] The processing module is used to map the computing task to the processing core group according to the computing instruction, so that the processing core group processes the computing task.

[0012] In a third aspect, the present disclosure provides an electronic device comprising: a plurality of processing cores; and an on-chip network configured to exchange data between the plurality of processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can perform the above-mentioned task processing method.

[0013] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned task processing method when executed by a processing core.

[0014] In a fifth aspect, an embodiment of the present disclosure further provides a computer program product, comprising a computer-readable code, or a non-volatile computer-readable storage medium carrying a computer-readable code. When the computer-readable code runs in a processing core of an electronic device, the processing core in the electronic device executes the above-mentioned task processing method.

[0015] In the embodiments provided by the present disclosure, when processing is performed through multiple task processing layers in a target computing scenario, the output processed by one task processing layer can be used as the input of the next task processing layer with a data connection relationship, that is, the computing task to be processed by the current task processing layer can be obtained by the previous task processing layer through real-time calculation, and usually the size of the computing task calculated by each task processing layer in real time is uncertain. If fixed resources are allocated to each task processing layer in advance, it may not match the computing task. Therefore, in the embodiments of the present disclosure, for this scenario, the computing task to be processed by the current task processing layer in the multi-core system is obtained, and according to the latency requirement of the computing task and the first data The computing task can be flexibly split from the time and space dimensions. The computing task can be split into multiple computing instructions from the time dimension, and the processing core group assigned to the computing task can be determined from the space dimension. Then, according to the computing instruction, the computing task is mapped to the processing core group so that the processing core group processes the computing task. In this way, the computing task can be dynamically and flexibly split in the space and time dimensions according to the latency requirement and the first data volume of the currently obtained computing task, which improves the accuracy of computing instruction splitting and computing resource allocation, so that the computing of computing tasks with different data volumes can be dynamically adapted, thereby improving the utilization rate and overall performance of computing resources in the many-core system.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0018] Figure 1 A flowchart of a task processing method provided by an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of the principle of splitting computing tasks in an embodiment of the present disclosure;

[0020] Figure 3 is an optimization flow chart of the target cost function in the embodiment of the present disclosure;

[0021] Figure 4 A schematic diagram of the principle of allocating shared storage areas between different processing core groups in an embodiment of the present disclosure;

[0022] Figure 5A schematic diagram of allocation of different processing core groups in an embodiment of the present disclosure;

[0023] Figure 6 A block diagram of a task processing device provided by an embodiment of the present disclosure;

[0024] Figure 7 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0026] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0027] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0030] Large models usually have complex structures and large-scale parameters, and have high demands on computing resources. It is very necessary to optimize the computation of large models. In related technologies, computing tasks of large models can be executed based on many-core systems. Many-core systems have multiple heterogeneous processing cores and can process computing tasks in parallel. Computing resources are usually allocated in advance, but the amount of computing data for computing tasks is usually uncertain, which brings challenges to efficient computing on many-core systems. Fixed computing resource allocation may not match the needs of computing tasks, resulting in resource waste or resource dissatisfaction.

[0031] That is, the input data size of large models is often uncertain. How to effectively schedule and optimize matrix operations of uncertain size in a many-core architecture to ensure efficient use of resources has become a key research direction in compilation technology.

[0032] Among them, the calculation of each network layer in the large model can usually be expressed as the product calculation between the input vector and the weight matrix of the network layer. That is, the calculation task of the large model can be understood as a matrix calculation task, and the amount of calculation data of the matrix calculation task represents the size of the calculation matrix.

[0033] Existing neural network accelerators often contain highly parallel matrix acceleration units, and then put the matrix (tensor) related calculations in the neural network into the neural network accelerator one by one for calculation. However, the scale of matrix calculations often does not match the fixed matrix acceleration units, resulting in a waste of computing resources.

[0034] The disclosed embodiments aim to propose a processing scheme for matrix computing tasks, which can efficiently adapt to the matrix operations of uncertain sizes in large models and improve the utilization rate of computing resources and overall performance. In order to efficiently and flexibly adapt to the matrix calculations of different sizes in large models and improve the utilization rate of computing resources of many-core chips, the scheme flexibly splits the computing task in two dimensions, time and space, according to the size of the computing matrix and the delay requirements.

[0035] According to the matrix size and computing delay requirements, the matrix calculation task can be split in time and space dimensions. The time dimension splitting is to split the matrix calculation task into multiple hardware instructions for execution, and the space dimension splitting is to distribute the matrix calculation task to multiple processing cores for calculation.

[0036] The task processing method according to the embodiment of the present disclosure can be executed by an electronic device such as a terminal device or a server, and the terminal device can be a vehicle-mounted device, a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor calling a computer-readable program instruction stored in a memory. Alternatively, the method can be executed by a server.

[0037] It should be noted that in the embodiments of the present disclosure, there is no limitation on the network model, and the network model can be used to perform any of image processing tasks, speech processing tasks, text processing tasks, and video processing tasks. The output result of the network model reasoning includes any of images, speech, text, and videos.

[0038] Figure 1 A flowchart of a task processing method provided by an embodiment of the present disclosure. Figure 1 , the method comprising:

[0039] Step S110: Obtain a computing task to be processed in a many-core system, where the many-core system includes multiple processing cores.

[0040] In the embodiment of the present disclosure, mainly for the compilation stage of the many-core system, computing instructions are split and processing cores are allocated to the computing tasks in the compilation stage. The computing task is obtained in real time through calculation by the previous task processing layer of the current task processing layer in the target computing scenario. The target computing scenario includes multiple task processing layers with data connection relationships.

[0041] In one possible embodiment, the task processing layer is the network layer in the network model, and the target computing scenario is a computing scenario based on the network model. The computing task can be the computing task to be processed corresponding to the network layer in the network model. The computing tasks of each network layer in the network model can be processed based on the task processing method in the embodiment of the present disclosure. For example, for the network layer in the network model, its computing task can be the product calculation between the input vector and the weight matrix of the network layer, that is, the computing task can also be understood as a matrix computing task.

[0042] The input vector of the current network layer in the network model can be the output of the previous network layer, and the output size of the previous network layer is uncertain. Therefore, the data size of the weight matrix and input vector of each network layer in the network model may not be the same, and the computing task size of each network layer is uncertain. Therefore, the computing resources required for each network layer may also not be the same. In the embodiment of the present disclosure, dynamic computing resource optimization can be performed for the computing tasks of each network layer.

[0043] Of course, in the embodiments of the present disclosure, computing tasks in other scenarios can also be targeted, and there is no limitation to this.

[0044] Step S120: According to the latency requirement of the computing task and the first data volume, the computing task is split into multiple computing instructions from the time dimension, and the processing core group assigned to the computing task is determined from the space dimension. The multiple computing instructions are used to indicate the execution logic of the computing task.

[0045] Among them, the computing instructions corresponding to the computing task can be understood as the hardware execution scheduling unit, which is used to control and instruct the hardware to perform certain operations and processing functions. A computing task can be divided into a computing instruction set, and the execution process of multiple computing instructions in the computing instruction set represents the computing logic of the computing task.

[0046] For example, based on the Single Instruction, Multiple Data (SIMD) technology, the computing task can be split into a SIMD computing instruction set. The SIMD allows one instruction to operate on multiple data elements at the same time, that is, multiple data elements can be processed in parallel to improve computing efficiency.

[0047] In the embodiments of the present disclosure, the computing tasks can be flexibly split in two dimensions, time and space, according to the latency requirements and the amount of data. For example, Figure 2 As shown in FIG. 1 , it is a schematic diagram of the principle of splitting computing tasks in the embodiment of the present disclosure. Splitting in the time dimension means splitting the computing task into multiple computing instructions, and splitting in the space dimension means allocating the computing task to multiple processing cores for computing. Figure 2 As shown, after splitting from the time and space dimensions, multiple processing cores can execute multiple computing instructions or computing tasks in parallel at the same time.

[0048] The first data volume of the computing task is usually positively correlated with the computing resources that need to be allocated, that is, the larger the first data volume is, the more computing resources need to be allocated, that is, the more processing cores need to be allocated.

[0049] In this way, in the embodiment of the present disclosure, the computing task is represented as multiple computing instructions, and the processing core group assigned to the computing task is determined, so that computing tasks with different data sizes can be flexibly adapted and the computing resource utilization in the many-core system can be improved.

[0050] Step S130: According to the computing instruction, the computing task is mapped to the processing core group, so that the processing core group processes the computing task.

[0051] The processing core of the many-core system may include a computing unit and a storage unit, wherein the computing unit is used to provide computing resources and the storage unit is used to provide storage resources. The computing unit of the processing core in the processing core group may be instructed to execute computing instructions according to computing instructions.

[0052] In the disclosed embodiment, for computing tasks to be processed in a many-core system, the computing tasks can be split into multiple computing instructions based on the latency requirements and the first data volume of the computing tasks, and a processing core group assigned to the computing tasks can be determined. Then, based on the computing instructions, the computing tasks can be mapped to the processing core group so that the processing core group processes the computing tasks. In this way, the computing tasks can be dynamically and flexibly split from the time dimension and the space dimension based on the latency requirements and the first data volume, which can efficiently adapt to computing tasks of different sizes and improve resource utilization.

[0053] The task processing method according to the embodiment of the present disclosure is described below.

[0054] As mentioned above, computing tasks can be subdivided in two dimensions, space and time. Splitting in the spatial dimension requires allocating more computing units, and splitting in the time dimension requires more computing instructions. However, due to hardware limitations and delay requirements of computing tasks, the computing units and computing instructions that can be allocated to computing tasks are limited. Therefore, for computing tasks of different sizes, the embodiments of the present disclosure also provide an implementation method for dynamically optimizing computing resources and computing time, which can dynamically determine the number of computing instructions and the number of processing cores allocated for the corresponding split of the computing task.

[0055] In a possible embodiment, according to the latency requirement of the computing task and the first data volume, the computing task is split into multiple computing instructions from the time dimension, and the processing core group assigned to the computing task is determined from the space dimension, including:

[0056] S1. Obtain a first data volume and a first duration of latency requirement of a computing task, as well as a second data volume that can be supported in a processing core and a second duration required to complete calculation of the second data volume.

[0057] For example, the first data volume of the computing task is S1, and the first duration of the delay requirement of the computing task is T thThe maximum second data volume that can be calculated in each processing core is S2, and the second time required for a single processing core to complete the calculation of the second data volume is t.

[0058] S2. Obtain, based on the first data amount and the second data amount, a total number of computing instructions required for the computing task when using one processing core.

[0059] For example, when one processing core, ie one computing unit, is used to complete the calculation of the computing task, the total number of computing instructions required is N, and N=S1 / S2.

[0060] S3. Determine the target number of processing cores for the computing task and the target number of computing instructions required for the computing task in a single processing core when the target number of processing cores is used, based on the first duration, the second duration, and the total number of computing instructions.

[0061] For step S3, the present disclosure provides possible implementations:

[0062] 1) Construct a target cost function, which represents a mapping function with the number of computing instructions required in a single processing core and the number of processing cores as variables and the cost value as the target.

[0063] 2) Obtaining the constraints of the target cost function, the constraints include: the product of the number of computing instructions and the second duration is less than or equal to the first duration, the number of processing cores is less than or equal to the total number of processing cores in the multi-core system, and the number of computing instructions is equal to the ratio of the total number of computing instructions to the number of processing cores.

[0064] For example, the target cost function is C: C = α*n s +β*n t

[0065] The constraints of the objective cost function include:

[0066] n t *t≤T th , n s ≤core num , n t =N / n s

[0067] Where N is the total number of computing instructions, and the number of computing instructions required in a single processing core is n t , the number of processing cores is n s , n s ∈N,n t ∈N, the first duration is T th , the second duration is t, core num is the total number of processing cores included in the many-core system, and α and β are preset parameters.

[0068] 3) Under the condition of satisfying the constraints, the target cost function is optimized to obtain the target number of computing instructions and the target number of processing cores for the computing task.

[0069] In the embodiments of the present disclosure, based on the target cost function and constraints, an optimization algorithm can be used to determine a set of optimal target numbers of computing instructions and target numbers of processing cores corresponding to the computing task, wherein the optimization algorithm is not limited in the embodiments of the present disclosure.

[0070] S4. From the time dimension, the computing task is split into multiple computing instructions according to the target number of computing instructions, and from the space dimension, a processing core group allocated to the computing task is determined, and the processing core group includes processing cores with the target number of processing cores.

[0071] In this way, in the embodiments of the present disclosure, the target number of processing cores to be allocated and the target number of computing instructions to be split in a single processing core can be dynamically determined based on the first data volume and latency requirements of the computing task, and the computing task can be split from the time dimension and the space dimension, thereby improving the utilization of computing resources in the many-core system.

[0072] In a possible embodiment, the present disclosure also provides a possible method for optimizing the target cost function, for example, see Figure 3 As shown, it is an optimization flow chart of the target cost function in the embodiment of the present disclosure, such as Figure 3 As shown, including:

[0073] Step S301: Determine the total number of computing instructions of the computing task.

[0074] For example, according to the ratio of the first data amount to the second data amount, the total number of computing instructions required for the computing task when one processing core is used is obtained.

[0075] Step S302: Determine the initial number of processing cores according to the first data volume, and determine the initial number of computing instructions according to the total number of computing instructions and the initial number of processing cores.

[0076] Regarding the method for determining the initial number of processing cores, the present disclosure provides a possible implementation scheme, which determines the first computing type of the computing task based on the first data volume, and determines the initial number of processing cores based on the first computing type and the mapping relationship between the computing type and the number of processing cores.

[0077] For example, the calculation type is set in advance, and the calculation types include low latency for large data volume, high latency for large data volume, low latency for small data volume, and high latency for small data volume. A mapping relationship table between the calculation type and the number of processing cores is set, and then according to the first data volume and latency requirements of the calculation task, the first calculation type of the calculation task is determined, and the mapping relationship table is searched to determine the initial number of processing cores corresponding to the first calculation type, and then the ratio of the total number of calculation instructions to the initial number of processing cores is determined as the initial number of calculation instructions.

[0078] Step S303: Filter out a new number of processing cores from the preset list of processing core numbers, and determine a new number of computing instructions according to the total number of computing instructions and the new number of processing cores.

[0079] Step S304: Calculate the cost increment value.

[0080] Taking the first round of calculation as an example, the initial cost value is obtained according to the initial number of processing cores and the initial number of calculation instructions, as well as the target cost function. The first number of processing cores closest to the initial number of processing cores is selected from the preset list of processing core numbers, and the first number of calculation instructions is determined according to the total number of calculation instructions and the first number of processing cores. The first generation value is obtained according to the first number of processing cores and the first number of calculation instructions, as well as the target cost function, and then the cost increment value can be obtained according to the initial cost value and the first generation value. For example, the difference between the first generation value and the initial cost value is calculated to obtain the cost increment value.

[0081] Step S305: Determine whether the cost increment value is less than 0, if so, execute step S306, if not, execute step S309.

[0082] Step S306: taking the new number of processing cores as the target number of processing cores, and taking the new number of computing instructions as the target number of computing instructions.

[0083] Step S307: Determine whether the end condition is met, if so, execute step S308, if not, execute step S309.

[0084] Step S308: End.

[0085] Step S309: Determine whether the search is sufficient, if so, execute step S310, otherwise, return to continue executing step S303.

[0086] Here, whether the search is sufficient is determined, that is, whether the list of the number of processing cores has been traversed.

[0087] Step 310: No solution.

[0088] In the disclosed embodiment, when the cost increment value is greater than or equal to 0 and the list of the number of processing cores has not been traversed completely, the new number of processing cores and the new number of computing instructions for the next round continue to be determined based on the number of processing cores and the number of computing instructions in this round until the termination condition is met or the list of the number of processing cores has been traversed completely.

[0089] In this way, in the embodiment of the present disclosure, optimization processing can be performed according to the target cost function to determine the target number of computing instructions and the target number of processing cores corresponding to the computing task. The target number of computing instructions is the number of instructions that need to be split in a single processing core. Then, based on the target number of computing instructions, the computing task is split into multiple computing instructions, and the target number of processing cores is determined for the computing task, thereby improving the accuracy of computing instruction splitting and processing core resource allocation, and improving computing and resource allocation performance.

[0090] In the embodiment of the present disclosure, a computing task is split into multiple computing instructions from the time dimension, and a processing core group assigned to the computing task is determined from the spatial dimension. Then, the computing task can be processed by the processing core group according to the computing instruction. Different computing tasks can be assigned to different processing core groups, and there may be a data transmission relationship between different processing core groups. For example, the calculation result of one processing core group is the input of the computing task of another processing core group. Therefore, in the embodiment of the present disclosure, in order to describe the data transmission relationship between the processing core groups, the abstract concept of a data pad can be introduced to represent the communication abstraction of hardware storage resources. The data pad can be understood as a shared storage area between different processing core groups. In a possible embodiment, the many-core system also includes storage resources. Different computing tasks are assigned to different processing core groups. Based on the storage resources in the many-core system, a shared storage area can be allocated for communication data between different processing core groups.

[0091] In addition, since in the embodiments of the present disclosure, computing tasks can be split from the time and space dimensions, that is, there can be computing tasks that are parallel and serial in time, the shared storage area can also include a first shared storage area of ​​a first type and a second shared storage area of ​​a second type; wherein the first shared storage area of ​​the first type is used for communication data interaction between asynchronously executed processing core groups, and the second shared storage area of ​​the second type is used for communication data interaction between processing core groups that are serially executed in time.

[0092] For example, see Figure 4 As shown, it is a schematic diagram of the principle of allocating shared storage areas between different processing core groups in the embodiment of the present disclosure, such as Figure 4As shown, different computing tasks can be split into corresponding computing instruction sets, and different computing tasks are assigned to different processing core groups, that is, one computing instruction set can correspond to one processing core group, and multiple computing instructions in the computing instruction set are processed by the processing core group. A shared storage area is introduced between different processing core groups, and a vertical first shared storage area is inserted between asynchronously executed processing core groups. The first shared storage area can be implemented by shared storage, shared on-chip network (Network-on-Chip, NOC), ddr_save / ddr_load, etc., where the ddr_save operation mainly represents saving data from the internal memory of the many-core system to the external double data rate (Double Data Rate, DDR) memory, and the ddr_load operation mainly represents loading data from the DDR memory to the internal memory of the many-core system.

[0093] A horizontal type of second shared storage area is inserted between the processing core groups that are executed serially in time. The second shared storage area can use the static random access memory (SRAM) on the chip in the many-core system to temporarily store data, ddr_save / ddr_load and other operations, and the second shared storage area does not necessarily need to be executed serially with related computing instructions when implemented in the underlying hardware, but can be implemented using several specific data cores and executed in parallel with the processing cores, so that data storage and reading in the second shared storage area can be executed in parallel.

[0094] In the embodiment of the present disclosure, by setting the above-mentioned shared storage area, processing cores that are not adjacent in physical implementation can be divided into the same processing core group to complete the processing of computing tasks. For example, see Figure 5 As shown, it is a schematic diagram of the allocation of different processing core groups in the embodiment of the present disclosure, such as Figure 5 As shown, a flexible combination of processing cores located at any physical location can be achieved, and communication and data transmission can be carried out between different processing core groups through the allocated shared storage area without affecting the processing of computing tasks. In this way, the splitting of computing instructions of computing tasks and the allocation of processing core groups can be made more flexible, thereby more efficiently adapting to computing tasks of different sizes and improving resource utilization and performance.

[0095] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0096] In addition, the present disclosure also provides a task processing device, an electronic device, a computer-readable storage medium, and a computer program product, all of which can be used to implement any task processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0097] Figure 6 A block diagram of a task processing device provided in an embodiment of the present disclosure.

[0098] Reference Figure 6 , an embodiment of the present disclosure provides a task processing device, the task processing device comprising:

[0099] An acquisition module 61 is used for acquiring a computing task to be processed in a many-core system, wherein the many-core system includes a plurality of processing cores; the computing task is obtained in real time by computing a task processing layer above a current task processing layer in a target computing scenario, wherein the target computing scenario includes a plurality of task processing layers having a data connection relationship;

[0100] A determination module 62 is used to split the computing task into multiple computing instructions from a time dimension according to the latency requirement of the computing task and the first data volume, and determine a processing core group allocated to the computing task from a space dimension, wherein the multiple computing instructions are used to indicate the execution logic of the computing task;

[0101] The processing module 63 is used to map the computing task to the processing core group according to the computing instruction, so that the processing core group processes the computing task.

[0102] In a possible embodiment, when the computing task is split into a plurality of computing instructions from a time dimension according to the latency requirement of the computing task and the first data volume, and a processing core group assigned to the computing task is determined from a spatial dimension, the determination module 62 is used to:

[0103] Acquire a first data volume and a first duration of latency requirement of the computing task, as well as a second data volume that can be supported by the processing core and a second duration required to complete calculation of the second data volume;

[0104] According to the first data amount and the second data amount, obtaining a total number of computing instructions required for the computing task when one processing core is used;

[0105] The target number of processing cores for the computing task and the target number of computing instructions required for the computing task in a single processing core when the target number of processing cores is used are determined based on the first duration, the second duration and the total number of computing instructions.

[0106] From the time dimension, the computing task is split into multiple computing instructions according to the target number of computing instructions, and from the space dimension, a processing core group allocated to the computing task is determined, and the processing core group includes processing cores with the target number of processing cores.

[0107] In a possible embodiment, the target number of processing cores for the computing task is determined according to the first duration, the second duration, and the total number of computing instructions, and when the target number of computing instructions required for the computing task corresponding to a single processing core is used, the determination module 62 is used to:

[0108] Constructing a target cost function, wherein the target cost function represents a mapping function with the number of computing instructions required in a single processing core and the number of processing cores as variables and the cost value as a target;

[0109] Obtaining constraints of the target cost function, the constraints comprising: a product of the number of computing instructions and the second duration is less than or equal to the first duration, the number of processing cores is less than or equal to the total number of processing cores in the many-core system, and the number of computing instructions is equal to a ratio of the total number of computing instructions to the number of processing cores;

[0110] Under the condition that the constraint conditions are met, the target cost function is optimized to obtain the target number of computing instructions and the target number of processing cores of the computing task.

[0111] In a possible embodiment, when the target cost function is optimized to obtain the target number of computing instructions and the target number of processing cores for the computing task while satisfying the constraint condition, the determination module 62 is used to:

[0112] Determine a first computing type of the computing task according to the first data volume, and determine an initial number of processing cores according to the first computing type and a mapping relationship between the computing type and the number of processing cores;

[0113] Determining an initial number of computing instructions according to the total number of computing instructions and the initial number of processing cores;

[0114] Obtaining an initial cost value according to the initial number of processing cores, the initial number of computing instructions, and the target cost function;

[0115] Filtering out a first number of processing cores that is closest to the initial number of processing cores from a preset list of numbers of processing cores, and determining a first number of computing instructions according to the total number of computing instructions and the first number of processing cores;

[0116] Obtaining a first generation value according to the first number of processing cores, the first number of computing instructions, and the target cost function;

[0117] Obtaining a cost increment value according to the initial cost value and the first cost value;

[0118] When the cost increment value is less than 0 and the termination condition is satisfied, taking the first number of processing cores as the target number of processing cores and taking the first number of computing instructions as the target number of computing instructions;

[0119] When the cost increment value is greater than or equal to 0 and the list of processing core numbers has not been traversed completely, continue to determine the second number of processing cores and the second number of computing instructions for the next round based on the first number of processing cores until the end condition is met or the list of processing core numbers has been traversed completely.

[0120] In one possible embodiment, the many-core system also includes storage resources, different computing tasks are assigned to different processing core groups, and also includes an allocation module for: allocating shared storage areas for communication data between different processing core groups based on the storage resources in the many-core system.

[0121] In a possible embodiment, the shared storage area includes a first shared storage area of ​​a first type and a second shared storage area of ​​a second type;

[0122] The first shared storage area of ​​the first type is used for communication data interaction between asynchronously executed processing core groups; the second shared storage area of ​​the second type is used for communication data interaction between time-serially executed processing core groups.

[0123] In a possible embodiment, the computing task is a computing task to be processed corresponding to a network layer in a network model.

[0124] Figure 7 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0125] Reference Figure 7 An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 701 and an on-chip network 702, wherein the multiple processing cores 701 are connected to the on-chip network 702, and the on-chip network 702 is used to exchange data between the multiple processing cores and external data.

[0126] One or more instructions are stored in one or more processing cores 701 , and the one or more instructions are executed by one or more processing cores 701 , so that the one or more processing cores 701 can execute the above-mentioned task processing method.

[0127] In some embodiments, the electronic device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0128] The embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned task processing method when executed by the processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0129] The embodiment of the present disclosure also provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processing core of an electronic device, the processing core in the electronic device executes the above-mentioned task processing method.

[0130] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0131] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0132] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0133] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0134] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0135] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0136] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0137] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0138] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0139] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A task processing method, characterized in that: The method comprises: Obtaining a computing task to be processed in a many-core system, the many-core system including a plurality of processing cores; the computing task is obtained in real time by computing a task processing layer above a current task processing layer in a target computing scenario, the target computing scenario including a plurality of task processing layers having a data connection relationship; According to the latency requirement of the computing task and the first data volume, splitting the computing task into a plurality of computing instructions from a time dimension, and determining a processing core group allocated to the computing task from a space dimension, wherein the plurality of computing instructions are used to indicate the execution logic of the computing task; According to the computing instruction, the computing task is mapped to the processing core group so that the processing core group processes the computing task.

2. The method according to claim 1, characterized in that The step of splitting the computing task into a plurality of computing instructions from a time dimension according to the latency requirement of the computing task and the first data volume, and determining a processing core group allocated to the computing task from a space dimension includes: Acquire a first data volume and a first duration of latency requirement of the computing task, as well as a second data volume that can be supported by the processing core and a second duration required to complete calculation of the second data volume; According to the first data amount and the second data amount, obtaining a total number of computing instructions required for the computing task when one processing core is used; Determine, according to the first duration, the second duration, and the total number of computing instructions, a target number of processing cores for the computing task, and a target number of computing instructions required for the computing task in a single processing core when the target number of processing cores is used; From the time dimension, the computing task is split into multiple computing instructions according to the target number of computing instructions, and from the space dimension, a processing core group allocated to the computing task is determined, and the processing core group includes processing cores with the target number of processing cores.

3. The method according to claim 2, characterized in that The determining, according to the first duration, the second duration, and the total number of computing instructions, a target number of processing cores for the computing task, and a target number of computing instructions required for the computing task in a single processing core when the target number of processing cores is used, includes: Constructing a target cost function, wherein the target cost function represents a mapping function with the number of computing instructions required in a single processing core and the number of processing cores as variables and the cost value as a target; Obtaining constraints of the target cost function, the constraints comprising: a product of the number of computing instructions and the second duration is less than or equal to the first duration, the number of processing cores is less than or equal to the total number of processing cores in the many-core system, and the number of computing instructions is equal to a ratio of the total number of computing instructions to the number of processing cores; Under the condition that the constraint conditions are met, the target cost function is optimized to obtain the target number of computing instructions and the target number of processing cores of the computing task.

4. The method according to claim 3, characterized in that: The step of optimizing the target cost function to obtain a target number of computing instructions and a target number of processing cores for the computing task while satisfying the constraint condition comprises: Determine a first computing type of the computing task according to the first data volume, and determine an initial number of processing cores according to the first computing type and a mapping relationship between the computing type and the number of processing cores; Determining an initial number of computing instructions according to the total number of computing instructions and the initial number of processing cores; Obtaining an initial cost value according to the initial number of processing cores, the initial number of computing instructions, and the target cost function; Filtering out a first number of processing cores that is closest to the initial number of processing cores from a preset list of numbers of processing cores, and determining a first number of computing instructions according to the total number of computing instructions and the first number of processing cores; Obtaining a first generation value according to the first number of processing cores, the first number of computing instructions, and the target cost function; Obtaining a cost increment value according to the initial cost value and the first cost value; When the cost increment value is less than 0 and the termination condition is satisfied, taking the first number of processing cores as the target number of processing cores and taking the first number of computing instructions as the target number of computing instructions; When the cost increment value is greater than or equal to 0 and the list of processing core numbers has not been traversed completely, continue to determine the second number of processing cores and the second number of computing instructions for the next round based on the first number of processing cores until the end condition is met or the list of processing core numbers has been traversed completely.

5. The method according to any one of claims 1 to 4, characterized in that: The multi-core system also includes storage resources, and different processing core groups are allocated to different computing tasks. The method also includes: Based on the storage resources in the many-core system, a shared storage area is allocated for communication data between different processing core groups.

6. The method according to claim 5, characterized in that The shared memory area comprises a first shared memory area of ​​a first type and a second shared memory area of ​​a second type; Wherein, the first shared storage area of ​​the first type is used for communication data interaction between asynchronously executed processing core groups; The second shared storage area of ​​the second type is used for communication data interaction between processing core groups that are executed serially in time.

7. The method according to claim 1, characterized in that The computing task is a computing task to be processed corresponding to the network layer in the network model.

8. A task processing device, characterized in that: include: An acquisition module, configured to acquire a computing task to be processed in a many-core system, wherein the many-core system includes a plurality of processing cores; The computing task is obtained by real-time computing of a previous task processing layer of the current task processing layer in a target computing scenario, wherein the target computing scenario includes a plurality of task processing layers having a data connection relationship; a determination module, configured to split the computing task into a plurality of computing instructions from a time dimension according to a latency requirement of the computing task and a first data volume, and to determine a processing core group allocated to the computing task from a space dimension, wherein the plurality of computing instructions are used to indicate an execution logic of the computing task; The processing module is used to map the computing task to the processing core group according to the computing instruction, so that the processing core group processes the computing task.

9. An electronic device, characterized in that: include: Multiple processing cores; as well as An on-chip network is configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the task processing method described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the task processing method according to any one of claims 1 to 7.

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