A flash memory rereading method, device, medium and product

Abstract

The present invention discloses a flash memory rereading method, device, medium and product, relating to the field of storage technologies. This solution makes full use of the syndrome weight returned when the low-density parity-check code decoding is successful and the basic characteristics of the NAND flash memory. When the decoding fails under the default voltage axis, the initial syndrome weight in the low-density parity-check code decoder is recorded, and a target voltage axis that meets the preset requirements is first selected in the rereading voltage axis table and the rereading decoding operation is performed; if the decoding fails, the new syndrome weight returned when the decoding fails and the previously reserved initial syndrome weight are used to timely correct the error direction of the rereading attempt, determine a new target voltage axis in the rereading voltage axis table, and repeat the decoding operation until the decoding is successful, greatly reducing the rereading delay, improving the voltage axis selection efficiency and the SSD performance.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular, to a flash memory rereading method, device, medium, and product. Background Art

[0002] Due to the physical characteristics of NAND flash memory, read errors may occur during use. Solid State Drives (SSDs) usually use Low Density Parity Code (LDPC) for data protection. When the number of read error bits exceeds the LDPC decoding ability, the SSD will trigger a rereading mechanism to reduce the number of error bits by adjusting the voltage axis. NAND flash memory manufacturers provide a rereading voltage axis table, which contains multiple offset voltage axes to adapt to different physical scenarios. In the current rereading execution process, one way is to try the read voltages in the table one by one, and the other way is to record the success times of each voltage axis and perform the rereading operation in the order of success rate from large to small.

[0003] However, both of the above methods have disadvantages: trying each voltage axis one by one will consume a large amount of time delay, while the method of only recording the success times can reduce the number of rereadings, but does not fully utilize the additional return information of the decoder. When multiple voltage axes have similar success rates, the efficiency improvement is limited.

[0004] In view of the above, how to solve the problems of high time delay and low efficiency in the voltage axis selection method during the current SSD rereading process, which have an adverse impact on the SSD performance, is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The present invention provides a flash memory rereading method, device, medium, and product to at least solve the problems of high time delay and low efficiency in the voltage axis selection method during the current SSD rereading process, which have an adverse impact on the SSD performance.

[0006] The present invention provides a flash memory rereading method applied to a solid state drive; the method includes:

[0007] When decoding fails under the default voltage axis, obtain the initial syndrome weight in the current Low Density Parity Code decoder;

[0008] Determine a target voltage axis that meets the preset requirements among the voltage axes in the rereading voltage axis table;

[0009] Perform a rereading decoding operation based on the target voltage axis and determine whether the decoding is successful;

[0010] If not, obtain the new syndrome weight in the current Low Density Parity Code decoder;

[0011] Determine a new target voltage axis among the voltage axes of the reread voltage axis table according to the initial syndrome weight and the new syndrome weight, and use the new syndrome weight as the initial syndrome weight, and return to the step of performing the reread decoding operation based on the target voltage axis;

[0012] If so, end the reread process.

[0013] The present invention also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above flash memory reread methods when executing the computer program.

[0014] The present invention also provides a computer-readable storage medium, in which a computer program is stored, and wherein the computer program implements the steps of any of the above flash memory reread methods when executed by a processor.

[0015] The present invention also provides a computer program product, including a computer program, and the computer program implements the steps of any of the above flash memory reread methods when executed by a processor.

[0016] The beneficial effects of the present invention are as follows: The syndrome weight returned when the low-density parity-check code decoding is successful and the basic characteristics of the NAND flash memory are fully utilized. When the decoding fails under the default voltage axis, the initial syndrome weight in the low-density parity-check code decoder is recorded, and a target voltage axis that meets the preset requirements is first selected in the reread voltage axis table and the reread decoding operation is performed; if the decoding fails, the new syndrome weight returned when the decoding fails and the initial syndrome weight reserved before are used to timely correct the direction of the reread attempt error, determine a new target voltage axis in the reread voltage axis table, and repeat the decoding operation until the decoding is successful, greatly reducing the reread delay and improving the voltage axis selection efficiency and SSD performance.

[0017] In addition, the present invention also provides a flash memory reread device, medium and product, and the effects are the same as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings according to these drawings without creative efforts.

[0019] Figure 1 It is a flowchart of a flash memory reread method provided by an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the threshold voltage distribution provided by an embodiment of the present invention;

[0021] Figure 3 Schematic diagram of the overall flash memory reread process provided by an embodiment of the present invention;

[0022] Figure 4 Schematic diagram of a flash memory reread device provided by an embodiment of the present invention. Detailed implementation manners

[0023] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects and not to describe a specific order or sequence.

[0025] In order to enable those skilled in the art in the technical field to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0026] Currently, due to its physical characteristics, NAND flash memory is affected by factors such as erasure and writing, data retention time, and read interference during use, resulting in the threshold voltage shifting and broadening, thus causing read errors. To address this issue, SSDs usually adopt error correction codes, such as LDPC codes, to protect data. When the number of error bits during reading is within the protection range of the LDPC code, the data can be restored through a single conventional read operation. However, when the threshold voltage undergoes severe shifting and broadening, using the original read reference voltage for reading will result in an excessive number of error bits, exceeding the decoding ability of the LDPC, thus causing decoding failure.

[0027] After decoding failure, the SSD will trigger a reread mechanism to offset the threshold voltage shift by adjusting the voltage axis to reduce the number of error bits during reading. However, the reread operation usually involves a large number of read operations, which will increase the read operation latency and reduce the read performance. Therefore, efficiently selecting an appropriate read voltage axis to reduce the impact of the reread operation on performance is the main technical problem to be solved by the present invention; the application scenario of the present invention is a solid-state drive.

[0028] Figure 1The flowchart of a flash memory rereading method provided by an embodiment of the present invention. As Figure 1 shown, the method includes:

[0029] S10: When decoding fails under the default voltage axis, obtain the initial syndrome weight in the current low-density parity-check (LDPC) decoder.

[0030] Specifically, when the solid-state drive (SSD) triggers the rereading mechanism and LDPC decoding fails under the default voltage axis, in order to select a suitable voltage axis for rereading again, in this embodiment, it is first necessary to obtain the initial syndrome weight in the current LDPC decoder. The following explains LDPC and its syndrome weight:

[0031] The decoding algorithm of LDPC is implemented by performing information iteration between check nodes and variable nodes on a Tanner graph. The syndrome weight of decoding is defined as the number of check nodes that fail the check after the first iteration. In the SSD read operation, the syndrome weight is positively correlated with the raw bit error rate (RBER) of the initial data input to the decoder, that is, the higher the RBER of the read data, the greater the syndrome weight. Both the RBER and the syndrome weight can reflect the degree of deviation of the current voltage axis. Currently, when the LDPC decoder reads successfully (i.e., when LDPC decoding is successful), it will return the number of error bits in the read (the decoder will report the number of "0" errors becoming "1" and the number of "1" errors becoming "0", that is, the number of 0 misread as 1 errors and the number of 1 misread as 0 errors). In addition, regardless of whether the decoding is successful, the LDPC decoder can obtain the syndrome weight. It can be understood that the initial syndrome weight in the current LDPC decoder is the syndrome weight output by the decoder when decoding fails under the current default voltage axis.

[0032] S11: Determine a target voltage axis that meets the preset requirements among the voltage axes in the rereading voltage axis table.

[0033] It should be noted that NAND flash memory manufacturers usually provide a rereading voltage axis table (Retry Read Table, RRT). The rereading voltage axis table usually contains dozens of voltage axes corresponding to different physical scenarios such as program / erase cycles (PE), retention time (RET), and read disturb (RDD).

[0034] In this embodiment, after obtaining the initial syndrome weight, a target voltage axis that meets the preset requirements is determined among the voltage axes of the re-reading voltage axis table. In this embodiment, there is no limitation on the preset requirements. For example, it can be that the re-reading success rate of the voltage axis is the highest during the previous re-reading process, or the number of error bits is the least, etc., depending on the specific implementation situation.

[0035] S12: Perform a re-reading decoding operation based on the target voltage axis and determine whether the decoding is successful; if not, proceed to step S13; if so, end the re-reading process.

[0036] S13: Obtain the new syndrome weight in the current low-density parity-check (LDPC) decoder.

[0037] S14: Determine a new target voltage axis among the voltage axes of the re-reading voltage axis table according to the initial syndrome weight and the new syndrome weight, and use the new syndrome weight as the initial syndrome weight, then return to step S12.

[0038] Further, perform a re-reading decoding operation based on the target voltage axis and determine whether the decoding is successful. If it is confirmed that the decoding is successful, end the re-reading process and return the read data to the host. If it is confirmed that the decoding fails, it is considered that the current target voltage axis still does not meet the requirements and needs to be reselected.

[0039] Specifically, obtain the new syndrome weight in the current LDPC decoder. It can be understood that the new syndrome weight here is the syndrome weight in the LDPC decoder when the re-reading decoding fails under the target voltage axis. Finally, determine a new target voltage axis among the voltage axes of the re-reading voltage axis table according to the initial syndrome weight and the new syndrome weight, and use the new syndrome weight as the initial syndrome weight, then return to the step of performing the re-reading decoding operation based on the target voltage axis, and repeat the re-reading decoding operation until the decoding is successful.

[0040] It should be noted that in this embodiment, there is no limitation on the specific process of determining a new target voltage axis among the voltage axes of the re-reading voltage axis table according to the initial syndrome weight and the new syndrome weight.

[0041] In this embodiment, the syndrome weight returned when the low-density parity-check (LDPC) code decoding is successful and the basic characteristics of the NAND flash are fully utilized. When the decoding fails under the default voltage axis, the initial syndrome weight in the LDPC decoder is recorded. First, a target voltage axis that meets the preset requirements is selected from the re-read voltage axis table and the re-read decoding operation is performed. If the decoding fails, the new syndrome weight returned when the decoding fails and the previously reserved initial syndrome weight are used to timely correct the direction of the re-read attempt error, determine a new target voltage axis in the re-read voltage axis table, and repeat the decoding operation until the decoding is successful, greatly reducing the re-read delay and improving the voltage axis selection efficiency and SSD performance.

[0042] Based on the above embodiment, in some embodiments, determining a target voltage axis that meets the preset requirements among the voltage axes of the re-read voltage axis table includes:

[0043] S111: According to the pre-constructed voltage axis weight table, determine the target voltage axis with the smallest corresponding number of error bits and without performing the re-read operation among the voltage axes of the re-read voltage axis table;

[0044] Among them, the voltage axis weight table includes the number of error bits of each voltage axis after reading, and the offset direction relative to the ideal voltage axis.

[0045] In order to more quickly and accurately select a suitable target voltage axis, the present invention utilizes the return value of the LDPC decoder and combines the NAND characteristics to additionally provide a voltage axis weight table RRT_weight in the SSD main control outside the RRT.

[0046] The voltage axis weight table includes the number of error bits of each voltage axis in the RRT after reading, and the offset direction relative to the ideal voltage axis. That is to say, the size of the voltage axis weight table RRT_weight is the same as the number of voltage axes in the RRT. In this embodiment, in order to select the target voltage axis, mainly according to the pre-constructed voltage axis weight table RRT_weight, determine the target voltage axis with the smallest corresponding number of error bits and without performing the re-read operation among the voltage axes of the re-read voltage axis table RRT. In this way, a suitable voltage axis can be selected more quickly and accurately. Since the target voltage axis has fewer corresponding error bits than other voltage axes and has not performed the re-read operation, the re-read success rate of the target voltage axis is higher than that of other voltage axes. The construction process of the voltage axis weight table RRT_weight will be described in detail below with specific embodiments:

[0047] The construction process of the voltage axis weight table includes:

[0048] S112: Set the initial weight value of the voltage axis.

[0049] Among them, the size of the initialized weight value is 2 bytes.

[0050] S113: When decoding is successful under the voltage axis, correspondingly obtain the number of original error bits and the number of 1-to-0 errors output by the low-density parity-check (LDPC) decoder.

[0051] S114: Determine the number of 0-to-1 errors according to the number of original error bits and the number of 1-to-0 errors.

[0052] S115: Determine whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors; if so, go to step S116; if not, go to step S117.

[0053] S116: Record the highest bit of the initialized weight value of the voltage axis as 1, and use the remaining bits to record the number of original error bits to generate the weight value of the voltage axis.

[0054] S117: Record the highest bit of the initialized weight value of the voltage axis as 0, and use the remaining bits to record the number of original error bits to generate the weight value of the voltage axis.

[0055] Specifically, in the SSD, only when the read is successful, the LDPC decoder will return the and . It should be noted that is the number of original error bits, is the number of "1" errors reported by the decoder as "0", that is, the number of 1-to-0 errors. Also, because = + , is the number of "0" errors reported by the decoder as "1", that is, the number of 0-to-1 errors, so the number of 0-to-1 errors can be directly calculated from the number of 1-to-0 errors and the number of original error bits.

[0056] At the same time, the number of original error bits can be used as an evaluation criterion for whether the current voltage axis is closer to the ideal voltage axis: The smaller it is, the closer the current voltage axis is to the ideal voltage axis. In addition, and The difference between them can reflect the offset direction of the voltage axis. Specifically as follows:

[0057] Figure 2 This is the schematic diagram of the threshold voltage distribution provided by the embodiment of the present invention. As Figure 2 shown, among the two peaks of the threshold voltage distribution, the left side is the "1" peak and the right side is the "0" peak. RL is the ideal voltage axis of the current threshold voltage distribution. If the voltage axis RL on the left side of the ideal voltage axis is used for reading, then there will be Greater than , as shown by the two shaded areas in the figure, RL The area of the shaded area on the right represents , and the shaded area on the left represents . Similarly, the voltage axis that is to the right of the ideal voltage axis is RL , and there will be Greater than situation.

[0058] Therefore, based on the above principle, a voltage axis weight table RRT_weight is maintained for each flash page in the SSD controller. The weight of each voltage axis includes the number of error bits after reading for each voltage axis and the offset direction relative to the ideal voltage axis. First, set the initial weight value of the voltage axis, specifically set to 0xFFFF, and the size of the initial weight value is 2 bytes. When decoding is successful under the voltage axis, obtain the original number of error bits output by the LDPC decoder and the number of 1 mistaken for 0 errors , and according to the original number of error bits and the number of 1 mistaken for 0 errors , determine the number of 0 mistaken for 1 errors . Determine whether the number of 0 mistaken for 1 errors is not less than the number of 1 mistaken for 0 errors, that is, determine whether .

[0059] If it is confirmed that the number of 0 mistaken for 1 errors is not less than the number of 1 mistaken for 0 errors, record the highest bit of the initial weight value of the voltage axis as 1, and the remaining bits are used to record the original number of error bits (that is, represent the weight amplitude) to generate the weight value of the voltage axis. If it is confirmed that the number of 0 mistaken for 1 errors is less than the number of 1 mistaken for 0 errors, record the highest bit of the initial weight value of the voltage axis as 0, and the remaining bits are used to record the original number of error bits (that is, represent the weight amplitude) to generate the weight value of the voltage axis. In summary, the weight of the i-th voltage axis RRT[i] in RRT is represented by two-byte RRT_weight[i], the highest bit is used to record the sign bit (1 or 0), and the remaining bits are used to represent the weight amplitude.

[0060] It should also be noted that since the read operation is performed in units of flash pages, the dimension of the voltage axis weight table is the same as the number of word lines and flash pages. In other words, for single-level cell (SLC) storage, there is only one flash page in a word line, so only one set of voltage axis weight tables needs to be maintained for a set of voltage axes. If it is triple-level cell (TLC) flash, there are three flash pages in a word line, and then a voltage axis weight table needs to be maintained for the lower page, middle page, and upper page of each set of voltage axes respectively.

[0061] In this embodiment, the weights of all voltage axes in the RRT table are constructed by using the original error bit number and the 1-to-0 error number of the current read operation returned by LDPC when the SSD read is successful. The weight amplitude is used to identify the distance from the ideal voltage axis, and the sign bit identifies the direction of the current voltage axis from the ideal voltage axis, so as to quickly and accurately select the entry voltage axis for the reread operation when the reread operation is triggered.

[0062] Based on the above embodiment, in some embodiments, according to the initial syndrome weight and the new syndrome weight, determining a new target voltage axis among the voltage axes of the reread voltage axis table includes:

[0063] S141: Determine the first difference between the new syndrome weight and the initial syndrome weight.

[0064] S142: Determine the weight value of the target voltage axis according to the voltage axis weight table.

[0065] S143: According to the first difference and the weight value of the target voltage axis, determine the index of the new target voltage axis corresponding to the target voltage axis according to the pre-constructed reread index table.

[0066] Among them, the reread index table contains the indexes corresponding to the voltage axes in the reread voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the other voltage axes in the reread voltage axis table.

[0067] S144: Determine the new target voltage axis among the voltage axes of the reread voltage axis table according to the index.

[0068] In order to determine the new target voltage axis among the voltage axes of the RRT, in this embodiment, the first difference between the new syndrome weight and the initial syndrome weight is specifically determined, and the weight value of the target voltage axis is determined according to the voltage axis weight table RRT_weight. Further, according to the first difference and the weight value of the target voltage axis, the index of the new target voltage axis corresponding to the target voltage axis is determined according to the pre-constructed reread index table.

[0069] It should be noted that the re - read index table contains the indexes corresponding to each voltage axis in the re - read voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the remaining voltage axes in the re - read voltage axis table. Specifically, the re - read index table actually combines the characteristics of the NAND threshold voltage distribution, calculates and selects two new target voltage axes in the 0 and 1 directions for subsequent re - reading for each different flash page of each voltage axis according to the voltage axis distance definition, thereby optimizing the operation of traversing the RRT in the original re - read operation and reducing the re - read time delay. The construction process of the re - read index table is described in detail below:

[0070] The construction process of the re - read index table includes:

[0071] S145: Determine the distance values between each voltage axis in the re - read voltage axis table and the remaining voltage axes.

[0072] S146: Sort the distance values corresponding to each voltage axis respectively to obtain the distance queue corresponding to each voltage axis.

[0073] S147: Determine the index corresponding to each voltage axis according to each distance queue.

[0074] Specifically, the present invention defines the distance between any two sets of voltage axes for each flash page. For example, the voltage axis Vth1 is , and the voltage axis Vth2 is . m represents the number of reference voltages of the current flash page. For example, in a common TLC NAND, there are 8 threshold voltage states in total, and there are 7 read reference voltage axes. The number of voltage axes of three flash pages is 2, 3, and 2 respectively. Define the distance between the two sets of voltage axes Vth1 and Vth2 as:

[0075] ;

[0076] Among them, is the absolute distance moved from to , is whether the movement from to is a left - hand movement or a right - hand movement; the sign(x) function is a sign function, that is, when x > 0, sign = 1, and when x < 0, sign(x)=0. represents whether increases or decreases during the right - hand movement of the i - th voltage axis; if i is odd, the right - hand movement is a movement towards the "0" peak, decreases; if i is even, the right - hand movement is a movement towards the "1" peak, increases.

[0077] Therefore, using To mark the case of moving from the voltage axis Vth1 to Vth2, the change. When is negative, it can be considered that when moving from Vth1 to Vth2, the number of "1" errors decreases; when is positive, it can be considered that when moving from Vth1 to Vth2, the number of "1" errors increases.

[0078] In summary, using the above distance formula, the distance between each voltage axis in the reread voltage axis table RRT and the remaining voltage axes in the table can be calculated: If the size of the RRT table is N, the distance between the i-th group of voltage axes RRT[i] and the remaining voltage axes in the table is as follows:

[0079] ;

[0080] Furthermore, the N - 1 distance values corresponding to each voltage axis are sorted respectively to obtain the distance queue corresponding to each voltage axis. Finally, the index corresponding to each voltage axis is determined according to each distance queue. In this embodiment, there is no limitation on the specific method of determining the index corresponding to each voltage axis according to each distance queue. In this embodiment, by constructing a reread index table, combining the NAND threshold voltage distribution characteristics, for each voltage axis of different flash memory pages, according to the voltage axis distance definition, the new target voltage axes in the two directions of 0 and 1 for subsequent rereading are calculated and selected, thereby optimizing the operation of traversing the RRT in the original reread operation and reducing the reread delay.

[0081] It should be noted that in the present invention, the index corresponding to the voltage axis and the index of the voltage axis are two different concepts. Taking voltage axis A and voltage axis B as examples, voltage axis A and voltage axis B each have an index. Through the index of voltage axis A, voltage axis A can be queried, and through the index of voltage axis B, voltage axis B can be queried. In this case, the corresponding voltage axis is found through the index itself. When the index corresponding to voltage axis A is the index of voltage axis B, it means that there is a corresponding relationship between the index of voltage axis B and voltage axis A. That is to say, through the index of voltage axis B corresponding to voltage axis A, voltage axis B can be queried. In this case, another voltage axis is queried through the index corresponding to one voltage axis.

[0082] Based on the above embodiments, in some embodiments, sorting the distance values corresponding to each voltage axis respectively to obtain the distance queue corresponding to each voltage axis includes:

[0083] S151: Among the multiple distance values corresponding to the voltage axis, sort the distance values with negative values in ascending order of the corresponding absolute values to generate the first distance queue corresponding to the voltage axis.

[0084] S152: Among the multiple distance values corresponding to the voltage axis, sort the distance values with positive numerical values in ascending order of their corresponding absolute values to generate a second distance queue corresponding to the voltage axis.

[0085] In order to obtain the distance queues corresponding to each voltage axis, in this embodiment, specifically among the N - 1 distance values corresponding to the voltage axis, sort the distance values with negative numerical values in ascending order of their corresponding absolute values to generate a first distance queue corresponding to the voltage axis; among the N - 1 distance values corresponding to the voltage axis, sort the distance values with positive numerical values in ascending order of their corresponding absolute values to generate a second distance queue corresponding to the voltage axis. Since the distance values in the first distance queue and the second distance queue are negative and positive respectively, representing different moving directions of the voltage axis, the index of the new target voltage axis can be determined more accurately based on the first distance queue and the second distance queue.

[0086] Based on the above embodiments, in some embodiments, determining the index corresponding to each voltage axis according to each distance queue includes:

[0087] S153: Determine the first two distance values in the first distance queue to obtain a first distance value and a second distance value.

[0088] Among them, the absolute value of the first distance value is less than the absolute value of the second distance value.

[0089] S154: Determine the first two distance values in the second distance queue to obtain a third distance value and a fourth distance value.

[0090] Among them, the absolute value of the third distance value is less than the absolute value of the fourth distance value.

[0091] S155: Respectively determine a first candidate voltage axis corresponding to the first distance value, a second candidate voltage axis corresponding to the second distance value, a third candidate voltage axis corresponding to the third distance value, and a fourth candidate voltage axis corresponding to the fourth distance value.

[0092] S156: Respectively determine the index of the first candidate voltage axis, the index of the second candidate voltage axis, the index of the third candidate voltage axis, and the index of the fourth candidate voltage axis as the index corresponding to the voltage axis.

[0093] After obtaining the first distance queue and the second distance queue of the voltage axis, in order to determine the index corresponding to the voltage axis, specifically determine the first two distance values in the first distance queue to obtain a first distance value and a second distance value, and the absolute value of the first distance value is less than the absolute value of the second distance value. It can be understood that the first distance value and the second distance value are the two distance values with the smallest absolute values in the first distance queue. Determine the first two distance values in the second distance queue to obtain a third distance value and a fourth distance value, and the absolute value of the third distance value is less than the absolute value of the fourth distance value. It can be understood that the third distance value and the fourth distance value are the two distance values with the smallest absolute values in the second distance queue.

[0094] Further, respectively determine a first candidate voltage axis corresponding to the first distance value, a second candidate voltage axis corresponding to the second distance value, a third candidate voltage axis corresponding to the third distance value, and a fourth candidate voltage axis corresponding to the fourth distance value. For example, if the first distance value of voltage axis A is the distance value between voltage axis A and voltage axis 1, the second distance value of voltage axis A is the distance value between voltage axis A and voltage axis 2, the third distance value of voltage axis A is the distance value between voltage axis A and voltage axis 3, and the fourth distance value of voltage axis A is the distance value between voltage axis A and voltage axis 4, then the first candidate voltage axis corresponding to the first distance value of voltage axis A, the second candidate voltage axis corresponding to the second distance value, the third candidate voltage axis corresponding to the third distance value, and the fourth candidate voltage axis corresponding to the fourth distance value are voltage axis 1, voltage axis 2, voltage axis 3, and voltage axis 4 respectively.

[0095] Finally, respectively take the index of the first candidate voltage axis , the index of the second candidate voltage axis , the index of the third candidate voltage axis and the index of the fourth candidate voltage axis as the index corresponding to the voltage axis . Taking the above content as an example, take the index of voltage axis 1, the index of voltage axis 2, the index of voltage axis 3, and the index of voltage axis 4 as the index corresponding to voltage axis A. The index corresponding to each voltage axis together constitutes the resampling index table.

[0096] In this way, the determination of the index corresponding to each voltage axis in the resampling index table is realized. Two groups of indexes are additionally recorded for each voltage axis in the resampling index table, and the offline calculation does not increase the complexity and latency in actual use, improving the search efficiency of the new target voltage axis.

[0097] It should also be noted that since the read operation is performed in units of flash pages, the dimension of the reread index table is the same as the number of word lines and flash pages. In other words, for SLC, there is only one flash page in a word line, so only one reread index table needs to be maintained for a group of voltage axes. If it is TLC flash, there are three flash pages in a word line, and a reread index table needs to be maintained for the Lower Page, Middle Page, and Upper Page of each group of voltage axes respectively.

[0098] Based on the above embodiments, in some embodiments, according to the first difference and the weight value of the target voltage axis, determining the index of the new target voltage axis corresponding to the target voltage axis according to the pre-constructed reread index table includes:

[0099] S161: Determine the second difference between the initial syndrome weight and the corresponding previous syndrome weight.

[0100] S162: Judge whether both the first difference and the second difference are greater than 0; if not, go to step S163; if so, go to step S164.

[0101] S163: Determine the index of the new target voltage axis in the reread index table according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis.

[0102] S164: Re-determine the new target voltage axis with the smallest corresponding number of error bits and without performing the reread operation among the voltage axes of the reread voltage axis table according to the voltage axis weight table, and enter step S12.

[0103] To determine the index of the new target voltage axis, when the k-th reread is performed and the decoding fails when using the target voltage axis as RRk, the new syndrome weight corresponding to the target voltage axis RRk at this time is , and the corresponding initial syndrome weight is , then the first difference is ; the initial syndrome weight the corresponding previous syndrome weight is , then the second difference between the initial syndrome weight and the corresponding previous syndrome weight is . It should be noted that in this embodiment, there is no limit to the size of k. For example, k can be set to 3.

[0104] Further determine whether both the first difference and the second difference are greater than 0. If it is confirmed that both the first difference and the second difference are greater than 0, it indicates that the syndrome weight increases twice in a row, corresponding to an increase in RBER, which means that the current moving direction of the voltage axis is incorrect. Then, when rereading at the (k + 1)-th time, it is necessary to re-determine, according to the voltage axis weight table, a new target voltage axis with the smallest corresponding number of error bits among the voltage axes in the rereading voltage axis table and that has not performed the rereading operation, timely correct the incorrect direction of the rereading attempt, and try the rereading decoding operation again to reduce the number of rereading times and latency. If it is confirmed that the first difference and / or the second difference are not greater than 0, determine the index of the new target voltage axis in the rereading index table according to the usage of the voltage axes in the rereading voltage axis table and the weight value of the target voltage axis. The following is a specific description:

[0105] Based on the above embodiments, in some embodiments, determining the index of the new target voltage axis in the rereading index table according to the usage of the voltage axes in the rereading voltage axis table and the weight value of the target voltage axis includes:

[0106] S165: When the highest bit of the weight value of the target voltage axis is 0, determine whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading.

[0107] S166: If it is confirmed that neither the first candidate voltage axis nor the second candidate voltage axis has been used in the previous rereading, determine the index of the first candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis.

[0108] S167: If it is confirmed that the first candidate voltage axis has been used in the previous rereading and the second candidate voltage axis has not been used in the previous rereading, determine the index of the second candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis.

[0109] S168: When the highest bit of the weight value of the target voltage axis is 1, determine whether the third candidate voltage axis and the fourth candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading.

[0110] S169: If it is confirmed that neither the third candidate voltage axis nor the fourth candidate voltage axis has been used in the previous rereading, determine the index of the third candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis.

[0111] S170: If it is confirmed that the third candidate voltage axis has been used in the previous rereading and the fourth candidate voltage axis has not been used in the previous rereading, determine the index of the fourth candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis.

[0112] It can be understood that the index corresponding to the target voltage axis RRk is , which are respectively the indices of the first candidate voltage axis corresponding to the target voltage axis RRk , the index of the second candidate voltage axis , the index of the third candidate voltage axis and the index of the fourth candidate voltage axis . Therefore, when the most significant bit of the weight value of the target voltage axis RRk is 0, it indicates that the current voltage axis needs to shift towards the "0" peak to approach the ideal voltage axis, and correspondingly, a new target voltage axis needs to be selected from the first candidate voltage axis and the second candidate voltage axis.

[0113] Specifically, it is determined whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in the previous re-reading. If it is confirmed that neither the first candidate voltage axis nor the second candidate voltage axis has been used in the previous re-reading, since the first candidate voltage axis is closer to the target voltage axis, the index of the first candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis. If it is confirmed that the first candidate voltage axis has been used in the previous re-reading and the second candidate voltage axis has not been used in the previous re-reading, then the index of the second candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis, that is, the second candidate voltage axis is used as the voltage axis for the next re-reading operation, and this operation avoids switching back and forth between the two adjacent voltage axes that are closest.

[0114] When the most significant bit of the weight value of the target voltage axis RRk is 1, it indicates that the current voltage axis needs to shift towards the "1" peak direction to approach the ideal voltage axis, and correspondingly, a new target voltage axis needs to be selected from the third candidate voltage axis and the fourth candidate voltage axis.

[0115] Specifically, it is determined whether the third candidate voltage axis and the fourth candidate voltage axis corresponding to the target voltage axis have been used in the previous re-reading. If it is confirmed that neither the third candidate voltage axis nor the fourth candidate voltage axis has been used in the previous re-reading, since the third candidate voltage axis is closer to the target voltage axis, the index of the third candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis. If it is confirmed that the third candidate voltage axis has been used in the previous re-reading and the fourth candidate voltage axis has not been used in the previous re-reading, then the index of the fourth candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis, that is, the fourth candidate voltage axis is used as the voltage axis for the next re-reading operation, and this operation avoids switching back and forth between the two adjacent voltage axes that are closest.

[0116] In summary, in this embodiment, by querying the weight sign bit of the current target voltage axis, determining the voltage axis index of the next group to perform the rereading operation in the rereading index table according to the sign bit, and selecting the corresponding voltage axis to perform the rereading operation in the next step, the fine-tuning correction of the rereading direction is realized, the rereading delay is reduced, and the rereading efficiency is improved.

[0117] Based on the above embodiment, in some embodiments, if it is confirmed that both the first candidate voltage axis and the second candidate voltage axis have been used in the previous rereading, or it is confirmed that both the third candidate voltage axis and the fourth candidate voltage axis have been used in the previous rereading, it further includes:

[0118] S171: Re-determine, according to the voltage axis weight table, the new target voltage axis with the smallest corresponding number of error bits and not yet performing the rereading operation among the voltage axes in the rereading voltage axis table, and enter step S12.

[0119] In specific implementation, if both the first candidate voltage axis and the second candidate voltage axis have been used in the previous rereading, or both the third candidate voltage axis and the fourth candidate voltage axis have been used in the previous rereading, it means that the first candidate voltage axis and the second candidate voltage axis, as well as the third candidate voltage axis and the fourth candidate voltage axis, are no longer suitable as new target voltage axes to participate in the next rereading operation. At this time, it is necessary to re-determine, according to the voltage axis weight table, the new target voltage axis with the smallest corresponding number of error bits and not yet performing the rereading operation among the voltage axes in the rereading voltage axis table, so as to timely correct the rereading voltage axis entry, try the rereading decoding operation again, and reduce the number of rereadings and the delay.

[0120] Based on the above embodiment, in some embodiments, if it is confirmed that the decoding is successful, it further includes:

[0121] S172: Obtain the new original number of error bits and the new number of 1-to-0 errors returned by the low-density parity-check code decoder.

[0122] S173: Determine the new number of 0-to-1 errors according to the new original number of error bits and the new number of 1-to-0 errors.

[0123] S174: When the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis, update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table with the new original number of error bits.

[0124] S175: When the new number of 0-to-1 errors is not less than the new number of 1-to-0 errors, record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 1.

[0125] S176: When the new number of 0-to-1 errors is less than the new number of 1-to-0 errors, record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 0.

[0126] In a specific implementation, when the decoding of the target voltage axis is successful, in order to ensure the accuracy of the voltage axis weight table and facilitate the selection of the voltage axis for the next rereading, it is also necessary to update the voltage axis weight table.

[0127] Specifically, obtain the new number of original error bits and the new number of 1-to-0 errors returned by the LDPC decoder. Determine the new number of 0-to-1 errors based on the new number of original error bits and the new number of 1-to-0 errors. When the new number of original error bits is not less than the number of original error bits corresponding to the target voltage axis, update the number of original error bits corresponding to the target voltage axis in the voltage axis weight table, that is, update the weight amplitude corresponding to the target voltage axis in the voltage axis weight table to the new number of original error bits; otherwise, retain the original weight amplitude corresponding to the target voltage axis in the voltage axis weight table.

[0128] When the new number of 0-to-1 errors is not less than the new number of 1-to-0 errors, record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 1. When the new number of 0-to-1 errors is less than the new number of 1-to-0 errors, record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 0, thereby realizing the update of the weight sign bit of the target voltage axis, ensuring the accuracy of the voltage axis weight table, and facilitating the selection of the voltage axis for the next rereading.

[0129] Based on the above embodiments, in some embodiments, if it is confirmed that the decoding fails, it further includes:

[0130] S177: Determine whether each voltage axis in the rereading voltage axis table has performed a rereading operation; if so, end the rereading process and execute the read recovery process; if not, enter step S13.

[0131] In a specific implementation, if it is confirmed that the decoding fails, it can be further determined whether each voltage axis in the rereading voltage axis table has performed a rereading operation. If it is confirmed that each voltage axis in the rereading voltage axis table has performed a rereading operation, it is considered that all voltage axes do not support normal rereading decoding, directly end the rereading process, and execute the read recovery process. If it is confirmed that there is a voltage axis in the rereading voltage axis table that has not performed a rereading operation, enter step S13 to perform a new target voltage axis selection and rereading process. This avoids meaningless voltage axis selection and rereading from wasting system resources.

[0132] In addition, if data cannot be successfully read after traversing all voltage axes in the RRT, and it is determined that the error is caused by physical layer factors (such as read interference accumulation or temperature drift), physical layer data recovery operations need to be performed. For the read interference problem, data can be migrated to a new storage block and the original block can be erased to reset the threshold voltage distribution; for the threshold voltage shift caused by temperature, the temperature of the NAND chip can be actively adjusted (such as heating to a stable operating condition) and combined with a cross-temperature calibration algorithm to compensate for the voltage parameter deviation caused by environmental changes, thereby restoring readability. These two types of methods alleviate the irreversible deterioration of storage cell characteristics at the physical level through the cooperation of hardware intervention and algorithms.

[0133] Figure 3 This is a schematic diagram of the overall flash memory rereading process provided by the embodiments of the present invention. As Figure 3 shown, the present invention utilizes the return value of the LDPC decoder and combines the NAND characteristics to additionally maintain two tables in the main controller for the RRT: the voltage axis weight table is used to select the entry voltage axis for the rereading operation, and the rereading index table is used to select the index of the voltage axis for the next operation, thereby optimizing the operation of traversing the RRT in the original rereading operation and optimizing the rereading delay. Among the two additional tables, the rereading index table additionally records two groups of indexes for each voltage axis, and the offline calculation does not increase the complexity and delay in actual use; the size of the voltage axis weight table is the same as that of the RRT, and only comparison and update are performed after each read. Compared with the traditional scheme, this scheme only consumes very little memory and computational complexity and can reduce the delay of the rereading operation.

[0134] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0135] Figure 4 This is a schematic diagram of a flash memory rereading device provided by the embodiments of the present invention. The device is applied to a solid-state drive; as Figure 4 shown, the device includes:

[0136] A first acquisition module 10, configured to acquire the initial syndrome weight in the current low-density parity-check code decoder when decoding fails on the default voltage axis.

[0137] A first determination module 11, configured to determine a target voltage axis that meets the preset requirements among the voltage axes of the rereading voltage axis table.

[0138] A rereading decoding and judgment module 12, configured to perform a rereading decoding operation based on the target voltage axis and judge whether the decoding is successful; if so, end the rereading process. If not, trigger a second acquisition module 13.

[0139] The second acquisition module 13 is configured to acquire the new syndrome weight in the current low-density parity-check (LDPC) decoder.

[0140] The second determination module 14 is configured to determine a new target voltage axis among the voltage axes of the reread voltage axis table according to the initial syndrome weight and the new syndrome weight, use the new syndrome weight as the initial syndrome weight, and trigger the reread decoding and determination module 12.

[0141] In some embodiments, the first determination module 11 includes:

[0142] The first determination sub-module is configured to determine, according to a pre-constructed voltage axis weight table, a target voltage axis with the minimum corresponding number of error bits and without performing a reread operation among the voltage axes of the reread voltage axis table;

[0143] The voltage axis weight table includes the number of error bits after reading for each voltage axis and the offset direction relative to the ideal voltage axis.

[0144] In some embodiments, the construction process of the voltage axis weight table includes: setting an initial weight value for the voltage axis; the size of the initial weight value is 2 bytes; when decoding is successful under the voltage axis, correspondingly acquire the original number of error bits output by the LDPC decoder and the number of 1-to-0 errors; determine the number of 0-to-1 errors according to the original number of error bits and the number of 1-to-0 errors; determine whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors; if so, record the highest bit of the initial weight value of the voltage axis as 1, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis; if not, record the highest bit of the initial weight value of the voltage axis as 0, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis.

[0145] In some embodiments, the second determination module 14 includes:

[0146] The first determination sub-module is configured to determine a first difference between the new syndrome weight and the initial syndrome weight;

[0147] The second determination sub-module is configured to determine the weight value of the target voltage axis according to the voltage axis weight table;

[0148] The third determination sub-module is configured to determine the index of the new target voltage axis corresponding to the target voltage axis according to the first difference and the weight value of the target voltage axis according to a pre-constructed reread index table; the reread index table includes the indexes corresponding to the voltage axes in the reread voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the other voltage axes in the reread voltage axis table;

[0149] A fourth determination sub-module, configured to determine a new target voltage axis from each voltage axis of the re-reading voltage axis table according to the index.

[0150] In some embodiments, the construction process of the re-reading index table includes: determining the distance values between each voltage axis in the re-reading voltage axis table and the remaining voltage axes; sorting the distance values corresponding to each voltage axis respectively to obtain a distance queue corresponding to each voltage axis; and determining the index corresponding to each voltage axis according to each distance queue.

[0151] In some embodiments, sorting the distance values corresponding to each voltage axis respectively to obtain a distance queue corresponding to each voltage axis includes: among the multiple distance values corresponding to a voltage axis, sorting the negative distance values in ascending order of the corresponding absolute values to generate a first distance queue corresponding to the voltage axis; and among the multiple distance values corresponding to a voltage axis, sorting the positive distance values in ascending order of the corresponding absolute values to generate a second distance queue corresponding to the voltage axis.

[0152] In some embodiments, determining the index corresponding to each voltage axis according to each distance queue includes: determining the first two distance values in the first distance queue to obtain a first distance value and a second distance value, where the absolute value of the first distance value is less than the absolute value of the second distance value; determining the first two distance values in the second distance queue to obtain a third distance value and a fourth distance value, where the absolute value of the third distance value is less than the absolute value of the fourth distance value; respectively determining a first candidate voltage axis corresponding to the first distance value, a second candidate voltage axis corresponding to the second distance value, a third candidate voltage axis corresponding to the third distance value, and a fourth candidate voltage axis corresponding to the fourth distance value; and respectively determining the index of the first candidate voltage axis, the index of the second candidate voltage axis, the index of the third candidate voltage axis, and the index of the fourth candidate voltage axis as the index corresponding to the voltage axis.

[0153] In some embodiments, the third determination sub-module includes:

[0154] A fifth determination sub-module, configured to determine a second difference between the initial check sub-weight and the corresponding previous check sub-weight;

[0155] A first judgment sub-module, configured to judge whether both the first difference and the second difference are greater than 0; if not, trigger a sixth determination sub-module; if so, trigger a seventh determination sub-module;

[0156] A sixth determination sub-module, configured to determine the index of the new target voltage axis in the re-reading index table according to the usage of the voltage axis in the re-reading voltage axis table and the weight value of the target voltage axis;

[0157] The seventh determination sub-module is configured to re-determine, according to the voltage axis weight table, a new target voltage axis with the smallest corresponding number of error bits among the voltage axes in the re-read voltage axis table and that has not performed the re-read operation, and trigger the re-read decoding and judgment module.

[0158] In some embodiments, the sixth determination sub-module includes:

[0159] The second judgment sub-module is configured to, when the highest bit of the weight value of the target voltage axis is 0, judge whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in the previous re-read; if it is confirmed that neither the first candidate voltage axis nor the second candidate voltage axis has been used in the previous re-read, determine the index of the first candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis; if it is confirmed that the first candidate voltage axis has been used in the previous re-read and the second candidate voltage axis has not been used in the previous re-read, determine the index of the second candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis.

[0160] The third judgment sub-module is configured to, when the highest bit of the weight value of the target voltage axis is 1, judge whether the third candidate voltage axis and the fourth candidate voltage axis corresponding to the target voltage axis have been used in the previous re-read; if it is confirmed that neither the third candidate voltage axis nor the fourth candidate voltage axis has been used in the previous re-read, determine the index of the third candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis; if it is confirmed that the third candidate voltage axis has been used in the previous re-read and the fourth candidate voltage axis has not been used in the previous re-read, determine the index of the fourth candidate voltage axis corresponding to the target voltage axis as the index of the new target voltage axis.

[0161] In some embodiments, it further includes:

[0162] The selection module is configured to re-determine, according to the voltage axis weight table, a new target voltage axis with the smallest corresponding number of error bits among the voltage axes in the re-read voltage axis table and that has not performed the re-read operation, and trigger the re-read decoding and judgment module.

[0163] In some embodiments, it further includes:

[0164] The second acquisition sub-module is configured to acquire the new original number of error bits and the new number of 1-to-0 errors returned by the low-density parity-check code decoder.

[0165] The seventh determination sub-module is configured to determine the new number of 0-to-1 errors according to the new original number of error bits and the new number of 1-to-0 errors.

[0166] The first update sub-module is configured to, when the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis, update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table with the new original number of error bits.

[0167] A second update sub-module, configured to record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 1 when the number of new 0-to-1 errors is not less than the number of new 1-to-0 errors;

[0168] A third update sub-module, configured to record the highest bit of the weight value of the target voltage axis in the voltage axis weight table as 0 when the number of new 0-to-1 errors is less than the number of new 1-to-0 errors.

[0169] In some embodiments, it further includes:

[0170] A fourth determination sub-module, configured to determine whether each voltage axis in the re-read voltage axis table has performed a re-read operation; if so, end the re-read process and execute the read recovery process; if not, trigger the second acquisition module 13.

[0171] For the description of the features in the corresponding embodiments of the flash memory re-read device, reference can be made to the relevant descriptions in the corresponding embodiments of the flash memory re-read method, which will not be elaborated here one by one.

[0172] An embodiment of the present invention further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the flash memory re-read method.

[0173] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the flash memory re-read method when running.

[0174] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk, or optical disc, etc., various media that can store computer programs.

[0175] An embodiment of the present invention further provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the flash memory re-read method.

[0176] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the flash memory re-read method.

[0177] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0178] The above has introduced in detail a flash memory rereading method, device, medium, and product provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A flash memory rereading method, characterized in that: Applied to a solid state hard disk; the method comprises: When decoding fails under the default voltage axis, an initial syndrome weight in the current low-density parity check code decoder is obtained; wherein the syndrome weight is the number of check nodes that fail to pass the check after the first iteration; Determining a target voltage axis that meets preset requirements among the voltage axes in the re-read voltage axis table; Performing a reread decoding operation based on the target voltage axis and determining whether the decoding is successful; If not, obtaining a new syndrome weight in the current low-density parity-check code decoder; Determine a new target voltage axis in each voltage axis of the reread voltage axis table according to the initial syndrome weight and the new syndrome weight, use the new syndrome weight as the initial syndrome weight, and return to the step of performing a reread decoding operation based on the target voltage axis; If yes, then end the re-reading process; Wherein, determining a new target voltage axis in each voltage axis of the re-read voltage axis table according to the initial syndrome weight and the new syndrome weight includes: determining a first difference between the new syndrome weight and the initial syndrome weight; Determining the weight value of the target voltage axis according to a voltage axis weight table; wherein the voltage axis weight table includes the number of error bits of each voltage axis after reading, and the offset direction relative to the ideal voltage axis; According to the first difference and the weight value of the target voltage axis, the index of the new target voltage axis corresponding to the target voltage axis is determined according to a pre-constructed rereading index table; wherein the rereading index table contains the index corresponding to each voltage axis in the rereading voltage axis table; the index is determined according to the distance value between the corresponding voltage axis and the remaining voltage axes in the rereading voltage axis table; The new target voltage axis is determined in each voltage axis of the re-read voltage axis table according to the index.

2. The flash memory rereading method according to claim 1, characterized in that: Determine a target voltage axis that meets preset requirements in each voltage axis of the re-read voltage axis table, including: According to a pre-constructed voltage axis weight table, determining the target voltage axis having the smallest corresponding error bit number and not performing a reread operation among the voltage axes in the reread voltage axis table; The voltage axis weight table includes the number of error bits of each voltage axis after reading, and the offset direction relative to the ideal voltage axis.

3. The flash memory rereading method according to claim 2, characterized in that: The process of constructing the voltage axis weight table includes: Setting an initialization weight value of the voltage axis; wherein the size of the initialization weight value is 2 bytes; When decoding is successful under the voltage axis, the original number of error bits and the number of 1-to-0 errors output by the low-density parity check code decoder are obtained accordingly; Determine the number of 0-error-to-1 errors according to the original number of error bits and the number of 1-error-to-0 errors; Determine whether the number of 0-to-1 errors is not less than the number of 1-to-0 errors; If yes, the highest bit of the initialization weight value of the voltage axis is recorded as 1, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis; If not, the highest bit of the initialized weight value of the voltage axis is recorded as 0, and the remaining bits are used to record the original number of error bits to generate the weight value of the voltage axis.

4. The flash memory rereading method according to claim 1, characterized in that: The process of constructing the reread index table includes: Determine the distance value between each voltage axis and the remaining voltage axes in the re-read voltage axis table; Sort the distance values ​​corresponding to each voltage axis respectively to obtain the distance queue corresponding to each voltage axis; The index corresponding to each voltage axis is determined respectively according to each of the distance queues.

5. The flash memory rereading method according to claim 4, characterized in that: The distance values ​​corresponding to each voltage axis are sorted respectively to obtain the distance queue corresponding to each voltage axis, including: Among the multiple distance values ​​corresponding to the voltage axis, the distance values ​​with negative values ​​are sorted in ascending order according to the corresponding absolute values, so as to generate a first distance queue corresponding to the voltage axis; Among the multiple distance values ​​corresponding to the voltage axis, the distance values ​​with positive values ​​are sorted in ascending order according to the corresponding absolute values ​​to generate a second distance queue corresponding to the voltage axis.

6. The flash memory rereading method according to claim 5, characterized in that: Determining the index corresponding to each voltage axis according to each of the distance queues respectively includes: Determine the first two distance values ​​in the first distance queue to obtain a first distance value and a second distance value; wherein the absolute value of the first distance value is smaller than the absolute value of the second distance value; Determine the first two distance values ​​in the second distance queue to obtain a third distance value and a fourth distance value; wherein the absolute value of the third distance value is less than the absolute value of the fourth distance value; respectively determining a first to-be-selected voltage axis corresponding to the first distance value, a second to-be-selected voltage axis corresponding to the second distance value, a third to-be-selected voltage axis corresponding to the third distance value, and a fourth to-be-selected voltage axis corresponding to the fourth distance value; The index of the first to-be-selected voltage axis, the index of the second to-be-selected voltage axis, the index of the third to-be-selected voltage axis and the index of the fourth to-be-selected voltage axis are respectively determined as the indexes corresponding to the voltage axes.

7. The flash memory rereading method according to claim 6, characterized in that: Determining the index of the new target voltage axis corresponding to the target voltage axis according to the first difference and the weight value of the target voltage axis and according to a pre-constructed rereading index table includes: Determining a second difference between the initial syndrome weight and a corresponding previous syndrome weight; Determine whether the first difference and the second difference are both greater than 0; If not, determining the index of the new target voltage axis in the reread index table according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis; If so, then the new target voltage axis with the smallest number of corresponding error bits and no reread operation is performed is determined again according to the voltage axis weight table, and the step of performing a reread decoding operation based on the target voltage axis is entered.

8. The flash memory rereading method according to claim 7, characterized in that: Determining the index of the new target voltage axis in the reread index table according to the voltage axis usage of the reread voltage axis table and the weight value of the target voltage axis includes: When the highest bit of the weight value of the target voltage axis is 0, determining whether the first candidate voltage axis and the second candidate voltage axis corresponding to the target voltage axis have been used in a previous rereading; If it is confirmed that the first candidate voltage axis and the second candidate voltage axis have not been used in the previous rereading, the index of the first candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; If it is confirmed that the first candidate voltage axis has been used in the previous rereading, and the second candidate voltage axis has not been used in the previous rereading, the index of the second candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; When the highest bit of the weight value of the target voltage axis is 1, determining whether the third candidate voltage axis and the fourth candidate voltage axis corresponding to the target voltage axis have been used in the previous rereading; If it is confirmed that the third candidate voltage axis and the fourth candidate voltage axis have not been used in the previous rereading, the index of the third candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis; If it is confirmed that the third candidate voltage axis has been used in the previous rereading and the fourth candidate voltage axis has not been used in the previous rereading, the index of the fourth candidate voltage axis corresponding to the target voltage axis is determined as the index of the new target voltage axis.

9. The flash memory rereading method according to claim 8, characterized in that: If it is confirmed that the first candidate voltage axis and the second candidate voltage axis have been used in the previous rereading, or it is confirmed that the third candidate voltage axis and the fourth candidate voltage axis have been used in the previous rereading, the method further includes: According to the voltage axis weight table, a new target voltage axis with the smallest number of corresponding error bits and without performing a reread operation is determined among the voltage axes in the reread voltage axis table, and the step of performing a reread decoding operation based on the target voltage axis is entered.

10. The flash memory rereading method according to any one of claims 3 to 9, characterized in that: If the decoding is successful, it also includes: Obtain the new original error bit number and the new 1-to-0 error number returned by the low-density parity check code decoder; Determine a new number of 0-error-to-1 errors according to the new original number of erroneous bits and the new number of 1-error-to-0 errors; When the new original number of error bits is not less than the original number of error bits corresponding to the target voltage axis, using the new original number of error bits to update the original number of error bits corresponding to the target voltage axis in the voltage axis weight table; When the new number of 0-to-1 errors is not less than the new number of 1-to-0 errors, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 1; When the new number of 0-to-1 errors is less than the new number of 1-to-0 errors, the highest bit of the weight value of the target voltage axis in the voltage axis weight table is recorded as 0.

11. The flash memory rereading method according to claim 10, characterized in that: If the decoding fails, it also includes: Determining whether each voltage axis of the re-read voltage axis table has been re-read; If yes, then the reread process ends and the read recovery process is executed; If not, the process proceeds to the step of obtaining a new syndrome weight in the current low-density parity-check code decoder.

12. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the flash memory rereading method according to any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the flash memory rereading method according to any one of claims 1 to 11.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the flash memory rereading method according to any one of claims 1 to 11 are implemented.

Images