Double-layer codes with low parity check cost for memory subsystems

Abstract

A memory subsystem is configured to encode data using error-correcting codes and erasure codes for storing data in memory cells, and configured to decode data retrieved from the memory cells. For example, data cells of a predetermined size are individually encoded using the error-correcting codes (e.g., low-density parity-check (LDPC) codes) to generate parity-check data of a first layer. The erasure codes are used to cross-encode symbols within the data cells. Parity-check symbols of a second layer are calculated based on the erasure codes. The error-correcting codes can also be used to encode a set of parity-check symbols having a total size equal to the predetermined size to generate parity-check data containing the parity-check symbols.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 883,839, filed May 26, 2020, entitled "Two-Layer Code with Low Parity Cost for Memory Sub-Systems," which claims priority to U.S. Patent Application No. 62 / 864,876, filed June 21, 2019, entitled "Two-Layer Code with Low Parity Cost for Memory Sub-Systems," the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] In summary, at least some of the embodiments disclosed herein relate to memory systems, and more specifically, to, but not limited to, two-layer code for storing data in a memory subsystem and retrieving data from a memory subsystem. Background Technology

[0004] The memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0005] Embodiments are illustrated by way of example rather than limitation in the accompanying drawings, in which similar reference numerals indicate similar elements.

[0006] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 This demonstrates a dynamic data placer, which is configured to determine the media layout in a way that reduces and / or avoids conflicts in concurrent media access when writing data.

[0008] Figure 3 This section demonstrates an example of a memory subsystem with dynamic data placement.

[0009] Figure 4 This describes an instance of a data structure configured to support dynamic data placement.

[0010] Figure 5 This section illustrates an example of a defined dynamic media layout.

[0011] Figure 6 This describes the allocation of block groups across integrated circuit dies for multiple-pass programming of data.

[0012] Figure 7 Explain the layout of two-layer code spanning multiple planes.

[0013] Figure 8 This explains how to encode data using a two-layer code.

[0014] Figure 9 This describes a method for decoding data encoded using double-layer codes.

[0015] Figure 10 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0016] At least some aspects of this disclosure relate to dynamic data placement in a memory subsystem and two-layer coding with low parity cost for encoding data for storage in the memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0017] The media layout specifies the mapping between addresses used in commands received from the host system within the memory subsystem and physical memory locations in the memory media of the memory subsystem. A fixed media layout can cause media access conflicts between active write streams, increased buffer lifetime, and / or increased buffering requirements. Buffer lifetime corresponds to the lifetime of data buffered in the memory subsystem before data is committed, written, stored, or programmed into the memory media of the memory subsystem. For example, a host system to which the memory subsystem is connected, a waste cell collection process running in the memory subsystem, and / or one or more write streams from the host system (e.g., for writing to different areas of a namespace configured in the memory subsystem) can generate multiple write command streams. The memory media may have multiple memory devices capable of writing data in parallel. Therefore, when data is committed to the memory media of the memory subsystem, at least some write command streams can be executed in parallel within the memory subsystem. However, a memory device may only support one write operation at a time. When two write commands are mapped via the media layout to operate on the same memory device, an access conflict occurs. Each conflict increases the corresponding buffer lifetime. Media layout can be randomized by mapping logical addresses to random memory locations in the memory media of the memory subsystem. Randomized media layout reduces collisions. However, collisions can still occur when a predetermined media layout is used, even if the number of write streams is equal to or less than the number of memory devices that can perform write operations independently in parallel.

[0018] At least some aspects of this disclosure address the above and other shortcomings through dynamic data placement. For example, the determination of a portion of the media layout for the logical addresses used in incoming write commands can be postponed until the write command can be executed without conflict. When the memory media is configured on an integrated circuit die (e.g., as a NAND memory cell), the media layout determination can be based on the identifiers of the integrated circuit dies available for performing write operations during I / O scheduling. The media layout is determined such that the logical addresses of commands to be executed in parallel are mapped to different integrated circuit dies available for conflict-free concurrent / parallel operations. Therefore, media access conflicts between write commands from different activity streams can be completely avoided. When the number of active write streams is less than the number of integrated circuit dies in the memory subsystem, no media access conflicts occur when using dynamic media layout. Generally, a write stream contains a set of commands that write, fine-tune, or rewrite a group of data together. In said group, data can be written sequentially, randomly, or pseudo-sequentially in the logical space. Preferably, data in the group is written to an erase block group, where memory cells in the erase block group store data from the stream but not data from other streams. The erase block group can be erased to remove data from the stream without erasing data from other streams. In some cases, conflicts may occur when logical addresses of different streams are mapped to the same erase block group in which data from different streams cannot be erased individually. Such conflicts can also be avoided using dynamic media layout techniques. Optionally, data to be stored in the memory subsystem can be dynamically placed across multiple integrated circuit dies and memory cell planes for multiple programming passes to achieve an optimal or improved match between the allocated memory capacity for the next atomic write operation and the size of the data to be stored in the allocated memory capacity.

[0019] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 102), one or more non-volatile memory devices (e.g., memory device 104), or a combination of such devices.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0023] Host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to and read data from memory subsystem 110.

[0024] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can also utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 104). The physical host interface provides an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] The processing unit 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processor core, an execution unit, etc. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and / or a starter. In one example, the controller 116 controls communication via a bus coupled between the host system 120 and the memory subsystem 110. Generally, the controller 116 may send commands or requests for desired access to memory devices 102, 104 to the memory subsystem 110. The controller 116 may also include an interface circuitry for communicating with the memory subsystem 110. The interface circuitry may translate responses received from the memory subsystem 110 into information for the host system 120.

[0026] The controller 116 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading, writing, or erasing data at memory devices 102, 104, and other such operations. In some cases, the controller 116 is integrated within the same package as the processing device 118. In other cases, the controller 116 is packaged separately from the processing device 118. The controller 116 and / or the processing device 118 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or combinations thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0027] Memory devices 102 and 104 may include different types of non-volatile memory components and / or any combination of volatile memory components. Volatile memory devices (e.g., memory device 102) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory components include NAND flash memory and in-place write memory, such as three-dimensional crosspoint ("3D crosspoint") memory. Crosspoint arrays of non-volatile memory can be combined with stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 104 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 104 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 104 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] While non-volatile memory devices, such as 3D crosspoint type and NAND type memory (e.g., 2D NAND, 3D NAND), are described, memory device 104 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 104 to perform operations, such as reading, writing, or erasing data at the memory device 104, and other such operations (e.g., in response to commands scheduled on the command bus by controller 116). Controller 115 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. Controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0032] Controller 115 may include processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines to control the operation of memory subsystem 110, including handling communication between memory subsystem 110 and host system 120.

[0033] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1 The instance memory subsystem 110 is described as including controller 115, but in another embodiment of this disclosure, memory subsystem 110 does not include controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Generally, controller 115 can receive commands or operations from host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve desired access to memory device 104. Controller 115 may handle other operations such as wear leveling, unused cell collection, error detection and correction coding (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 104. Controller 115 may also include host interface circuitry for communicating with host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing memory device 104 and responses associated with memory device 104 into information for host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that receives and decodes an address from the controller 115 to access the memory device 104.

[0036] In some embodiments, memory device 104 includes a local media controller 105 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 104. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 104 (e.g., perform media management operations on memory device 104). In some embodiments, memory device 104 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 105) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The computing system 100 may optionally include a dynamic data placer 113 in a memory subsystem 110 that dynamically determines the media layout to place data associated with logical addresses in media units / memory devices 102 to 104. The computing system 100 may optionally include a dual-layer encoder / decoder 114 in the memory subsystem 110, which uses a combination of error-correcting and erasure codes to transform data for storage in media units 109A to 109N. In some embodiments, a controller 115 in the memory subsystem 110 includes at least a portion of the dynamic data placer 113 and / or the dual-layer encoder / decoder 114. In other embodiments, or in combination, a controller 116 and / or a processing device 118 in the host system 120 includes at least a portion of the dynamic data placer 113 and / or the dual-layer encoder / decoder 114. For example, controllers 115, 116, and / or 118 may include logic circuitry implementing the dynamic data placer 113 and / or the dual-layer encoder / decoder 114. For example, the controller 115 or the processing device 118 (processor) of the host system 120 may be configured to execute instructions stored in memory for performing the operations of the dynamic data placer 113 and / or the dual-layer encoder / decoder 114 described herein. In some embodiments, the dynamic data placer 113 and / or the dual-layer encoder / decoder 114 is implemented in an integrated circuit chip housed in the memory subsystem 110. In other embodiments, the dynamic data placer 113 and / or the dual-layer encoder / decoder 114 is part of the operating system, device driver, or application of the host system 120.

[0038] Based on the availability of media units / memory devices 102 to 104 for writing, programming, storing, and committing data during input / output scheduling in memory subsystem 110, dynamic data placer 113 determines a media layout for placing a portion of the logical addresses at logical addresses in media units / memory devices 102 to 104. When a media unit / memory device (e.g., 102 or 104) is available for committing / programming data, a write command is scheduled for execution in memory subsystem 110; and dynamic data placer 113 generates a portion of the media layout for the write command and maps the logical addresses used in the write command to identify memory locations in conjunction with the media unit / memory device (e.g., 102 or 104). Execution of the write command causes memory subsystem 110 to commit / program the data associated with the write command into the media unit / memory device (e.g., 102 or 104). Since the operation of known media unit / memory devices (e.g., 102 or 104) for submitting / programming data is independent of the operation of other media unit / memory devices (e.g., 102 or 104), there are no media access conflicts during the execution of write commands. When multiple media unit / memory devices (e.g., 102 and 104) are available, the logical addresses used in commands from multiple write streams can be mapped to the multiple media unit / memory devices (e.g., 102 and 104) respectively through the dynamic generation portion of the media layout, so that there are no media access conflicts when executing commands from multiple write streams. Further details regarding the operation of the dynamic data placer 113 are described below.

[0039] Figure 2 A dynamic data placer 113 is shown, which is configured to determine the media layout 130 in a manner that reduces and / or avoids conflicts in concurrent media access when writing data. For example, it can be used... Figure 1 The computer system 100 implements a dynamic data placer 113 and a media layout 130.

[0040] exist Figure 2 In this process, multiple write commands 123A to 123N are scheduled for parallel execution. The number of write commands 123A to 123N scheduled for parallel execution is based on the media unit / memory devices 109A to 109N available for parallel operation (e.g., Figure 1 The number of memory devices 102 and / or 104 described. Write commands 123A to 123N may come from multiple write streams respectively.

[0041] Write commands 123A to 123N use logical block addressing (LBA) addresses 131, ..., 133 to specify the location for the write operation.

[0042] When scheduling write commands 123A to 123N, the dynamic data placer 113 generates a mapping of logical block addressing (LBA) addresses 131, ..., 133 to physical addresses 141, ..., 143. Since media unit / memory devices 109A to 109N are determined to be available for parallel write operations, the dynamic data placer 113 maps each of the LBA addresses 131, ..., 133 to a different one of the media unit / memory devices 109A, ..., 109N. Therefore, the physical addresses 141, ..., 143 of the LBA addresses 131, ..., 133 correspond to memory areas 151, ..., 153 in different media unit / memory devices 109A, ..., 109N. Since no two of the physical addresses 141, ..., 143 are used for memory areas in the same media unit (e.g., 109A or 109N), no conflicts occur when executing write commands 123A, ..., 123N in parallel. Therefore, media access conflicts were eliminated.

[0043] Generally, write operations across different media units / memory devices 109A to 109N may be inconsistent. Therefore, when a subset of media units / memory devices 109A, ..., 109N becomes available for the next write operation, another subset may still be busy and unavailable for the next write operation. Some of the media units / memory devices 109A, ..., 109N may be busy performing other operations, such as read or erase operations, and therefore unavailable for write operations. Generally, when one or more write commands are scheduled for an available subset of media units / memory devices 109A, ..., 109N, the dynamic data placer 113 generates a portion of the media layout 103 to map the LBA addresses of the scheduled write commands to the physical addresses of memory regions within the available subsets of media units / memory devices 109A, ..., 109N. Therefore, scheduled commands can be executed without media access conflicts.

[0044] Figure 3 This demonstrates an example of a storage subsystem with dynamic data placement. For instance, it can be used... Figure 2 The dynamic data placer 113 in Figure 1 Implemented in memory subsystem 110 Figure 3 The memory subsystem. However, Figure 1 and Figure 2 The technology is not limited to Figure 3 The implementation scheme of the memory subsystem described herein. For example, the technology can be implemented as a regular block device, a namespace-supporting device, or a partitioned namespace-supporting device (e.g., Figure 3(The memory subsystem described herein). Therefore, the disclosure presented herein is not limited to... Figure 3 Examples.

[0045] exist Figure 3 In this context, namespace 201 is configured across the media storage capacity of memory subsystem 110. Namespace 201 provides a logical block addressing space that the host system 120 can use to specify memory locations for read or write operations. Namespace 201 can be allocated across a portion or the entire media storage capacity of memory subsystem 110. In some cases, multiple namespaces can be allocated across separate, non-overlapping portions of the media storage capacity of memory subsystem 110.

[0046] exist Figure 3 In this context, namespace 201 is configured with multiple zones 211, 213, ..., 219. Each zone (e.g., 211) in the namespace allows random read access to LBA addresses within that zone (e.g., 211) and sequential write access to LBA addresses within that zone (e.g., 211), but does not allow random write access to random LBA addresses within that zone (211). Therefore, data is written to zones (e.g., 211) in a predetermined order within the LBA address space of namespace 201.

[0047] When configuring a region (e.g., 211) in namespace 201, it is possible (e.g., for simplicity) to predefine a media layout for said region (e.g., 211). LBA addresses in the region (e.g., 211) may be pre-mapped to media 203 of memory subsystem 110. However, as discussed above, such a predetermined media layout can cause media access conflicts when multiple concurrent write streams are present. Randomizing the mapping from LBA addresses in the region (e.g., 211) to memory locations in media 203 can reduce conflicts, but cannot eliminate them.

[0048] Preferably, a dynamic data placer 113 is configured in the memory subsystem 110 to create a portion of the media layout 130 when scheduling write commands for execution, thereby completely eliminating conflicts.

[0049] For example, the media 203 of the memory subsystem 110 may have multiple integrated circuit dies 205, ..., 207. Each integrated circuit die (e.g., 205) may have multiple planes 221, ..., 223 of memory cells (e.g., NAND memory cells). Each plane (e.g., 221) may have multiple blocks 231, ..., 233 of memory cells (e.g., NAND memory cells). Each block (e.g., 231) may have multiple pages 241, ..., 243 of memory cells (e.g., NAND memory cells). The memory cells in each page (e.g., 241) are configured to be programmed to store / write / commit data together in an atomic operation; and the memory cells in each block (e.g., 231) are configured to erase data together in an atomic operation.

[0050] When a write command (e.g., 123A) for storing data in one region (e.g., 211) and another write command (e.g., 123N) for storing data in another region (e.g., 213) are scheduled for parallel execution because two integrated circuit dies (e.g., 205 and 207) are available for concurrent operation, the dynamic data placer 113 maps the LBA addresses (e.g., 131 and 133) of the write commands (e.g., 123A and 123N) to pages located on different dies (e.g., 205 and 207). This avoids media access conflicts.

[0051] Figure 4 This describes an instance of a data structure configured to support dynamic data placement. For example, you could use... Figure 4 To implement data structures Figure 2 Or a media layout of 3130.

[0052] exist Figure 4 In this configuration, zone mapping 301 is configured to provide media layout information for zones (e.g., 211) within a namespace (e.g., 201). Zone mapping 301 may have multiple entries. Each entry in zone mapping 301 identifies information about a zone (e.g., 211), such as the starting LBA address 311 of the zone (e.g., 211), the block group identifier 313 of the zone (e.g., 211), the cursor value 315 of the zone (e.g., 211), the status 317 of the zone (e.g., 211), etc.

[0053] Host system 120 writes data to a region (e.g., 211) starting at region-starting LBA address 311. Host system 120 sequentially writes data to the region (e.g., 211) within the LBA space. After a certain amount of data has been written to the region (e.g., 211), a cursor value 315 identifies the current starting LBA address for writing subsequent data. Each write command for the region moves the cursor value 315 to a new starting LBA address for the next write command for the region. State 317 may have values ​​indicating that the region (e.g., 211) is empty, full, implicitly open, explicitly open, closed, etc.

[0054] exist Figure 4 In this context, the logical-to-physical block mapping 303 is configured to facilitate the translation of LBA addresses (e.g., 331) into physical addresses in the media (e.g., 203).

[0055] The logical-to-physical block mapping 303 may have multiple entries. An LBA address (e.g., 331) may be used as an index to, or converted into, an entry in the logical-to-physical block mapping 303. The index can be used to look up an entry for the LBA address (e.g., 331). Each entry in the logical-to-physical block mapping 303 identifies the physical address of a memory block in the media (e.g., 203) relative to the LBA address (e.g., 331). For example, the physical address of a memory block in the media (e.g., 203) may include a die identifier 333, a block identifier 335, a page mapping entry identifier 337, etc.

[0056] The die identifier 333 identifies a specific integrated circuit die (e.g., 205 or 207) in the media 203 of the memory subsystem 110.

[0057] Block identifier 335 identifies a specific memory block (e.g., NAND flash memory) within an integrated circuit die (e.g., 205 or 207) identified by die identifier 333.

[0058] Page mapping entry identifier 337 identifies an entry in page mapping 305.

[0059] Page mapping 305 may have multiple entries. Each entry in page mapping 305 may contain a page identifier 351 that identifies a memory cell page within a memory cell block (e.g., a NAND memory cell). For example, page identifier 351 may contain the word line number and sub-block number of the page within the NAND memory cell block. Furthermore, the page entry may contain a page programming mode 353. For example, the page may be programmed in SLC mode, MLC mode, TLC mode, or QLC mode. When configured in SLC mode, each memory cell in the page stores one data bit. When configured in MLC mode, each memory cell in the page stores two data bits. When configured in TLC mode, each memory cell in the page stores three data bits. When configured in QLC mode, each memory cell in the page stores four data bits. Different pages in an integrated circuit die (e.g., 205 or 207) may have different modes for data programming.

[0060] exist Figure 4 In this context, block group table 307 stores data that controls various aspects of the dynamic media layout of a region (e.g., 211).

[0061] Block group table 307 may have multiple entries. Each entry in block group table 307 identifies the number / count 371 of integrated circuit dies (e.g., 205 and 207) for which data is stored in a region (e.g., 211). For each integrated circuit die (e.g., 205 and 207) used for a region (e.g., 211), the entry in block group table 307 has a die identifier 373, a block identifier 375, a page mapping entry identifier 377, etc.

[0062] Die identifier 373 identifies a specific integrated circuit die (e.g., 205 or 207) in media 203 of memory subsystem 110, on which subsequent data can be stored in a region (e.g., 211).

[0063] Block identifier 375 identifies a specific block (e.g., 231 or 233) of memory (e.g., NAND flash memory) within an integrated circuit die (e.g., 205 or 207) identified by die identifier 373, and subsequent data in a storable area (e.g., 211) within said specific block (e.g., 231 or 233).

[0064] Page mapping entry identifier 337 identifies an entry in page mapping 305 that identifies a page (e.g., 241 or 242) of subsequent data available in the storage area (e.g., 211).

[0065] For example, memory subsystem 110 receives multiple write command streams. For example, in one embodiment, each corresponding stream of the multiple streams is configured to sequentially write data in the logical address space; and in another embodiment, the streams of the multiple streams are configured to pseudo-sequentially or, in one embodiment, randomly write data in the logical address space. Each write stream contains a set of commands labeled to write, fine-tune, or rewrite a group of data together as a group. Within the group, data may be written sequentially, randomly, or pseudo-sequentially in the logical space. Preferably, the data in the group is written to an erase block group, wherein memory cells in the erase block group store the data of the stream, but not data from other streams. The erase block group can be erased to remove the data of the stream without erasing data from other streams.

[0066] For example, each write stream is allowed to write sequentially at LBA addresses in a region (e.g., 211) of a namespace (e.g., 201) allocated on media 203 of memory subsystem 110, but out-of-order writing of data in the LBA address space is prohibited.

[0067] The dynamic data placer 113 of the memory subsystem 110 identifies multiple media units (e.g., 109A to 109N) in the memory subsystem that are available for concurrent data writing.

[0068] The dynamic data placer 113 selects a first command from multiple streams to execute concurrently in multiple media units available for writing data.

[0069] In response to the first command being selected for concurrent execution across multiple media units, the dynamic data placer 113 dynamically generates and stores a portion of the media layout 130, which is mapped from a logical address identified by the first command in the logical address space to a physical address of a memory cell in the multiple media units.

[0070] The memory subsystem 110 concurrently executes the first command by storing data into a memory cell according to the physical address.

[0071] For example, when scheduling a first command for execution, the execution of a second command may be performed on a subset of the memory cells of the media in memory subsystem 110. Therefore, the subset of memory cells used to execute the second command cannot be used for the first command. After scheduling the first command and determining the portion of the media layout used for the logical addresses employed in the first command, the first command may be executed concurrently in multiple media cells and / or concurrently with the execution process of the second command in the remaining media cells of memory subsystem 110.

[0072] For example, after identifying multiple memory cells (e.g., integrated circuit dies) available for executing subsequent commands, the dynamic data placer 113 can identify from the block group table 307 the physical address that can be used to store data for the subsequent commands. This physical address can be used to update the corresponding entry in the logical-to-physical block mapping 303 for the LBA address used in the subsequent command.

[0073] For example, when an integrated circuit die (e.g., 205) is freely writable, the dynamic data placer 113 can determine commands for regions that can be written to / programmed into memory cells within the integrated circuit die (e.g., 205). Based on block group table 307, the dynamic data placer 113 locates the entry for the region (e.g., 205), locates the block identifier 375 and page map entry identifier 377 associated with the identifier 373 of the integrated circuit die (e.g., 205), and uses the die identifier 373, block identifier 375, and page map entry identifier 377 to update the corresponding fields of the entries in the logical-to-physical block map 303 using the LBA address 331 used in the commands for the region (e.g., 211). Therefore, for LBA address 331, commands for the region (e.g., 211) can be executed without media access conflicts.

[0074] Figure 5 This section illustrates an example of a defined dynamic media layout.

[0075] exist Figure 5 In the example, two concurrent write streams 420 and 430 are illustrated. Stream 420 has entries 421, 423, 425, ..., 429 to be written to memory cells of integrated circuit dies 441, 443, 445, ... . Stream 430 has entries 431, 433, 435, ..., 439 to be written to memory cells of integrated circuit dies 441, 443, 445, ... . If entry 421 of stream 420 and entry 431 of stream 432 are allocated to be written to the same die (e.g., 441), a conflict will occur because the die (e.g., 441) cannot be used for concurrent writing of entry 421 of stream 420 and entry 431 of stream 430. Therefore, a dynamic data placer (e.g., ... Figure 1 , 2 Or 113 in 3) allocates items 421 and 431 of concurrent streams 420 and 430 to pages 451 and 454 in different bare dies 441 and 443, as follows Figure 5As explained in [the document]. Similarly, items 423 and 433 from concurrent streams 420 and 430 are allocated to pages 453 and 42 in different dies 443 and 441. For example, when item 425 of stream 420 is allocated to page 455 in die 455, concurrent item 435 is allocated to be written to a page in another die; and page 457 in die 445 can be allocated to item 439 of stream 430, which is not concurrently written / programmed with item 425 of stream 420. Thus, conflicts are avoided. The dynamic media layout changes the order in which items are written relative to the order of dies 441, 443, 445, ... For example, items 421 to 429 of stream 420 are written to bare dies 441, 443, 445, ... in one order; and items 431 to 439 of stream 430 are written to bare dies 441, 443, 445, ... in another order, so that streams 420 and 430 do not access the same bare die simultaneously. Figure 5 In this process, data from different streams 420 and 430 are labeled to be written into different erase blocks. For example, pages 451 in the bare die 441 used to store data items 421 of stream 420 and pages 452 in the bare die 441 used to store data items 431 of stream 430 are in separate erase block groups, such that pages 451 of stream 420 can be erased without erasing pages 452 of data stored in stream 430, and pages 452 of stream 430 can be erased without erasing pages 451 of data stored in stream 420.

[0076] In at least some of the embodiments disclosed herein, the dynamic data placer 113 can place data across multiple integrated circuit dies (e.g., 205 to 207) and memory cell planes (e.g., 221 to 223) for multiple-pass programming of data provided by the host system 120 to be stored in the memory subsystem 110. This flexibility in multiple-pass programming data across multiple integrated circuit dies (e.g., 205 to 207) and planes (e.g., 221 to 223) allows the dynamic data placer 113 to improve the match between the dynamically allocated storage capacity for the next atomic write operation and the size of the data to be stored in said allocated storage capacity. This improved match reduces or eliminates the need for zero-padding for data programming operations, reduces buffering time of data in the memory subsystem, reduces attrition amplification and storage space amplification, and improves storage performance.

[0077] For example, memory subsystem 110 may have NAND (“NAND”) flash memory. Atomic write / programming operations program pages (e.g., 241) of memory cells together to store data. If the size of the data to be programmed / written into a page is smaller than the size of the page, zeros (or other values) can be padded / added to the data to program the entire page (e.g., 241) together. However, padded zeros (or other values) reduce the utilization of the storage capacity of the page (e.g., 241) and may increase wear amplification and storage space amplification. On the other hand, if memory subsystem 110 receives more data than can be programmed into a page (e.g., 241), a portion of the received data can be buffered in memory subsystem 110 for use in the next atomic write operation. However, buffering excess data in memory to wait for the next operation increases the time and amount of data to be buffered in memory subsystem 110, and thus increases the capacity requirements of the power-fail hold-up circuit, which is used to power the volatile buffer memory (e.g., 119) of memory subsystem 110 during a power failure event until the data in the buffer memory (e.g., 119) can be cleared to non-volatile memory.

[0078] Atomic write operations can be implemented in NAND devices in various ways. Using single-pass programming techniques, atomic write operations in NAND devices can program / store data into single-plane, dual-plane, quad-plane, or multi-plane pages. Using multi-pass programming techniques, atomic write operations in NAND devices can program / store data into pages in SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Three-Level Cell), or QLC (Quad-Level Cell) modes. Pages programmed in atomic write operations can have different sizes in different modes. For example, using multi-pass programming, an SLC page can be 64 kilobytes (KB) in size, an MLC or TLC page can be 128 KB in size, and a QLC page can be 64 KB in size.

[0079] When data pages of different write streams in different programming modes are interleaved in a NAND device, the size of the next available page may differ among blocks of NAND memory cells (e.g., 221 to 223) on different integrated circuit dies (e.g., 205 to 207) of the NAND device.

[0080] When a NAND device supports multi-pass programming, a given amount of data can be programmed for different passes using different combinations of memory page programming modes and locations. For example, when memory subsystem 110 receives 192KB of data from a host system, the NAND device can be configured to program the data using three first-pass SLC programming operations on three single-plane pages in three integrated circuit dies, where each integrated circuit die performs an atomic operation of first-pass SLC programming of 64KB of data. Alternatively, the NAND device can be configured to program the data using first-pass SLC programming on a single-plane page in one integrated circuit die and second-pass TLC or MLC programming on another single-plane page in the same integrated circuit die or another integrated circuit die.

[0081] Using various programming options, the dynamic data placer 113 can dynamically determine the data placement in integrated circuit dies 205 to 207 based on the availability of data programming operations to be performed on integrated circuit dies 205 to 207 and the data programming mode (e.g., 353) of the next available block (e.g., 241) in the integrated circuit dies (e.g., 205) that can be used to perform data programming operations.

[0082] For example, when memory subsystem 110 receives one or more commands from the host system to store a given amount of host data, dynamic data placer 113 queues one or more commands (e.g., in local memory 119) and determines a portion of media layout 130 for the physical placement of data in integrated circuit dies 205-207. When the integrated circuit die (e.g., 205) is available to perform data programming operations, dynamic data placer 113 allocates a portion of the host data (to be retrieved from host system 120) for data programming operations in the integrated circuit die (e.g., 205). The amount of data allocated to the integrated circuit die (e.g., 205) is based on the data programming pattern (353) of pages (e.g., 241) in the available block (e.g., 231). This process of allocating data to the next available integrated circuit die is repeated until the entire host data is allocated to a set of integrated circuit dies (e.g., 205 and 207), where each integrated circuit die (e.g., 205 and 207) is used to store a portion of the host data using an atomic data write operation. The storage capacity (e.g., pages) allocated from multiple integrated circuit dies (e.g., 205 and 207) can be combined for multiple programming passes. In response to the completion of physical memory allocation, the memory subsystem 110 may allocate buffer space for transferring host data; and transfer different data portions to different circuit dies (e.g., 205 and 207) according to dynamically determined physical memory allocation, such that the integrated circuit dies (e.g., 205 and 207) can perform corresponding data programming operations to store their data portions.

[0083] Figure 6 This describes the block group 281 allocated across integrated circuit dies 205 to 207 for multiple-pass programming of data.

[0084] exist Figure 6 In the process, integrated circuit die A 205 has planes 221 to 223 and blocks (e.g., 231 to 233); and integrated circuit die B 207 has planes 261 to 263 and blocks (e.g., 271 to 273).

[0085] Block group 281 is allocated for a stream. Data for that stream is stored in block group 281; data for other streams is not stored in block group 281. Therefore, when block group 281 is erased, only the data for that stream is erased. The entire data of a stream can be erased by erasing block group 281.

[0086] Usable Figure 4 The entries in block group table 307, as described, identify block group 281. Generally, block group 281 can be allocated on a subset of integrated circuit dies (e.g., 205, 207, ...) in media 203. For each block (e.g., 271), the entries in block group table 307 identify the die (e.g., 207) using a die identifier (e.g., 373), the block within the die (e.g., 207) using a block identifier (e.g., 375), and the next page available for storing data within the block using a page mapping entry identifier 377. Page mapping entry identifier 373 identifies entries in page mapping 305. Entries in page mapping 305 display the page identifier 351 and programming mode 353 of the page within the block (e.g., 271).

[0087] In block group 281, dynamic data placer 113 may allocate a page of programmable data from one die (e.g., 205) and repeat the allocation from another die (e.g., 207). Dynamic data placer 113 may allocate individual pages from different dies for multiple programming passes and select dies for allocation to reduce or eliminate padding until all host data to be transferred from host system 120 to memory subsystem is allocated in a single communication.

[0088] In a method involving dynamic data placement for multi-pass programming data across an integrated circuit die, memory subsystem 110 receives a command from host system 120 that identifies the size of the data to be stored in memory subsystem 110.

[0089] The commands are scheduled in a memory subsystem 110 having memory cells formed on multiple integrated circuit dies 205 to 207.

[0090] Based on data programming operations determined that each of the plurality of integrated circuit dies 205 to 207 (e.g., 205 and 207) is available to execute the command, the dynamic data placer 113 allocates memory cell pages in the plurality of dies (e.g., 205 and 207).

[0091] Dynamic data placer 113 generates a portion of media layout 130 to at least map the logical addresses of the data identified in the command to the allocated pages.

[0092] After the aforementioned portion of the media layout is generated and / or after the page is allocated, the memory subsystem 110 receives data from the host system in response to the command.

[0093] The memory subsystem 110 uses multi-pass programming techniques to store data in pages, where atomic multi-pass programming operations can program at least a portion of the data using at least two pages in a single die or a single plane (e.g., two planes in a single die) across multiple integrated circuit dies. For example, based on per-plane page mapping and die availability, data received from the host system can be flexibly mapped for programming across a single plane, two planes, or four planes in a single or dual die. Single-die mapping can accommodate the minimum size of the stream.

[0094] For example, portions of the data can be programmed into at least two pages in atomic operations. Instructions are sent to each of the bare dies to perform a write operation. Instructions are not sent to each of the bare dies to perform repeated write operations for the command.

[0095] The at least two pages may include a first page in a first integrated circuit die and a second page in a second integrated circuit die. Multiple programming operations may include a first programming of the first page and a second programming of the second page. The first programming may be in a first mode, and the second programming may be in a second mode. For example, the first mode and the second mode are different from the following: single-level cell (SLC) mode; multi-level cell (MLC) mode; three-level cell (TLC) mode; and four-level cell (QLC) mode.

[0096] For example, the allocation of executable pages is designed to minimize the mismatch between the storage capacity of pages programmed using multi-pass programming techniques and the size of the data identified in the command.

[0097] Optionally, pages can be allocated from a block group configured to be erased together.

[0098] For example, dynamic data placer 113 may store page maps 305, each page having entries for pages in its respective identifier block and memory cell programming modes (e.g., 353) for those pages. Dynamic data placer 113 may allocate pages based on the memory cell programming modes (e.g., 353) identified in page maps 305. The programming mode (e.g., 353) indicates the size of the available pages; and dynamic data placer 113 allocates the pages such that the allocated storage capacity matches the size of the data to be received from host system 120.

[0099] In some implementations, the communication channel between the processing device 118 and the memory subsystem 110 includes a computer network, such as a local area network, wireless local area network, wireless personal area network, cellular communication network, or broadband high-speed always-connected wireless communication connection (e.g., current or future generation mobile network link); and the processing device 118 and the memory subsystem may be configured to communicate with each other using data storage management and usage commands similar to those in the NVMe protocol.

[0100] The memory subsystem 110 may typically have a non-volatile storage medium. Examples of non-volatile storage media include memory cells formed in integrated circuits and magnetic materials coated on a hard disk. Non-volatile storage media can maintain the data / information stored therein without consuming power. Memory cells can be implemented using various memory / storage technologies, such as NAND logic gates, NOR logic gates, phase-change memory (PCM), magnetic random access memory (MRAM), resistive random access memory, crosspoint memory, and memory devices (e.g., 3D XPoint memory). Crosspoint memory devices use transistorless memory elements, each of which has memory cells and selectors stacked together in a column. The column of memory elements is connected via two vertical wire layers, one layer above the column and the other layer below. Each memory element can be individually selected at the intersection of a wire on each of the two layers. Crosspoint memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

[0101] The controller (e.g., 115) of the memory subsystem (e.g., 110) may run firmware to operate in response to communications from the processing device 118. Typically, firmware is a computer program that provides control, monitoring, and data manipulation of an engineered computing device.

[0102] Some embodiments involving the operation of controller 115 may be implemented using computer instructions (such as firmware of controller 115) executed by controller 115. In some cases, hardware circuitry may be used to implement at least some functions. The firmware may be initially stored in non-volatile storage media or another non-volatile device and loaded into volatile DRAM and / or in-processor cache memory for execution by controller 115.

[0103] Non-transitory computer storage media may be used to store instructions for the firmware of a memory subsystem (e.g., 110). When executed by controller 115 and / or processing device 117, the instructions cause controller 115 and / or processing device 117 to perform the methods described above.

[0104] Errors can occur between storing data in memory cells and retrieving data from memory cells. To facilitate error-free data retrieval, the memory subsystem can encode data received from the host system using error-correcting codes such as low-density parity-check (LDPC) codes, and store the encoded data in memory cells. Decoding the encoded data retrieved from memory cells can remove or reduce errors.

[0105] Error rates are unevenly distributed across multiple memory pages and / or word lines in flash memory, regardless of their programming modes. For example, a memory subsystem may contain pages programmed in SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Three-Level Cell), and QLC (Quadruple-Level Cell) modes. When configured in SLC mode, each memory cell in a page stores one data bit. When configured in MLC mode, each memory cell in a page stores two data bits. When configured in TLC mode, each memory cell in a page stores three data bits. When configured in QLC mode, each memory cell in a page stores four data bits. As the number of bits stored in a cell increases, the probability of errors in the data retrieved from the cell increases. Most memory cells in a block may be in QLC mode, and some memory cells may be in SLC and / or TLC modes. When LP, MP, UP, and XP pages are used to program memory cells in QLC mode using multi-pass programming techniques, decoding an LP page is similar to decoding a page in SLC mode, which has the highest signal-to-noise ratio (S / N) and the lowest bit error rate (BER). Decoding MP and UP pages is similar to decoding a page in TLC mode, which has a medium S / N ratio and a medium BER. Decoding an XP page is similar to decoding a page in QLC mode, which has the lowest S / N ratio and the highest BER. Non-uniformity in error rate distribution can cause over-rate design of the low-density parity-check (LDPC) codes used in the memory subsystem to meet bit error rate requirements, especially when Redundant Array of Independent NAND (RAIN) technology is not used. Furthermore, over-rate design can cause misalignment between the sector size of host data and the memory page size, leading to additional wasted memory space in the memory subsystem.

[0106] In at least some of the embodiments disclosed herein, a two-layer code with low parity cost is provided to address the problem associated with non-uniform error rate distribution across pages with different programming modes. For example, the two-layer code may comprise a first-layer LDPC code configured according to a nominal bit error rate (e.g., 0.005) rather than a worst-case bit error rate (e.g., 0.01). A second-layer erasure code is configured to span codewords across multi-plane pages with different programming modes (e.g., SLC, MLC, TLC, QLC) in different planes. For example, the symbol size of the erasure code used in the second layer may be 16 bytes. An iterative LDPC decoding and erasure decoding method can be used to decode data retrieved from memory cells of multi-plane pages. In the iterative method, operations are performed to identify the location of missing symbols such that subsequent iterations can follow after symbols are regenerated via an erasure decoding operation.

[0107] For example, the first layer can use a 4K LDPC with a code rate of 0.9, resulting in a 0.9 ratio between the LDPC payload size and the LDPC codeword size. The second layer can use a 63+1 (or 15+1) erasure code with a symbol size of 16 bytes, allowing parity symbols to be generated for every 63 (or 15) data symbols, so that if any of the 64 (or 16) symbols are missing, the missing symbol can be recovered or calculated from the remaining 63 (or 15) symbols. The net data efficiency is the product of the code rates of the first and second layers (e.g., 0.9 multiplied by 63 / 64 for a 63+1 erasure code, or 0.9 multiplied by 15 / 16 for a 15+1 erasure code). The net data efficiency, as the product of the code rates of the first and second layers, can be expected to be higher than the code rate of a single over-engineered LDPC code.

[0108] Figure 7 Explain the layout of two-layer code spanning multiple planes.

[0109] For example, pages 501, 503, 505 and 507 can be programmed in different modes on different planes in one or more integrated circuit dies (e.g., 205 to 207) of the memory subsystem (e.g., 110).

[0110] For example, page 501 can be in SLC mode; page 503 can be in MLC or TLC mode; page 505 can be in TLC mode; and page 507 can be in QLC mode. Optionally, this set of pages 501 to 507 can be programmed as multi-plane pages via multiple programming operations across multiple planes.

[0111] exist Figure 7 In this diagram, each row represents a data unit of a predetermined size (e.g., 4KB) of payload encoded using LDPC codes. For example, data symbols S1_1, S1_2 to S1_N can be encoded using LDPC codes to generate parity data P1; data symbols S2_1, S2_2 to S2_N can be encoded using LDPC codes to generate parity data P2; and data symbols S15_1, S15_2 to S15_N can be encoded using LDPC codes to generate parity data P15. Typically, data symbols Sm_1, Sm_2 to Sm_N can be encoded using LDPC codes to generate parity data Pm, where m = 1, 2, ... M. Figure 7 The example where M=15 is illustrated. Data symbols Sm_1, Sm_2 to Sm_N form data units with a total size equal to a predetermined size (e.g., 4KB) of the payload used for LDPC encoding.

[0112] Erasure coding can be used to encode data symbols across data units to generate parity symbols. For example, 15+1 erasure coding can be used to encode data symbols S1_1, S2_1 to S15_1 to generate parity symbol PS_1, such that if any of the 16 symbols S1_1, S2_1 to S15_1 and PS_1 is missing, the missing symbol can be calculated from the remaining 15 symbols. Alternatively, 30+2 erasure coding can be used to generate two parity symbols PS_1 and PS_2 from 30 data symbols S1_1, S2_1 to S15_1 and S2_1, S2_2 to S15_2. In a manner similar to encoding data symbol units (e.g., Sm_1, Sm_2 to Sm_N) received from host system 120, a set of parity symbols PS_1, PS_2 to PS_N with a total size equal to the payload used for LDPC codes can be encoded to generate parity data labeled PPS. Therefore, data recovery can be performed on parity symbols PS_1, PS_2 to PS_N based on the LDPC codes using the LDPC parity data PPS.

[0113] Figure 8 This explains how to encode data using a two-layer code. Figure 8 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 8 The method is at least in part by Figure 1 The dual-layer encoder / decoder 114 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0114] For example, the dynamic data placer 113 may allocate media units to perform multi-pass programming based on the availability of multiple planes across one or more media units (e.g., integrated circuit dies). Figure 8 The method. In some embodiments, Figure 8 The method can be used in memory subsystems that do not have a dynamic data placer 113.

[0115] At box 521, the dual-layer encoder / decoder 114 splits the data received from the host system into data units according to a predetermined payload size for error correction codes (e.g., low-density parity-check codes). For example, each data unit may be 4KB in size for LDPC encoding.

[0116] At box 523, the dual-layer encoder / decoder 114 uses error-correcting codes to encode each corresponding data unit of the payload size to generate parity data for the first layer (e.g., ...). Figure 7 (P1, P2 to P15 in the text).

[0117] At box 525, the dual-layer encoder / decoder 114 uses erasure coding to encode the symbols within the data unit.

[0118] At box 527, the dual-layer encoder / decoder 114, based on the symbol (e.g., Figure 7 The Sm_1, Sm_2 to Sm_N (where m = 1, 2, ..., 15) are encoded to calculate the parity check symbol of the second layer of the double-layer code (e.g., Figure 7 (PS_1, PS_2 to PS_N in the original text). Erasure coding allows the regeneration of missing symbols based on parity symbols. For example, erasure coding can be performed on symbols spanning different pages 501 to 507 located on different planes.

[0119] At box 529, the dual-layer encoder / decoder 114 uses error-correcting codes to correct the parity symbols (e.g., Figure 7 The parity data (PS_1, PS_2 to PS_N) in the parity check symbol is encoded to generate parity check data (e.g., Figure 7 PPS in the middle).

[0120] For example, parity symbols can be grouped according to the predetermined payload size for encoding with error-correcting codes to generate parity data of parity symbols.

[0121] After encoding using error correction codes and erasure codes, the memory subsystem can store the symbols of data units, the parity data of the first layer, the parity symbols, and the parity data of the parity symbols in a separate plane in one or more integrated circuit dies.

[0122] For example, in parity symbols, each corresponding parity symbol stored in the plane can be generated based on the storage of the data unit's symbol in a portion of the plane where the corresponding parity symbol is not stored. For example, multiple programming operations can be used to store portions of the data unit's symbol and the parity symbol in separate planes.

[0123] For example, the multi-pass programming operation may include a first pass programming of a first page on a first plane and a second pass programming of a second page on a second plane. Individual planes may be programmed via different modes, such as different modes among single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC) modes.

[0124] Figure 9 This describes a method for decoding data encoded using double-layer codes. Figure 9 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 9 The method is at least in part by Figure 1 The dual-layer encoder / decoder 114 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0125] For example, after using multi-pass programming techniques to store encoded data into memory cells across multiple planes in one or more media units (e.g., an integrated circuit die), and then retrieving the encoded data from the memory cells in case of errors during memory cell retrieval, execution is possible. Figure 9 Methods to restore use Figure 8 The method of encoding data.

[0126] At box 541, the dual-layer encoder / decoder 114 decodes the data retrieved from the memory cell based on error correction codes (e.g., low-density parity check codes).

[0127] At box 543, the dual-layer encoder / decoder 114 determines whether decoding based on the error correction code (e.g., LDPC) was successful. All codewords generated using the error correction code (e.g., LDPC) can be transmitted via parity data (e.g., ...). Figure 7 When P1 in the memory is successfully decoded and / or recovered, the original data (the encoded data is generated, stored and then retrieved from the memory unit based on the original data) is successfully recovered.

[0128] If some codewords cannot be successfully decoded using error-correcting codes (e.g., LDPC), the dual-layer encoder / decoder 114 identifies the symbols that could not be successfully decoded via the error-correcting codes at box 545. Unsatisfied parity checks in the LDPC codes can be used to identify bits in the LDPC codewords that cannot be reliably decoded. The identified symbols can be considered missing / erased. The erasure codes can then be used to decode those few ambiguous symbols. Decoding based on the erasure codes can be performed to recover the missing / erased symbols.

[0129] At box 547, the dual-layer encoder / decoder 114 recovers the identified symbols based on erasure coding.

[0130] The recovered symbols can be used to replace the corresponding symbols retrieved from the memory cells and further decoded via error-correcting codes (e.g., low-density parity-check codes) for data recovery.

[0131] At box 549, the dual encoder / decoder 114 determines whether to perform further iterations. For example, if fewer than a threshold number of iterations (e.g., 4) have been performed, the dual encoder / decoder 114 may repeat operations 541 to 547 for another iteration to recover the data. After performing the threshold number of iterations (e.g., 4) and decoding still unsuccessfully, the dual encoder / decoder 114 may report data recovery / decoding failure.

[0132] Figure 10 An example machine is described as a computer system 600, within which an instruction set is executable to cause the machine to perform any one or more methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or the memory subsystem 113 or the dual-layer encoder / decoder 114 may be used to perform operations (e.g., execute instructions to perform operations corresponding to the reference). Figures 1 to 9 The operation of the described dynamic data placer 113 and / or dual-layer encoder / decoder 114. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, with the capabilities of a server or client machine in a client-server network environment.

[0133] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine has been described, the term "machine" should be understood to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any of the methods discussed herein.

[0134] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (e.g., SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630 (which may include multiple buses).

[0135] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may also include a network interface device 608 for communication via network 620.

[0136] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more sets of instructions 626 or software embodying any one or more methods or functions described herein. Instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0137] In one embodiment, instruction 626 includes instructions for implementing a dynamic data placer 113 and / or a dual-layer encoder / decoder 114 (e.g., reference...). Figures 1 to 9The described dynamic data placer 113 and / or dual-layer encoder / decoder 114) contain functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0138] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms here are, and are generally considered, a self-consistent sequence of operations that produce the desired result. These operations are those that require physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for general reasons.

[0139] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0140] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each media coupled to a computer system bus.

[0141] The algorithms and demonstrations presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0142] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0143] In this description, for simplicity, various functions and operations may be described as being executed or caused by computer instructions. However, those skilled in the art will recognize that such expressions are intended to mean that the functions are generated by one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively or in combination, the functions and operations may be implemented using a dedicated circuit system, with or without software instructions, such as using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Embodiments may be implemented using a hardwired circuit system, either without or in combination with software instructions. Therefore, the technology is neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a data processing system.

[0144] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for encoding data, comprising: splitting data received from a host system into data units according to a predetermined payload size for an error correction code; encoding each respective data unit of the payload size using the error correction code to generate parity data for a first tier; encoding symbols within the data units using an erasure correction code; calculating parity symbols for a second tier according to the erasure correction code; and encoding the parity symbols using the error correction code to generate parity data for the parity symbols.

2. The method of claim 1, wherein the error correction code is a low density parity check (LDPC) code.

3. The method of claim 2, wherein the parity symbols are grouped according to the predetermined payload size for encoding using the error correction code to generate the parity data for the parity symbols.

4. The method of claim 2, further comprising: storing the symbols of the data units, the parity data for the first tier, the parity symbols, and the parity data for the parity symbols in separate planes in one or more integrated circuit dies.

5. The method of claim 4, wherein each respective parity symbol stored in a plane among the parity symbols is generated based on a portion of the symbols of the data units stored in a plane that does not store the respective parity symbol.

6. The method of claim 5, wherein the portion of the symbols of the data units and the parity symbols are stored in the separate planes using a multiple pass programming operation.

7. The method of claim 6, wherein the multiple pass programming operation includes a first pass programming of a first page on a first plane and a second pass programming of a second page on a second plane.

8. The method of claim 6, wherein the separate planes are programmed via different modes.

9. The method of claim 8, wherein the different modes include a first mode and a second mode; and the first mode and the second mode are different ones of: a single level cell (SLC) mode; a multi-level cell (MLC) mode; a triple level cell (TLC) mode; and a quad level cell (QLC) mode.

10. A non-transitory computer storage medium storing instructions that, when executed in a memory sub-system, cause the memory sub-system to perform a method, the method comprising: decoding data retrieved from a memory cell based on an error correction code; determining that the decoding is unsuccessful; identifying a first symbol that was not successfully decoded via the error correction code; generating a second symbol based on an erasure correction code as a replacement for the first symbol; and decoding the second symbol based on the error correction code.

11. The non-transitory computer storage medium of claim 10, wherein the method further comprises repeating: identifying a third symbol that was not successfully decoded via the error correction code; generating a replacement symbol for the third symbol based on the erasure correction code as a replacement for the third symbol; and decoding the substitute symbols based on the error correction code.

12. The non-transitory computer storage medium of claim 11, wherein the error correction code includes a low density parity check (LDPC) code.

13. The non-transitory computer storage medium of claim 12, wherein the method further comprises: retrieving the data from the memory cells in a multi-plane page programmed using a multi-pass programming operation.

14. The non-transitory computer storage medium of claim 13, wherein the multi-plane page includes first data programmed on a first plane and second data programmed on a second plane.

15. The non-transitory computer storage medium of claim 14, wherein the first data is programmed in a first mode; and the second data is programmed in a second mode.

16. The non-transitory computer storage medium of claim 15, wherein the first mode and the second mode are different ones of: a mode that stores one bit in each memory cell; a mode that stores two bits in each memory cell; a mode that stores three bits in each memory cell; and a mode that stores four bits in each memory cell.

17. The non-transitory computer storage medium of claim 15, wherein the second data includes parity symbols generated based on symbols in the first data.

18. A memory sub-system, comprising: a plurality of integrated circuit dies having memory cells; at least one processing device configured to: split data received from a host system into data units according to a predetermined payload size for an error correction code; encode each respective data unit of the payload size using the error correction code to generate parity data for a first tier; encode symbols within the data units using an erasure code; calculate parity symbols for a second tier according to the erasure code; and encode the parity symbols using the error correction code to generate parity data for the parity symbols.

19. The memory sub-system of claim 18, wherein the at least one processing device is configured to: program the symbols of the data units, the parity symbols, and the parity data for the parity symbols in at least two planes in one or more of the integrated circuit dies using a multi-pass programming technique; wherein the parity symbols are programmed in a first plane; and wherein the parity symbols are generated based at least in part on a portion of the symbols of the data units programmed in a second plane different from the first plane.

20. The memory sub-system of claim 19, wherein the at least one processing device is configured to: retrieve data from memory cells storing the symbols of the data units, the parity symbols, and the parity data for the parity symbols; decode the retrieved data based on the error correction code; determine that the decoding is unsuccessful; identifying a first symbol that cannot be successfully decoded via the error correction code; generating a second symbol based on the erasure code as a replacement for the first symbol; and decoding the second symbol based on the error correction code.

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