Chip computing power test method and device and storage medium

Abstract

The embodiment of the invention provides a chip computing power testing method and device and a storage medium, and the method comprises the steps: determining a testing environment of a to-be-tested chip, and enabling the required computing power of the chip to change according to a preset rule in the testing environment; in the test environment, running the chip to be tested; for a to-be-tested chip in operation, first change data, second change data, process delay and accuracy of the to-be-tested chip are collected, the first change data are used for representing data of chip temperature changing along with time, and the second change data are used for representing data of output computing power changing along with time; and evaluating the computing power fluctuation degree of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested. According to the technical scheme provided by the invention, the problems that the real performance of the chip is difficult to reflect truly and the accuracy of chip evaluation is reduced in the prior art are solved.

Description

Technical Field

[0001] This document relates to the technical field of chip performance evaluation, and in particular to a chip computing power testing method, device and storage medium. Background Art

[0002] With the continuous development of the new energy vehicle industry, the value of automotive electronics in the era of smart cars continues to increase, and automotive computing chips have become the core of the development of smart cars. Driven by a variety of different applications, the requirements for computing performance of smart car computing chips continue to grow.

[0003] Current automotive chip evaluations mainly use computing power as the true performance evaluation standard, where computing power refers to the chip's peak computing power, reflecting the chip's extreme processing capabilities.

[0004] However, the actual performance of automotive computing chips will be affected by task diversity, software SDK (Software Development Kit), algorithms and models, environment, energy efficiency and actual application scenarios. Therefore, it is difficult for existing technologies to truly reflect the actual performance of the chip, thereby reducing the accuracy of chip evaluation. Summary of the invention

[0005] In view of the above scheme, the present application aims to propose a chip computing power testing method, device and storage medium to solve at least one of the above technical problems.

[0006] In a first aspect, one or more embodiments of this specification provide a chip computing power testing method, including: determining a test environment for a chip to be tested, in which the chip required computing power changes according to a preset rule;

[0007] In the test environment, running the chip to be tested;

[0008] For a running chip to be tested, first change data, second change data, process delay and accuracy of the chip to be tested are collected, wherein the first change data is used to characterize the data of chip temperature change over time, and the second change data is used to characterize the data of output computing power change over time; and

[0009] The computing power fluctuation degree of the chip to be tested is evaluated according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

[0010] Furthermore, determining the operating environment of the chip to be tested includes:

[0011] Determine the chip operating environment temperature and the computing power percentage of the chip in the test environment, where the computing power percentage is the percentage of the output computing power to the benchmark computing power.

[0012] Furthermore, the test environment includes multiple scenarios, each of which requires different computing power; and

[0013] The chip computing power requirement changes according to the preset rules including:

[0014] The multiple scenes are switched according to a preset cycle or sequence.

[0015] Furthermore, the acquisition process latency and accuracy include:

[0016] Collect the process delay and accuracy in each of the described scenarios.

[0017] Further, for each scenario, the computing power fluctuation degree of the chip to be tested is evaluated according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested, including:

[0018] Determine a curve of output computing power changing with temperature according to the first change data and the second change data; and

[0019] The computing power fluctuation of the chip to be tested is evaluated according to the curve of the computing power changing with temperature, the process delay and the accuracy.

[0020] In a second aspect, an embodiment of the present application provides a chip computing power testing device, including: a determination module, an operation module, a collection module and a data processing module;

[0021] The determination module is used to determine a test environment for the chip to be tested, in which the chip's required computing power changes according to a preset rule;

[0022] The running module is used to run the chip to be tested in the test environment;

[0023] The acquisition module is used to collect first change data, second change data, process delay and accuracy of the chip to be tested in operation, wherein the first change data is used to represent the data of chip temperature change over time, and the second change data is used to represent the data of output computing power change over time; and

[0024] The data processing module is used to evaluate the degree of fluctuation of the computing power of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

[0025] Furthermore, the determination module is used to determine the chip working environment temperature and the computing power percentage of the chip in the test environment, wherein the computing power percentage is the percentage of the output computing power to the benchmark computing power.

[0026] Furthermore, the test environment includes multiple scenarios, each of which requires different computing power; and

[0027] The determining module is used to switch the multiple scenes according to a preset cycle or time sequence.

[0028] Furthermore, the data processing module is used to determine a curve of output computing power changing with temperature based on the first change data and the second change data; determine computing power loss based on the process delay and the accuracy; and evaluate computing power fluctuations of the chip to be tested based on the curve of computing power changing with temperature and the computing power loss.

[0029] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the chip computing power testing method as described in any one of the first aspects is implemented.

[0030] Compared with the prior art, this application can at least achieve the following technical effects:

[0031] In view of the characteristics of the ever-changing demand for computing power in real driving scenarios. This application chooses to evaluate the fluctuations in the computing power of the chip. Specifically, the demand for computing power is constantly changing in the test environment. While the demand for computing power is constantly changing, data that changes with the demand for computing power (first change data, second change data, process delay, and accuracy) is collected to realize the digitization of the change in demand for computing power. Finally, based on the first change data, the second change data, the process delay, and the accuracy, the evaluation of the fluctuation in computing power is completed to achieve an accurate evaluation of the chip computing power under conditions close to the actual situation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 A flow chart of a chip computing power testing method provided for one or more embodiments of this specification;

[0034] Figure 2 A schematic diagram of output computing power and required computing power changing over time provided for one or more embodiments of this specification;

[0035] Figure 3A schematic diagram of a process delay and required computing power changing over time provided for one or more embodiments of this specification;

[0036] Figure 4 A schematic diagram of the change of accuracy, output computing power and required computing power over time provided for one or more embodiments of this specification;

[0037] Figure 5 A schematic diagram of temperature, output computing power, and required computing power changing over time for one or more embodiments of this specification;

[0038] Figure 6 A schematic diagram of the structure of a chip computing power testing device provided for one or more embodiments of this specification. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0040] The output computing power, process delay and accuracy obtained by the DIMPS (Dhrystone Million Instructions Per Second per Megahertz) test are performance results obtained in a constant environment. This is a general practice in the industry, but this measurement method only represents the benchmark computing power of the chip. Since the chip design and operators will be optimized according to the application environment, the benchmark test cannot fully represent the actual computing power of the chip. For example, in the actual environment, only 50 computing power is needed when driving on a flat road. If you only look at the benchmark computing power, any computing power greater than 50 will do. But in the actual scenario, it is not as simple as driving on a flat road. Sudden braking, turning, and uphill and downhill are all common changes. Each scenario has different required computing power, which means that the required computing power in the actual scenario is constantly changing. The constant change of the required computing power cannot be solved by relying on the benchmark computing power. When the required computing power changes, the output computing power of the chip must also change. In this process, the output computing power cannot always match the required computing power. This mismatch is the computing power fluctuation. Therefore, the computing power fluctuation is a direct response to the chip performance in the actual scenario.

[0041] In order to evaluate the computing power fluctuation, the present application embodiment provides a computing power testing method, such as Figure 1As shown, the following steps are included:

[0042] Step 1: Determine the test environment of the chip to be tested.

[0043] In an embodiment of the present application, in order to simulate a real environment, the computing power required by the chip in the test environment changes according to preset rules.

[0044] Step 2: Run the chip to be tested in the test environment.

[0045] In the embodiment of the present application, the chip is tested in an environment where the required computing power is constantly changing. Specifically, multiple curves, multiple slopes or multiple road conditions can be set in the test environment to achieve the continuous change of the required computing power.

[0046] The method to set up the scene is:

[0047] S1. Determine the data collection location categories: roads, cities, residents, campuses, and pedestrians.

[0048] S2. Determine the type of data collected: grayscale image (png), color image (png), 3D velodyne point cloud (bin), GPS / IMU data (txt), calibration file, label file (xml).

[0049] S3. Expand the data type description:

[0050] Column 1 String: object category, mainly including 8 categories, cars, vans, trucks, pedestrians, seated people, cyclists, trams, and miscellaneous items.

[0051] Column 2 Float: whether it is truncated, the value is between 0 and 1.

[0052] Column 3 Int: Whether it is occluded (Occluded), using 0, 1, 2, 3 to indicate the degree of occlusion.

[0053] Column 4 Rad: Observation angle alpha, expressed in radians, ranging from -π to π.

[0054] Columns 5-8 Float: object 2D bbox, xmin, ymin, xmax, ymax.

[0055] Columns 9-11 Float: object 3D size, h, w, l.

[0056] Columns 12-14 Float: Object position, x, y, z in the camera coordinate system.

[0057] Column 15 Rad: The spatial orientation of the object, which represents the angle between the object's forward direction and the x-axis of the camera coordinate system, ranging from -π to π.

[0058] Column 16Float: confidence score.

[0059] By the above method, various scenes and road conditions can be simulated in the test environment. It should be noted that the above embodiment is a preferred solution of the present application, and those skilled in the art can think of other methods to realize various scenes and road conditions in the simulated environment.

[0060] Step 3: For the chip to be tested that is in operation, collect the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

[0061] In an embodiment of the present application, the first change data is used to characterize the data of chip temperature changing over time, and the second change data is used to characterize the data of output computing power changing over time.

[0062] For the first change data, based on the simulation technology in step 2, a virtual sensor can be set to collect the temperature of the chip. Temperature can significantly affect the performance of the chip. In actual scenarios, the temperature of the chip will inevitably rise, and the performance of the chip will inevitably change. Therefore, temperature is the main factor affecting the fluctuation of computing power.

[0063] For the second change data, the output computing power is the amount of data that the chip can process per unit time, which reflects the computing power of the chip. The chip has a variety of computing modules, such as: computing unit (CPU), graphics processing unit (GPU), neural computing unit (NPU), etc., and this application mainly tests the computing power of the computing unit (CPU) in the chip. The output computing power can be measured using special software, such as benchmark.

[0064] Regarding process delay, process delay is the waiting time experienced by the chip to complete instructions, algorithms and processing time. It takes time to read and store data inside the chip. After completing an instruction, the computing unit needs to complete the storage of old data and the reading of new data before it can perform operations on new data. This period of time is the process delay. Therefore, process delays will cause fluctuations in computing power. In actual scenarios, process delays come from the following four aspects: 1. Instruction delay: the time required from the instruction being taken out to the completion of execution; 2. Data delay: the time required to read data from memory or other storage devices; 3. Communication delay: the time required for communication between cores in a multi-core processor; 4. Cache delay: the delay when accessing the CPU cache. It can be seen from this that in actual scenarios, process delays will be more obvious and have a more obvious impact on computing power fluctuations. Process delay is the difference between the actual value and the theoretical value of the data processed by the chip.

[0065] As for accuracy, it does not actually affect the computing power output, but in the process of testing and application, the erroneous data will be discarded by default, so the higher the accuracy of the chip during the calculation process means the higher the output computing power, and the less computing power is lost in dealing with dynamic scenarios. In addition, the accuracy is a comprehensive reflection of the performance of each module in the chip, but in actual scenarios, as the chip temperature increases, the performance of each module in the chip changes, which will cause the accuracy of the chip to fluctuate, and then cause computing power fluctuations during the test process. The accuracy rate is the ratio of the erroneous data output by the chip to the total data output within a certain period of time.

[0066] Step 4: Evaluate the degree of fluctuation of the computing power of the chip to be tested based on the first change data, the second change data, the process delay and the accuracy of the chip to be tested.

[0067] In the embodiments of the present application, as described above, in actual scenarios, the first change data, the second change data, the process delay and the accuracy rate all have an impact on the fluctuation of computing power. Therefore, it is possible to select one or more of the first change data, the second change data, the process delay and the accuracy rate to evaluate the fluctuation of computing power.

[0068] For example, accuracy and process delay can be used to evaluate the performance of the chip when switching between multiple scenarios from the dimension of computing power loss. The greater the computing power loss, the more likely it is that the computing power will fluctuate. Each chip has its own operating temperature range, and the changing temperature of the chip can be determined based on the first change data. Then, based on the changing temperature of the chip, the computing power fluctuation is determined. The faster the temperature changes and the closer it is to the chip's limit temperature, the greater the computing power fluctuation. The second change data can intuitively reflect the change in output computing power, so the amplitude of the change in computing power can be directly obtained. The greater the amplitude of the change in computing power, the greater the computing power fluctuation. In addition, the above evaluation methods can be arbitrarily combined to obtain a more objective evaluation.

[0069] Specifically, Figure 2As shown in the figure, as the computing power required by the scene changes, the first dotted red box on the left will find that the output computing power is later than the required computing power. The longer the delay, the higher the delay of the chip in responding to sudden changes in computing power. The second red dotted box on the left finds that when the required computing power decreases from 80 to 55, the chip output computing power also lags behind and will be lower than the required computing power. As the computing power recovers, it gradually increases, but soon the required computing power suddenly increases to 90. At this time, the output computing power gradually recovers and increases the computing power, and soon it can reach 90 computing power, indicating that the chip has a certain effect on the scene. The prediction ability, the faster the response, the stronger the prediction ability, and the smaller the corresponding computing power fluctuation; the third dotted box, in the process of computing power reduction, the output computing power is lower than the required computing power, but it quickly stabilizes to the same as the required computing power, indicating that the scheduling has predicted the future computing power changes and is consistent with the required computing power to reduce power consumption; the fourth red dotted box, there is also a sudden change in the required computing power. The reduction in computing power indicates that the core temperature or other factors affect the computing power instability at this time, but the output computing power soon gradually recovers to the required computing power. The shorter the recovery time, the smaller the computing power fluctuation. In addition, the sudden drop in the figure corresponds to the computing power loss. The smaller the drop, the smaller the computing power fluctuation.

[0070] like Figure 3 As shown in the figure, the process delay will increase with the increase of the required computing power, and the process delay will also decrease when the required computing power decreases. This change is consistent with the results of the normal test process. However, from the change degree of the process delay curve, from the process delay of the red dotted box in the figure, when the required computing power decreases from 75 computing power to 55 computing power, the process delay is higher than the process delay when the computing power rises to 44 computing power before 50 seconds; after the computing power decreases from 90 computing power to 55 computing power, the process delay is also higher than the process from 75 to 55. The reason for the above changes is that the chip temperature is getting higher and higher during the test, resulting in a large heat dissipation pressure inside the chip, and the process delay will also increase accordingly. When the required computing power returns to 55 in the later stage of the test, the process delay also becomes lower, but it does not return to the process delay when the chip temperature is low in the early stage of the test. Therefore, it can be seen that the chip temperature has a significant impact on the process delay, which shows that the chip temperature is an important factor affecting the computing power fluctuation, and it also shows that the computing power fluctuation can be evaluated in combination with the chip temperature and process delay.

[0071] like Figure 4As shown, the accuracy is related to the size of the required computing power, and will decrease accordingly as the demand increases. In the figure, since the accuracy will affect the output computing power efficiency (the higher the computing power efficiency, the lower the computing power loss), this will lead to a lag in computing power when the required computing power increases. When the required computing power decreases, the output computing power will also decrease accordingly. However, due to the problem of accuracy, when the required computing power drops to the lowest position, in order to reduce the impact of the accuracy, the output computing power will be lower, that is, when the computing power efficiency decreases, the output computing power decreases, resulting in an increase in computing power fluctuations. And as the required computing power stabilizes, the accuracy increases, and the output computing power will slowly climb to stability, that is, when the computing power efficiency increases, the output computing power increases, thereby reducing computing power fluctuations. During the test, the accuracy will also increase with the increase of the test pressure. In the later stage of the test, the accuracy will be lower under the same required computing power. This also affects the situation in which the output is higher than the required computing power at 250 seconds in this figure. This is because of the impact of reducing the accuracy. Therefore, for the accuracy, the stability of the chip computing power can also be evaluated from the ratio of the output computing power to the required computing power. The lower the ratio, the smaller the computing power fluctuation.

[0072] Like process delay, it also changes with the required computing power, but the higher the accuracy, the better. As the test process becomes longer, it will be found that under the same required computing power conditions, the accuracy in the later stage of the test is lower than that in the early stage of the test. This is related to the higher chip temperature in the later stage of the test. From the evaluation point of view, as the test progresses, the various chip parameters (process delay, output computing power, accuracy) change the least between the early and late stages under the same required computing power, and it can be considered that the output computing power reliability is higher. Therefore, it can be seen that the chip temperature has a significant impact on the accuracy, which shows that the chip temperature is an important factor affecting the computing power fluctuation, and it also shows that the computing power fluctuation can be evaluated in combination with the chip temperature and accuracy.

[0073] like Figure 5As shown in the figure, temperature is a parameter for observing the thermal power consumption of the chip. The chip's process capability, heat dissipation design, and stability can be evaluated. From the trend in the figure, we can see that when the required computing power is 75, the temperature can still be stable, indicating that the heat dissipation capacity can control the temperature under the condition of the required computing power of 75; when the required computing power reaches 90, the temperature and output computing power become higher, which is consistent with the physical characteristics of the chip. However, due to the limited heat dissipation, the temperature of this chip reaches 100 degrees Celsius, which is a peak value of the chip temperature. When the required computing power reaches 55 from 90, the temperature will not return to the previous temperature due to the problem of heat dissipation capacity. This will also cause the temperature to reach 100 when the later required computing power rises to 70. At this time point, it can be considered that the chip has reached the highest value of heat dissipation. At this time, it can be observed that the output computing power is higher than the required computing power, indicating that the chip has invested more computing power at this time to affect the temperature. Then, how much higher than the required computing power can be used to evaluate the stability of the chip output computing power.

[0074] It can be seen that the technical solution of this application simulates the actual scene by setting a constantly changing scene. When collecting the first change data, the second change data, the process delay and the accuracy, a data foundation is laid for improving the accuracy of evaluating the computing power fluctuation. Finally, the computing power fluctuation can be evaluated from multiple dimensions, thereby improving the applicability and accuracy of the computing power test.

[0075] In an embodiment of the present application, when determining the operating environment of the chip to be tested, the chip working environment temperature and the computing power percentage of the chip in the test environment are determined, where the computing power percentage is the percentage of the output computing power to the benchmark computing power.

[0076] Specifically, because multiple scenes need to be set during the test, and the ambient temperature of each scene may be different, for example, the temperature on a cloudy day is usually lower than that on a sunny day. Therefore, the ambient temperature will affect the final result. In order to eliminate this effect, this application defines a test change temperature to replace the chip temperature. The definition of the test temperature change is:

[0077] Chip operating temperature - test environment temperature = test change temperature

[0078] Therefore, when determining the operating environment of the chip to be tested, the chip operating environment temperature is determined.

[0079] The required computing power of the test simulation environment is set according to the percentage of the chip output computing power and the benchmark computing power. This setting avoids the influencing factor of different computing powers of chips of different sizes. At the same time, it can flexibly realize more scene changes while reducing the impact between different chip specifications.

[0080] In an embodiment of the present application, the test environment includes multiple scenes, and the required computing power of each scene is different; the chip required computing power changes according to preset rules, including: switching the multiple scenes according to a preset cycle or timing. As mentioned above, temperature change is an important influencing factor of computing power fluctuations, so the test computing power fluctuation requires changing the temperature of the chip during the test. In order to achieve this goal, the test environment needs to set up multiple scenes, and the required computing power of each scene is different. For example, flat roads and turns are two scenes in the test environment. When turning from flat roads, the required computing power of the chip increases, and the increase in required computing power means an increase in power, and the increase in power will cause the chip temperature to rise. Therefore, if the tester wants to see the computing power fluctuation of the chip during the process of increasing 10°C, 50 turns and 50 flat roads can be set, so that the temperature of the chip will gradually increase, so that the tester can obtain the corresponding data. Preferably, in order to ensure that the temperature can be steadily injured rather than rapidly increased, you can choose to turn once a minute, or a flat road scene followed by two turning scenes, so that the chip temperature can be guaranteed to grow steadily.

[0081] In the embodiment of the present application, the temperature of each scene in the test environment will change, that is, the temperature of each scene will vary. In order to make the computing power evaluation closer to the actual scene, the tester can analyze the computing power fluctuation for each scene in the test environment. Specifically, for each scene, according to the first change data and the second change data, determine the curve of the output computing power changing with the temperature; based on the curve of the computing power changing with the temperature, the process delay and the accuracy, evaluate the computing power fluctuation of the chip to be tested.

[0082] In order to illustrate the feasibility of the above solution, this application gives a specific example:

[0083] For the determined simulation scene object of "Rainy Mountain Road", the design of the change in computing power first defines that the appearance of the rainy day object means that the computing power in the simulation scene cannot be lower than 60% of the benchmark computing power of the test chip. When a curve appears, the required computing power will increase to 100% and maintain for the time used to pass the curve. After the curve, the required computing power will return to 60%. There are 100 curves in this "Rainy Mountain Road" scene. It is known that the operating temperature of the chip will increase as the computing power increases, so the test change temperature will also increase. As the test progresses, the temperature accumulation will cause the output computing power, process delays and accuracy to deteriorate. As the number of curve runs increases, the chip test working temperature will reach a constant temperature due to limited heat dissipation, and the output computing power, process delay and accuracy will also fluctuate less after the temperature becomes constant. Finally, the relative changes in the output computing power, process delay and accuracy at this time are compared with the benchmark computing power to judge the computing power reliability, such as the ratio of the output computing power change to the benchmark computing power change. The smaller the relative change, the smaller the computing power fluctuation. At the same time, the time required from the start of the chip test to the state of small computing power fluctuation is recorded. The longer the time used, the less the chip computing power is affected by temperature, and it can change flexibly with the computing power change, and the smaller the computing power fluctuation. The shorter the time required, the greater the chip is affected by temperature, and it will quickly reach the highest temperature and the computing power will deteriorate rapidly, indicating that the chip has poor flexibility in computing power allocation to cope with changing scenarios, and the greater the computing power fluctuation.

[0084] The present application embodiment provides a chip computing power testing device, such as Figure 6 As shown, it includes: a determination module 201, an operation module 202, a collection module 203 and a data processing module 204;

[0085] The determination module 201 is used to determine the test environment of the chip to be tested, in which the chip demand computing power changes according to a preset rule;

[0086] The running module 202 is used to run the chip to be tested in the test environment;

[0087] The acquisition module 203 is used to collect first change data, second change data, process delay and accuracy of the chip to be tested in operation, wherein the first change data is used to characterize the data of chip temperature change over time, and the second change data is used to characterize the data of output computing power change over time; and

[0088] The data processing module 204 is used to evaluate the fluctuation degree of the computing power of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

[0089] In the embodiment of the present application, the determination module 201 is used to determine the chip working environment temperature and the computing power percentage of the chip in the test environment, where the computing power percentage is the percentage of the output computing power to the benchmark computing power.

[0090] In the embodiment of the present application, the test environment includes multiple scenarios, each of which requires different computing power; and

[0091] The determination module 201 is used to switch the multiple scenes according to a preset cycle or time sequence.

[0092] In an embodiment of the present application, the data processing module 204 is used to determine a curve of output computing power changing with temperature based on the first change data and the second change data; determine the computing power loss based on the process delay and the accuracy; and evaluate the computing power fluctuation of the chip to be tested based on the curve of computing power changing with temperature and the computing power loss.

[0093] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the chip computing power testing method described in any of the above embodiments is implemented.

[0094] It should be noted that the embodiments of the storage medium in this specification and the embodiments of the blockchain-based service provision method in this specification are based on the same inventive concept. Therefore, the specific implementation of this embodiment can refer to the aforementioned corresponding implementation of the blockchain-based service provision method, and the repeated parts will not be repeated.

[0095] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0096] In the 1930s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0097] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0098] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0099] For the convenience of description, the above devices are described in terms of functions and are divided into various units. Of course, when implementing the embodiments of this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0100] It should be understood by those skilled in the art that one or more embodiments of this specification may be provided as a method, system or computer program product. Therefore, one or more embodiments of this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0101] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0102] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0104] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0105] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0106] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0107] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0108] One or more embodiments of the present specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of the present specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0109] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0110] The above description is only an embodiment of this document and is not intended to limit this document. For those skilled in the art, this document may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this document should be included in the scope of the claims of this document.

Claims

1. A chip computing power testing method, characterized in that include: Determine a test environment for the chip to be tested, in which the computing power required by the chip changes according to a preset rule; In the test environment, running the chip to be tested; For the chip to be tested that is in operation, first change data, second change data, process delay and accuracy of the chip to be tested are collected, wherein the first change data is used to characterize the data of chip temperature change over time, and the second change data is used to characterize the data of output computing power change over time; as well as The computing power fluctuation degree of the chip to be tested is evaluated according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

2. The method according to claim 1, characterized in that: Determine the operating environment of the chip to be tested, including: Determine the chip operating environment temperature and the computing power percentage of the chip in the test environment, where the computing power percentage is the percentage of the output computing power to the benchmark computing power.

3. The method according to claim 1, characterized in that The test environment includes multiple scenarios, each of which requires different computing power; and The chip computing power requirement changes according to the preset rules including: The multiple scenes are switched according to a preset cycle or sequence.

4. The method according to claim 3, characterized in that Collection process delays and accuracy include: Collect the process delay and accuracy in each of the described scenarios.

5. The method according to claim 4, characterized in that For each scenario, the computing power fluctuation degree of the chip to be tested is evaluated according to the first change data, the second change data, the process delay and the accuracy of the chip to be tested, including: Determine a curve of output computing power changing with temperature according to the first change data and the second change data; and The computing power fluctuation of the chip to be tested is evaluated according to the curve of the computing power changing with temperature, the process delay and the accuracy.

6. A chip computing power testing device, characterized in that include: Determine module, operation module, acquisition module and data processing module; The determination module is used to determine a test environment for the chip to be tested, in which the chip's required computing power changes according to a preset rule; The running module is used to run the chip to be tested in the test environment; The acquisition module is used to collect first change data, second change data, process delay and accuracy of the chip to be tested in operation, wherein the first change data is used to represent the data of chip temperature change over time, and the second change data is used to represent the data of output computing power change over time; and The data processing module is used to evaluate the degree of fluctuation of the computing power of the chip to be tested according to the first change data, the second change data, the process delay and the accuracy rate of the chip to be tested.

7. The device according to claim 6, characterized in that The determination module is used to determine the chip working environment temperature and the computing power percentage of the chip in the test environment, wherein the computing power percentage is the percentage of the output computing power to the reference computing power.

8. The device according to claim 6, characterized in that The test environment includes multiple scenarios, each of which requires different computing power; and The determining module is used to switch the multiple scenes according to a preset cycle or time sequence.

9. The device according to claim 6, characterized in that The data processing module is used to determine a curve of output computing power changing with temperature according to the first change data and the second change data; and determine computing power loss according to the process delay and the accuracy rate; And based on the curve of the computing power changing with temperature and the computing power loss, the computing power fluctuation of the chip to be tested is evaluated.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the chip computing power testing method according to any one of claims 1 to 5 is implemented.

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