Memory data real-time monitoring and transmission method, circuit and system and electronic equipment
By introducing CRC check bits into the memory and outputting error correction status in real time, the problem that existing memory cannot monitor and correct stored data errors in real time is solved, efficient data monitoring and error correction are achieved, and hardware costs are reduced.
Patent Information
- Application Number
- CN202411967314.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
When existing memory handles bad blocks, it is impossible to monitor and correct errors in stored data in real time, and increases hardware costs, limiting its application scenarios.
By introducing a CRC check bit into the memory, the error correction state of the memory is output in real time, real-time monitoring and error correction of memory output data is realized. This method does not require additional hardware costs and is compatible with existing transmission protocols.
Real-time monitoring and error correction of memory data is realized, reducing system integration difficulty, reducing chip production costs, and improving data reliability.
Smart Images
Figure CN119883816A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of circuit design, and in particular to a method, circuit, system and electronic equipment for real-time monitoring and transmission of memory data. Background Art
[0002] Various types of non-volatile storage devices are used in various existing processing systems to maintain and store data or instruction data. The reliability of memory storage data is crucial to the performance of the entire system. Otherwise, not only will the system fail to operate, but it will also cause irreversible consequences in certain scenarios with high-speed transmission and extremely high reliability requirements.
[0003] Generally, the storage reliability of storage units is improved mainly through process improvements to reduce the occurrence of bad blocks, while the reasonable handling of bad blocks requires improvements in the memory circuit design and storage system design. The main means of handling bad blocks that are more common are redundant bit replacement (Redundancy Repair) and error detection and correction (Error Correction Code, ECC). Redundant bit replacement means that each group of storage units will have a number of redundant bits during chip design. When there are failed bits in this group of storage units, they can be replaced with redundant bits. Redundant bit replacement is configured and set by testing when the chip leaves the factory, and cannot be changed during the customer's use of the chip, that is, redundant bit replacement cannot handle new failed bits that appear during the use of the memory. Error detection and correction is a dynamic processing method for failed bits. The error detection and correction function can be implemented through software or hardware. The hardware implementation can be realized in the host (controller) or in the memory.
[0004] When implementing error checking and correction functions inside the memory, the memory needs to provide a way for the host (controller) to query the error correction status. The existing methods mainly include status register query and specific pin signal output. The status register query method has hysteresis, and the specific pin signal output increases the system hardware cost and is limited by the packaging and the wiring between the host (controller) and the memory. Its application scenarios are limited and the system cost increases. These problems need to be solved urgently. Summary of the invention
[0005] In view of the deficiencies in the prior art, the present invention provides a method, circuit, system and electronic device for real-time monitoring and transmission of storage data, which can achieve real-time storage data monitoring without increasing additional hardware costs.
[0006] The present invention solves the technical problem by adopting the following technical solution:
[0007] The present invention provides a method for real-time monitoring and transmission of memory data, the method comprising:
[0008] Execute the storage instruction, generate storage data with check error correction bits based on the input data encoding and write them into the storage cell array;
[0009] Execute the read instruction, read the storage data in the target storage cell array, decode to obtain preliminary output data and check error correction data;
[0010] Based on the check and error correction data, check and correct the preliminary output data to generate channel data and error correction status data;
[0011] A CRC check code is generated based on the channel data and the error correction status data, and the channel data, the error correction status data and the CRC check code are output according to a preset timing matching.
[0012] Preferably, the step of performing check and error correction on the preliminary output data based on the check and error correction data to generate channel data and error correction status data comprises:
[0013] Based on the verification and error correction data, determine whether the preliminary output data is incorrect.
[0014] If there is an error, the position information of the abnormal data in the preliminary output data is obtained, and the data on the position information is inverted, and the data after the operation is defined as the channel data;
[0015] Otherwise, the preliminary data is directly defined as channel data, and the error correction status data is output.
[0016] Preferably, when it is determined that the preliminary output data is erroneous based on the verification and error correction data, the method further includes:
[0017] Based on the data after the inversion operation, the original stored data in the memory cell array is reconfigured.
[0018] Preferably, the generation of the stored data with the check error correction bit based on the input data encoding is generated by a coding algorithm including Hamming code;
[0019] The error correction status data is used to indicate whether the channel data is erroneous.
[0020] The present invention also provides a memory circuit capable of executing the steps of the data real-time monitoring transmission method as described above, wherein the memory circuit comprises an interface module, a storage cell array module, an encoding write control module, a decoding read control module, a CRC module and an output control module, wherein:
[0021] The interface module is configured to communicate with the outside to input or output data;
[0022] The memory cell array module is configured to store data;
[0023] The encoding and writing control module is configured to generate storage data with check error correction bits based on input data encoding, and implement control of writing the storage data into the storage cell array module;
[0024] The decoding read control module is configured to read the storage data in the target storage cell array, decode to obtain preliminary output data and check and error correction data, and perform check and error correction on the preliminary output data based on the check and error correction data to generate channel data and error correction status data;
[0025] The CRC module is configured to generate a CRC check code based on the channel data and the error correction status data;
[0026] The output control module is configured to output channel data, error correction status data and CRC check code to the interface module according to a preset timing matching.
[0027] Preferably, the decoding and reading control module is further configured to:
[0028] Based on the verification and error correction data, determine whether the preliminary output data is incorrect.
[0029] If there is an error, the position information of the abnormal data in the preliminary output data is obtained, and the data on the position information is inverted, and the data after the operation is defined as the channel data;
[0030] Otherwise, the preliminary data is directly defined as channel data, and the error correction status data is output;
[0031] At the same time, based on the data after the inversion operation, the original storage data in the storage cell array is reconfigured.
[0032] The present invention also provides a high-speed and stable data transmission system, comprising:
[0033] A memory circuit as described above;
[0034] A controller is coupled to the memory circuit, and is configured to issue a storage instruction or a read instruction to the memory chip, and to send input data to the interface module or receive output data in real time.
[0035] The present invention also provides a chip, comprising the memory circuit as described above.
[0036] The present invention also provides an electronic device, comprising:
[0037] at least one processor; and
[0038] a memory communicatively connected to the at least one processor; wherein,
[0039] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the memory data real-time monitoring and transmission method as described above.
[0040] The present invention also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the memory data real-time monitoring and transmission method as described above.
[0041] Compared with the prior art, the present invention has the following beneficial effects:
[0042] The memory data real-time monitoring and transmission method of the present invention can output the memory error correction status in real time with the help of CRC check bits, so as to achieve real-time monitoring of whether the memory output data is correct or not. On the basis of realizing the check and error correction functions, the transmission data and the storage data of the storage array unit are synchronously corrected and updated. It is compatible with the existing transmission protocol and does not require additional pins, which greatly reduces the difficulty of later system integration. The memory circuit structure designed based on this method is simple and reasonable, can effectively reduce the production cost of the chip, and has practical value in a real sense.
[0043] Other outstanding essential features and significant improvements of the present invention compared to the prior art are further described in detail in the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:
[0045] Figure 1 It is a schematic diagram of the transmission protocol of the CRC check bit;
[0046] Figure 2 It is a signal output schematic diagram when the error correction state is output with a specific pin signal;
[0047] Figure 3 A schematic diagram of the connection relationship between the host and the memory when the error correction state is output with a specific pin signal;
[0048] Figure 4 This is a schematic diagram of signal output when the rising edge is output in Example 1;
[0049] Figure 5 This is a schematic diagram of signal output when the falling edge is output in Example 1;
[0050] Figure 6 Schematic diagram of the structure of the memory circuit in Example 2. DETAILED DESCRIPTION
[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0052] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that a person of ordinary skill in the art may use different names to refer to the same component. The specification and claims of this application do not use differences in names as a way to distinguish components, but use substantial differences in the functions of components as the criterion for distinguishing components. As used in the specification and claims of this application, "including" or "comprising" is an open term, which should be interpreted as "including but not limited to" or "including but not limited to". The embodiments described in the specific implementation section are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.
[0053] In addition, it is known to those skilled in the art that various aspects of the present invention may be implemented as a system, method or computer program product. Therefore, various aspects of the present invention may be specifically implemented in the form of a combination of software and hardware, which may be collectively referred to herein as a "circuit", "module" or "system". In addition, in some embodiments, various aspects of the present invention may also be implemented in the form of a computer program product in one or more microcontroller-readable media, which contains program code readable by the microcontroller.
[0054] Example 1
[0055] Before introducing the content of this example, the theoretical and technical basis and design intention of the implementation scheme of this embodiment are further introduced:
[0056] On the one hand, in addition to the storage unit itself causing data reliability problems, the integrity of the data transmission channel will also affect the reliability of the data. Generally, a cyclic redundancy check (CRC), such as a parity check, is introduced during data transmission to improve the transmission integrity between the storage and the host (controller), thereby improving the reliability of the storage data. This method transmits an additional CRC check bit after transmitting a certain amount of data, such as Figure 1 As shown, after receiving the data and the CRC check bit, the host can check whether the data is transmitted correctly through the agreed algorithm. Existing memory chips, especially high-speed serial port memory chips, are increasingly using this transmission protocol including CRC check.
[0057] On the other hand, the reason why there is a lag in obtaining the internal error correction status of the memory by querying the memory status register is mainly because:
[0058] If the host (controller) or processor continuously reads the data in the memory and processes or executes it, when the erroneous data causes the system to interrupt or program error, the host (controller) or processor can only query the memory status register afterwards to confirm whether the memory data is erroneous. If the host (controller) or processor reads the memory status register after reading the data of the error correction code encoding length, only when the error correction status indicates that the data is correct will this part of the data be processed or executed, which will greatly reduce the system efficiency and performance.
[0059] In addition, when a specific pin signal is used to output the error correction status, the hysteresis disadvantage of the status register query can be solved. Taking the serial port memory as an example, the memory outputs the error correction status to an additional pin while outputting data, such as Figure 2 As shown, the level or change edge of this pin can indicate the error correction status. Figure 2 In the example, a low level indicates that the current data is wrong and a high level indicates that the current data is correct. The host (controller) detects the state of this pin while receiving the memory data. If the error correction code status pin is detected to be low, the host (controller) or processor knows that the data of the current error correction code encoding length is wrong and unusable, and the exception can be handled in time. However, this method adds additional pins, thereby increasing the integration cost of the host (controller) and the memory, such as Figure 3 At the same time, some memory packaging forms cannot increase the pins for outputting error correction status, such as 4-wire serial port memory with 8-pin packaging, where power, ground, 4 data lines, chip select and clock have already occupied all 8 pins. Therefore, outputting error correction status with a specific pin signal can solve the hysteresis disadvantage of status register query, but its application scenarios are limited and increase system cost.
[0060] In view of this, this embodiment provides a method for real-time monitoring and transmission of storage data, the method comprising:
[0061] Execute the storage instruction, generate storage data with check and error correction bits based on the input data encoding and write them into the storage cell array. In this embodiment, a coding algorithm including Hamming code can be used to generate storage data with check and error correction bits, that is, Hamming code and its variants can be used as the coding algorithm of this embodiment, such as SEC (Single Error Correct), SEC-DEC (Single Error Correction-Double Error Detection) and other algorithms. Similar to other error checking codes, Hamming code also uses the concept of parity check bits. By adding some bits after the data bits, the validity of the data can be verified. By using more than one check bit, the Hamming code can not only verify whether the data is valid, but also indicate the error position when the data is wrong, which will not be repeated here;
[0062] Execute the read instruction, read the storage data in the target storage cell array, decode to obtain preliminary output data and check error correction data;
[0063] Based on the check and error correction data, the preliminary output data is checked and corrected to generate channel data and error correction status data. In this embodiment, the steps specifically include:
[0064] Based on the verification and error correction data, determine whether the preliminary output data is incorrect.
[0065] If there is an error, the position information of the abnormal data in the preliminary output data is obtained, and the data on the position information is inverted, and the data after the operation is defined as channel data. At the same time, based on the data after the inversion operation, the original storage data in the storage unit array is reconfigured;
[0066] Otherwise, the preliminary data is directly defined as channel data, and error correction status data is output. In this embodiment, the error correction status data is used to indicate whether the channel data is erroneous;
[0067] Generate CRC checksum based on channel data and error correction status data, and output channel data, error correction status data and CRC checksum according to preset timing matching. CRC is the most commonly used error checking code in the field of data communication. Its characteristic is that the length of information field and check field can be arbitrarily selected. The process of using CRC for error detection can be simply described as follows: at the sending end, according to the k-bit binary code sequence to be transmitted, an r-bit supervision code (CRC code) for verification is generated according to certain rules, attached to the original information, forming a new binary code sequence with a total of k+r bits, and then sent out. At the receiving end, the information code and the CRC code are checked according to the rules followed to determine whether there is an error in the transmission. I will not go into details here.
[0068] In order to further explain in detail the method steps of the memory data real-time monitoring transmission method of this embodiment, taking the single-bit error correction of 16-bit data bits as an example, it is further explained as follows:
[0069] By Hamming inequality:
[0070] 2 k ≥n+k
[0071] It can be seen that n = 16 data bits require k = 5 check bits, where the check bit (P m , m=1,2,3……k) are placed in the new code 2 m-1 ,m=1,2,3……k, the data bit (D j , j=1,2,3……n) insert the new code in the original order, as shown in Table 1 below:
[0072] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 <![CDATA[P1]]> <![CDATA[P2]]> <![CDATA[D1]]> <![CDATA[P3]]> <![CDATA[D2]]> <![CDATA[D3]]> <![CDATA[D4]]> <![CDATA[P4]]> <![CDATA[D5]]> <![CDATA[D6]]> <![CDATA[D7]]> <![CDATA[D8]]> <![CDATA[D9]]> <![CDATA[D 10 ]]> <![CDATA[D 11 ]]> <![CDATA[P5]]> <![CDATA[D 12 ]]> <![CDATA[D 13 ]]> <![CDATA[D 14 ]]> <![CDATA[D 15 ]]> <![CDATA[D 16 ]]>
[0073] Table 1
[0074] The check bit P1 is obtained by differentiating or differentiating the first bit (the check bit is initially 0 when encoded), 3, 5, 7, 9, 11, 13, 15, 17, 19, and 21 of the new code; the check bit P2 is obtained by differentiating or differentiating the second bit (the check bit is initially 0 when encoded), 3, 6, 7, 10, 11, 14, 15, 18, and 19 of the new code; the check bit P3 is obtained by differentiating or differentiating the fourth bit (the check bit is initially 0 when encoded), 5, 6, 7, 12, 13, 14, 15, 20, and 21 of the new code; the check bit P4 is obtained by differentiating or differentiating the eighth bit (the check bit is initially 0 when encoded), 9, 10, 11, 12, 13, 14, and 15 of the new code; the check bit P5 is obtained by differentiating or differentiating the sixteenth bit (the check bit is initially 0 when encoded), 17, 18, 19, 20, and 21 of the new code, that is:
[0075] P1=0^D1^D2^D4^D5^D7^D9^D 11 ^D 12 ^D 14 ^D 16
[0076] P2=0^D1^D3^D4^D6^D7^D 10 ^D 11 ^D 13 ^D 14
[0077] P3=0^D2^D3^D4^D8^D9^D 10 ^D 11 ^D 15 ^D 16
[0078] P4=0^D5^D6^D7^D8^D9^D 10 ^D 11
[0079] P5=0^D 12 ^D 13 ^D 14 ^D 15 ^D 16
[0080] Taking a specific coded data as an example, the 16-bit input data is 1101001100011110, and the encoded storage data is shown in Table 2:
[0081] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 <![CDATA[P1]]> <![CDATA[P2]]> <![CDATA[D1]]> <![CDATA[P3]]> <![CDATA[D2]]> <![CDATA[D3]]> <![CDATA[D4]]> <![CDATA[P4]]> <![CDATA[D5]]> <![CDATA[D6]]> <![CDATA[D7]]> <![CDATA[D8]]> <![CDATA[D9]]> <![CDATA[D 10 ]]> <![CDATA[D 11 ]]> <![CDATA[P5]]> <![CDATA[D 12 ]]> <![CDATA[D 13 ]]> <![CDATA[D 14 ]]> <![CDATA[D 15 ]]> <![CDATA[D 16 ]]> <![CDATA[P1]]> <![CDATA[P2]]> 1 <![CDATA[P3]]> 1 0 1 <![CDATA[P4]]> 0 0 1 1 0 0 0 <![CDATA[P5]]> 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0
[0082] Table 2
[0083] Assume that the data bit D5 of the storage data in the storage cell array is erroneously flipped from 0 to 1, that is, the data read is as shown in Table 3:
[0084] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 <![CDATA[P1]]> <![CDATA[P2]]> <![CDATA[D1]]> <![CDATA[P3]]> <![CDATA[D2]]> <![CDATA[D3]]> <![CDATA[D4]]> <![CDATA[P4]]> <![CDATA[D5]]> <![CDATA[D6]]> <![CDATA[D7]]> <![CDATA[D8]]> <![CDATA[D9]]> <![CDATA[D 10 ]]> <![CDATA[D 11 ]]> <![CDATA[P5]]> <![CDATA[D 12 ]]> <![CDATA[D 13 ]]> <![CDATA[D 14 ]]> <![CDATA[D 15 ]]> <![CDATA[D 16 ]]> 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 1 0
[0085] Table 3
[0086] The data read above is decoded to obtain preliminary output data and check error correction data, as shown in Table 4:
[0087] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 <![CDATA[P′1]]> <![CDATA[P′2]]> <![CDATA[D1]]> <![CDATA[P′3]]> <![CDATA[D2]]> <![CDATA[D3]]> <![CDATA[D4]]> <![CDATA[P′4]]> <![CDATA[D5]]> <![CDATA[D6]]> <![CDATA[D7]]> <![CDATA[D8]]> <![CDATA[D9]]> <![CDATA[D 10 ]]> <![CDATA[D 11 ]]> <![CDATA[P′5]]> <![CDATA[D 12 ]]> <![CDATA[D 13 ]]> <![CDATA[D 14 ]]> <![CDATA[D 15 ]]> <![CDATA[D 16 ]]> 1 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0
[0088] Table 4
[0089] The generation process of the checksum and error correction data is as follows:
[0090] P′1=P1^D1^D2^D4^D5^D7^D9^D 11 ^D 12 ^D 14 ^D 16 =1
[0091] P′2=P2^D1^D3^D4^D6^D7^D 10 ^D 11 ^D 13 ^D 14 =0
[0092] P′3=P3^D2^D3^D4^D8^D9^D 10 ^D 11 ^D 15 ^D 16 =0
[0093] P′4=P4^D5^D6^D7^D8^D9^D 10 ^D 11 =1
[0094] P′5=P5^D 12 ^D 13 ^D 14 ^D 15 ^D 16 =0
[0095] Based on the checksum error correction data 5'b01001, it is found that the error occurs at the position of the newly encoded 5'b01001, that is, the 9th bit (D5). Inverting this bit will give the correct data after error correction, as shown in Table 5:
[0096] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 <![CDATA[P′1]]> <![CDATA[P′2]]> <![CDATA[D1]]> <![CDATA[P′3]]> <![CDATA[D2]]> <![CDATA[D3]]> <![CDATA[D4]]> <![CDATA[P′4]]> <![CDATA[D5]]> <![CDATA[D6]]> <![CDATA[D7]]> <![CDATA[D8]]> <![CDATA[D9]]> <![CDATA[D 10 ]]> <![CDATA[D 11 ]]> <![CDATA[P′5]]> <![CDATA[D 12 ]]> <![CDATA[D 13 ]]> <![CDATA[D 14 ]]> <![CDATA[D 15 ]]> <![CDATA[D 16 ]]> 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0
[0097] Table 5
[0098] The original stored data in the storage unit array is reconfigured based on the correct data. The correct data after error correction is the channel data. After the error correction is completed, error correction status data is generated to indicate that the channel data is correct. Then, a CRC check code is generated with the channel data and the error correction status data, and the channel data, error correction status data and CRC check code are output according to the preset timing matching. This encoding method is suitable for application scenarios where high-speed transmission and transmission channel noise are large and communication is unstable. An example of an agreed timing is as follows Figure 4 As shown in the figure, the channel data and error correction status data are output on the rising edge of the clock signal, and the CRC check code data is output on the falling edge of the clock signal. The output sequence is to output the channel data first, then the error correction status data, and finally the CRC check code data. Of course, the channel data and error correction status data can also be output on the falling edge of the clock signal, and the CRC check code data can be output on the rising edge of the clock signal, such as Figure 5 shown.
[0099] The memory data real-time monitoring and transmission method provided in this embodiment can output the memory error correction status in real time with the help of CRC check bits, so as to achieve real-time monitoring of the correctness of the memory output data. On the basis of realizing the check and error correction functions, the transmission data and the storage data of the storage array unit are synchronously corrected and updated.
[0100] Example 2
[0101] This embodiment provides a memory circuit capable of executing the steps of the data real-time monitoring transmission method in Embodiment 1, such as Figure 6 As shown, the memory circuit includes an interface module 1, a storage cell array module 2, an encoding and writing control module 3, a decoding and reading control module 4, a CRC module 5 and an output control module 6, wherein:
[0102] The interface module 1 is configured to communicate with the outside to input or output data;
[0103] The memory cell array module 2 is configured to store data;
[0104] The encoding and writing control module 3 is configured to generate storage data with check and error correction bits based on the input data encoding, and realize the control of writing the storage data into the storage unit array module 2, that is, the encoding and writing control module 3 has two parts of functions, one part of the encoding module function, and one part of the writing control function. Of course, the two parts of functions can also be realized by two independent modules, which will not be repeated here;
[0105] The decoding read control module 4 is configured to read the storage data in the target storage unit array module 2, decode to obtain the preliminary output data and the check and error correction data, and perform check and error correction on the preliminary output data based on the check and error correction data to generate channel data and error correction status data;
[0106] The CRC module 5 is configured to generate a CRC check code based on the channel data and the error correction status data;
[0107] The output control module 6 is configured to output channel data, error correction status data and CRC check code to the interface module 1 according to a preset timing matching. The output control module 6 can be an independent module or integrated with the interface module 1, which will not be described in detail here.
[0108] Example 3
[0109] This embodiment provides a high-speed and stable data transmission system, including:
[0110] The memory circuit as in Embodiment 2;
[0111] The controller is coupled to the memory circuit and is configured to issue a storage instruction or a read instruction to the memory chip, and to send input data to the interface module or receive output data in real time.
[0112] Example 4
[0113] This embodiment provides a chip on which the memory circuit as in Embodiment 2 is integrated.
[0114] Example 5
[0115] This embodiment provides an electronic device, including:
[0116] at least one processor; and
[0117] a memory communicatively connected to the at least one processor; wherein,
[0118] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the memory data real-time monitoring and transmission method described in Example 1.
[0119] Example 4
[0120] This embodiment provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the memory data real-time monitoring and transmission method as described in Example 1.
[0121] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0122] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A method for real-time monitoring and transmission of storage data, characterized in that: The method comprises: Execute the storage instruction, generate storage data with check error correction bits based on the input data encoding and write them into the storage cell array; Execute the read instruction, read the storage data in the target storage cell array, decode to obtain preliminary output data and check error correction data; Based on the check and error correction data, check and correct the preliminary output data to generate channel data and error correction status data; A CRC check code is generated based on the channel data and the error correction status data, and the channel data, the error correction status data and the CRC check code are output according to a preset timing matching.
2. A method for real-time monitoring and transmission of memory data according to claim 1, characterized in that: The step of performing check and error correction on the preliminary output data based on the check and error correction data to generate channel data and error correction status data comprises: Based on the verification and error correction data, determine whether the preliminary output data is incorrect. If there is an error, the position information of the abnormal data in the preliminary output data is obtained, and the data on the position information is inverted, and the data after the operation is defined as the channel data; Otherwise, the preliminary data is directly defined as channel data, and the error correction status data is output.
3. A memory data real-time monitoring and transmission method according to claim 2, characterized in that: When the preliminary output data is determined to be erroneous based on the verification and error correction data, it also includes: Based on the data after the inversion operation, the original stored data in the memory cell array is reconfigured.
4. A method for real-time monitoring and transmission of storage data according to claim 1, characterized in that: The storage data with check error correction bits generated based on the input data encoding is generated by using an encoding algorithm including Hamming code; The error correction status data is used to indicate whether the channel data is erroneous.
5. A memory circuit, characterized in that: The method can execute the steps of the data real-time monitoring transmission method as described in any one of claims 1 to 4, wherein the memory circuit includes an interface module, a storage cell array module, an encoding write control module, a decoding read control module, a CRC module and an output control module, wherein: The interface module is configured to communicate with the outside to input or output data; The memory cell array module is configured to store data; The encoding and writing control module is configured to generate storage data with check error correction bits based on input data encoding, and implement control of writing the storage data into the storage cell array module; The decoding read control module is configured to read the storage data in the target storage unit array module, decode to obtain preliminary output data and check and error correction data, and perform check and error correction on the preliminary output data based on the check and error correction data to generate channel data and error correction status data; The CRC module is configured to generate a CRC check code based on the channel data and the error correction status data; The output control module is configured to output channel data, error correction status data and CRC check code to the interface module according to a preset timing matching.
6. The memory circuit according to claim 5, characterized in that: The decoding read control module is also configured to: Based on the verification and error correction data, determine whether the preliminary output data is incorrect. If there is an error, the position information of the abnormal data in the preliminary output data is obtained, and the data on the position information is inverted, and the data after the operation is defined as the channel data; Otherwise, the preliminary data is directly defined as channel data, and the error correction status data is output; At the same time, based on the data after the inversion operation, the original storage data in the storage cell array is reconfigured.
7. A high-speed and stable data transmission system, characterized in that: include: The memory circuit according to any one of claims 5 to 6; A controller is coupled to the memory circuit, and is configured to issue a storage instruction or a read instruction to the memory chip, and to send input data to the interface module or receive output data in real time.
8. A chip, characterized in that: The invention is integrated with a memory circuit comprising the memory circuit as claimed in any one of claims 5 to 6.
9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the memory data real-time monitoring and transmission method according to any one of claims 1 to 4.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the memory data real-time monitoring and transmission method according to any one of claims 1 to 4.