Control management system and method, electronic equipment and storage medium

Abstract

The invention provides a control management system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system is applied to an ARM server, and the system comprises an out-of-band JTAG link management module used for monitoring a plurality of JTAG signals output by an ARM processor system-on-chip, identifying fault information of the ARM processor system-on-chip, and sending the fault information to a BMC; the JTAG module is also used for generating a JTAG link routing control signal; the ARM processor system-on-chip is used for sending a plurality of JTAG signals to the out-of-band JTAG link management module; the JTAG link switching module is also used for receiving and responding to the JTAG link routing control signal and switching the topology mode of the JTAG link; and the BMC is used for receiving and recording the fault information and sending the fault information to the remote operation and maintenance terminal. According to the technical scheme, the core problems that in a traditional scheme, manual point-by-point detection efficiency is low, physical operation dependency is high, and CPU downtime monitoring fails are solved, operation and maintenance delay and cost are remarkably reduced, and high-reliability and low-delay operation and maintenance support is provided for ARM server large-scale deployment.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a control management system, method, electronic device and storage medium. Background Art

[0002] The rapid development of the digital computing industry has driven the expansion of data centers, and the requirements for server reliability and operation and maintenance efficiency have continued to increase. Compared with traditional X86 platform servers, ARM platform servers have become the core choice for high-energy efficiency scenarios due to their advantages such as multiple cores, small size, and low power consumption. However, the large-scale deployment of ARM servers also faces challenges such as low fault location efficiency and complex operation and maintenance. Especially when there is an abnormal startup (such as a firmware crash) or a downtime, traditional JTAG link management relies on manual point-by-point detection, resulting in operation and maintenance delays, which seriously restricts business continuity and becomes a key bottleneck for large-scale commercial use of ARM servers.

[0003] At present, conventional ARM servers use a point-to-point direct connection JTAG (Joint Test Action Group) topology, and the JTAG module is directly connected to the physical pins, which has significant defects, including: 1. The fixed unidirectional path cannot dynamically switch routes or collect signals in parallel. Troubleshooting requires capturing data from each module, which is inefficient; 2. It relies on physical operations and has no remote debugging function. Abnormal information cannot be transmitted in real time, and on-site intervention is required, which is costly; 3. The control logic relies on CPU in-band processing. When the CPU crashes, the monitoring function fails, which is high-risk; 4. The fault code is fragmented and stored in different JTAG channels, which is difficult to integrate and analyze. Summary of the invention

[0004] The present disclosure provides a control management system, method, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a control management system is provided, the system being applied to an ARM server, the system comprising: an out-of-band JTAG link management module, an ARM processor system-on-chip, and a baseboard management controller BMC; the out-of-band JTAG link management module is communicatively connected to the ARM processor system-on-chip and the BMC respectively; The out-of-band JTAG link management module is used to monitor multiple JTAG signals output by the ARM processor system-on-chip after the ARM server is powered on, identify fault information of the ARM processor system-on-chip during startup and operation, and send the fault information to the BMC; and is also used to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip; The ARM processor system-on-chip is used to send multiple JTAG signals to the out-of-band JTAG link management module after the ARM server is powered on, wherein the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; and is also used to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link; The BMC is used to receive and record the fault information, and send the fault information to a remote operation and maintenance end.

[0006] In one possible implementation, the out-of-band JTAG link management module is implemented by a complex programmable logic device CPLD or a field programmable gate array FPGA, and includes: a JTAG control module and a JTAG slave device module; The JTAG control module is used to monitor multiple JTAG ports on the ARM processor system-on-chip to obtain corresponding multiple JTAG signals, analyze the multiple JTAG signals in parallel through the CPLD or FPGA to obtain the fault information, and send the fault information to the JTAG slave device module; The JTAG slave device module is used to receive the fault information and send it to the BMC through a multiplexer.

[0007] In one possible implementation, the JTAG control module includes a monitoring unit and a fault judgment unit: The monitoring unit is used to monitor multiple JTAG ports of the ARM processor system-on-chip to obtain multiple JTAG signals; The fault judgment unit is used to detect whether the power-on completion indication signal of the ARM processor system-on-chip is normally issued when the JTAG signal fault is identified; If the power-on completion indication signal is not normally issued, determining first fault information; If the power-on completion indication signal is sent normally, a detection process is started for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

[0008] In one possible implementation manner, the fault judgment unit, when starting detection on the CPU management core and obtaining the detection result, is specifically used to: If the startup completion signal of the CPU management core is not detected within the preset time, determining the second fault information; If the startup completion signal of the CPU management core is detected within the preset time, it is determined that the ARM server is running normally.

[0009] In one possible implementation, the ARM processor system-on-chip includes a master CPU processor and a slave CPU processor; The master CPU processor and the slave CPU processor are respectively provided with a first general purpose input and output GPIO and a plurality of JTAG ports; The first GPIO is used to receive the JTAG link routing control signal; The multiple JTAG ports include at least: a debug access port, a peripheral management port, a power management port and an on-chip system port.

[0010] In one possible implementation, the slave CPU processor is provided with a presence signal output port for sending a presence output signal to the master CPU processor, BMC and CPLD or FPGA to detect whether the slave CPU processor is in place; If the slave CPU processor is in place, the JTAG control module reads the JTAG signal of the slave CPU processor and sends a JTAG link routing control signal; If the slave CPU processor is not in place, the JTAG control module stops reading the JTAG signal of the slave CPU processor and stops sending the JTAG link routing control signal to the slave CPU processor.

[0011] In one possible implementation, the BMC includes a JTAG master device module, which is used to receive fault information of the JTAG master device module, and record the fault information in a time record table through the BMC; The BMC is also used to generate alarm information based on the fault information and feed it back to the remote operation and maintenance end.

[0012] In one possible implementation manner, the JTAG master device module is further configured to send a firmware upgrade instruction or an information acquisition instruction to the CPLD or FPGA through the multiplexer.

[0013] In one possible implementation, the system further includes a local interface module, which is used for an external debugging terminal to connect to the out-band JTAG link management module through the local interface module to obtain the fault information; and is also used for the external debugging terminal to send a JTAG link routing control signal to the out-band JTAG link management module through the local interface module; the external debugging terminal is hardware or software connected to the ARM server.

[0014] According to a second aspect of the present disclosure, a control management method is provided, which is applied to an out-of-band JTAG link management module in an ARM server, wherein the out-of-band JTAG link management module is respectively connected to an ARM processor system on chip and a baseboard management controller BMC in communication, and the method comprises: After the ARM server is powered on, multiple JTAG signals output by the ARM processor system-on-chip are monitored, wherein the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; According to the multiple JTAG signals, identifying fault information of the ARM processor system on chip during startup and operation; The fault information is sent to the BMC, so that the BMC records the fault information and sends it to the remote operation and maintenance end.

[0015] In one possible implementation manner, the out-of-band JTAG link management module is implemented by a complex programmable logic device (CPLD) or a field programmable gate array (FPGA).

[0016] In one possible implementation, the ARM processor system-on-chip includes a master CPU processor and a slave CPU processor, the master CPU processor and the slave CPU processor are respectively provided with a first general purpose input and output GPIO and a plurality of JTAG ports, and the method further includes: Generate a JTAG link routing control signal and send it to the first GPIO of the ARM processor system on chip to switch the topology mode of the JTAG link; The multiple JTAG ports include at least: a debug access port, a peripheral management port, a power management port and an on-chip system port.

[0017] In one possible implementation, the monitoring of multiple JTAG signals output by the ARM processor system-on-chip includes: Monitoring multiple JTAG ports of the ARM processor system-on-chip to obtain corresponding multiple JTAG signals; The step of identifying fault information of the ARM processor system-on-chip during startup and operation according to the JTAG signal includes: By means of the CPLD or FPGA, the plurality of JTAG signals are analyzed in parallel to obtain the fault information; The sending the fault information to the BMC includes: The fault information is sent to the BMC using a multiplexer.

[0018] In one possible implementation manner, the obtaining the fault information by parsing the multiple JTAG signals in parallel through the CPLD or FPGA includes: When the JTAG signal failure is identified, detecting whether a power-on completion indication signal of the ARM processor system-on-chip is normally issued; If the power-on completion indication signal is not normally issued, determining first fault information; If the power-on completion indication signal is sent normally, a detection process is started for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

[0019] In one possible implementation, the process of starting the detection process for the CPU management core in the ARM processor system-on-chip includes: If the startup completion signal of the CPU management core is not detected within the preset time, determining the second fault information; If the startup completion signal of the CPU management core is detected within the preset time, it is determined that the ARM server is running normally.

[0020] In one embodiment, the method further comprises: Receiving an in-place output signal sent from an in-place signal output port of a slave CPU processor to detect whether the slave CPU processor is in place; If the slave CPU processor is in place, read the JTAG signal of the slave CPU processor and send a corresponding JTAG link routing control signal; If the slave CPU processor is not in place, stop reading the JTAG signal of the slave CPU processor and stop sending the JTAG link routing control signal to the slave CPU processor.

[0021] In one embodiment, the method further comprises: Receiving a firmware upgrade instruction or an information acquisition instruction from the BMC through a multiplexer; The firmware upgrade instruction is executed to update the logic code of the CPLD or FPGA, or the information acquisition instruction is responded to to feed back status information.

[0022] In one embodiment, the method further comprises: Connecting to an external debugging terminal through a local interface module to obtain the fault information or receive a JTAG link routing control signal sent by the external debugging terminal; The external debugging terminal is hardware or software connected to the ARM server.

[0023] According to a third aspect of the present disclosure, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0024] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0025] The control management system, method, electronic device and storage medium disclosed in the present invention are applied to an ARM server, and include: an out-of-band JTAG link management module, which is used to monitor multiple JTAG signals output by an ARM processor system-on-chip after the ARM server is powered on, identify fault information of the ARM processor system-on-chip during startup and operation, and send the fault information to a BMC; it is also used to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip; the ARM processor system-on-chip is used to send multiple JTAG signals to the out-of-band JTAG link management module after the ARM server is powered on, and the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; it is also used to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link; the BMC is used to receive and record fault information and send the fault information to a remote operation and maintenance end. In this way, the out-of-band JTAG link management module runs independently of the ARM processor on-chip system, and multiple JTAG signals are analyzed in real time and in parallel to obtain fault information, and the JTAG link routing control signal is generated to switch the JTAG link mode, and the fault information is transmitted to the BMC to realize structured storage and remote alarm. The technical solution disclosed in this disclosure solves the core problems of low efficiency of manual point-by-point detection, strong dependence on physical operations, and failure of CPU downtime monitoring in traditional solutions, achieving significant reduction in operation and maintenance delays and costs, and providing high-reliability, low-latency operation and maintenance support for large-scale deployment of ARM servers.

[0026] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0028] Figure 1 The structure of the control management system of the present disclosure is shown in FIG. Figure 1 ; Figure 2 A schematic diagram of the structure of an out-of-band JTAG link management module according to an embodiment of the present disclosure is shown; Figure 3 The structure of the control management system of the present disclosure is shown in FIG. Figure 2 ; Figure 4 A schematic diagram of the implementation process of the control management method according to the embodiment of the present disclosure is shown; Figure 5 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0030] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0032] The present disclosure proposes a control management system, which is applied to an ARM server, such as Figure 1 As shown, the system includes: an out-of-band JTAG link management module 10, an ARM processor system-on-chip 20 and a baseboard management controller BMC30; the out-of-band JTAG link management module 10 is respectively connected to the ARM processor system-on-chip 20 and the BMC30 for communication; The out-of-band JTAG link management module 10 is used to monitor multiple JTAG signals output by the ARM processor system-on-chip 20 after the ARM server is powered on, identify fault information of the ARM processor system-on-chip 20 during startup and operation, and send the fault information to the BMC 30; it is also used to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip 20.

[0033] In this example, the out-of-band JTAG link management module 10 is connected to the ARM processor system-on-chip 20 and the BMC 30 through a physical communication link, and its core functions include: after the ARM server is powered on, continuously monitoring multiple JTAG signals output by the ARM processor system-on-chip 20, the JTAG signals cover the status information generated by the ARM processor system-on-chip 20 during the startup phase (such as firmware verification, register initialization) and the operation phase (such as peripheral communication, power management); then, by parsing the JTAG signals, identifying the fault type of the ARM processor system-on-chip 20, such as startup timeout, operation downtime and other abnormal conditions, and transmitting the fault information to the BMC 30. At the same time, the out-of-band JTAG link management module 10 can also dynamically adjust the topological connection mode of the JTAG link by actively generating a JTAG link routing control signal and sending it to the ARM processor system-on-chip 20.

[0034] The ARM processor system on chip 20 is used to send multiple JTAG signals to the out-of-band JTAG link management module 10 after the ARM server is powered on. The multiple JTAG signals carry the startup information and operation information of the ARM processor system on chip 20; and is also used to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link.

[0035] In this example, after the ARM processor system-on-chip (ARM Processor System-on-Chip, ARMSoC for short) 20 is powered on on the server, it outputs multiple JTAG signals correspondingly through multiple JTAG ports set inside it. These signals carry the startup information and operation information of the ARM processor system-on-chip 20, such as the register status of the debug access port, the initialization result of the peripheral interface, the voltage / temperature parameters of the power supply, and the global status of the system-on-chip, etc. At the same time, the ARM processor system-on-chip 20 is also used to receive the JTAG link routing control signal from the out-of-band JTAG link management module 10, and adjust the physical connection path of the internal JTAG link in response to the signal, so as to achieve flexible adaptation of different debugging or monitoring scenarios.

[0036] The BMC 30 is used to receive and record the fault information, and send the fault information to a remote operation and maintenance terminal.

[0037] In this example, the BMC (Baseboard Management Controller) 30 receives and stores fault information from the out-of-band JTAG link management module 10, and records it in chronological order, including fault type identification, occurrence timestamp, and associated processor node information. In addition, the BMC 30 is also used to push fault information to a remote operation and maintenance terminal, allowing operation and maintenance personnel to view fault details in real time and perform remote diagnosis operations.

[0038] The present disclosure provides a control management system, which is applied to an ARM server, including: an out-of-band JTAG link management module 10, which is used to monitor multiple JTAG signals output by an ARM processor system-on-chip 20 after the ARM server is powered on, identify fault information of the ARM processor system-on-chip 20 during startup and operation, and send the fault information to a BMC 30; it is also used to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip 20; the ARM processor system-on-chip 20 is used to send multiple JTAG signals to the out-of-band JTAG link management module 10 after the ARM server is powered on, and the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip 20; it is also used to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link; the BMC 30 is used to receive and record fault information, and send the fault information to a remote operation and maintenance end. In this way, the out-of-band JTAG link management module 10 runs independently of the ARM processor on-chip system 20, and multiple JTAG signals are analyzed in real time and in parallel to obtain fault information, and the JTAG link routing control signal is generated to switch the JTAG link mode, and the fault information is transmitted to the BMC 30 to realize structured storage and remote alarm. The technical solution disclosed in this disclosure solves the core problems of low efficiency of manual point-by-point detection, strong dependence on physical operations, and failure of CPU downtime monitoring in traditional solutions, and significantly reduces operation and maintenance delays and costs, providing high-reliability, low-latency operation and maintenance support for large-scale deployment of ARM servers.

[0039] In one example, the out-of-band JTAG link management module 10 is implemented by a complex programmable logic device CPLD or a field programmable gate array FPGA, such as Figure 2 As shown, it includes: a JTAG control module 101 and a JTAG slave device module 102.

[0040] In the technical solution of the present disclosure, the out-of-band JTAG link management module 10 can be implemented based on a complex programmable logic device CPLD or a field programmable gate array FPGA. Figure 2 and Figure 3Taking the CPLD to implement the out-of-band JTAG link management module 10 function as an example, the JTAG control module 101 (JTAG Switch, JTAG SW) and the JTAG slave device module 102 (JTAG SLAVE) are integrated internally to respectively implement the parallel analysis of multiple JTAG signals of the ARM processor system-on-chip 20 and the directional transmission of fault information. The specific implementation logic is as follows: The JTAG control module 101 is used to monitor multiple JTAG ports on the ARM processor system-on-chip 20 to obtain corresponding multiple JTAG signals, parse the multiple JTAG signals in parallel through the CPLD or FPGA to obtain the fault information, and send the fault information to the JTAG slave device module 102.

[0041] In this example, the JTAG control module 101 captures the original signal streams of multiple JTAG signals by monitoring multiple JTAG ports on the ARM processor system-on-chip 20. In the CPLD or FPGA, after preprocessing the multiple original JTAG signals to eliminate the high-frequency noise interference in the original signals, the multiple JTAG signals are analyzed in parallel to obtain the analysis results. A fault information data packet containing the fault type, timestamp and signal source is generated according to the analysis results, and the fault information is transmitted to the JTAG slave device module 102.

[0042] The JTAG slave device module 102 is used to receive the fault information and send it to the BMC 30 through a multiplexer.

[0043] In this example, the JTAG slave device module 102 receives the data packet of fault information sent by the JTAG control module 101 and routes it to the BMC30 through a multiplexer (MUX). Specifically, the multiplexer selects the transmission path according to the BMC30 interface status. If the BMC30 interface is idle, the high-speed direct connection mode is adopted to transmit the complete data packet at one time through a parallel bus (such as 8-bit GPIO); if the BMC30 interface is busy, the serial mode is enabled to split the data packet into single-byte units and transmit it in time-sharing through the I2C interface to avoid data blocking.

[0044] In one example, the JTAG control module 101, such as Figure 2 As shown, it includes a monitoring unit 1011 and a fault judgment unit 1012: The monitoring unit 1011 is used to monitor multiple JTAG ports of the ARM processor system on chip 20 to obtain multiple JTAG signals.

[0045] In this example, the monitoring unit 1011 consists of a signal capture circuit inside the CPLD or FPGA, which collects multiple original JTAG signals output by multiple JTAG ports on the ARM processor system-on-chip 20 in real time, pre-processes the original signals to remove high-frequency noise interference, and then transmits the multiple stable JTAG signals to the fault judgment unit 1012 for parallel analysis and fault judgment.

[0046] The fault judgment unit 1012 is used to detect whether the power-on completion indication signal of the ARM processor system on chip 20 is normally issued when the JTAG signal fault is identified; if the power-on completion indication signal is not normally issued, determine the first fault information; if the power-on completion indication signal is normally issued, start the detection process for the CPU management core in the ARM processor system on chip 20 to obtain the detection result.

[0047] In this example, when the fault judgment unit 1012 detects that the JTAG signal has a fault anomaly, it triggers the power-on completion indication signal detection logic in the ARM processor chip system 20, including: The CPU_PWR_GOOD pin level state of the ARM processor system-on-chip 20 is read. If it is not pulled up to a valid level after power-on, it is determined that the power-on completion indication signal is not normally issued, and first fault information is generated based on the determination result and fed back to the BMC 30.

[0048] If the CPU_PWR_GOOD pin level is pulled up to a valid level after power-on, it is judged that the power-on completion indication signal is sent normally. At this time, further analysis and judgment of the source of the fault are required. Therefore, the detection process of the CPU management core in the ARM processor chip system 20 is started to obtain the detection results for analysis and judgment.

[0049] In one example, the fault judgment unit 1012, when performing startup detection on the CPU management core and obtaining the detection result, is specifically used to: if the startup completion signal of the CPU management core is not detected within a preset time, determine the second fault information; if the startup completion signal of the CPU management core is detected within the preset time, determine that the ARM server is operating normally.

[0050] In this example, the fault judgment unit 1012 starts the timer after detecting the power-on completion execution signal of the ARM processor chip system 20, and continuously monitors the startup completion signal SCP_READY of the CPU management core. If the startup completion signal is detected to be stable at a high level within a preset time, such as 10 seconds, it is determined that the ARM server is started and running normally; if no valid signal is detected within the preset time, it is determined to be a "CPU startup abnormality" fault, and the second fault information is generated and the system state parameters (such as voltage value, the last signal sampling result) at the time of timeout are recorded for subsequent diagnosis and analysis.

[0051] In one example, the ARM processor system on chip 20 includes a master CPU processor and a slave CPU processor.

[0052] In this example, the ARM processor system-on-chip 20 adopts a multi-CPU architecture, including a master CPU processor and at least one slave CPU processor. The master and slave CPU processors are independently configured with the same hardware interface, including a first general purpose input and output GPIO and multiple JTAG ports, to implement the out-of-band JTAG link management module 10 to perform dynamic JTAG link control and multi-dimensional status monitoring. Among them: The first GPIO is used to receive the JTAG link routing control signal.

[0053] Take dual CPU processor as an example. Figure 3 As shown, the first general purpose input and output GPIO interface of the master CPU processor (CPU0) and the slave CPU processor (CPU1) is used to receive the JTAG link routing control signal JTAG_DAISYCHAIN_DIS from the out-of-band JTAG link management module 10, so that the ARM processor chip system 20 switches the topology mode of the JTAG link according to the signal. The correspondence between the JTAG_DAISYCHAIN_DIS signal level and the JTAG link mode is as follows: when the level is low, it indicates that the merge mode is enabled, and when the level is high, it indicates that the independent mode is enabled.

[0054] The multiple JTAG ports include at least: a debug access port, a peripheral management port, a power management port and an on-chip system port. Figure 3 As shown: Debug access port (JTAG_DAP): provides access to the CPU core register group. For example, the JTAG_DAP of the master CPU processor supports full register reading and writing, and sends the CPU0_JTAG_DAP signal to the out-of-band JTAG link management module 10; the JTAG_DAP of the slave CPU processor only opens some registers to reduce the debugging load, and sends the CPU1_JTAG_DAP signal to the out-of-band JTAG link management module 10.

[0055] Peripheral management port (JTAG_IPP): monitors the status of peripheral controllers connected to the CPU. For example, the JTAG_IPP of the master CPU processor covers the PCIe / USB and other controllers, and sends the CPU0_JTAG_IPP signal to the out-of-band JTAG link management module 10; the JTAG_IPP of the slave CPU processor only monitors the basic peripherals and sends the CPU1_JTAG_IPP signal to the out-of-band JTAG link management module 10.

[0056] Power management port (JTAG_PM): transmits data such as voltage / temperature of the power module. For example, the JTAG_PM of the main CPU processor samples the core voltage and sends the CPU0_JTAG_PM signal to the out-of-band JTAG link management module 10; the JTAG_PM of the slave CPU processor monitors the I / O voltage and sends the CPU1_JTAG_PM signal to the out-of-band JTAG link management module 10.

[0057] System on chip port (JTAG_SoC): Feedback global status information of the system on chip. For example, the JTAG_SoC of the main CPU processor carries the secure boot verification result and the multi-core synchronization flag, and sends the CPU0_JTAG_SoC signal to the out-of-band JTAG link management module 10; the JTAG_SoC of the slave CPU processor only feeds back the local boot status, and sends CPU1_JTAG_SoC to the out-of-band JTAG link management module 10.

[0058] For the topology mode switching of the JTAG link, the first GPIO interface of the master and slave CPU processors is connected to the out-band JTAG link management module 10, which receives the JTAG link routing control signal in real time. When the first GPIO of the master and slave CPU processors receives a high-level JTAG link routing control signal, the JTAG link of the master and slave CPU processors is switched to an independent mode. Taking the two groups of JTAG ports on the above-mentioned master and slave CPU processors as an example, in the independent mode, the two groups of ports each independently send a JTAG signal to the out-band JTAG link management module 10. When the first GPIO of the master and slave CPU processors receives a low-level JTAG link routing control signal, the JTAG link of the master and slave CPU processors is switched to a merge mode. In the merge mode, all JATG signals are aggregated and sent to the out-band JTAG link management module 10 through a main port (e.g., JTAG_DAP).

[0059] In addition, based on the above merging mode, a group of JTAG signals in one CPU processor may be arranged and combined and then routed to another CPU processor, and the JTAG signals may be output through a main port of one CPU processor.

[0060] It should be noted that the JTAG port disclosed in the present invention includes but is not limited to the above four types (debugging access port, peripheral management port, power management port and system-on-chip port). Any physical or logical interface that interacts with the out-of-band JTAG link management module 10 and is set inside the ARM processor system-on-chip 20 belongs to the protection scope of the JTAG port described in the present invention, including but not limited to the extended debugging port, the security engine status feedback port, the multi-core synchronous monitoring port, etc. The core feature of such a port is that it establishes a communication link with the out-of-band JTAG link management module 10 through a standard JTAG protocol or a compatibility protocol, and is associated with the startup and running status, debugging data or control instructions of the ARM processor system-on-chip 20. Its functional implementation and interaction logic are all covered in the technical solution of the present invention.

[0061] In one example, the slave CPU processor is provided with a presence signal output port for sending a presence output signal to the master CPU processor, BMC30 and CPLD or FPGA to detect whether the slave CPU processor is in place.

[0062] In this example, if Figure 3 As shown, the slave CPU processor transmits the in-place output signal to the master CPU processor, BMC30 and CPLD / FPGA through the set in-place signal output port (SLAVE_PRESENT_N) to inform the slave CPU processor whether it is correctly in place. Among them, the master CPU processor is provided with a position signal detection port (SLAVE_PRESENT_N). It should be noted that due to the different sending and receiving entities of the in-place signal, SLAVE_PRESENT_N is the in-place signal detection port on the master CPU processor and the in-place signal output port on the slave CPU processor; BMC30 monitors the in-place status of the slave CPU processor to update the system topology configuration; the CPLD or FPGA JTAG control module 101 receives the in-place signal through the input buffer to trigger the internal state machine switch. The specific logic is as follows: If the slave CPU processor is in place, the JTAG control module 101 reads the JTAG signal of the slave CPU processor and sends a JTAG link routing control signal.

[0063] In this example, when the SLAVE_PRESENT_N signal is at a low level (the slave CPU processor is in place), the JTAG control module 101 inside the CPLD or FPGA starts the JTAG signal acquisition and processing process of the slave CPU processor; at the same time, the JTAG control module 101 generates a JTAG link routing control signal for the slave CPU processor, and sends it to the first GPIO interface of the slave CPU processor, triggering it to adjust the topology mode of the JTAG link.

[0064] If the slave CPU processor is not in place, the JTAG control module 101 stops reading the JTAG signal of the slave CPU processor and stops sending the JTAG link routing control signal to the slave CPU processor.

[0065] In this example, if the SLAVE_PRESENT_N signal is high (the slave CPU processor is not in place), the JTAG control module 101 of the CPLD or FPGA disables all JTAG signal channels in the slave CPU processor: turns off the enable signal of the corresponding MUX channel, stops the JTAG_DAP, JTAG_IPP, JTAG_PM and JTAG_SoC signal sampling and analysis operations of the slave CPU processor; at the same time, resets the state machine and timer dedicated to the slave CPU processor to release hardware resources to avoid invalid power consumption. In addition, the JTAG control module 101 stops generating and sending JTAG link routing control signals for the slave CPU processor to prevent signal conflicts or misoperation, and ensure the stable operation of the JTAG link of the master CPU processor and other in-place devices.

[0066] In one example, the BMC30 includes a JTAG master device module, which is used to receive fault information of the JTAG master device module and record the fault information in a time record table through the BMC30; the BMC30 is also used to generate alarm information based on the fault information and feed it back to the remote operation and maintenance end.

[0067] In this example, if Figure 3 As shown, the BMC30 integrates a JTAG master module (JTAG MASTER), which is connected to the out-of-band JTAG link management module 10 through a multiplexer and lines BMC_JTAG and BMC_JTAG_MUX to receive a data packet of fault information (including a fault code, a timestamp and associated parameters). The JTAG master module of BMC30 parses the received data packet and writes it into the time record table of the system event log (SEL) for storage. When a new fault information is recorded in the time record table, BMC30 extracts the fault type code and timestamp of the most recent record, encapsulates it into an alarm message, and sends it to the remote operation and maintenance terminal. After receiving the message, the operation and maintenance terminal parses the message content and displays information such as the fault type, occurrence time, and associated hardware nodes through the user display interface.

[0068] In one example, the JTAG master device module is further used to send a firmware upgrade instruction or an information acquisition instruction to the CPLD or FPGA through the multiplexer.

[0069] In this example, after BMC30 receives the firmware upgrade instruction or information acquisition instruction sent by the user through the remote operation and maintenance end, the JTAG master device module set in BMC30 is connected to the instruction receiving port of CPLD / FPGA through the second GPIO and multiplexer, line CPLD_JTAG, and transmits the user's firmware upgrade instruction and information acquisition instruction, namely, BMC_CPLD_SELs signal.

[0070] Among them, the firmware upgrade instruction is used to update the hardware logic code of the CPLD or FPGA, such as repairing the routing logic defects of the debugging link, optimizing the signal analysis algorithm or enhancing the anti-interference capability, to ensure the functional iteration and reliability improvement of the out-of-band JTAG link management module 10. The information acquisition instruction is used to read the internal status information of the CPLD or FPGA in real time, including the current JTAG link configuration mode, fault counter value, etc., to provide the operation and maintenance personnel with visual data of the underlying hardware operating status, and support the root cause analysis of faults and the system health assessment.

[0071] Through the above-mentioned command interaction, BMC30 can directly control the function upgrade and status monitoring of CPLD or FPGA without relying on processor resources, thereby enhancing the remote operation and maintenance capabilities of ARM servers.

[0072] In one example, the system also includes a local interface module, which is used for the external debugging terminal to connect to the out-band JTAG link management module 10 through the local interface module to obtain the fault information; and is also used for the external debugging terminal to send a JTAG link routing control signal to the out-band JTAG link management module 10 through the local interface module; the external debugging terminal is hardware or software connected to the ARM server.

[0073] In this example, the local interface module is directly connected to the out-of-band JTAG link management module 10 (CPLD / FPGA) through a physical interface such as a socket, etc., to support on-site operation and maintenance personnel to access the debugging tool to obtain fault information. Figure 3 The local interface module shown integrates a standardized hardware interface (such as HDR2 or CON1 connector), and its core functions include: Through a parallel bus or serial protocol, the fault information data packet is read from the JTAG control module 101 of the out-of-band JTAG link management module 10; the external debugging tool is supported to send debugging instructions (such as JTAG link routing control signals) through the interface, and the debugging instructions are sent to the JTAG control module 101 in the out-of-band JTAG link management module 10 for execution, and the instructions are responded to and returned to the debugging tool. By connecting to this interface, on-site operation and maintenance personnel can directly access the fault storage area of ​​the out-of-band JTAG link management module 10 or monitor the JTAG link status in real time without relying on the remote channel of BMC30. It is suitable for network isolation environments or emergency hardware diagnosis scenarios, and significantly improves the efficiency of on-site problem location.

[0074] In an example, the BMC 30 is further configured to send a JTAG link routing control signal and a local interface control signal to the out-of-band JTAG link management module 10 .

[0075] like Figure 3 As shown, when BMC30 receives the JTAG link routing switching instruction from the remote operation and maintenance end, it sends the JTAG link routing control signal CPU_JTAG_DSYCHN_DIS_BMC_GPIO to the out-of-band JTAG link management module 10, so that the out-of-band JTAG link management module 10 responds to the signal and forwards the JTAG link routing control signal to the ARM processor on-chip system 20, thereby realizing the switching of the JTAG link topology mode in the master and slave CPU processors.

[0076] In addition, the BMC 30 is also used to send a local interface control signal BMC_CON1_SEL_BMC_GPIO to the out-band JTAG link management module 10 to control the connection and data transmission between the local interface module and the out-band JTAG link management module 10 .

[0077] In addition to the BMC 30 being able to send JTAG link routing control signals and local interface control signals to the out-of-band JTAG link management module 10 , the system may also be provided with a jumper setting module to also achieve the above functions.

[0078] The present disclosure also provides a control management method, which is applied to an out-of-band JTAG link management module in an ARM server, wherein the out-of-band JTAG link management module is respectively connected to the ARM processor system on chip and the baseboard management controller BMC, such as Figure 4 As shown, the method includes: Step 401: After the ARM server is powered on, multiple JTAG signals output by the ARM processor system-on-chip are monitored, wherein the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; Step 402: Identify fault information of the ARM processor system-on-chip during startup and operation according to the multiple JTAG signals; Step 403: Send the fault information to the BMC, so that the BMC records the fault information and sends it to the remote operation and maintenance end.

[0079] In one example, the out-of-band JTAG link management module is implemented by a complex programmable logic device (CPLD) or a field programmable gate array (FPGA).

[0080] In one example, the ARM processor system-on-chip includes a master CPU processor and a slave CPU processor, the master CPU processor and the slave CPU processor are respectively provided with a first general purpose input and output GPIO and a plurality of JTAG ports, and the method further includes: Generate a JTAG link routing control signal and send it to the first GPIO of the ARM processor system on chip to switch the topology mode of the JTAG link; The multiple JTAG ports include at least: a debug access port, a peripheral management port, a power management port and an on-chip system port.

[0081] In one example, the monitoring of multiple JTAG signals output by the ARM processor system-on-chip includes: Monitoring multiple JTAG ports of the ARM processor system-on-chip to obtain corresponding multiple JTAG signals; The step of identifying fault information of the ARM processor system-on-chip during startup and operation according to the JTAG signal includes: By means of the CPLD or FPGA, the plurality of JTAG signals are analyzed in parallel to obtain the fault information; The sending the fault information to the BMC includes: The fault information is sent to the BMC using a multiplexer.

[0082] In one example, the obtaining the fault information by parsing the multiple JTAG signals in parallel through the CPLD or FPGA includes: When the JTAG signal failure is identified, detecting whether a power-on completion indication signal of the ARM processor system-on-chip is normally issued; If the power-on completion indication signal is not normally issued, determining first fault information; If the power-on completion indication signal is sent normally, a detection process is started for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

[0083] In one example, the initiating a detection process for a CPU management core in the ARM processor system-on-chip includes: If the startup completion signal of the CPU management core is not detected within the preset time, determining the second fault information; If the startup completion signal of the CPU management core is detected within the preset time, it is determined that the ARM server is running normally.

[0084] In one example, the method further includes: Receiving an in-place output signal sent from an in-place signal output port of a slave CPU processor to detect whether the slave CPU processor is in place; If the slave CPU processor is in place, read the JTAG signal of the slave CPU processor and send a corresponding JTAG link routing control signal; If the slave CPU processor is not in place, stop reading the JTAG signal of the slave CPU processor and stop sending the JTAG link routing control signal to the slave CPU processor.

[0085] In one example, the method further includes: Receiving a firmware upgrade instruction or an information acquisition instruction from the BMC through a multiplexer; The firmware upgrade instruction is executed to update the logic code of the CPLD or FPGA, or the information acquisition instruction is responded to to feed back status information.

[0086] In one example, the method further includes: Connecting to an external debugging terminal through a local interface module to obtain the fault information or receive a JTAG link routing control signal sent by the external debugging terminal; The external debugging terminal is hardware or software connected to the ARM server.

[0087] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0088] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0089] like Figure 5 As shown, the electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0090] A number of components in the device 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0091] The computing unit 501 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as the control management method. For example, in some embodiments, the control management method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the control management method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the control management method in any other appropriate manner (e.g., by means of firmware).

[0092] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0093] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0094] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0095] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0096] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0097] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0098] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0099] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0100] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A control management system, characterized in that: The system is applied to an ARM server, and comprises: an out-of-band JTAG link management module, an ARM processor system-on-chip, and a baseboard management controller BMC; the out-of-band JTAG link management module is respectively connected to the ARM processor system-on-chip and the BMC for communication; The out-of-band JTAG link management module is used to monitor multiple JTAG signals output by the ARM processor system-on-chip after the ARM server is powered on, identify fault information of the ARM processor system-on-chip during startup and operation, and send the fault information to the BMC; and is also used to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip; The ARM processor system-on-chip is used to send multiple JTAG signals to the out-of-band JTAG link management module after the ARM server is powered on, wherein the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; and is also used to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link; The BMC is used to receive and record the fault information, and send the fault information to a remote operation and maintenance end.

2. The system according to claim 1, characterized in that The out-of-band JTAG link management module is implemented by a complex programmable logic device CPLD or a field programmable gate array FPGA, and includes: a JTAG control module and a JTAG slave device module; The JTAG control module is used to monitor multiple JTAG ports on the ARM processor system-on-chip to obtain corresponding multiple JTAG signals, analyze the multiple JTAG signals in parallel through the CPLD or FPGA to obtain the fault information, and send the fault information to the JTAG slave device module; The JTAG slave device module is used to receive the fault information and send it to the BMC through a multiplexer.

3. The system according to claim 2, characterized in that The JTAG control module includes a monitoring unit and a fault judgment unit: The monitoring unit is used to monitor multiple JTAG ports of the ARM processor system-on-chip to obtain multiple JTAG signals; The fault judgment unit is used to detect whether the power-on completion indication signal of the ARM processor system-on-chip is normally issued when the JTAG signal fault is identified; If the power-on completion indication signal is not normally issued, determining first fault information; If the power-on completion indication signal is sent normally, a detection process is started for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

4. The system according to claim 3, characterized in that The fault judgment unit, when starting detection on the CPU management core and obtaining the detection result, is specifically used to: If the startup completion signal of the CPU management core is not detected within the preset time, determining the second fault information; If the startup completion signal of the CPU management core is detected within the preset time, it is determined that the ARM server is running normally.

5. The system according to claim 2, characterized in that The ARM processor system-on-chip includes a master CPU processor and a slave CPU processor; The master CPU processor and the slave CPU processor are respectively provided with a first general purpose input and output GPIO and a plurality of JTAG ports; The first GPIO is used to receive the JTAG link routing control signal; The multiple JTAG ports include at least: a debug access port, a peripheral management port, a power management port and an on-chip system port.

6. The system according to claim 5, characterized in that The slave CPU processor is provided with an in-place signal output port for sending an in-place output signal to the master CPU processor, BMC and CPLD or FPGA to detect whether the slave CPU processor is in place; If the slave CPU processor is in place, the JTAG control module reads the JTAG signal of the slave CPU processor and sends a JTAG link routing control signal; If the slave CPU processor is not in place, the JTAG control module stops reading the JTAG signal of the slave CPU processor and stops sending the JTAG link routing control signal to the slave CPU processor.

7. The system according to claim 2, characterized in that The BMC includes a JTAG master device module, which is used to receive fault information of the JTAG master device module and record the fault information in a time record table through the BMC; The BMC is also used to generate alarm information based on the fault information and feed it back to the remote operation and maintenance end.

8. The system according to claim 7, characterized in that The JTAG master device module is also used to send a firmware upgrade instruction or an information acquisition instruction to the CPLD or FPGA through the multiplexer.

9. The system according to claim 1, characterized in that The system also includes a local interface module, which is used for an external debugging terminal to connect to the out-band JTAG link management module through the local interface module to obtain the fault information; and is also used for the external debugging terminal to send a JTAG link routing control signal to the out-band JTAG link management module through the local interface module; the external debugging terminal is hardware or software connected to the ARM server.

10. A control management method, characterized in that: An out-of-band JTAG link management module is applied to an ARM server, wherein the out-of-band JTAG link management module is respectively connected to an ARM processor system-on-chip and a baseboard management controller BMC for communication, and the method comprises: After the ARM server is powered on, multiple JTAG signals output by the ARM processor system-on-chip are monitored, wherein the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; According to the multiple JTAG signals, identifying fault information of the ARM processor system on chip during startup and operation; The fault information is sent to the BMC, so that the BMC records the fault information and sends it to the remote operation and maintenance end.

11. The method according to claim 10, characterized in that The out-of-band JTAG link management module is implemented by a complex programmable logic device CPLD or a field programmable gate array FPGA.

12. The method according to claim 11, characterized in that The ARM processor system-on-chip includes a master CPU processor and a slave CPU processor, wherein the master CPU processor and the slave CPU processor are respectively provided with a first general purpose input and output GPIO and a plurality of JTAG ports, and the method further includes: Generate a JTAG link routing control signal and send it to the first GPIO of the ARM processor system on chip to switch the topology mode of the JTAG link; The multiple JTAG ports include at least: a debug access port, a peripheral management port, a power management port and an on-chip system port.

13. The method according to claim 12, characterized in that The monitoring of multiple JTAG signals output by the ARM processor system-on-chip includes: Monitoring multiple JTAG ports of the ARM processor system-on-chip to obtain corresponding multiple JTAG signals; The step of identifying fault information of the ARM processor system-on-chip during startup and operation according to the JTAG signal includes: By means of the CPLD or FPGA, the plurality of JTAG signals are analyzed in parallel to obtain the fault information; The sending the fault information to the BMC includes: The fault information is sent to the BMC using a multiplexer.

14. The method according to claim 13, characterized in that The obtaining of the fault information by analyzing the multiple JTAG signals in parallel through the CPLD or FPGA includes: When the JTAG signal failure is identified, detecting whether a power-on completion indication signal of the ARM processor system-on-chip is normally issued; If the power-on completion indication signal is not normally issued, determining first fault information; If the power-on completion indication signal is sent normally, a detection process is started for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

15. The method according to claim 14, characterized in that The process of starting the detection process of the CPU management core in the ARM processor system-on-chip includes: If the startup completion signal of the CPU management core is not detected within the preset time, determining the second fault information; If the startup completion signal of the CPU management core is detected within the preset time, it is determined that the ARM server is running normally.

16. The method according to claim 12, characterized in that The method further comprises: Receiving an in-place output signal sent from an in-place signal output port of a slave CPU processor to detect whether the slave CPU processor is in place; If the slave CPU processor is in place, read the JTAG signal of the slave CPU processor and send a corresponding JTAG link routing control signal; If the slave CPU processor is not in place, stop reading the JTAG signal of the slave CPU processor and stop sending the JTAG link routing control signal to the slave CPU processor.

17. The method according to claim 11, characterized in that The method further comprises: Receiving a firmware upgrade instruction or an information acquisition instruction from the BMC through a multiplexer; The firmware upgrade instruction is executed to update the logic code of the CPLD or FPGA, or the information acquisition instruction is responded to to feed back status information.

18. The method according to claim 10, characterized in that The method further comprises: Connecting to an external debugging terminal through a local interface module to obtain the fault information or receive a JTAG link routing control signal sent by the external debugging terminal; The external debugging terminal is hardware or software connected to the ARM server.

19. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 10 to 18.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 10-18.

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