USB (Universal Serial Bus) equipment performance verification method, system and device

Abstract

The invention provides a USB equipment performance verification method, system and device. The USB equipment performance verification device comprises an uplink interface, a processing chip, a plurality of connection indicating lamps and a plurality of downlink interfaces, the processing chip is electrically connected with an uplink interface, a plurality of communication indicating lamp ports and a plurality of downlink interfaces, the uplink interface is used for connecting a USB host, the downlink interfaces are used for connecting a tested USB device, the communication indicating lamps are in one-to-one correspondence with the downlink interfaces, and the communication indicating lamp ports are in one-to-one correspondence with the downlink interfaces. And the lengths of the USB links formed by the downlink interfaces and the processing chip are different from each other. The verification efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of network communication technology, and in particular to a USB device performance verification method, system and device thereof. Background Art

[0002] There are various devices with USB interfaces on the market, such as USB flash drives, mice, and keyboards. USB cables can also be used to interconnect boards in complete electronic products such as notebooks and servers.

[0003] Taking the most common USB wired mouse as an example, the different lengths of the USB cable on the USB wired mouse will cause different degrees of attenuation of the USB signal, and the quality differences of the PCB board design on it will also cause different degrees of attenuation of the USB signal. If the overall link of the USB wired mouse attenuates the USB signal too much, it is easy to fail to recognize the USB mouse in a harsh environment, such as when the working environment temperature is high or the PCB board temperature is high.

[0004] Therefore, when designing USB devices, companies will perform signal verification on the USB link of USB devices in order to ensure the reliability of USB devices. The conventional verification method is to use high-speed oscilloscopes, network analyzers, etc. to verify the electrical performance data of USB devices, that is, to determine whether the USB signal sent from the USB device from the sending end is still consistent with the waveform of the USB signal at the sending end when it reaches the receiving end, to determine the reliability. Among them, if the waveforms of the previous and subsequent USB signals are closer, the higher the reliability of the USB device, and the more stable it can work in a complex environment. If the waveform of the USB signal at the receiving end becomes very poor, the reliability is worse. Judging the reliability of USB devices in this way not only has a slow verification speed, making the entire verification cycle very long, but also requires a lot of human resources and costs. Summary of the invention

[0005] To solve the above problems, the present invention provides a USB device performance verification method, system and apparatus thereof, which can improve verification efficiency and save human resources and costs by processing a chip and multiple downstream interfaces.

[0006] In a first aspect, the present invention provides a USB device performance verification device, the USB device performance verification device comprising: an upstream interface, a processing chip, a plurality of connection indicator lights and a plurality of downstream interfaces;

[0007] The processing chip is electrically connected to an upstream interface, multiple connectivity indicator ports and multiple downstream interfaces respectively. The upstream interface is used to connect to a USB host, and the downstream interface is used to connect to a USB device under test. The connectivity indicator lights correspond to the downstream interfaces one by one, and the length of the USB link formed by each downstream interface and the processing chip is different.

[0008] Optionally, the USB device performance verification apparatus further includes: a plurality of capacitors;

[0009] Each downstream interface is electrically connected to the processing chip via a capacitor on the corresponding USB link.

[0010] Optionally, the USB device performance verification apparatus further includes: a plurality of power supply control modules;

[0011] The power supply control module corresponds to the downstream interface one by one, and the power supply control module includes: a control end, an input end and an output end;

[0012] The control end is electrically connected to the processing chip, the input end is used to connect to an external power supply, the output end is electrically connected to a corresponding downlink interface, and the processing chip controls the on and off of the input end and the output end through the control end.

[0013] Optionally, the USB device performance verification apparatus further includes: a circuit board;

[0014] The upstream interface, the processing chip, the plurality of connection indicator lights and the plurality of downstream interfaces are all fixedly arranged on the circuit board, and the processing chip is electrically connected to the plurality of downstream interfaces through the circuit board to form a USB link;

[0015] The dielectric loss factor of the circuit board is greater than or equal to 0.1 and less than 0.5.

[0016] In a second aspect, the present invention provides a USB device performance verification method, which is applied to a processing chip, the processing chip is electrically connected to an upstream interface, a plurality of connectivity indicator ports, and a plurality of downstream interfaces, the upstream interface is used to connect to a USB host, the downstream interface is used to connect to a USB device under test, the connectivity indicator lights correspond to the downstream interfaces one by one, and the lengths of USB links formed by each downstream interface and the processing chip are different;

[0017] Methods include:

[0018] When the target downstream interface is connected to the USB device under test, determining whether the USB device under test is identified, the target downstream interface being the downstream interface currently connected to the USB device under test;

[0019] When the USB device under test is identified, the connectivity indicator light corresponding to the target downstream interface is lit.

[0020] Optionally, before the step of determining whether the tested USB device is identified, the method further includes:

[0021] Power the USB device under test through the target downstream interface;

[0022] The method also includes:

[0023] When the USB device under test is not identified, determining whether the number of times the USB device under test is not identified under the target downstream interface exceeds an identification threshold;

[0024] When the number of times that the USB device under test is not recognized at the target downstream interface does not exceed the recognition threshold, the step of supplying power to the USB device under test through the target downstream interface is performed.

[0025] Optionally, after the step of lighting up a connectivity indicator light corresponding to the target downlink interface, the method further includes:

[0026] Determine whether the USB link formed by the target downstream interface and the processing chip is the longest USB link;

[0027] When the USB link formed by the target downstream interface and the processing chip is not the longest USB link, the next connected downstream interface with a longer USB link is switched as the target downstream interface, and the step of determining whether the tested USB device is identified is performed.

[0028] In a third aspect, the present invention provides a USB device performance verification system, the system is applied to a processing chip, the processing chip is electrically connected to an upstream interface, a plurality of connectivity indicator ports and a plurality of downstream interfaces respectively, the upstream interface is used to connect to a USB host, the downstream interface is used to connect to a USB device under test, the connectivity indicator lights correspond to the downstream interfaces one by one, and the length of the USB link formed by each downstream interface and the processing chip is different;

[0029] The system includes:

[0030] A first judgment module is configured to judge whether the USB device under test is identified when the target downstream interface is connected to the USB device under test, the target downstream interface being the downstream interface currently connected to the USB device under test;

[0031] The lighting module is configured to light up the connectivity indicator light corresponding to the target downstream interface when the USB device under test is identified.

[0032] Optionally, the system further comprises:

[0033] A power supply module, configured to supply power to the USB device under test through the target downstream interface before executing the first determination module;

[0034] The second judgment module is configured to judge whether the number of times that the USB device under test is not recognized under the target downstream interface exceeds the recognition threshold when the first judgment module judges that the processing chip does not recognize the USB device under test;

[0035] The trigger module is configured to trigger the power supply module to supply power to the USB device under test through the target downstream interface when the second judgment module determines that the number of times the USB device under test is not recognized under the target downstream interface does not exceed the recognition threshold.

[0036] Optionally, the system further comprises:

[0037] A third judgment module is configured to judge whether the USB link formed by the target downstream interface and the processing chip is the longest USB link after the lighting module lights up the connectivity indicator corresponding to the target downstream interface;

[0038] The switching module is configured to switch the next connected downstream interface with a longer USB link as the target downstream interface when the third judgment module determines that the USB link formed by the target downstream interface and the processing chip is not the longest USB link, and trigger the first judgment module to determine whether the USB device under test is identified.

[0039] The USB device performance verification method, system and device provided by the embodiment of the present invention form USB links of different lengths with each downstream interface and a processing chip, so that when the USB device under test is inserted into a certain downstream interface, the processing chip determines whether the USB device under test is identified; at the same time, when the USB device under test is identified, the connection indicator light corresponding to the downstream interface is lit, so that the reliability of the USB device can be quickly verified, the verification efficiency is improved, and human resources and the cost of setting up a verification environment are saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a schematic structural diagram of a USB device performance verification apparatus according to an embodiment of the present application;

[0042] Figure 2 A schematic circuit diagram of a power supply control module according to an embodiment of the present application;

[0043] Figure 3 A schematic flowchart of a USB device performance verification method according to an embodiment of the present application.

[0044] Reference numerals:

[0045] 1. Uplink interface; 2. Processing chip; 3. Connectivity indicator light; 4. Downlink interface; 5. Capacitor; 6. Power supply control module; 7. Circuit board; 8. Power management unit; 9. Storage unit; 10. Clock unit. DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be an intermediate element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0050] Example 1

[0051] This embodiment provides a USB device performance verification device, see Figure 1 The USB device performance verification device includes: an upstream interface 1, a processing chip 2, a plurality of connection indicator lights 3 and a plurality of downstream interfaces 4.

[0052] The processing chip 2 is electrically connected to the upstream interface 1, multiple connectivity indicator lights 3 and multiple downstream interfaces 4 respectively. The upstream interface 1 is used to connect to the USB host. The downstream interface 4 is used to connect to the USB device under test. The connectivity indicator lights 3 correspond to the downstream interfaces 4 one by one. The length of the USB link formed by each downstream interface 4 and the processing chip 2 is different.

[0053] The USB device performance verification device provided in this embodiment has a simple structure and low preparation cost. By forming USB links of different lengths between each downstream interface 4 and the processing chip 2, the processing chip 2 determines whether the USB device under test is recognized when the USB device under test is inserted into a certain downstream interface 4; at the same time, when the USB device under test is recognized, the connectivity indicator light 3 corresponding to the downstream interface 4 is turned on, thereby quickly realizing the verification of the reliability of the USB device, improving the verification efficiency, and saving human resources and the cost of setting up the verification environment.

[0054] Specifically, the processing chip 2 can determine whether the tested USB device is successfully identified by determining whether the tested USB device connected to the downstream interface 4 has successfully shaken hands with the USB host. If the processing chip 2 identifies that the tested USB device connected to the downstream interface 4 has successfully shaken hands with the USB host, the connection indicator light 3 corresponding to the downstream interface 4 is lit to indicate that the tested USB device can achieve stable USB communication on the USB link connected to the downstream interface 4. If the processing chip 2 does not identify that the tested USB device connected to the downstream interface 4 has successfully shaken hands with the USB host, the connection indicator light 3 corresponding to the downstream interface 4 is kept off to indicate that the tested USB device cannot achieve USB communication on the USB link connected to the downstream interface 4.

[0055] In this embodiment, the number of the connected indicator lights 3 and the downstream interfaces 4 is four, namely indicator lights A, B, C, D and downstream interfaces PortA, PortB, PortC, PortD, but not limited thereto. Among them, indicator light A corresponds to downstream interface PortA and is used to indicate the result of the tested USB device being identified by the processing chip 2 after the tested USB device is connected to the downstream interface PortA, and the same applies to indicator lights B, C, D, which will not be described in detail here.

[0056] Meanwhile, in this embodiment, the USB link A formed by the downstream interface PortA and the processing chip 2 is the longest, and the USB link D formed by the downstream interface PortD and the processing chip 2 is the shortest. Figure 1 In this way, four USB links A, B, C, and D with different distances can be formed for verification of the USB device under test, that is, five verification standards are provided, namely, the reliability of the USB device under test is very strong, the reliability of the USB device under test is strong, the reliability of the USB device under test is relatively strong, the reliability of the USB device under test is average, and the reliability of the USB device under test is poor.

[0057] Among them, when the processing chip 2 successfully identifies the USB device under test through USB link A, indicator light A is on, indicating that the reliability of the USB device under test is very strong; when the processing chip 2 successfully identifies the USB device under test through USB link B, indicator light B is on, indicating that the reliability of the USB device under test is strong; when the processing chip 2 successfully identifies the USB device under test through USB link C, indicator light C is on, indicating that the reliability of the USB device under test is relatively strong; when the processing chip 2 successfully identifies the USB device under test through USB link D, indicator light D is on, indicating that the reliability of the USB device under test is average. If indicator light D is off, it means that the reliability of the USB device under test is poor.

[0058] It is understandable that during the verification process, the USB device under test may be connected to any downstream interface 4 first, and then it is determined whether to switch to the next downstream interface 4 to connect to the USB device under test or to stop the verification according to the recognition result.

[0059] Specifically, when the USB device under test is first connected to the downstream interface PortA, if the processing chip 2 recognizes the USB device under test, if the processing chip 2 does not recognize the USB device under test, the USB device under test can be connected to any one of the downstream interfaces PortB, PortC, and PortD. Here, the downstream interface 4 is switched in the order of the length of the corresponding USB links B, C, and D from long to short until the recognition is successful or there is no downstream interface 4 that can be successfully identified, thereby completing the verification of the USB device under test.

[0060] For example, when the USB device under test is first connected to the downstream interface PortC, if the processing chip 2 does not recognize the USB device under test, the USB device under test can be connected to the downstream interface PortD to continue verifying the USB device under test; if the processing chip 2 recognizes the USB device under test, the USB device under test can be connected to the downstream interface PortB or PortA to continue verifying the USB device under test. Here, the downstream interface 4 is switched in the order of the length of the corresponding USB links B and A from short to long until the recognition is successful on the USB link A or the recognition is unsuccessful, thereby completing the verification of the USB device under test.

[0061] For example, when the USB device under test is first connected to the downstream interface PortD, if the processing chip 2 does not recognize the USB device under test, the verification of the USB device under test can be directly ended at this time, and the indicator light D can be kept off to indicate that the reliability of the USB device under test is unqualified; if the processing chip 2 recognizes the USB device under test, the USB device under test can be connected to the downstream interface PortC, PortB or PortA to continue verifying the USB device under test, and the downstream interface 4 is switched in the order of the length of the corresponding USB links C, B, and A from short to long until the recognition is successful on the USB link A or the recognition is unsuccessful, thereby completing the verification of the USB device under test.

[0062] In this embodiment, the downstream interface 4 is switched in the order of the length of the USB link from short to long, that is, when the USB device under test is verified on the USB device performance verification device for the first time, it is first connected to the downstream interface PortD until it is successfully identified on the USB link A or an identification failure occurs, thereby completing the verification of the USB device under test.

[0063] Combination Figure 1 In this embodiment, the process of judging the reliability level of the USB device according to whether the connectivity indicator light 3 is on or off is as follows:

[0064] When only indicator light D is on, the reliability level of the USB device is determined to be D;

[0065] When only indicator lights D and C are on, the USB device reliability level is determined to be C;

[0066] When only indicator lights D, C, and B are on, the USB device reliability level is determined to be B;

[0067] When indicator lights D, C, B, and A are all on, the USB device reliability level is determined to be A.

[0068] Among them, the reliability level of USB devices decreases step by step from A to D.

[0069] Furthermore, the USB device performance verification apparatus further includes: a plurality of capacitors 5. Each downstream interface 4 is electrically connected to the processing chip 2 on the corresponding USB link via a capacitor 5. By providing a capacitor 5 on each USB link, the stability of the USB link can be improved, thereby improving the accuracy of the verification result of the USB device performance verification apparatus.

[0070] The USB device performance verification device also includes: a plurality of power supply control modules 6, combined with Figure 2 The power supply control module 6 corresponds to the downlink interface 4 one by one. The power supply control module 6 includes: a control end, an input end and an output end.

[0071] The control end is electrically connected to the processing chip 2, the input end is used to connect to an external power supply, and the output end is electrically connected to the corresponding downstream interface 4. The processing chip 2 controls the input and output ends through the control end. The external power supply can be a system power supply on the USB host, or a power supply module independent of the USB host and the USB device performance verification device.

[0072] In this embodiment, the external power supply is the system power supply on the USB host, that is, the input end is electrically connected to the USB host. The processing chip 2 controls the on and off of the input end and the output end by sending a control signal to the control end. The power supply control module 6 also includes: an N-type MOS tube and a P-type MOS tube. Among them, the gate of the N-type MOS tube is electrically connected to the control end, the source of the N-type MOS tube is grounded, the drain of the N-type MOS tube is electrically connected to the gate of the P-type MOS tube D, and the source and drain of the P-type MOS tube are electrically connected to the input end and the output end respectively.

[0073] When the control signal sent by the processing chip 2 to the downstream interface 4 is at a high level, the N-type MOS tube is turned on, the P-type MOS tube is also turned on, and the USB host supplies power to the corresponding downstream interface 4. When the control signal sent by the processing chip 2 to the downstream interface 4 is at a low level, the N-type MOS tube is not turned on, the P-type MOS tube is also not turned on, and the USB host cannot supply power to the corresponding downstream interface 4. It should be noted that when the USB device under test is inserted into any downstream interface 4, the processing chip 2 will detect the insertion of the USB device under test, and control the corresponding power supply control module 6 to connect the external power supply to the corresponding downstream interface 4, so as to identify and judge the USB device under test.

[0074] Furthermore, the power supply control module 6 also includes: a first resistor RP1, a second resistor RP2, a third resistor RP3 and a filter capacitor CP1. The value of the first resistor RP1 is 10K ohms; the value of the second resistor RP2 is 47K ohms; the value of the third resistor RP3 is 10K ohms; and the value of the filter capacitor CP1 is 0.1uF.

[0075] One end of the first resistor RP1 and one end of the second resistor RP2 are both electrically connected to the drain of the N-type MOS tube, one end of the third resistor RP3 is electrically connected to the gate of the N-type MOS tube, the other end of the third resistor RP3 is electrically connected to the control end, the other end of the first resistor RP1 and one end of the filter capacitor CP1 are both electrically connected to the source of the P-type MOS tube, and the other end of the filter capacitor CP1 and the other end of the second resistor RP2 are both electrically connected to the gate of the P-type MOS tube. By setting the first resistor RP1, the second resistor RP2, the third resistor RP3 and the filter capacitor CP1, the stability and safety of the power supply control module 6 can be improved.

[0076] It should be noted that the connectivity indicator light 3 in the present invention can indicate the result of each verification in a variety of ways. For example, when the USB device performance verification device is started and before the USB device under test is verified, all connectivity indicator lights 3 can remain in a completely off state, or can remain in a completely on state, or can remain in a completely flashing state, etc.

[0077] If all connectivity indicator lights 3 remain fully lit or flashing before the USB device under test is verified, when the processing chip 2 completes the verification and identifies successfully on a certain downstream interface 4, the power supply regulation module 6 is controlled to connect the corresponding connectivity indicator light 3 with the external power supply to light up the connectivity indicator light 3, so that the connectivity indicator light 3 is in a normally lit or flashing state, and the other connectivity indicator lights 3 can all be off, or the power supply regulation module 6 is controlled to keep the corresponding connectivity indicator light 3 in a normally lit state, and the other connectivity indicator lights 3 can all be in a flashing state.

[0078] If all connectivity indicator lights 3 remain off before the USB device under test is verified, when the processing chip 2 completes the verification and identifies successfully on a certain downstream interface 4, the power supply regulation module 6 is controlled to connect the corresponding connectivity indicator light 3 with the external power supply to light up the connectivity indicator light 3, so that the connectivity indicator light 3 is in a normally on or flashing state, and the other connectivity indicator lights 3 can continue to remain off, or the power supply regulation module 6 is controlled to keep the corresponding connectivity indicator light 3 in a normally on state, and all the other connectivity indicator lights 3 are adjusted to a flashing state.

[0079] In addition, taking the example of all connectivity indicator lights 3 remaining off before the USB device under test is verified, when the downstream interface 4 connected to the USB device under test for the first time is PortB and is successfully identified, the processing chip 2 controls the power supply control module 6 to connect the corresponding connectivity indicator light 3 with the external power supply to light up indicator light B, and at the same time lights up the connectivity indicator light 3 corresponding to the USB link shorter than USB link B, that is, lights up indicator lights C and D. After that, it is only necessary to connect the USB device under test to PortA for verification to complete the verification of the USB device under test.

[0080] In this embodiment, before the USB device under test is verified, all connectivity indicator lights 3 remain off. When the processing chip 2 completes the verification and successfully identifies a certain downstream interface 4, the power supply control module 6 is controlled to connect the corresponding connectivity indicator light 3 to the external power supply to light up the connectivity indicator light 3, so that the connectivity indicator light 3 is in a normally on state, and the other connectivity indicator lights 3 continue to remain off.

[0081] It should be noted that when the USB device under test is connected to multiple downstream interfaces 4 in sequence, it can be achieved by manual plugging and unplugging, or by electric control. For example, the processing chip 2 controls a mechanical arm connected to the USB device under test to plug and unplug the USB device under test between multiple downstream interfaces 4.

[0082] In a further optional embodiment of this embodiment, the USB device performance verification apparatus further includes: a multiple-choice-one connector. The multiple downstream interfaces 4 are electrically connected to the USB device under test through the multiple-choice-one connector.

[0083] The multiple-choice connector includes: a control end, a first connection end and a plurality of second connection ends. The first connection end is selectively electrically connected to the plurality of second connection ends, and the length of the USB link formed by the first connection end and each second connection end is the same, but not limited to this; the control end is electrically connected to the processing chip 2, and the plurality of second connection ends correspond to the plurality of downstream interfaces 4 one by one and are electrically connected to each other; the processing chip 2 controls the first connection end to be electrically connected to one of the plurality of second connection ends through the control end.

[0084] By setting a multiple-choice-one connector, the USB device under test can be automatically switched between multiple downstream interfaces 4, thereby further improving the verification efficiency.

[0085] In a further optional embodiment of this embodiment, the USB device performance verification apparatus further includes: a status indicator light for indicating whether the verification of the tested USB device is completed. The status indicator light can be an indicator light independent of the connectivity indicator light 3 or directly the connectivity indicator light 3.

[0086] Specifically, taking the switching sequence of multiple downstream interfaces 4 and the working status of multiple connectivity indicator lights 3 controlled by the processing chip 2 in this embodiment as an example, when the processing chip 2 fails to identify the USB device under test through the downstream interface PortB, the corresponding indicator light B will always remain off. However, for the user, by observing the indicator light B, it is not certain whether the current USB device under test is in the stage of being verified through the downstream interface PortB, or in the stage of completing the verification through the downstream interface PortB, or in the state of verification stagnation due to device failure, etc. In this way, by setting the status indicator light, the user can quickly determine whether the verification of the USB device under test has been completed.

[0087] Among them, when the status indicator light is the connectivity indicator light 3, the indicator light's color and / or specific lighting state can be adjusted to distinguish whether the indicator light indicates whether the processing chip 2 has successfully identified or recognized, or whether the verification of the tested USB device is completed.

[0088] For example, when the processing chip 2 identifies the USB device under test through the downstream interface PortB, if the identification is successful, the indicator light B is always on, and if the identification is not successful, the indicator light B is off. After the processing chip 2 successfully identifies the USB device under test through the downstream interface PortB, the processing chip 2 controls the multiple-choice selector to connect the USB device under test to the downstream interface PortA. In the case that the processing chip 2 does not identify the USB device under test through the downstream interface PortA, the indicator light A is off, and the indicator light B or the indicator lights B to D are controlled to flash synchronously to indicate that the verification of the USB device under test is completed; in the case that the processing chip 2 identifies the USB device under test through the downstream interface PortA, the processing chip 2 controls the indicator light A or the indicator lights A to D to flash synchronously to indicate that the verification of the USB device under test is completed.

[0089] When the processing chip 2 fails to identify the USB device under test through the downstream interface PortD, the processing chip 2 controls the indicator lights A to D to flash alternately to indicate that the verification of the USB device under test is completed and to distinguish it from the highly reliable verification result of the USB device under test.

[0090] In this embodiment, a timing module is provided on the processing chip 2. The timing module is used to start timing when it is detected that the USB device under test is plugged into the downstream interface 4, and trigger the processing chip 2 to execute the sending status reminder process after the timing starts and a preset period of time has passed, so that the processing chip 2 controls the status indicator light to give corresponding indications according to the connection status of the USB device under test and the downstream interface 4, so as to indicate that the processing chip 2 has completed the verification of the USB device under test. At the same time, this embodiment does not specifically limit the processing chip 2 to control the corresponding indicator light to indicate whether the verification of the USB device under test is completed.

[0091] Furthermore, the USB device performance verification device further includes: a circuit board 7. The upstream interface 1, the processing chip 2, the plurality of connection indicator lights 3 and the plurality of downstream interfaces 4 are all fixedly arranged on the circuit board 7, and the processing chip 2 is electrically connected to the plurality of downstream interfaces 4 through the circuit board 7 to form a USB link.

[0092] The multiple-choice connector is fixedly set on the circuit board 7 and is electrically connected to the multiple downstream interfaces 4 through the circuit board 7. The lengths of the multiple USB links formed by the first connection end and the processing chip 2 through the multiple downstream interfaces 4 are different from each other, but are not limited to this; the processing chip 2 is electrically connected to the multiple-choice connector and the upstream interface 1 through the circuit board 7.

[0093] In this embodiment, the circuit board 7 is a PCB (Printed Circuit Board), the length of the USB link formed by the first connection end and each downstream interface 4 is the same, and the length of the USB link formed by each downstream interface 4 and the processing chip 2 is different; the dielectric loss factor of the circuit board 7 is greater than or equal to 0.1 and less than 0.5, such as 0.2, 0.25, 0.3, 0.35, 0.4 or 0.45, but is not limited to this.

[0094] By using a PCB made of high dielectric loss factor material, it is possible to simulate the loss of a larger spatial length within a limited spatial length, thereby increasing the USB link loss and creating a harsh environment.

[0095] Furthermore, the USB device performance verification apparatus also includes: a power management unit 8, used to allocate a power network to the processing chip 2; a storage unit 9, used to store the logic code involved in this embodiment; and a clock unit 10, which provides a clock to the USB device performance verification apparatus.

[0096] The USB device performance verification device provided in this embodiment has a simple structure and low preparation cost, which not only improves the verification efficiency but also saves human resources and the cost of setting up the verification environment.

[0097] Example 2

[0098] This embodiment provides a USB device performance verification method, which is applied to the processing chip 2 in Embodiment 1.

[0099] Combination Figures 1 to 3 , the method comprising:

[0100] When the target downstream interface is connected to the USB device under test, determining whether the USB device under test is identified, the target downstream interface is the downstream interface 4 currently connected to the USB device under test;

[0101] When the USB device under test is identified, the connectivity indicator light 3 corresponding to the target downstream interface is lit.

[0102] In a further optional embodiment of this embodiment, before the step of determining whether the tested USB device is identified, the method further includes:

[0103] Power the USB device under test through the target downstream interface;

[0104] The method also includes:

[0105] When the USB device under test is not identified, determining whether the number of times the USB device under test is not identified under the target downstream interface exceeds an identification threshold;

[0106] When the number of times the USB device under test is not recognized under the target downstream interface does not exceed the recognition threshold, the step of supplying power to the USB device under test through the target downstream interface is performed to perform power-on recognition of the USB device under test again through the target downstream interface.

[0107] The recognition threshold may be 2, 3, or 4. In this embodiment, the recognition threshold is 2.

[0108] In a further optional embodiment of this embodiment, after the step of lighting up the connectivity indicator light 3 corresponding to the target downlink interface, the method further includes:

[0109] Determine whether the USB link formed by the target downstream interface and the processing chip 2 is the longest USB link;

[0110] When the USB link formed by the target downstream interface and the processing chip 2 is not the longest USB link, the next connected downstream interface 4 with a longer USB link is switched as the target downstream interface, and the step of determining whether the tested USB device is identified is performed.

[0111] It can be understood that the step of switching the next connected USB downstream interface 4 with a longer link as the target downstream interface is to connect the USB device under test to the next connected USB downstream interface 4 with a longer link, which can be achieved manually or electrically, and will not be elaborated here.

[0112] Example 3

[0113] Based on Example 2, this example also provides a USB device performance verification method, which is applied to the processing chip 2 in Example 1.

[0114] Combination Figures 1 to 3 , the method comprising:

[0115] When the USB device under test is inserted into the target downstream interface, the corresponding power supply control module 6 is controlled to supply power to the USB device under test through the target downstream interface, and the target downstream interface is the downstream interface 4 currently connected to the USB device under test; wherein the USB device under test is inserted into the corresponding downstream interface 4 in the order of the USB link connected to the downstream interface 4 from short to long;

[0116] Determine whether the USB device under test is recognized;

[0117] When the USB device under test is identified, the connectivity indicator light 3 corresponding to the target downstream interface is lit;

[0118] When the USB device under test is not identified, determining whether the number of times the USB device under test is not identified under the target downstream interface exceeds an identification threshold;

[0119] When the number of times that the USB device under test is not recognized under the target downstream interface does not exceed the recognition threshold, performing the step of supplying power to the USB device under test through the target downstream interface;

[0120] When the number of times that the USB device under test is not recognized under the target downstream interface exceeds the recognition threshold, it indicates that the verification of the USB device under test is completed, and the control status indicator light is adjusted to a state for indicating the end of verification, so as to end the verification of the device under test;

[0121] After the step of lighting up the connectivity indicator light 3 corresponding to the target downstream interface, determining whether the USB link formed by the target downstream interface and the processing chip 2 is the USB link A;

[0122] When the USB link formed by the target downstream interface and the processing chip 2 is not the USB link A, according to the order of the USB links connected to the downstream interfaces 4 from short to long, the next downstream interface 4 with a longer USB link is switched as the target downstream interface, and the step of controlling the corresponding power supply control module 6 to supply power to the USB device under test through the target downstream interface is first executed, and then the step of determining whether the USB device under test is identified is sequentially executed;

[0123] When the USB link formed by the target downstream interface and the processing chip 2 is USB link A, it means that the verification of the USB device under test is completed, and the control status indicator light is adjusted to a state indicating the end of verification to end the verification of the device under test.

[0124] Example 4

[0125] Based on Embodiments 2 and 3, this embodiment provides a USB device performance verification system, the system is applied to a processing chip 2, the processing chip 2 is electrically connected to an upstream interface 1, a plurality of connectivity indicator lights 3 and a plurality of downstream interfaces 4, respectively, the upstream interface 1 is used to connect to a USB host, the downstream interface 4 is used to connect to a USB device under test, the connectivity indicator lights 3 correspond to the downstream interfaces 4 one by one, and the length of the USB link formed by each downstream interface 4 and the processing chip 2 is different;

[0126] Combination Figures 1 to 3 The system comprises:

[0127] A first judgment module is configured to judge whether the USB device under test is identified when the target downstream interface is connected to the USB device under test, and the target downstream interface is the downstream interface 4 currently connected to the USB device under test;

[0128] The lighting module is configured to light up the connectivity indicator light 3 corresponding to the target downstream interface when the USB device under test is identified.

[0129] In a further optional embodiment of this embodiment, the system further includes:

[0130] A power supply module, configured to supply power to the USB device under test through the target downstream interface before executing the first judgment module;

[0131] The second judgment module is configured to judge whether the number of times that the USB device under test is not recognized under the target downstream interface exceeds the recognition threshold when the first judgment module judges that the processing chip 2 does not recognize the USB device under test;

[0132] The trigger module is configured to trigger the power supply module to supply power to the USB device under test through the target downstream interface when the second judgment module determines that the number of times the USB device under test is not recognized under the target downstream interface does not exceed the recognition threshold.

[0133] In a further optional embodiment of this embodiment, the system further includes:

[0134] A third judgment module is configured to judge whether the USB link formed by the target downstream interface and the processing chip 2 is the longest USB link after the lighting module lights up the connectivity indicator light 3 corresponding to the target downstream interface;

[0135] The switching module is configured to switch the next connected downstream interface 4 with a longer USB link as the target downstream interface when the third judgment module determines that the USB link formed by the target downstream interface and the processing chip 2 is not the longest USB link, and trigger the first judgment module to determine whether the USB device under test is identified.

[0136] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0137] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A USB device performance verification device, characterized in that: The USB device performance verification device comprises: an upstream interface, a processing chip, a plurality of connection indicator lights and a plurality of downstream interfaces; The processing chip is electrically connected to the upstream interface, multiple connectivity indicator ports and multiple downstream interfaces respectively. The upstream interface is used to connect to a USB host, and the downstream interface is used to connect to a USB device under test. The connectivity indicator lights correspond to the downstream interfaces one by one, and the length of the USB link formed by each downstream interface and the processing chip is different.

2. The USB device performance verification device according to claim 1, characterized in that: The USB device performance verification device further includes: a plurality of capacitors; Each of the downstream interfaces is electrically connected to the processing chip via one of the capacitors on the corresponding USB link.

3. The USB device performance verification device according to claim 1, characterized in that: The USB device performance verification device further includes: a plurality of power supply control modules; The power supply control module corresponds to the downlink interface one by one, and the power supply control module includes: a control end, an input end and an output end; The control end is electrically connected to the processing chip, the input end is used to connect to an external power supply, the output end is electrically connected to the corresponding downlink interface, and the processing chip controls the on and off of the input end and the output end through the control end.

4. The USB device performance verification device according to any one of claims 1 to 3, characterized in that: The USB device performance verification device further includes: a circuit board; The upstream interface, the processing chip, the plurality of connectivity indicator lights and the plurality of downstream interfaces are all fixedly arranged on the circuit board, and the processing chip is electrically connected to the plurality of downstream interfaces through the circuit board to form the USB link; The dielectric loss factor of the circuit board is greater than or equal to 0.1 and less than 0.

5.

5. A USB device performance verification method, characterized in that: The method is applied to a processing chip, wherein the processing chip is electrically connected to an upstream interface, a plurality of connectivity indicator ports, and a plurality of downstream interfaces respectively, wherein the upstream interface is used to connect to a USB host, and the downstream interface is used to connect to a USB device under test, wherein the connectivity indicator lights correspond to the downstream interfaces one by one, and the lengths of USB links formed between each of the downstream interfaces and the processing chip are different; The method comprises: When a target downstream interface is connected to the USB device under test, determining whether the USB device under test is identified, the target downstream interface being the downstream interface currently connected to the USB device under test; When the tested USB device is identified, the connectivity indicator light corresponding to the target downstream interface is turned on.

6. The method according to claim 5, characterized in that Before the step of determining whether the tested USB device is identified, the method further includes: Supplying power to the USB device under test through the target downstream interface; The method further comprises: When the USB device under test is not identified, determining whether the number of times that the USB device under test is not identified on the target downstream interface exceeds an identification threshold; When the number of times that the USB device under test is not recognized at the target downstream interface does not exceed the recognition threshold, the step of supplying power to the USB device under test through the target downstream interface is performed.

7. The method according to claim 5 or 6, characterized in that: After the step of lighting up the connectivity indicator light corresponding to the target downlink interface, the method further includes: Determine whether the USB link formed by the target downstream interface and the processing chip is the longest USB link; When the USB link formed by the target downstream interface and the processing chip is not the longest USB link, the next connected downstream interface with a longer USB link is switched as the target downstream interface, and the step of determining whether the tested USB device is identified is performed.

8. A USB device performance verification system, characterized in that: The system is applied to a processing chip, the processing chip is electrically connected to an upstream interface, a plurality of connectivity indicator ports and a plurality of downstream interfaces respectively, the upstream interface is used to connect to a USB host, the downstream interface is used to connect to a USB device under test, the connectivity indicator lights correspond to the downstream interfaces one by one, and the lengths of the USB links formed by each of the downstream interfaces and the processing chip are different; The system comprises: A first judgment module is configured to judge whether the USB device under test is identified when the target downstream interface is connected to the USB device under test, wherein the target downstream interface is the downstream interface currently connected to the USB device under test; The lighting module is configured to light up the connectivity indicator light corresponding to the target downstream interface when the tested USB device is identified.

9. The system according to claim 8, characterized in that The system further comprises: a power supply module, configured to supply power to the USB device under test through the target downstream interface before executing the first determination module; A second judgment module is configured to judge whether the number of times that the USB device under test is not recognized under the target downstream interface exceeds a recognition threshold when the first judgment module judges that the processing chip fails to recognize the USB device under test; The trigger module is configured to trigger the power supply module to supply power to the USB device under test through the target downstream interface when the second judgment module determines that the number of times the USB device under test is not recognized under the target downstream interface does not exceed the recognition threshold.

10. The system according to claim 8 or 9, characterized in that The system further comprises: A third judgment module is configured to judge whether the USB link formed by the target downstream interface and the processing chip is the longest USB link after the lighting module lights up the connectivity indicator light corresponding to the target downstream interface; The switching module is configured to switch the next connected downstream interface with a longer USB link as the target downstream interface when the third judgment module determines that the USB link formed by the target downstream interface and the processing chip is not the longest USB link, and trigger the first judgment module to determine whether the tested USB device is identified.

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