Cache consistency optimization method and device, equipment and storage medium

Abstract

The embodiment of the invention relates to the technical field of computers, and discloses a cache consistency optimization method and device, equipment and a storage medium, and the method comprises the steps: responding to a cache consistency operation request sent by a current processor core, and obtaining a memory address corresponding to the cache consistency operation request; determining a target interception bus from the multiple sets of buses according to a memory address corresponding to the cache consistency operation request, and using the target interception bus to complete the cache consistency operation request; or, according to the memory address corresponding to the cache consistency operation request, a plurality of related processor cores needing to respond to the cache consistency operation request are determined, the current processor and all the related processor cores are used for completing the cache consistency operation request, and efficient maintenance of cache consistency is achieved with low overhead.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technology, and in particular to a cache consistency optimization method, device, equipment and storage medium. Background Art

[0002] Each processor core on a modern multi-core processor has a cache to improve data access speed and ensure the convenience of program writing. When running parallel programs, multiple threads or processes running on multiple processor cores may read and write data in the same shared memory area. In order to ensure the correctness of parallel program operation, cache coherence is required between different processors in the same computing node and between different processor cores of the same processor, so that the same data is consistent between the caches of multiple processor cores.

[0003] The snooping-based consistency protocol (snooping protocol for short) is one of the main ways to maintain cache consistency. The implementation of the snooping protocol relies on a bus or bus-like network connection (such as 2D Mesh, etc.). Based on this network connection, all requests issued by the private cache of a single processor core will be broadcast to the private caches of all other processor cores in the system, and the access requests of all processor cores can also be sequenced on this bus to achieve the requirements for memory access order in the cache consistency model and storage identity model.

[0004] Although the snooping protocol has low hardware implementation overhead and low operating power consumption, the competitive access and orderly response of all processor cores to the bus will cause performance bottlenecks, making the snooping protocol almost only applicable to the case of a small number of processor cores. Currently, the number of cores in a CPU has reached hundreds, and a computing node of a supercomputer usually has at least two CPUs, which requires supporting cache consistency for 200 or even more processor cores. Therefore, it is urgent to optimize the snooping protocol so that the snooping protocol can be applied to the case of a large number of cores, so as to achieve the goal of efficiently maintaining cache consistency with less hardware overhead. Summary of the invention

[0005] The purpose of the present invention is to at least provide a cache consistency optimization method, device, equipment and storage medium, which can at least solve the performance bottleneck of the existing listening protocol and at least achieve the effect of efficiently maintaining cache consistency with less hardware overhead.

[0006] To solve the above technical problems, at least one embodiment of the present application provides a cache consistency optimization method, including:

[0007] In response to a cache coherence operation request initiated by the current processor core, obtaining a memory address corresponding to the cache coherence operation request;

[0008] A target listening bus is determined from multiple buses according to a memory address corresponding to a cache coherence operation request, and the target listening bus is used to complete the cache coherence operation request; or, a number of related processor cores that need to respond to the cache coherence operation request are determined according to a memory address corresponding to the cache coherence operation request, and the cache coherence operation request is completed using the current processor and all related processor cores.

[0009] In some optional embodiments, determining a target listening bus from a plurality of buses according to a memory address corresponding to a cache coherence operation request includes:

[0010] Determine an address tag of a memory address corresponding to the cache coherence operation request, the address tag including memory address bits in the memory address excluding a cache block size;

[0011] A target listening bus is determined from multiple buses according to a mapping relationship between an address tag and a bus number.

[0012] In some optional embodiments, the method further comprises:

[0013] Determine the load balance of multiple buses within a preset time period, where the load balance is used to measure the proximity of the number of cache coherence operation requests processed by each bus;

[0014] When the load balance of the multiple buses is lower than a preset threshold within a preset time period, the mapping relationship between the address tag and the bus number is adjusted.

[0015] In some optional embodiments, determining the load balance of multiple buses within a preset time period includes:

[0016] The ratio of an average value of the number of cache coherence operation requests processed by the multiple buses within a preset time period to a maximum value is determined as the load balance of the multiple buses within the preset time period.

[0017] In some optional embodiments, determining a number of related processor cores that need to respond to the cache coherence operation request according to the memory address corresponding to the cache coherence operation request includes:

[0018] According to the memory address corresponding to the cache consistency operation request and the global cache status bit table, a number of related processor cores that need to respond to the cache consistency operation request are determined, each table entry in the global cache status bit table corresponds to a processor core, and a status bit of each table entry corresponds to an identification address segment, which is used to characterize whether the corresponding processor core currently caches the data of the corresponding identification address segment, and the global cache status bit table is consistent with the real-time cache status table of each processor core; wherein, an identification address segment is a subspace with continuous addresses in the memory address space.

[0019] In some optional embodiments, the method further comprises:

[0020] If all data cached by the current core group belongs to the same identification address segment and all other processor cores do not cache data in the identification address segment, the local bus of the current core group is separated from the global bus; wherein all processor cores of the current processor are divided into several non-overlapping core groups.

[0021] In some optional embodiments, determining a number of related processor cores that need to respond to the cache coherence operation request according to the memory address corresponding to the cache coherence operation request includes:

[0022] According to the memory address corresponding to the cache consistency operation request and the directory table entries of each core group, the relevant core group that needs to respond to the cache consistency operation request is determined, and monitoring is initiated for all relevant processor cores of all relevant core groups. The directory table entries record the sharing status of each cache block among all core groups; among them, all processor cores of the current processor are divided into several non-overlapping core groups.

[0023] In some optional embodiments, the directory entry records the sharing of each cache block among all core groups, including:

[0024] The method for the directory entry to record the sharing status of each cache block among all core groups includes any one of a real-time counting method, a historical marking method or a bitmap method or a combination thereof;

[0025] The real-time counting method has several counters in each directory entry, where each counter records the real-time sharing times of the corresponding cache block by the core set composed of several core groups;

[0026] The history marking method has several history marking bits in each directory table entry, where each history marking bit records whether a core set consisting of several core groups has ever accessed a corresponding cache block;

[0027] The bitmap method is used to record the precise sharing status of the corresponding cache block among the processor cores in the owner core group when a directory entry belongs to a unique owner core group.

[0028] At least one embodiment of the present application further provides a cache consistency optimization device, including:

[0029] A response module, used to respond to a cache coherence operation request initiated by the current processor core and obtain a memory address corresponding to the cache coherence operation request;

[0030] A processing module is used to determine a target listening bus from multiple buses according to a memory address corresponding to a cache consistency operation request, and use the target listening bus to complete the cache consistency operation request; or, determine a number of related processor cores that need to respond to the cache consistency operation request according to a memory address corresponding to the cache consistency operation request, and use the current processor and all related processor cores to complete the cache consistency operation request.

[0031] At least one embodiment of the present application also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned cache consistency optimization method.

[0032] At least one embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned cache consistency optimization method when executed by a processor.

[0033] The cache consistency optimization method, apparatus, device and storage medium provided by the embodiments of the present application obtain the memory address corresponding to the cache consistency operation request by responding to the cache consistency operation request initiated by the current processor core; determine the target listening bus from multiple buses according to the memory address corresponding to the cache consistency operation request, and use the target listening bus to complete the cache consistency operation request; or, determine a number of related processor cores that need to respond to the cache consistency operation request according to the memory address corresponding to the cache consistency operation request, and use the current processor and all related processor cores to complete the cache consistency operation request, thereby achieving efficient maintenance of cache consistency with relatively low overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] One or more embodiments are exemplarily described by the pictures in the corresponding drawings, and these exemplary descriptions do not constitute limitations on the embodiments.

[0035] Figure 1 This is a process of a cache consistency optimization method provided by an embodiment of the present application Figure 1 ;

[0036] Figure 2 This is the process of the cache consistency optimization method provided by another embodiment of the present application Figure 2 ;

[0037] Figure 3 This is a process of a cache consistency optimization method provided by another embodiment of the present application. Figure 3 ;

[0038] Figure 4 This is the process of the cache consistency optimization method provided by another embodiment of the present application Figure 4 ;

[0039] Figure 5 is a schematic diagram of a cache consistency optimization device provided by an embodiment of the present application;

[0040] Figure 6 It is a schematic diagram of the structure of an electronic device provided by another embodiment of the present application. DETAILED DESCRIPTION

[0041] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0042] In order to facilitate understanding of the embodiments of the present application, relevant content about cache consistency is first introduced here.

[0043] There are two main cache consistency protocols: the consistency protocol based on the form of listening (hereinafter referred to as the listening protocol) and the consistency protocol based on the directory structure (hereinafter referred to as the directory protocol). Among them, the implementation of the listening protocol depends on a bus or bus-like network connection. Using this network connection, all requests issued by the private cache of a single processor core will be broadcast to the private caches of all other processor cores in the system, and the access requests of all processors can also be sequenced on this bus to achieve the requirements for access order in the cache consistency model and the storage identity model. The listening protocol can also handle multiple conflicting requests for the same data block well through the bus structure, and the private caches of multiple processors can also communicate directly through this bus structure, reducing communication delays. The directory protocol uses a directory structure to manage cache blocks (Cache lines). In the directory protocol, the memory access request issued by the private cache of the processor core will first be sent to the directory structure that has the corresponding cache block. This directory structure records the sharing status of the current cache block. The controller will determine the private cache or memory of the processor core that responds to this request based on the current sharing status.

[0044] The snooping protocol and the directory protocol each have their own advantages and disadvantages. For specific applications in current commercial CPUs, the snooping protocol has low hardware implementation overhead and low operating power consumption, but it is easy to become a bottleneck for parallel performance due to the competitive access and orderly response of all processor cores to the bus; the directory protocol can enable the consistency maintenance of cache blocks with different addresses to be completed in parallel, so it can efficiently achieve cache consistency, but on the one hand, it causes hardware overhead due to the need to record the shared access status of a large number of cache blocks, and on the other hand, the process of finding the corresponding record of a cache block from the directory will also introduce a large delay. Moreover, the number of cores in a CPU has reached hundreds, and a computing node of a supercomputer usually has at least two CPUs, which requires supporting the cache consistency of 200 or even more processor cores. For the snooping protocol, the competitive use of the bus (or network) will also restrict the performance of parallel programs more significantly. The directory protocol will encounter bottleneck problems, especially the directory will become larger and the access delay will be increased. In response to the above problems, for example, a simplified directory protocol or a multi-level hybrid of the directory protocol and the snooping protocol can be adopted. Specifically, a table entry in the directory manages the shared information of multiple (such as 4 or 8) consecutive cache blocks of memory addresses to significantly reduce the size of the directory (i.e., the number of table entries); the processor cores are grouped, each group of processor cores shares a directory, and each directory corresponds to a physical memory with a continuous address range, and the memory address ranges corresponding to different directories do not overlap; the processor cores are grouped, each group of processor cores shares a bus for monitoring, and directories are used between groups, wherein each table entry in the directory records which core groups use the corresponding cache block (without recording the specific cores in the core group).

[0045] In order to solve at least one of the above technical problems, the present invention proposes a cache consistency optimization method. The implementation details of the cache consistency optimization method of this embodiment are specifically described below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for the implementation of this solution.

[0046] Embodiment 1:

[0047] The cache consistency optimization method provided in this embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as follows: Figure 1 As shown, including:

[0048] S101. In response to a cache coherence operation request initiated by a current processor core, obtain a memory address corresponding to the cache coherence operation request.

[0049] In the case of multiple sets of buses, it is necessary to ensure that multiple cache consistency operation requests corresponding to the same cache block initiated by different processor cores are assigned to the same set of buses. In other words, it is necessary to ensure that cache consistency operation requests processed on different buses correspond to different cache blocks. Whether two cache consistency operation requests belong to the same cache block is determined by the memory addresses corresponding to the two requests. The memory address corresponding to the cache consistency operation request is obtained in order to confirm the bus that processes the cache consistency operation request. In the NUMA structure based on multi-channel memory technology, each identification address segment can correspond to the memory of a channel, and each memory channel corresponds to a core group. The memory address corresponding to the cache consistency operation request is obtained in order to confirm the core group that processes the cache consistency operation request.

[0050] S102. Determine a target listening bus from multiple buses according to the memory address corresponding to the cache consistency operation request, and use the target listening bus to complete the cache consistency operation request; or, determine a number of related processor cores that need to respond to the cache consistency operation request according to the memory address corresponding to the cache consistency operation request, and use the current processor and all related processor cores to complete the cache consistency operation request.

[0051] The cache consistency optimization method provided in this embodiment obtains the memory address corresponding to the cache consistency operation request by responding to the cache consistency operation request initiated by the current processor core; and determines the target listening bus from multiple buses according to the memory address corresponding to the cache consistency operation request, and uses the target listening bus to complete the cache consistency operation request; or, determines a number of related processor cores that need to respond to the cache consistency operation request according to the memory address corresponding to the cache consistency operation request, and uses the current processor and all related processor cores to complete the cache consistency operation request, thereby achieving efficient maintenance of cache consistency with a relatively small overhead, so that the listening protocol can be applied to the case of a large number of cores, and solves the performance bottleneck caused by competitive use of the bus.

[0052] Embodiment 2:

[0053] In this application, "bus" is used to collectively refer to the bus or bus-like network connection required by the listening protocol. In traditional processors that use the listening protocol, only one set of buses is often used to maintain cache consistency between all processor cores managed by the listening protocol. However, with the continuous development of computer technology, there will be multiple sets of buses between all processor cores in the computer. Letting multiple sets of buses cooperate and complete multiple cache consistency operations in parallel is an important means to improve the efficiency of cache consistency maintenance.

[0054] The cache consistency optimization method provided in this embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as follows: Figure 2 As shown, including:

[0055] S201. In response to a cache coherence operation request initiated by a current processor core, obtain a memory address corresponding to the cache coherence operation request.

[0056] When multiple processor cores initiate multiple cache consistency operation requests at the same time, it is necessary to determine which set of buses each cache consistency operation request uses. The bus has the function of sequencing multiple cache consistency operation requests to ensure that multiple cache consistency operation requests corresponding to the same cache block are executed in order. In the case of multiple sets of buses, it is necessary to ensure that multiple cache consistency operation requests corresponding to the same cache block initiated by different processor cores are assigned to the same set of buses. In other words, it is necessary to ensure that cache consistency operation requests processed on different buses correspond to different cache blocks. Whether two cache consistency operation requests belong to the same cache block is determined by the memory addresses corresponding to the two requests. Therefore, in this embodiment, when responding to the cache consistency operation request initiated by the current processor core, the memory address corresponding to the cache consistency operation request is obtained to determine the cache block corresponding to the cache consistency operation request.

[0057] S202: Determine an address tag of a memory address corresponding to a cache coherence operation request, where the address tag includes memory address bits in the memory address except for a cache block size.

[0058] Whether two cache coherence operation requests belong to the same cache block is determined by the memory addresses corresponding to the two requests, in particular, by the memory address bits other than the cache block size. For example, corresponding to a 64-bit memory address and a 64-byte cache block size, if the upper 58 bits of the memory addresses corresponding to the two requests are the same, then the two requests correspond to the same cache block. In this application, the memory address bits other than the cache block size are recorded as address tags. Therefore, in this embodiment, after obtaining the memory address corresponding to the cache coherence operation request, the memory address bits in the memory address other than the cache block size are determined as the address tags of the memory address corresponding to the cache coherence operation request.

[0059] S203: Determine a target listening bus from multiple buses according to a mapping relationship between the address tag and the bus number, and use the target listening bus to complete the cache coherence operation request.

[0060] The key to bus collaboration lies in the mapping relationship between address tags and bus numbers. The mapping relationship between address tags and bus numbers can be established in advance, and each bus can be matched with a different cache block through the mapping relationship. In an optional implementation, some bits in the address tag of the cache consistency operation request can be used to determine the bus number corresponding to the request. For example, the lowest few bits in the address tag can be used to determine the bus number. Take 4 sets of buses as an example, these buses are numbered 0 to 3, and then the bus number is determined by the lowest two bits in the address tag. When the lowest two bits in the address tag of a cache consistency operation request are 10, the request is completed by bus No. 2, that is, the target listening bus at this time is bus No. 2. The maximum memory capacity of a computing node often does not exceed 4TB, and the size of the cache block is usually 64 bytes. Therefore, for the address tag, 36 bits are sufficient, that is, the address bit width on a set of buses is sufficient to be 36 bits, which can separate multiple sets of buses from the network for exchanging cache block data between processing cores.

[0061] In this embodiment, after determining the address tag of the memory address corresponding to the cache consistency operation request, the target listening bus can be determined from multiple buses based on the mapping relationship between the address tag and the bus number, and the target listening bus can be used to complete the cache consistency operation request. This makes it possible to have only one network for exchanging cache block data between processing cores even when there are multiple listening buses, which can significantly reduce the hardware overhead of implementing multiple listening buses.

[0062] It is understandable that when there are multiple sets of buses, load balancing needs to be maintained between the multiple sets of buses so that the multiple sets of buses can fully play the role of acceleration when the cache consistency operation requests are intensive. One way to quantify load balancing is to see whether the number of cache consistency operation requests processed by different buses is similar over a period of time. The target listening bus that responds to the cache consistency operation request can be adjusted based on the load balancing to further improve the efficiency of maintaining cache consistency. Based on the above embodiment, the cache consistency optimization method provided in this embodiment can further include:

[0063] S204: Determine the load balance of the multiple buses within a preset time period, where the load balance is used to measure the proximity of the number of cache coherence operation requests processed by each bus.

[0064] In this embodiment, load balancing is used to measure the proximity of the number of cache consistency operation requests processed by each bus. A specific method for calculating load balancing can be to find the ratio of the maximum number of requests between all buses to the average number of requests between all buses. The closer the ratio is to 1, the more balanced it is.

[0065] In some optional implementations, determining the load balance of multiple buses within a preset time period may specifically include: determining the load balance of multiple buses within the preset time period as the ratio of an average value to a maximum value of the number of cache coherence operation requests processed by the multiple buses within the preset time period. The lower the ratio, the more unbalanced the loads of the buses are.

[0066] S205: When the load balance of the multiple buses within a preset time period is lower than a preset threshold, adjust the mapping relationship between the address tag and the bus number.

[0067] The matching degree of the memory access mode and mapping relationship of each thread of the application determines the load balancing to a large extent. For example, the mapping relationship using the lowest few bits of the address tag is suitable for the situation where each thread performs sequential memory access; when each thread jumps to access memory at intervals of 4 cache blocks, it is possible that most cache consistency operation requests are assigned to the same bus while other buses are idle. The memory access behavior of an application is often not fixed, and the memory access behavior between different applications is often different. Therefore, in this embodiment, load balancing of multiple buses can be achieved by adjusting the mapping relationship.

[0068] In this embodiment, the mapping relationship can be divided into two categories: static mapping relationship and dynamic mapping relationship. Static mapping relationship means that there is only one mapping relationship in the processor, that is, different applications and different time periods of the same application use the same mapping relationship; dynamic mapping relationship means that the specific mapping relationship can change during the program running process. In order to achieve load balancing of multiple sets of buses, dynamic mapping relationship is adopted in this embodiment. A specific implementation method is: the management device of multiple sets of buses monitors the load balance between multiple sets of buses within a threshold period (or preset duration), and when it is found that the load balance is lower than the preset threshold, the mapping relationship is adjusted. For example, for the case of 4 sets of buses, when it is found that the mapping relationship using the lowest two bits of the address mark causes load imbalance, the mapping relationship can be adjusted to use the lowest second and third bits of the address mark. For multiple sets of buses, it is easy to dynamically adjust the mapping relationship, on the one hand because the number of buses will not be too many, and on the other hand because the bus does not save data but only performs transaction processing. When the mapping relationship needs to be adjusted dynamically, it is only necessary to suspend the assignment of new cache consistency operation requests to the bus. After all existing cache consistency operation requests on all buses have been completed, the mapping relationship can be adjusted. After the mapping relationship is adjusted, new cache consistency operation requests can be assigned according to the new mapping relationship.

[0069] The cache consistency optimization method provided in this embodiment, based on the above embodiment, further realizes load balancing between multiple buses by dynamically adjusting the mapping relationship between address tags and bus numbers, thereby further improving the efficiency of maintaining cache consistency.

[0070] Embodiment three:

[0071] At present, many multi-core processors use the non-uniform memory access (NUMA) structure based on multi-channel memory. Specifically, when a processor can connect to 8 memory channels, all processor cores are divided into 8 core groups, and each core group corresponds to a memory channel. Each core group has a fast access speed to the memory of its corresponding channel, while the access speed to the memory of other channels is much slower. Generally speaking, the memory address segments of different channels are completely separated, which can be specifically manifested as the memory addresses of different channels are different in the high-order segments. For example, there are 8 channel memories (numbered 0 to 7) and the memory capacity of each channel is 32GB. The 0th to 34th bits of the memory address (the 0th bit is the lowest bit) are used to distinguish different memory locations in the same channel, and the 35th to 37th bits are the memory channel number. Modern operating systems, compilers and even parallel programmers will make many performance optimizations based on the NUMA structure, so that a core group can access its corresponding channel memory as much as possible and try to avoid using other channel memories, thereby improving the performance of parallel programs. Therefore, in most cases, the cache consistency operations initiated by each processor core in a core group will only involve the processor cores in the core group. Despite this, traditional snooping protocols will still broadcast any cache coherence operations to all processor cores and require responses from all processor cores, which not only results in a large amount of redundant response overhead, but also causes each processor core to perform a large number of redundant address queries and corresponding power consumption.

[0072] In order to reduce redundant responses and redundant address queries of the snooping protocol, in this embodiment, the memory address space is first divided into several non-overlapping address segments, which are called identification address segments. When there is a NUMA structure based on multi-channel memory technology, each identification address segment can correspond to the memory of a channel, and each memory channel corresponds to a core group. Each processor core records whether its private cache currently caches the data of each identification address segment, that is, maintains the real-time cache status table of all identification address segments. When cache replacement occurs, the real-time cache status table changes. In a specific implementation, each table entry in the real-time cache status table is a cache block count of an identification address segment, that is, when a cache block corresponding to an identification address segment is swapped in, the table entry of the real-time cache status table corresponding to the identification address segment is increased by 1; when a cache block corresponding to an identification address segment is swapped out, the table entry of the real-time cache status table corresponding to the identification address segment is reduced by 1. When the table entry corresponding to an identification address segment in the real-time cache status table is 0, it indicates that the current processor core does not cache the data in the corresponding identification address segment. The listening protocol management device records the global cache status bit table of all processor cores, wherein each table entry in the global cache status bit table corresponds to a processor core, and a status bit of each table entry corresponds to an identification address segment, which is used to indicate whether the corresponding processor core currently caches the data of the corresponding identification address segment. The global cache status bit table needs to be consistent with the real-time cache status table of each processor core, but the global cache status bit table does not need to be synchronized as soon as any real-time cache status table changes. Only when a table entry in a cache status table changes between 0 and non-0, the global cache status bit table needs to be changed accordingly. Such an implementation can avoid frequent changes to the global cache status bit table and corresponding overhead.

[0073] The cache consistency optimization method provided in this embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as follows: Figure 3 As shown, it may specifically include:

[0074] S301. In response to a cache coherence operation request initiated by a current processor core, obtain a memory address corresponding to the cache coherence operation request.

[0075] S302, according to the memory address corresponding to the cache coherence operation request and the global cache status bit table, determine a number of related processor cores that need to respond to the cache coherence operation request, and use the current processor and all related processor cores to complete the cache coherence operation request. Wherein, each table entry in the global cache status bit table corresponds to a processor core, and a status bit of each table entry corresponds to an identification address segment, which is used to indicate whether the corresponding processor core currently caches the data of the corresponding identification address segment, and the global cache status bit table is consistent with the real-time cache status table of each processor core; wherein, an identification address segment is a subspace with continuous addresses in the memory address space.

[0076] In response to the current cache consistency operation request initiated by the current processor core, the processor core to be monitored is determined according to the current memory address corresponding to the cache consistency operation request and the global cache status bit table, and the monitoring request is only initiated for these processor cores. The specific implementation method is to determine the current identification address segment corresponding to the current memory address, determine all related processor cores that have cached the current identification address segment data according to the global cache status bit table, and then initiate a monitoring request for these related processor cores. For all irrelevant processor cores that have not cached the current identification address segment data, no monitoring request will be initiated, and no response from these irrelevant processor cores will be waited for, which significantly reduces redundant responses and redundant address queries.

[0077] In order to further improve the efficiency of processing cache consistency operations, the cache consistency optimization method provided by this embodiment may also include: if all data cached by the current core group belongs to the same identification address segment and all other processor cores have not cached the data of the identification address segment, the local bus of the current core group is separated from the global bus. Specifically, when the listening protocol management device finds that all data cached by the current core group belongs to the same identification address segment and all other processor cores have not cached the data of the identification address segment, the local bus of the current core group can be separated from the global bus, so that the cache consistency operation of the core group can be processed in parallel with the cache consistency operation of other processor cores to speed up the efficiency of processing cache consistency operations.

[0078] Embodiment 4:

[0079] The pure bus-based snooping protocol cannot be used in the case of a large number of processor cores, and the pure directory protocol cannot be used in the case of a large number of cores, because accurately marking the sharing of each cache block among all cores will cause unbearable hardware overhead (one core requires 1 bit to mark, and hundreds of bits are required when there are hundreds of cores). Many-core processors can use a hybrid method of directory and snooping, such as the snoop filter method. On the one hand, a directory table entry can manage the sharing of multiple cache blocks with consecutive addresses, and on the other hand, it is not necessary to accurately record the sharing of cache blocks: for example, record the core number of one or a few owners of the cache block, the current number of valid shares, etc. In the case of inaccurately recording the sharing of cache blocks, a cache consistency operation may require snooping of all processor cores. For example, when a directory table entry can only record the numbers of two cores of the cache block at most, if a cache block is being read and shared by three or more cores, and one core wants to modify this cache block, it is necessary to snoop all processor cores, which will obviously greatly reduce the efficiency of maintaining cache consistency. In order to solve this problem, all processor cores are first divided into several non-overlapping core groups, each with its own subdirectory. When there is a NUMA structure based on multi-channel memory technology, all cores in the same core group and all entries in its subdirectories can correspond to the same memory channel. Each directory entry records the sharing of the corresponding cache blocks among all core groups. Specifically, the sharing between core groups can be recorded by using any one of the real-time counting method, historical marking method or bitmap method or a combination of them.

[0080] a) Real-time counting method: There are several counters in each directory entry, each of which records the number of real-time sharing of the corresponding cache block by the core set composed of several core groups. Specifically, each directory entry has at least two counters, each of which corresponds to the core set composed of several core groups, and records the real-time sharing of all cache blocks corresponding to the directory entry by all processor cores in each core set. The count in a counter in a directory entry can be understood as the number of cores in the corresponding core set that currently effectively cache the corresponding cache blocks of the directory entry. For example, a counter of a directory entry corresponds to 16 processor cores, and the directory entry corresponds to 2 cache blocks. When 6 of the 16 cores currently effectively cache the first cache block and 3 cores effectively cache the second cache block, the current count of the counter is 9. When a cache block of a core becomes valid or invalidated, the corresponding counter in the unique directory entry corresponding to the cache block will change (increase by 1 or decrease by 1). There can be multiple corresponding relationships between counters and core groups. When the number of counters is the same as the number of core groups, each counter can correspond to one core group. When the number of counters is half the number of core groups, each counter can correspond to two core groups. When the number of counters is 2 and the number of core groups is greater than 2, one counter of a directory entry can correspond to the owner core group of the directory entry (when a directory entry only appears in a subdirectory of a unique core group, the core group is called the owner core group of the directory entry), and the other counter can correspond to all core groups or all other core groups except the owner core group; through these two counters, the sharing of the corresponding cache block by the owner core group and the sharing of all other core groups as a whole can be determined.

[0081] b) Historical marking method: There are several historical marking bits in each directory entry, each of which records whether a core set consisting of several core groups has ever accessed the corresponding cache block. There are at least two historical marking bits in each specific directory entry, each of which corresponds to a core set consisting of several core groups, and records whether all processor cores in each core set have ever accessed all cache blocks corresponding to the directory entry. When a core set has not accessed any cache block corresponding to a directory entry, the corresponding historical marking bit of the directory entry is marked as unaccessed, otherwise it is marked as accessed. When a cache block of a core becomes invalid, the historical marking bit in the directory entry will not change. Therefore, the historical marking method cannot accurately record the sharing of cache blocks, that is, there is a situation where there was sharing in the past but not currently shared, but it is considered to be currently shared. There can be multiple corresponding relationships between historical marking bits and core groups. When the number of historical marking bits is the same as the number of core groups, each historical marking bit can correspond to one core group. When the number of historical marking bits is half of the number of core groups, each historical marking bit can correspond to two core groups. When the number of historical mark bits is 2 and the number of core groups is greater than 2, one historical mark bit of a directory table entry may correspond to the owner core group of the directory table entry, while the other historical mark bit may correspond to all other core groups except the owner core group; through these two historical mark bits, the sharing status of the corresponding cache block by the owner core group and the sharing status of all other core groups as a whole can be determined.

[0082] c) Bitmap method: used to record the precise sharing status of the corresponding cache block among the processor cores in the owner core group when a directory entry belongs to a unique owner core group.

[0083] When a directory entry belongs to a unique owner core group, the directory entry may combine the bitmap method with the real-time counting method or the historical marking method to simultaneously record the precise sharing of the corresponding cache block between the processor cores in the owner core group and the sharing between the core groups. For example, for a processor with 8 core groups and each core group having 16 cores, each directory entry may have 16 bits (i.e., a 16-bit bitmap) to record the precise sharing of the corresponding cache block between the processor cores in its owner core group, and combine the real-time counting method or the historical marking method to record the sharing between the core groups.

[0084] The cache consistency optimization method provided in this embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as follows: Figure 4 As shown, including:

[0085] S401. In response to a cache coherence operation request initiated by a current processor core, obtain a memory address corresponding to the cache coherence operation request.

[0086] S402. According to the memory address corresponding to the cache consistency operation request and the directory table entries of each core group, determine the relevant core group that needs to respond to the cache consistency operation request, and initiate monitoring of all relevant processor cores of all relevant core groups. The directory table entries record the sharing status of each cache block among all core groups; wherein all processor cores of the current processor are divided into several non-overlapping core groups.

[0087] The cache consistency protocol responds to the cache consistency operation initiated by the current processor core for the current cache block, and first determines whether the numbers of all processor cores sharing the current cache block can be accurately determined from the corresponding directory table entry. When it is determined that it cannot be accurately determined, all core groups related to the current cache block are determined according to the shared record method between core groups, and then all related cores of all related core groups are monitored, and all irrelevant core groups are filtered, that is, irrelevant core groups are not monitored. When it is found that only all related cores of the current core group to which the current processor core belongs need to be monitored, the primary bus of the current core group can be separated from the secondary bus between core groups, so that the monitoring between different core groups can be carried out in parallel, which is especially suitable for the situation where there is almost no data sharing between core groups, and can significantly improve the efficiency of maintaining cache consistency. At present, the core-to-core interconnection on the processor mostly adopts a method similar to the 2D mesh network, which can conveniently realize the function of initiating monitoring only for some cores, or conveniently realize the "separation of the primary bus and the secondary bus between core groups".

[0088] Embodiment five:

[0089] Another embodiment of the present application relates to a cache consistency optimization device. The implementation details of the cache consistency optimization device of this embodiment are specifically described below. The following content is only for the convenience of understanding the implementation details provided, and is not necessary for the implementation of this solution. The schematic diagram of the cache consistency optimization device of this embodiment can be as follows Figure 5 As shown, it includes a response module 501 and a processing module 502.

[0090] A response module 501 is used to respond to a cache coherence operation request initiated by the current processor core and obtain a memory address corresponding to the cache coherence operation request;

[0091] Processing module 502 is used to determine a target listening bus from multiple buses according to the memory address corresponding to the cache consistency operation request, and use the target listening bus to complete the cache consistency operation request; or, determine a number of related processor cores that need to respond to the cache consistency operation request according to the memory address corresponding to the cache consistency operation request, and use the current processor and all related processor cores to complete the cache consistency operation request.

[0092] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0093] In some optional implementations, the processing module 502 is used to determine a target listening bus from multiple buses according to the memory address corresponding to the cache coherence operation request, which may specifically include:

[0094] Determine an address tag of a memory address corresponding to the cache coherence operation request, the address tag including memory address bits in the memory address excluding a cache block size;

[0095] A target listening bus is determined from multiple buses according to a mapping relationship between an address tag and a bus number.

[0096] In some optional implementations, the processing module 502 is further configured to:

[0097] Determine the load balance of multiple buses within a preset time period, where the load balance is used to measure the proximity of the number of cache coherence operation requests processed by each bus;

[0098] When the load balance of the multiple buses is lower than a preset threshold within a preset time period, the mapping relationship between the address tag and the bus number is adjusted.

[0099] In some optional implementations, the processing module 502 is used to determine the load balance of multiple buses within a preset time period, which may specifically include:

[0100] The ratio of an average value of the number of cache coherence operation requests processed by the multiple buses within a preset time period to a maximum value is determined as the load balance of the multiple buses within the preset time period.

[0101] In some optional implementations, the processing module 502 is used to determine a number of related processor cores that need to respond to the cache coherence operation request according to the memory address corresponding to the cache coherence operation request, which may specifically include:

[0102] According to the memory address corresponding to the cache consistency operation request and the global cache status bit table, a number of related processor cores that need to respond to the cache consistency operation request are determined. Each table entry in the global cache status bit table corresponds to a processor core, and a status bit of each table entry corresponds to an identification address segment, which is used to indicate whether the corresponding processor core currently caches the data of the corresponding identification address segment, and the global cache status bit table is consistent with the real-time cache status table of each processor core.

[0103] In some optional implementations, the processing module 502 is further configured to:

[0104] If all data cached by the current core group belong to the same identification address segment and all other processor cores do not cache data in the identification address segment, the local bus of the current core group is separated from the global bus.

[0105] In some optional implementations, the processing module 502 is used to determine a number of related processor cores that need to respond to the cache coherence operation request according to the memory address corresponding to the cache coherence operation request, which may specifically include:

[0106] According to the memory address corresponding to the cache consistency operation request and the directory table entries of each core group, the relevant core group that needs to respond to the cache consistency operation request is determined, and monitoring is initiated for all relevant processor cores of all relevant core groups. The directory table entries record the sharing status of each cache block among all core groups.

[0107] Embodiment six:

[0108] Another embodiment of the present application relates to an electronic device, such as Figure 6 As shown, it includes: at least one processor 601; and a memory 602 that is communicatively connected to the at least one processor 601; wherein the memory 602 stores instructions that can be executed by the at least one processor 601, and the instructions are executed by the at least one processor 601 so that the at least one processor 601 can execute the cache consistency optimization method in the above-mentioned embodiments.

[0109] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium via an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0110] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0111] Embodiment seven:

[0112] Another embodiment of the present application relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0113] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as: ROM), random access memory (Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program codes.

[0114] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A cache consistency optimization method, characterized in that: include: In response to a cache coherence operation request initiated by the current processor core, obtaining a memory address corresponding to the cache coherence operation request; Determine a target listening bus from multiple buses according to the memory address corresponding to the cache consistency operation request, and use the target listening bus to complete the cache consistency operation request; or, determine a number of related processor cores that need to respond to the cache consistency operation request according to the memory address corresponding to the cache consistency operation request, and use the current processor and all related processor cores to complete the cache consistency operation request.

2. The method according to claim 1, characterized in that The step of determining a target listening bus from a plurality of buses according to a memory address corresponding to the cache coherence operation request includes: Determine an address tag of a memory address corresponding to the cache coherence operation request, wherein the address tag includes memory address bits in the memory address excluding a cache block size; A target listening bus is determined from multiple buses according to a mapping relationship between an address tag and a bus number.

3. The method according to claim 2, characterized in that The method further comprises: Determining load balancing of multiple buses within a preset time period, wherein the load balancing is used to measure the proximity of the number of cache coherence operation requests processed by each bus; When the load balance of the plurality of buses is lower than a preset threshold within a preset time period, the mapping relationship between the address mark and the bus number is adjusted.

4. The method according to claim 3, characterized in that The step of determining the load balance of the plurality of buses within a preset time period includes: The ratio of an average value of the number of cache coherence operation requests processed by the multiple buses within a preset time period to a maximum value is determined as the load balance of the multiple buses within the preset time period.

5. The method according to claim 1, characterized in that The determining, according to the memory address corresponding to the cache coherence operation request, a number of related processor cores that need to respond to the cache coherence operation request includes: According to the memory address corresponding to the cache coherence operation request and the global cache status bit table, a number of related processor cores that need to respond to the cache coherence operation request are determined, each table entry in the global cache status bit table corresponds to a processor core, a status bit of each table entry corresponds to an identification address segment, which is used to indicate whether the corresponding processor core currently caches data of the corresponding identification address segment, and the global cache status bit table is consistent with the real-time cache status table of each processor core; Among them, one of the identification address segments is a subspace with continuous addresses in the memory address space.

6. The method according to claim 5, characterized in that The method further comprises: If all data cached by the current core group belongs to the same identification address segment and all other processor cores do not cache data of the identification address segment, the local bus of the current core group is separated from the global bus; All processor cores of the current processor are divided into a number of non-overlapping core groups.

7. The method according to claim 1, characterized in that The determining, according to the memory address corresponding to the cache coherence operation request, a number of related processor cores that need to respond to the cache coherence operation request includes: Determine the relevant core group that needs to respond to the cache coherence operation request according to the memory address corresponding to the cache coherence operation request and the directory table entry of each core group, and initiate monitoring of all relevant processor cores of all relevant core groups, wherein the directory table entry records the sharing status of each cache block among all core groups; All processor cores of the current processor are divided into a number of non-overlapping core groups.

8. The method according to claim 7, characterized in that The directory entry records the sharing of each cache block among all core groups, including: The method for the directory entry to record the sharing status of each cache block among all core groups includes any one of a real-time counting method, a historical marking method or a bitmap method or a combination thereof; The real-time counting method has several counters in each directory entry, wherein each counter records the real-time sharing times of the corresponding cache block by the core set composed of several core groups; The history marking method has a plurality of history marking bits in each directory entry, wherein each history marking bit records whether a core set consisting of a plurality of core groups has ever accessed a corresponding cache block; The bitmap method is used to record the precise sharing status of the corresponding cache block among the processor cores in the owner core group when a directory entry belongs to a unique owner core group.

9. A cache consistency optimization device, characterized in that: include: A response module, configured to respond to a cache coherence operation request initiated by the current processor core and obtain a memory address corresponding to the cache coherence operation request; A processing module is used to determine a target listening bus from multiple buses according to a memory address corresponding to the cache consistency operation request, and use the target listening bus to complete the cache consistency operation request; or, determine a number of related processor cores that need to respond to the cache consistency operation request according to the memory address corresponding to the cache consistency operation request, and use the current processor and all related processor cores to complete the cache consistency operation request.

10. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the cache consistency optimization method according to any one of claims 1 to 8.

11. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the cache consistency optimization method according to any one of claims 1 to 8 is implemented.

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