A data transmission method and system in PCIE

Abstract

The application relates to the technical field of serial interfaces, and discloses a data transmission method and system in a PCIE, the method comprising the following steps: obtaining a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used for indicating the priority of each interface in the PCIE; determining the scheduling time of each interface in the PCIE according to the target arbitration strategy; for a target interface of the PCIE, if input data of the target interface is valid within the scheduling time of the target interface, setting an output enable signal corresponding to the target interface, so as to directly output data through the target interface or transmit data read from a cache corresponding to the target interface through the target interface. The above scheme enables multiple interfaces to arrange the scheduling time of each interface according to the priority when simultaneously performing receiving work, and directly outputs data or reads data from the cache within the scheduling time, so that the utilization rate of link bandwidth is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of serial interface, in particular to a data transmission method and system in PCIE. BACKGROUND

[0002] The main components of PCIe include RC (Root Complex), SW (Switch) and EP (Endpoint). The RC refers to a device connecting a CPU and a memory subsystem and a PCIe structure, and needs to support one or more PCIe ports for communication with all devices.

[0003] At present, in the implementation of the RC component of the traditional PCIe controller, a design method of using multiple controllers for independent transmission and reception and performing aggregation processing on the receiving side is mostly adopted. In order to enable the entire RC to run at the maximum bandwidth, the scheduling strategy needs to be more flexible and the link bandwidth utilization needs to be higher, so the arbitration and scheduling design of the receiving end is particularly important. Therefore, there is an urgent need for a data transmission method for improving the link bandwidth utilization in PCIE. SUMMARY

[0004] Therefore, the present application provides a data transmission method and system in PCIE to improve the link bandwidth utilization.

[0005] In a first aspect, the present application provides a data transmission method in PCIE, wherein the PCIE has multiple interfaces, and the method comprises:

[0006] obtaining a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used to indicate the priority of each interface in the PCIE;

[0007] determining the scheduling time of each interface in the PCIE according to the target arbitration strategy;

[0008] for a target interface of the PCIE, if the input data of the target interface is valid within the scheduling time of the target interface, setting the output enable signal corresponding to the target interface to output the data through the target interface or to transmit the data read from the cache corresponding to the target interface through the target interface.

[0009] In a possible implementation, when the target arbitration strategy indicates that the priorities of each interface in the PCIE are the same, the determination of the scheduling time of each interface in the PCIE according to the target arbitration strategy comprises:

[0010] polling each interface in the PCIE according to a specified period, and determining the specified time length after polling to each interface as the scheduling time of each interface in the PCIE.

[0011] In a possible implementation, the method further includes:

[0012] If the input data of the target interface is invalid when polling the target interface, polling a next interface of the target interface.

[0013] In a possible implementation, the obtaining of the target arbitration strategy corresponding to the PCIE includes:

[0014] obtaining the number of physical transmission channels of each interface in the PCIE;

[0015] generating the priority corresponding to each interface according to the number of physical transmission channels of each interface, to obtain the target arbitration strategy.

[0016] In a second aspect, a data transmission system in a PCIE is provided, and the system includes an arbitration transmission module and a cache receiving module corresponding to each interface;

[0017] The arbitration transmission module is configured to obtain a target arbitration strategy corresponding to the PCIE, and the target arbitration strategy is configured to indicate the priority of each interface in the PCIE.

[0018] The arbitration transmission module is further configured to determine the scheduling time of each interface in the PCIE according to the target arbitration strategy, and for a target interface of the PCIE, if the input data of the target interface is valid within the scheduling time of the target interface, set the output enable signal corresponding to the target interface.

[0019] The cache receiving module is configured to output the data transmitted by the target interface through a pass-through output or read the data from the cache corresponding to the target interface through the target interface after the output enable signal corresponding to the target interface is set.

[0020] In a possible implementation, the system further includes a data receiving module.

[0021] The data receiving module is configured to convert the data received by the physical layer of the PCIE into a specified format and output the data to the cache receiving module.

[0022] In a possible implementation, the cache receiving module includes a data transmission unit, a data cache unit, and a data output unit.

[0023] The data transmission unit is configured to transmit the data of the corresponding interface to the data output unit or write the data into the data cache unit.

[0024] The data buffer unit is configured to obtain data written by the data transmission unit or send data to the data output unit.

[0025] In a possible implementation, the data buffer unit is further configured to send a buffer state signal to the data transmission unit and the data output unit, where the buffer state signal is used to indicate whether the data buffer unit is empty or not; and when the buffer state signal indicates that the data buffer unit is not empty, the buffered data is read.

[0026] In a possible implementation, the data transmission unit is further configured to determine whether the buffer state signal is empty when receiving an output enable signal of a corresponding interface.

[0027] If the buffer state signal is empty, data of the corresponding interface is directly output to the data output unit.

[0028] In a possible implementation, the data output unit is further configured to read the buffered data when the buffer state signal indicates that the data buffer unit is not empty.

[0029] The technical scheme provided in the present application can have the following beneficial effects.

[0030] The data transmission system in the PCIE can first obtain a target arbitration strategy corresponding to the PCIE to obtain the priority of each interface in the PCIE, and then determine the scheduling time of each interface in the PCIE according to the priority of each interface in the PCIE; after the scheduling time of each interface in the PCIE is determined, for a target interface, data can be directly output through the target interface or data read from the buffer corresponding to the target interface can be input through the target interface within the scheduling time of the target interface. The above scheme enables the multiple interfaces to arrange the scheduling time of each interface according to the priority when performing receiving work at the same time, and directly output data or read data from the buffer within the scheduling time, thereby improving the usage rate of the link bandwidth. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art of the present application, the drawings needed in the description of the specific embodiments or prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0032] Figure 1 A data transmission system in a PCIE is shown.

[0033] Figure 2A module structure and a signal transmission schematic diagram related to an embodiment of the application are shown.

[0034] Figure 3 A logic block diagram of a data transmission module related to an embodiment of the application is shown.

[0035] Figure 4 A logic block diagram of a data output unit related to an embodiment of the application is shown.

[0036] Figure 5 A logic block diagram of a data cache unit related to an embodiment of the application is shown.

[0037] Figure 6 A FIFO read-write timing diagram related to an embodiment of the application is shown.

[0038] Figure 7 A self-adaptive configuration of each Port scheduling time division diagram related to an embodiment of the application is shown.

[0039] Figure 8 A polling scheduling strategy timing diagram related to an embodiment of the application is shown.

[0040] Figure 9 A self-adaptive configuration of scheduling mode timing diagram related to an embodiment of the application is shown.

[0041] Figure 10 A data transmission method in a PCIE related to an embodiment of the application is shown.

[0042] Figure 11 A structural schematic diagram of a computer device provided by an optional embodiment of the application is shown. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described below in detail with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the application.

[0044] In the description of the embodiments of the application, the term "corresponding" can represent a direct or indirect corresponding relationship between the two, can also represent an associated relationship between the two, or can indicate a relationship such as being indicated, configured, etc.

[0045] At present, in the traditional implementation of the RC component of the PCIe controller, a design method of using multiple controllers to independently transmit and receive and performing aggregation processing on the receiving side is mostly adopted. In order to enable the entire RC to run at the maximum bandwidth, the scheduling strategy needs to be more flexible and the link bandwidth utilization needs to be higher, and therefore the arbitration and scheduling design of the receiving end is particularly important.

[0046] Although the traditional design can realize the basic transmission and reception aggregation function, the following shortcomings and deficiencies exist:

[0047] 1. In the receiving work of the multiple-port controller, the link bandwidth utilization is not high;

[0048] 2. The receiving arbitration and scheduling strategy is single and has low flexibility.

[0049] Based on the above analysis, please refer to Figure 1 The embodiment of the present application shows a data transmission system in a PCIE. The data transmission system comprises an arbitration transmission module MAC_RX_ARB and a plurality of buffer receiving modules MAC_RX_BUF corresponding to respective interfaces. The buffer receiving module MAC_RX_BUF has MNP, and MNP is the number of ports.

[0050] In the embodiment of the present application, the number of buffer receiving modules corresponds to the number of ports (interfaces) of the PCIE, that is, each buffer receiving module has a corresponding port, and the buffer receiving module is used to receive or buffer the data of the corresponding port.

[0051] The arbitration transmission module MAC_RX_ARB is used to obtain a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used to indicate the priority of each interface in the PCIE;

[0052] The arbitration transmission module MAC_RX_ARB is also used to determine the scheduling time of each interface in the PCIE according to the target arbitration strategy; for a target interface of the PCIE, if the input data of the target interface is valid within the scheduling time of the target interface, the output enable signal corresponding to the target interface is set.

[0053] The buffer receiving module MAC_RX_BUF is also used to transmit the data of the target interface through a pass-through output after the output enable signal corresponding to the target interface is set, or to transmit the data read from the buffer corresponding to the target interface through the target interface.

[0054] Optionally, as shown in Figure 1 The system further comprises a data receiving module MAC_RX_PKT; the number of the data receiving module MAC_RX_PKT is also MNP, which corresponds to the number of interfaces of the PCIE.

[0055] The data receiving module MAC_RX_PKT is used for converting the data received by the PCIE physical layer into a specified format and outputting to the buffer receiving module. Specifically, the data receiving module MAC_RX_PKT can realize the packaging of PIPE received data into TLP and DLLP formats for output, and the data bit width is expanded to (PIPE data bit width * maximum link width, taking pipe data = 32 bits and MNL = 8 as an example, the pkt_data bit width is 32 * 8 = 256 bits).

[0056] The buffer receiving module MAC_RX_BUF can realize the multi-port data transmission on the buffer receiving path, and interactively controls the arbitration transmission module MAC_RX_ARB using a low-delay design, and sequentially outputs the received data of each port to the upstream. The unit is composed of mac_rx_buf_sel, mac_rx_buf_out and mac_rx_buf_fifo units, wherein the mac_rx_buf_sel unit realizes the judgment of the current valid received data as a straight-through output or writing into the mac_rx_buf_fifo, and the mac_rx_buf_out unit realizes the selection of the current output data source from the mac_rx_buf_sel unit straight-through or the mac_rx_buf_fifo.

[0057] The arbitration transmission module MAC_RX_ARB can provide an internal arbitration mechanism to control the output of the received data of each port MAC_RX_BUF module to the upstream and provide a Port number mark.

[0058] Please refer to Figure 2 which shows a module structure and a signal transmission schematic diagram related to an embodiment of the present application. As Figure 2 shown, the buffer receiving module MAC_RX_BUF includes a data transmission unit mac_rx_buf_sel, a data buffer unit mac_rx_buf_fifo and a data output unit mac_rx_buf_out.

[0059] First, the function of the data transmission unit mac_rx_buf_sel is introduced:

[0060] The data transmission unit mac_rx_buf_sel is used for transmitting the data of the corresponding interface to the data output unit mac_rx_buf_out or writing into the data buffer unit mac_rx_buf_fifo.

[0061] Specifically, when the data transmission unit mac_rx_buf_sel receives the output enable signal (pkt_grant = 1) of the corresponding interface, it can determine whether the buffer state signal is empty; if the buffer state signal is empty, the data of the corresponding interface is directly output to the data output unit mac_rx_buf_out.

[0062] Wherein, whether the buffer state signal is empty can be determined according to buf_empty; if buf_empty = 1, it means that the buffer state signal is empty (and the current fifo state is empty).

[0063] Please refer to Figure 3 , which shows a logic block diagram of a data transmission module according to an embodiment of the present application. As shown in Figure 3 , if pkt_grant = 1 (controlled by the MAC_RX_ARB module) and buf_empty = 1 (the current fifo state is empty), when the current Port input signal pkt_dv_p is valid (indicating that the input data is valid), the data is directly output from the mac_rx_buf_sel unit (i.e. the data transmission unit mac_rx_buf_sel) to the mac_rx_buf_out unit (the data output unit mac_rx_buf_out), without being written into the mac_rx_buf_fifo unit (i.e. the data buffer unit mac_rx_buf_fifo), thereby ensuring that the reception delay is minimized in this scenario.

[0064] In other cases, when pkt_dv_p is valid, the data is written from the mac_rx_buf_sel unit to the mac_rx_buf_fifo unit.

[0065] Secondly, the function of the data output unit mac_rx_buf_out is introduced:

[0066] In addition to receiving the direct data of the above-mentioned data transmission unit mac_rx_buf_sel, the data output unit mac_rx_buf_out can also determine whether the buffer state signal is empty (i.e. determine the value of buf_empty) when receiving the output enable signal (pkt_grant = 1) of the corresponding interface; if buf_empty = 0, that is, the buffer state signal is not empty, at this time the state of the buffer unit fifo is not empty, and the data output unit mac_rx_buf_out reads the buffered data in the buffer unit fifo.

[0067] Please refer to Figure 4 , which shows a logic block diagram of a data output unit according to an embodiment of the present application. As shown in Figure 4As shown, for the mac_rx_buf_out unit:

[0068] If pkt_grant = 1 and buf_empty = 1, the data of the mac_rx_buf_sel unit is output directly;

[0069] If pkt_grant = 1 and buf_empty = 0, the data of the mac_rx_buf_fifo unit is read, and then the next arbitration output is waited for;

[0070] If buf_empty = 0, the mac_rx_buf_fifo data is prefetched once, and then the next arbitration output is waited for;

[0071] If pkt_grant = 0, the corresponding data when pkt_rdy is valid is output and maintained.

[0072] Further, the function of the data buffer unit mac_rx_buf_fifo is introduced as follows:

[0073] The data buffer unit mac_rx_buf_fifo is used to obtain the data written by the data transmission unit or send the data to the data output unit mac_rx_buf_out.

[0074] Specifically, the data buffer unit mac_rx_buf_fifo is also used to send a buffer state signal buf_empty to the data transmission unit mac_rx_buf_sel and the data output unit mac_rx_buf_out. The buffer state signal buf_empty is used to indicate whether the data buffer unit is empty. When the buffer state signal buf_empty indicates that the data buffer unit is not empty, the buffered data is read.

[0075] Referring to Figure 5 , a logic block diagram of a data buffer unit is shown. As shown in Figure 5 , for the mac_rx_buf_fifo unit:

[0076] If pkt_grant = 1 and buf_empty = 0, a read fifo operation is performed, and the pkt_data is obtained in the next cycle;

[0077] If pkt_grant = 0 and buf_empty = 0, a pre-read fifo operation is performed, and the pkt_data is obtained in the next cycle;

[0078] If the pkt_grant of the current cycle = 1 and buf_empty = 1, no operation is performed;

[0079] If buf_empty = 0, or (buf_empty = 1 and pkt_dv = 1), set pkt_rdy valid, indicating that the output pkt_data is ready.

[0080] In the embodiment of the application, the buffer unit fifo in the MAC_RX_BUF module (i.e. the buffer receiving module) of the application uses pkt_dv_p* as a write enable, buffers the received data of the current Port after splicing, uses the pkt_grant signal corresponding to the current Port controlled by the MAC_RX_ARB module as a fifo read enable, reads the data and sets the pkt_dv_p* signal, and outputs them to the MAC_RX_ARB module. The corresponding fifo read-write timing design is shown in Figure 6 , which ensures that the transmission delay is maximally reduced.

[0081] Figure 6 The timing diagram in the above table is as follows:

[0082] At T1 moment: the current Port receives the upstream data 1st_data and writes it into the fifo operation, the fifo empty flag is set to non-empty in the next cycle, and the pre-reading data operation is performed. The pkt_rdy_p is set to indicate that the data is ready, and arbitration is waited.

[0083] At T2 moment: the fifo puts the 1st_data on the data line;

[0084] At T3 moment: the current Port receives the upstream data 2nd_data and writes it into the fifo operation, and the pkt_rdy_p is continuously set to indicate that the data is ready, and arbitration is continuously waited.

[0085] At T4 moment: the current Port gets the pkt_grant_p of the arbitration module, and the arbitration module samples the 1st_data on the data line. At this moment, the fifo is non-empty, and the reading operation is performed.

[0086] At T5 moment: the fifo puts the 2nd_data on the data line;

[0087] At T6 moment: the current Port gets the pkt_grant_p of the arbitration module, and the arbitration module samples the 2nd_data on the data line. At this moment, the fifo is non-empty, and the reading operation is performed, and the reading pointer jumps in the next cycle.

[0088] At T7 moment: the reading pointer jumps to the position of the writing pointer, at this moment, the fifo is empty, and the data line is invalid data.

[0089] And in the embodiments of the present application, since there are multiple ports in the PCIE, a polling scheduling mode involving the ports is needed.

[0090] In a possible implementation, the priority of each port is the same, at this time, the interfaces in the PCIE can be polled according to a specified period, and the specified time length after polling to each interface is determined as the scheduling time of each interface in the PCIE.

[0091] If the input data of the target interface is invalid when polling to the target interface, the next interface of the target interface is polled;

[0092] Specifically, the scheduling pointer is incremented by one after the currently pointed Port (interface) is scheduled, that is, the next Port is pointed. First, wait for any Port corresponding pkt_rdy to be valid, then record the current Port number (for example, multiple pkt_rdy are valid, then select the minimum value according to the order of Port0-7) as the scheduling start, and poll the remaining Port corresponding pkt_rdy in ascending order. Then output the pkt_data of the Port selected in the current cycle, and set the pkt_grant signal of the Port to 1 cycle, and the pkt_grant signals of the remaining Ports remain low (the default pkt_grant is low). The selected Port reads the fifo data once (read enable is valid, the next cycle outputs the data), and can directly output when selected next time. ③ Repeat the polling process MNP (number of Ports) times until all Ports are completed, and wait for the next start.

[0093] In another possible implementation, the target arbitration strategy corresponding to the PCIE can also be set to an actual Lane width self-adaptive configuration weight mode. At this time, the number of physical transmission channels of each interface in the PCIE can be obtained; according to the number of physical transmission channels of each interface, the priority corresponding to each interface is generated to obtain the target arbitration strategy.

[0094] Specifically, the Link width of each Port is obtained according to the Bifurcation configuration, and then the hardware self-adaptively determines the scheduling time allocation, initializes the current polling start point and order table, and polls the Port corresponding pkt_rdy according to the order table. The implementation is as follows:

[0095] If pkt_rdy is detected to be valid during polling, the pkt_data of the corresponding Port is output, and the pkt_grant signal of the Port is set to 1 cycle (as a fifo pre-read enable), and the pkt_grant signals of the remaining Ports remain low.

[0096] If the current port data is not ready, skip it and then check the next port data. The number of scheduled times in the whole cycle cannot exceed the weight setting value, otherwise, weight initialization is performed and then polling is performed;

[0097] The polling operation according to the allocated weight is continuously performed until reconfiguration.

[0098] For the above-mentioned adaptive weight configuration according to the actual Lane width, the embodiment of the present application can generate adaptive configuration according to the link width of each Port, that is, the scheduling weight is determined according to the Lane width of each Port configured by Bifurcation. The priority of the Port with greater Lane width is higher, and the specific configuration is shown in Table 1. The scheduling strategy of this kind of adaptive configuration generated according to the actual Lane width can usually achieve maximum bandwidth utilization. The reason is that in the scheduling process, the number of times each Port is scheduled in a scheduling cycle is proportional to the actual Lane width, that is, the Port with greater Lane width is scheduled more frequently. Taking the PIPE data bit width of 32 bits as an example, the upstream module will output to the MAC_RX_BUF module after the current Port is full of MNL*32 bit data. Therefore, even if the current Port is full of MNL*32 bit data and has not been scheduled, resulting in data being buffered in MAC_RX_BUF, but before the data is full of MNL*32 bit data again, this Port will be scheduled, thereby ensuring that MAC_RX_BUF does not overflow in the entire receiving operation process. In this way, the received data of all Lanes can be output without packet loss in the entire scheduling cycle, achieving maximum bandwidth utilization.

[0099] Table 1. Scheduling time allocation table using adaptive configuration generated according to actual Lane width

[0100] Maximum supported Lane width within a Port Weight 16 16 8 8 4 4 2 2 1 1

[0101] The above-mentioned adaptive weight configuration scheduling mode according to the actual Lane width is the default working mode of the present application. Taking MNL=8 as an example, the adaptive configuration of each Port scheduling time is divided as shown in Table 1: Figure 7

[0102] Bifurcation column: enumerates all multi-Port multiplexing 8 Lane combination forms;

[0103] Cycle column: divided into 0~7 cycles, and the current port data is selected in each cycle. If the current Port data does not apply for arbitration, the next Port is checked. If the number of times a Port is scheduled in the whole 8 cycle period reaches the weight setting value, weight initialization of all Ports is performed, and then the polling operation is restarted.​

[0104] In another possible implementation, the weights (or priorities) of the various interfaces in the embodiments of the present application can be dynamically controlled according to upstream hardware, which is similar to the above-mentioned adaptive configuration of weights according to actual Lane width, but the weight distribution is dynamically controlled and distributed by upstream hardware instead of being generated adaptively. The scheme shown in the embodiments of the present application supports dynamic control of weights by upstream hardware, and the advantage is that upstream hardware can dynamically adjust and distribute the scheduling weights of the design according to actual service data volume, so as to achieve the best running performance of the system.

[0105] In another possible implementation, the weights (or priorities) of the various interfaces in the embodiments of the present application can also be defined according to software. This way is similar to the above-mentioned adaptive configuration of weights according to actual Lane width, but supports user-defined weights of each Port, that is, software overwrites the current scheduling weight configuration, providing a more flexible use scenario.

[0106] In the embodiments of the present application, the MAC_RX_ARB unit takes 4 Ports and 8 Lanes as an example to select a Port polling scheduling strategy, please refer to Figure 8 , which shows a timing diagram of a polling scheduling strategy related to the embodiments of the present application. As shown in Figure 8 ,

[0107] At T1 moment: Port0~3 corresponding to the MAC_RX_BUF module are ready for pkt_data data, and place the data (pkt_data_p*) at the output interface and set the respective pkt_rdy_p*. The MAC_RX_ARB module adopts a Port polling arbitration strategy, selects the output Port0 data (pkt_data_p0.1st_data) and sets the corresponding pkt_grant_p0, and keeps the remaining pkt_grant low.

[0108] At T2 moment: the MAC_RX_ARB module checks according to the Port polling arbitration strategy that the Port1 corresponding pkt_rdy_p1 has been set, then outputs the data pkt_data_p1.1st_data and sets the corresponding pkt_grant_p1.

[0109] At T3 moment: similar to T2, check that the Port2 corresponding pkt_rdy_p2 has been set, then output the data pkt_data_p2.1st_data and set the corresponding pkt_grant_p2.

[0110] T4 time: similar to T3, check Port3 corresponding pkt_rdy_p3 has been set, then output data pkt_data_p3.1st_data, and set corresponding pkt_grant_p3.

[0111] T5 time: the current cycle only Port1 and Port2 corresponding pkt data are ready, according to the Port polling arbitration strategy, output data (blue) pkt_data_p1.1st_data, and set corresponding pkt_grant_p1.

[0112] T6 time: the current cycle Port3 corresponding pkt_data_p3 data is also ready, but according to the Port polling arbitration strategy, output data (blue) pkt_data_p2.1st_data, and set corresponding pkt_grant_p2.

[0113] T7 time: according to the Port polling arbitration strategy, check Port3 corresponding pkt_rdy_p3 is valid, so output data (blue) pkt_data_p3.1st_data, and set corresponding pkt_grant_p3.

[0114] T8 time: the current cycle Port0 corresponding pkt_data_p0 data is ready, so output data (blue) pkt_data_p0.1st_data, and set corresponding pkt_grant_p0.

[0115] The MAC_RX_ARB unit of the present application works in 1x4, 1x2, 2x1 mode with 4 Ports and 8 Lanes, and selects the adaptive configuration scheduling mode according to the actual Lane width as an example, selects the scheduling strategy of the aforementioned Bifurcation sequence number 4, sets Port0: x4, Port1: x2, Port2: x1, Port3: x1, please refer to Figure 9 , which shows a timing diagram of an adaptive configuration scheduling mode related to an embodiment of the present application. As Figure 9 shown:

[0116] Tl time: Port0~3 corresponding MAC_RX_BUF module pkt data ready, and the data (pkt_data_p*) placed in the output interface, set the respective pkt_rdy_p*. MAC_RX_ARB module using the actual Lane width according to the scheduling arbitration strategy, according to the table shown in Figure 0 output data (pkt_data_p0.1st_data) and set the corresponding pkt_grant_p0, keep the rest of the pkt_grant low. If the Port0 corresponding fifo is not empty, it will be read once, so that pkt_data_p0 in the next cycle is updated to new data (such as the pkt_data_p0.2nd_data of the left figure T2 time).

[0117] T2 time: According to the current scheduling strategy, check pkt_rdy_p1 is valid, output data (pkt_data_p1.1st_data) and set the corresponding pkt_grant_p1, keep the rest of the pkt_grant low.

[0118] T3 time: According to the current scheduling strategy, check pkt_rdy_p0 is valid, output data (pkt_data_p0.2nd_data) and set the corresponding pkt_grant_p0, keep the rest of the pkt_grant low.

[0119] T4 time: According to the current scheduling strategy, check pkt_rdy_p2 is valid, output data (pkt_data_p2.1st_data) and set the corresponding pkt_grant_p2, keep the rest of the pkt_grant low.

[0120] T5 time: According to the current scheduling strategy, check pkt_rdy_p0 is valid, output data (pkt_data_p0.3rd_data) and set the corresponding pkt_grant_p0, keep the rest of the pkt_grant low.

[0121] T6 time: According to the current scheduling strategy, check pkt_rdy_p1 is valid, output data (pkt_data_p1.2nd_data) and set the corresponding pkt_grant_p1, keep the rest of the pkt_grant low.

[0122] T7 time: According to the current scheduling strategy, check pkt_rdy_p0 is valid, output data (pkt_data_p0.4th_data) and set the corresponding pkt_grant_p0, keep the rest of the pkt_grant low.

[0123] T8 moment: according to the current scheduling strategy, check pkt_rdy_p3 is valid, output data (pkt_data_p3.1st_data) and set the corresponding pkt_grant_p3, keep the rest of the pkt_grant low.

[0124] The application provides a PCIe MAC layer multi-port receiving arbitration scheduling design method, which solves the problems of low link bandwidth utilization and low flexibility of receiving arbitration scheduling strategy in the traditional multi-port controller design during simultaneous receiving work. Using the application can maximize the utilization of link bandwidth, and can also adapt to various scheduling strategy application scenarios.

[0125] The advantages of using the application design are:

[0126] 1) The utilization rate of multi-port receiving link bandwidth reaches the theoretical upper limit of all Lane width;

[0127] 2) The low-latency design is used for the interaction between multi-port receiving cache and arbitration logic, which helps to improve the overall receiving path performance;

[0128] 3) Support four arbitration strategies, including port polling, adaptive configuration of scheduling weight according to current actual Lane width, upstream hardware dynamic control weight and software defined weight, flexible and configurable to meet various use scenarios;

[0129] 4) The number of ports and lanes is parameterized design, supporting various bifurcation configuration combination scenarios;

[0130] 5) The design code has strong maintainability and scalability;

[0131] 6) The internal fifo cache is designed to be adaptive and minimized according to the scheduling weight distribution, reducing design resource waste;

[0132] 7) Standard customization design, effectively reducing the difficulty of verification coverage convergence, shortening the product development time.

[0133] In summary, the data transmission system in the PCIE can first acquire the target arbitration strategy corresponding to the PCIE to acquire the priority of each interface in the PCIE, and then determine the scheduling time of each interface in the PCIE according to the priority of each interface in the PCIE. When the scheduling time of each interface in the PCIE is determined, for the target interface, data can be directly output through the target interface or data read from the cache corresponding to the target interface can be input through the target interface within the scheduling time of the target interface. The above scheme enables multiple interfaces to arrange the scheduling time of each interface according to the priority when performing receiving work at the same time, and directly outputs data or reads data from the cache within the scheduling time, thereby improving the utilization rate of link bandwidth.

[0134] Please refer to Figure 10 which shows a data transmission method in a PCIE related to the embodiments of the present application. The method is executed by a data transmission system in a PCIE as shown in Figure 1 The method comprises the following steps:

[0135] Step 1001: Acquire the target arbitration strategy corresponding to the PCIE. The target arbitration strategy is used to indicate the priority of each interface in the PCIE.

[0136] Step 1002: Determine the scheduling time of each interface in the PCIE according to the target arbitration strategy.

[0137] Step 1003: For the target interface of the PCIE, if the input data of the target interface is valid within the scheduling time of the target interface, set the output enable signal corresponding to the target interface to output data through the target interface in pass-through mode or transmit data read from the cache corresponding to the target interface through the target interface.

[0138] The specific execution mode of the above steps is the same as the logic in the embodiment of the data transmission system of the PCIE as shown in Figure 1 The specific execution mode of the above steps is the same as the logic in the embodiment of the data transmission system of the PCIE as shown in

[0139] In summary, the data transmission system in the PCIE can first acquire the target arbitration strategy corresponding to the PCIE to acquire the priority of each interface in the PCIE, and then determine the scheduling time of each interface in the PCIE according to the priority of each interface in the PCIE. When the scheduling time of each interface in the PCIE is determined, for the target interface, data can be directly output through the target interface or data read from the cache corresponding to the target interface can be input through the target interface within the scheduling time of the target interface. The above scheme enables multiple interfaces to arrange the scheduling time of each interface according to the priority when performing receiving work at the same time, and directly outputs data or reads data from the cache within the scheduling time, thereby improving the utilization rate of link bandwidth.

[0140] In this embodiment, the data transmission system is presented in the form of functional units. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0141] This application also provides a computer device that can implement PCIe-based data transmission through the system shown in this application embodiment. Please refer to... Figure 11 , Figure 11 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 11 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 11 Take a processor 10 as an example.

[0142] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0143] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0144] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required for at least one function, etc. The data storage area can store data created by the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory such as at least one disk storage device, a flash memory device, or other non-transitory solid state memory device. In some alternative embodiments, the memory 20 can optionally include memory that is remotely located with respect to the processor 10, and that can be connected to the computer device through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communications network, and combinations thereof.

[0145] The memory 20 can include a volatile memory, such as a random access memory, and / or can include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid state memory device. The memory 20 can also include an array of multi-state flash memory cells, which can be programmed to store one or more bits per cell. For example, multi-state flash memory cells can store two or more bits per cell. In a particular embodiment, the memory 20 can include a three-state flash memory cell, which can be programmed to store one or two bits per cell. In some embodiments, the memory 20 can include a combination of storage devices, such as one or more flash memory devices and one or more disk storage devices.

[0146] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0147] The embodiments of the present application also provide a computer readable storage medium. The above-mentioned method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code stored in a remote storage medium or a non-transitory machine readable storage medium and stored in a local storage medium to be downloaded through a network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned kinds of storage devices. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, the processor, or the hardware, implements the method shown in the above-mentioned embodiments.

[0148] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, can invoke or provide methods and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source files, executable files, installation package files and the like, and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0149] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A data transmission method in PCIe, characterized in that, The PCIe interface has multiple interfaces, and the method includes: Obtain the target arbitration policy corresponding to PCIe; the target arbitration policy is used to indicate the priority of each interface in PCIe; The scheduling time of each interface in the PCIe is determined according to the target arbitration strategy; For the target PCIe interface, if the input data of the target interface is valid during the scheduling time of the target interface, the output enable signal corresponding to the target interface is set so that the data can be output directly through the target interface, or the data read from the cache corresponding to the target interface can be transmitted through the target interface. The step of directly outputting data through the target interface, or transmitting data read from the cache corresponding to the target interface through the target interface, includes: When the output enable signal of the corresponding interface is received, it is determined whether the buffer status signal corresponding to the target interface is empty; If the cache status signal is empty, the data of the corresponding interface will be output directly. If the output enable signal corresponding to the target interface is invalid, and the cache status signal indicates that the cache status is not empty, then a pre-read FIFO operation is performed.

2. The data transmission method according to claim 1, characterized in that, When the target arbitration policy indicates that all interfaces in the PCIe have the same priority, determining the scheduling time of each interface in the PCIe according to the target arbitration policy includes: The PCIe interface is polled at a specified period, and the specified time after polling each interface is determined as the scheduling time of each interface in the PCIe.

3. The data transmission method according to claim 2, characterized in that, The method further includes: If the polling reaches the target interface and the input data of the target interface is invalid, then the polling proceeds to the next interface of the target interface.

4. The data transmission method according to claim 1, characterized in that, The process of obtaining the target arbitration strategy corresponding to PCIe includes: Obtain the number of physical transmission channels for each interface in the PCIe; Based on the number of physical transmission channels for each interface, a priority is generated for each interface to obtain the target arbitration strategy.

5. A data transmission system in PCIe, characterized in that, The system includes an arbitration transmission module and a buffer receiving module corresponding to each interface; The arbitration transmission module is used to obtain the target arbitration strategy corresponding to PCIe; The target arbitration strategy is used to indicate the priority of each interface in the PCIe; The arbitration transmission module is also used to determine the scheduling time of each interface in the PCIE according to the target arbitration strategy; For the target PCIe interface, if the input data of the target interface is valid during the scheduling time of the target interface, the output enable signal corresponding to the target interface is set. The buffer receiving module is used to, after the output enable signal corresponding to the target interface is set, output the data transmitted by the target interface through a pass-through, or transmit the data read from the buffer corresponding to the target interface through the target interface. The buffer receiving module includes a data transmission unit, a data buffer unit, and a data output unit; The data transmission unit is used to transmit data from the corresponding interface to the data output unit or write it to the data cache unit; The data caching unit is used to acquire data written by the data transmission unit or to send data to the data output unit; The data caching unit is also used to send a cache status signal to the data transmission unit and the data output unit; the cache status signal is used to indicate whether the status of the data caching unit is empty; when the cache status signal indicates that the cache unit is not empty, cached data is read. The data transmission unit is also used to determine whether the buffer status signal is empty when it receives the output enable signal of the corresponding interface; If the cache status signal is empty, the data of the corresponding interface will be directly output to the data output unit. The data caching unit is further configured to perform a pre-read FIFO operation when the output enable signal corresponding to the target interface is invalid and the cache status signal indicates that the cache status is not empty.

6. The data transmission system according to claim 5, characterized in that, The system also includes a data receiving module; The data receiving module is used to convert the data received by the PCIe physical layer into a specified format and output it to the buffer receiving module.

7. The data transmission system according to claim 5, characterized in that, The data output unit is also used to read cached data when the cache status signal indicates that the cache unit is not empty.

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