Access method and device capable of expanding interface address space, equipment and medium

Abstract

The invention relates to the technical field of computers, and discloses an extensible interface address space access method and device, equipment and a medium, and the method comprises the steps: obtaining an address classification table and multiple types of first extensible interface address spaces of first equipment; receiving first address request information and first data sent by the root complex; searching a type corresponding to the first target PCIe address from a plurality of types of a plurality of devices in an address classification table to obtain a first target type; determining a second extensible interface address space of the first target type of the first target device according to the identifier of the first target device and the first extensible interface address space of the first target type; and writing the first data in the second extensible interface address space of the first target type. Therefore, the technical effect of accessing the extensible interface address space through the PCIe address according to the address classification table and the multiple types of first extensible interface address spaces of the first equipment is achieved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for accessing an extensible interface address space. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial expansion bus standard widely used in high-performance computing and storage systems. In order to achieve efficient data transmission and resource management, especially in complex systems involving multiple devices and different address spaces, the address conversion and management between the PCIe and AXI (Advanced eXtensible Interface) of the device is particularly important. Summary of the invention

[0003] In view of this, the present invention provides a method, apparatus, device and medium for accessing an extensible interface address space to solve the problem of how to access the extensible interface address space in a complex system with multiple devices and different address spaces.

[0004] In a first aspect, the present invention provides a method for accessing an expandable interface address space, the method being applied to a converter, the converter being respectively connected to a root complex and a plurality of devices, the method comprising:

[0005] Obtain an address classification table and a first extensible interface address space of multiple types of a first device, wherein the first device is one of the multiple devices, and the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device; the number and type of the multiple types of each of the multiple types of the devices are the same, and each PCIe address corresponds to an extensible interface address space of a device;

[0006] receiving first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and an identifier of a first target device among the multiple devices;

[0007] From the multiple types of the multiple devices in the address classification table, searching for a type corresponding to the first target PCIe address to obtain a first target type; the first target PCIe address corresponds to a first scalable interface address space of the first target type;

[0008] Determine, according to the identifier of the first target device and the first extensible interface address space of the first target type, a second extensible interface address space of the first target device of the first target type;

[0009] The first data is written into a second extensible interface address space of the first target type.

[0010] The present invention provides a method for accessing an expandable interface address space, which has the following advantages:

[0011] By searching the first target type corresponding to the target PCIe address sent by the root complex from the address classification table, the first extensible interface address space of the first target type of the first device is determined, and according to the identifier of the first target device and the first extensible interface address space of the first target type, the second extensible interface address space of the first target type of the first target device is determined, and then the first data is written into the second extensible interface address space. Thus, the technical effect of accessing the extensible interface address space through the PCIe address according to the address classification table and the first extensible interface address spaces of multiple types of the first device is achieved, so that the address classification table and the first extensible interface address spaces of multiple types of the first device can be dynamically modified later, and the mapping relationship between the PCIe address and the extensible interface address space can be flexibly adjusted. At the same time, the second extensible interface address space of the first target type of the first target device is temporarily determined, which reduces the pre-configuration work of the extensible interface address space, reduces the conditions for accessing the extensible interface address space, further optimizes resource allocation and utilization, and improves the overall operation efficiency of the system.

[0012] In an optional implementation manner, after acquiring the address classification table and the first extensible interface address spaces of multiple types of the first device, the method further includes:

[0013] receiving a first configuration instruction sent by a processor;

[0014] Parsing the first configuration instruction to obtain a correspondence between the second target PCIe address and the multiple types of the multiple devices;

[0015] According to the correspondence between the second target PCIe address and the multiple types of the multiple devices, the device and type corresponding to the second target PCIe address in the address classification table are modified to obtain an updated address classification table.

[0016] Specifically, in the method steps, by modifying the device and type corresponding to the second target PCIe address in the address classification table according to the first configuration instruction sent by the processor, the address classification table is updated, thereby dynamically adjusting the mapping relationship between the PCIe address and the extensible interface address space, achieving the technical effect of real-time adjustment of resource allocation, allowing the system to adapt to various application scenarios more flexibly and improve overall resource utilization.

[0017] In an optional implementation, after modifying the device and type corresponding to the second target PCIe address in the address classification table according to the correspondence between the second target PCIe address and the multiple types of the multiple devices to obtain an updated address classification table, the method further includes:

[0018] Generate second address request information and second data, the second address request information including: the second target PCIe address and an identifier of a second target device among the multiple devices;

[0019] From the multiple types of the multiple devices in the updated address classification table, searching for a type corresponding to the second target PCIe address to obtain a second target type;

[0020] Determine, according to the identifier of the second target device and the first extensible interface address space of the second target type, a second extensible interface address space of the second target device of the second target type;

[0021] Writing the second data into a second extensible interface address space of the second target type;

[0022] Reading first actual data in a second extensible interface address space of the second target type;

[0023] Determine whether the second data is the same as the first actual data;

[0024] If yes, restoring the communication link between the root complex and the switch;

[0025] If not, the configuration failure information is fed back to the above processor.

[0026] Specifically, in the steps of the method, after updating the address classification table, the converter simulates the root complex to generate the second address request information and the second data, finds the second extensible interface address space of the corresponding second target type according to the same method as above, and writes the second data. Then, the first actual data in the second extensible interface address space is read, and by comparing the read first actual data with the second data, it is checked whether the first data is correctly stored in the second extensible interface address space. If so, the communication link between the root complex and the converter is restored, and if not, the configuration failure information is fed back to the processor. Thus, after updating the address classification table, the updated address classification table is verified to ensure the correctness and effectiveness of the address classification table update.

[0027] In an optional implementation manner, after acquiring the address classification table and the first extensible interface address spaces of multiple types of the first device, the method further includes:

[0028] receiving a second configuration instruction sent by the processor;

[0029] Parsing the second configuration instruction to obtain a modified first extensible interface address space;

[0030] According to the modified first extensible interface address space, the multiple types of first extensible interface address spaces of the first device are modified to obtain updated first extensible interface address spaces of the first device.

[0031] Specifically, in the method steps, by modifying the first extensible interface address space of multiple types of the above-mentioned first device according to the second configuration instruction sent by the processor, the extensible interface address space is dynamically adjusted to achieve the technical effect of real-time adjustment of resource allocation, so that the system can adapt to various application scenarios more flexibly and improve overall resource utilization.

[0032] In an optional implementation, after modifying the multiple types of first extensible interface address spaces of the first device according to the modified first extensible interface address space to obtain updated multiple types of first extensible interface address spaces of the first device, the method further includes:

[0033] Generate third address request information and third data, wherein the third address request information includes: the third target PCIe address and an identifier of a third target device among the plurality of devices;

[0034] From the multiple types of the multiple devices in the address classification table, searching for the type corresponding to the third target PCIe address to obtain a third target type;

[0035] Determine a second extensible interface address space of the third target type of the third target device according to the identifier of the third target device and the updated first extensible interface address space of the third target type;

[0036] Writing the third data into the second extensible interface address space of the third target type;

[0037] Reading second actual data in a second extensible interface address space of the third target type;

[0038] Determining whether the third data is the same as the second actual data;

[0039] If yes, restoring the communication link between the root complex and the switch;

[0040] If not, the configuration failure information is fed back to the above processor.

[0041] Specifically, in the steps of the method, after updating the first extensible interface address spaces of multiple types of the first device, the converter simulates the root complex to generate the second address request information and the second data, finds the corresponding third extensible interface address space of the second target type according to the same method as above, and writes the third data. Then, the first actual data in the third extensible interface address space is read, and by comparing the read second actual data with the third data, it is checked whether the third data is correctly stored in the second extensible interface address space. If so, the communication link between the root complex and the converter is restored, and if not, the configuration failure information is fed back to the processor. In this way, after the first extensible interface address space is updated, the updated first extensible interface address space is verified to ensure the correctness and effectiveness of the update of the first extensible interface address space.

[0042] In an optional implementation, each extensible interface address space includes: a starting address and a space size;

[0043] Determining, according to the identifier of the first target device and the first extensible interface address space of the first target type, a second extensible interface address space of the first target device of the first target type, comprises:

[0044] Determine the starting address of the second extensible interface address space of the first target type according to the identifier of the first target device, the starting address of the first extensible interface address space of the first target type, the space size of the first extensible interface address space of the first target type, and a preset relationship;

[0045] The space size of the second extensible interface address space of the first target type is the same as the space size of the first extensible interface address space of the first target type;

[0046] The above preset relationship is:

[0047]

[0048] Among them, VF v BAR b For the above target type is BAR b The corresponding identifier is the starting address of the second scalable interface address space of the first target device, VF0BAR b For the above target type is BAR b and the corresponding identifier is the starting address of the first extensible interface address space 0, For the above target type is BAR b And the corresponding identifier is 0, and the space size of the first extensible interface address space.

[0049] Specifically, in the steps of the method, an extensible interface address space is represented by a starting address and a space size. Then, the starting address of the second extensible interface address space of the first target type is determined by the identifier of the first target device, the starting address of the first extensible interface address space of the first target type, the space size of the first extensible interface address space of the first target type, and the preset relationship, and the space size of the first extensible interface address space of the first target type is used as the space size of the second extensible interface address space. In this way, the mapping relationship between the extensible interface address spaces of multiple devices is dynamically adjusted, the complexity of the user-side configuration is reduced, and the operating efficiency and management flexibility of the system are improved.

[0050] In an optional implementation manner, after acquiring the address classification table and the first extensible interface address spaces of multiple types of the first device, the method further includes:

[0051] storing the address classification table and a plurality of types of first extensible interface address spaces of the first device in the converter;

[0052] After feeding back the configuration failure information to the processor, the following further includes:

[0053] replacing the above updated address classification table with the above address classification table;

[0054] Alternatively, the first extensible interface address spaces of the first device of the first type are replaced with the first extensible interface address spaces of the first device of the first type;

[0055] A communication link between the root complex and the switch is restored.

[0056] Specifically, in the steps of the method, by backing up the address classification table and the first extensible interface address space of multiple types of the first device, after feeding back the configuration failure information to the processor, the backed-up address classification table and the first extensible interface address space of multiple types of the first device are used to back up and replace the updated address classification table and the first extensible interface address space of multiple types of the first device, and then the communication link between the root complex and the above-mentioned converter is restored. This avoids the problem that the root complex cannot normally access the extensible interface address space due to configuration failure, which in turn causes data transmission errors, and achieves the technical effect of improving system stability.

[0057] In a second aspect, the present invention provides an access device capable of extending an interface address space, the device being applied to a converter, the converter being respectively connected to a root complex and a plurality of devices, the device comprising:

[0058] an acquisition module, configured to acquire an address classification table and a first extensible interface address space of a plurality of types of a first device, wherein the first device is one of the plurality of devices, and the address classification table comprises: a plurality of types of the plurality of devices, and at least one PCIe address corresponding to each type of each device; the number and type of the plurality of types of each of the plurality of devices are the same, and each PCIe address corresponds to an extensible interface address space of a device;

[0059] A receiving module, configured to receive first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and an identifier of a first target device among the multiple devices;

[0060] A search module, configured to search for a type corresponding to the first target PCIe address from among the multiple types of the multiple devices in the address classification table to obtain a first target type; the first target PCIe address corresponds to a first scalable interface address space of the first target type;

[0061] a determination module, configured to determine a second extensible interface address space of the first target type of the first target device according to an identifier of the first target device and the first extensible interface address space of the first target type;

[0062] A writing module is used to write the first data in the second extensible interface address space of the first target type.

[0063] The present invention provides an access device capable of expanding an interface address space, which has the following advantages:

[0064] By searching the first target type corresponding to the target PCIe address sent by the root complex from the address classification table, the first extensible interface address space of the first target type of the first device is determined, and according to the identifier of the first target device and the first extensible interface address space of the first target type, the second extensible interface address space of the first target type of the first target device is determined, and then the first data is written into the second extensible interface address space. Thus, the technical effect of accessing the extensible interface address space through the PCIe address according to the address classification table and the first extensible interface address spaces of multiple types of the first device is achieved, so that the address classification table and the first extensible interface address spaces of multiple types of the first device can be dynamically modified later, and the mapping relationship between the PCIe address and the extensible interface address space can be flexibly adjusted. At the same time, the second extensible interface address space of the first target type of the first target device is temporarily determined, which reduces the pre-configuration work of the extensible interface address space, reduces the conditions for accessing the extensible interface address space, further optimizes resource allocation and utilization, and improves the overall operation efficiency of the system.

[0065] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the method for accessing the extensible interface address space of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0066] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method for accessing the extensible interface address space of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0068] Figure 1 is a schematic diagram of a converter according to an embodiment of the present invention;

[0069] Figure 2 is one of the flow charts of the method for accessing the scalable interface address space according to an embodiment of the present invention;

[0070] Figure 3This is a second flowchart of a method for accessing an extensible interface address space according to an embodiment of the present invention;

[0071] Figure 4 is a schematic diagram of address conversion according to an embodiment of the present invention;

[0072] Figure 5 is a schematic diagram of address space conversion according to an embodiment of the present invention;

[0073] Figure 6 is a schematic diagram of the structure of an access device for an expandable interface address space according to an embodiment of the present invention;

[0074] Figure 7 is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention;

[0075] Figure 8 4 is a schematic diagram of an access system for an extensible interface address space according to an embodiment of the present invention. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0077] According to an embodiment of the present invention, an embodiment of a method for accessing an extensible interface address space is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0078] Figure 1 is a schematic diagram of a converter according to an embodiment of the present invention, Figure 1 As shown, the converter is respectively connected to a root complex (RC) and multiple devices, such as device 0 to device 6, and the multiple devices can be multiple DUTs (Device Under Test) under a virtual function (Virtual Function, VF).

[0079] The converter includes: a configuration register, a manager, a NIC bridge (Network Interface Controller Bridge), and at least one interface, such as a first interface and a second interface, wherein the first interface may be a PCIe interface and the second interface may be an extensible interface. In addition, it should be understood that other more or fewer interfaces may also be included, and this embodiment does not limit this.

[0080] The manager connects the NIC bridge and the configuration registers respectively. The NIC bridge connects the root complex RC through the PCIe interface, and the NIC bridge also connects other devices through the AXI interface.

[0081] In addition, in a possible implementation manner, the converter further includes a backup register for backing up data in the configuration register.

[0082] In this embodiment, a method for accessing an expandable interface address space is provided, which can be used for the above-mentioned converter. Figure 2 is one of the flow charts of a method for accessing an extensible interface address space according to an embodiment of the present invention, the method comprising:

[0083] Step S201: Acquire an address classification table and a plurality of types of first extensible interface address spaces of a first device.

[0084] The first device is one of the above-mentioned multiple devices. The multiple types of first extensible interface address spaces of the first device may be an address space configured by a user.

[0085] The address classification table includes: multiple types of multiple devices, and at least one PCIe address corresponding to each type of each device. The number and type of the multiple types of each device are the same, and each PCIe address corresponds to an expandable interface address space of a device.

[0086] The multiple types may correspond to multiple BARs (Base Address Registers), for example, 6 types, namely BAR0 to BAR5. The address classification table may record at least one PCIe address corresponding to BAR0 to BAR5 of each device.

[0087] One implementation of obtaining the address classification table is that the manager obtains the address classification table from a configuration register, wherein the address allocation table is pre-stored in the configuration register. Similarly, the manager can also obtain multiple types of first extensible interface address spaces of the first device from the register.

[0088] Step S202: receiving first address request information and first data sent by the root complex.

[0089] The first address request information includes: a first target PCIe address and an identifier of a first target device among the multiple devices.

[0090] The first target PCIe address may be any one of at least one PCIe address corresponding to an extensible interface address space of a first device.

[0091] The first data may be data that needs to be written into the expandable interface address space corresponding to the first target PCIe address.

[0092] The identifier of the first target device may be a unique identification code of multiple devices, for example, 0 to 10.

[0093] In step S202, a specific implementation is: the root complex first obtains the first address request information and the first data, then converts the information and data into a TLP (Transaction Layer Packet) format, and finally sends the TLP format packet to the converter.

[0094] Step S203: searching for a type corresponding to the first target PCIe address from the multiple types of the multiple devices in the address classification table to obtain a first target type.

[0095] The first target PCIe address corresponds to a first extensible interface address space of a first target type.

[0096] Specifically, all PCIe addresses are scanned from the address classification table to find the first target PCIe address and its corresponding type as the first target type. Under the first target type, there are at least one PCIe address of the first target type, a first extensible interface address space of the first target type, and an extensible interface address space of the first target type of other devices (e.g., a second extensible interface address space of the first type of the first target device).

[0097] Step S204: Determine a second extensible interface address space of the first target type of the first target device according to the identifier of the first target device and the first extensible interface address space of the first target type.

[0098] Each device has multiple types of extensible interface address spaces, corresponding to different functions or resources. The second extensible interface address space is determined by the first extensible interface address space, which can be generated based on the corresponding target type, and the interval size between the address spaces is determined in combination with the identifier of the first target device, and then the first extensible interface address is shifted to determine the second extensible interface address space.

[0099] Step S205: write first data into a second extensible interface address space of the first target type.

[0100] The NIC bridge may initiate a write request to the second extensible interface address space of the first target type using the extensible interface protocol, and transmit the first data to the second extensible interface address space of the first target type through the extensible interface bus.

[0101] The method provided in this embodiment determines the first extensible interface address space of the first target type of the first device by searching the first target type corresponding to the target PCIe address sent by the root complex from the address classification table, determines the second extensible interface address space of the first target type of the first target device according to the identifier of the first target device and the first extensible interface address space of the first target type, and then writes the first data into the second extensible interface address space. Thus, the technical effect of accessing the extensible interface address space through the PCIe address according to the address classification table and the first extensible interface address spaces of multiple types of the first device is achieved, so that the address classification table and the first extensible interface address spaces of multiple types of the first device can be dynamically modified later, and the mapping relationship between the PCIe address and the extensible interface address space can be flexibly adjusted.

[0102] In addition, the method can also instantly determine the second extensible interface address space of the first target type of the first target device, thereby reducing the pre-configuration work for the extensible interface address space, lowering the conditions for accessing the extensible interface address space, further optimizing resource allocation and utilization, and improving the overall operating efficiency of the system.

[0103] In an optional implementation, in order to further dynamically adjust the mapping relationship between the PCIe address and the scalable interface address space, Figure 3 FIG. 2 is a second flowchart of a method for accessing an extensible interface address space according to an embodiment of the present invention. Figure 3 As shown, after the above step S201, it also includes:

[0104] Step S301: receiving a first configuration instruction sent by a processor.

[0105] The first configuration instruction may be a TLP message for modifying the data in the configuration register. The processor may be a CPU (Central Processing Unit).

[0106] Specifically, the converter may be connected to the processor via a PCIe bus to receive the first configuration instruction.

[0107] Step S302: parsing the first configuration instruction to obtain a correspondence between the second target PCIe address and the multiple types of the multiple devices.

[0108] Specifically, the converter parses the TLP message to obtain a correspondence between the second target PCIe address and the multiple types of the multiple devices.

[0109] Step S303: modify the device and type corresponding to the second target PCIe address in the address classification table according to the correspondence between the second target PCIe address and the multiple types of the multiple devices, and obtain an updated address classification table.

[0110] Specifically, the address classification table may be traversed to find the second target PCIe address, and the corresponding device and type may be modified.

[0111] The method provided in this embodiment modifies the device and type corresponding to the second target PCIe address in the address classification table according to the first configuration instruction sent by the processor, and updates the address classification table, thereby dynamically adjusting the mapping relationship between the PCIe address and the extensible interface address space, achieving the technical effect of real-time adjustment of resource allocation, so that the system can adapt to various application scenarios more flexibly and improve overall resource utilization.

[0112] In an optional implementation, in order to further verify whether the mapping relationship between the PCIe address and the scalable interface address space is adjusted successfully, after the above step S303, the following is further included:

[0113] Generate second address request information and second data, wherein the second address request information includes: the second target PCIe address and an identifier of a second target device among the multiple devices.

[0114] The second address request information and the second data may be one TLP message generated by the converter.

[0115] From the multiple types of the multiple devices in the updated address classification table, find the type corresponding to the second target PCIe address to obtain the second target type.

[0116] From the updated address classification table, the corresponding device type is searched according to the second target PCIe address, and the second target type is output.

[0117] According to the identifier of the second target device and the first extensible interface address space of the second target type, a second extensible interface address space of the second target type of the second target device is determined.

[0118] The second extensible interface address space of the second target type may be determined according to the identifier of the second target device and the first extensible interface address space corresponding thereto.

[0119] The second data is written into a second extensible interface address space of the second target type.

[0120] A write operation may be sent to the determined second extensible interface address space to write the second data.

[0121] The first actual data in the second extensible interface address space of the second target type is read.

[0122] The first actual data may be obtained by sending a read operation to the determined second extensible interface address space.

[0123] Determine whether the second data is the same as the first actual data.

[0124] The second data may be compared with the first actual data to determine whether they are the same.

[0125] If so, the communication link between the root complex and the switch is restored.

[0126] If they are the same, it means that the data is successfully transmitted and the communication link between the root complex and the converter can be restored. This means that the device can work normally and exchange data.

[0127] If not, the configuration failure information is fed back to the above processor.

[0128] That is, if they are different, it indicates that there may be a problem with data transmission, and the system needs to feedback configuration failure information to the processor for troubleshooting and repair.

[0129] In the method provided in this embodiment, after updating the address classification table, the converter simulates the root complex to generate the second address request information and the second data, finds the second extensible interface address space corresponding to the second target type according to the same method as above, and writes the second data. Then, the first actual data in the second extensible interface address space is read, and by comparing the read first actual data with the second data, it is checked whether the first data is correctly stored in the second extensible interface address space. If it is, the communication link between the root complex and the converter is restored, and if not, the configuration failure information is fed back to the processor. In this way, after updating the address classification table, the updated address classification table is verified to ensure the correctness and effectiveness of the address classification table update.

[0130] In an optional implementation, in order to further dynamically adjust the extensible interface address space, after the above step S201, the following is further included:

[0131] A second configuration instruction sent by the processor is received.

[0132] The second configuration instruction may be a TLP message for modifying the data in the configuration register. The processor may be a CPU.

[0133] Specifically, the converter may be connected to the processor via a PCIe bus to receive the second configuration instruction.

[0134] The second configuration instruction is parsed to obtain a modified first extensible interface address space.

[0135] Specifically, the converter parses the TLP message to obtain the modified first extensible interface address space and its type.

[0136] According to the modified first extensible interface address space, the multiple types of first extensible interface address spaces of the first device are modified to obtain updated first extensible interface address spaces of the first device.

[0137] Specifically, the configuration register may be traversed to find a first extensible interface address space of the same type as the modified first extensible interface address space, and the first extensible interface address space may be replaced with the modified first extensible interface address space.

[0138] The method provided in this embodiment modifies the first extensible interface address space of multiple types of the above-mentioned first device according to the second configuration instruction sent by the processor, thereby realizing dynamic adjustment of the extensible interface address space and achieving the technical effect of real-time adjustment of resource allocation, so that the system can adapt to various application scenarios more flexibly and improve overall resource utilization.

[0139] In an optional implementation, in order to further verify whether the dynamic adjustment of the extensible interface address space is successful, after modifying the multiple types of first extensible interface address spaces of the first device according to the modified first extensible interface address space to obtain the updated multiple types of first extensible interface address spaces of the first device, the method further includes:

[0140] Generate third address request information and third data, wherein the third address request information includes: the third target PCIe address and an identifier of a third target device among the multiple devices.

[0141] The third address request information and the third data may be one TLP message generated by the converter.

[0142] From the multiple types of the multiple devices in the address classification table, find the type corresponding to the third target PCIe address to obtain the third target type.

[0143] From the address classification table, find the corresponding device type according to the third target PCIe address and output the third target type.

[0144] A second extensible interface address space of the third target type of the third target device is determined according to the identifier of the third target device and the updated first extensible interface address space of the third target type.

[0145] The second extensible interface address space of the third target type may be determined according to the identifier of the first target device and its corresponding first extensible interface address space.

[0146] The third data is written into the second extensible interface address space of the third target type.

[0147] A write operation may be sent to the determined second extensible interface address space to write the third data.

[0148] The second actual data in the second extensible interface address space of the third target type is read.

[0149] The second actual data may be obtained by sending a read operation to the determined second extensible interface address space.

[0150] It is determined whether the third data is the same as the second actual data.

[0151] The third data may be compared with the second actual data to determine whether they are the same.

[0152] If so, the communication link between the root complex and the switch is restored.

[0153] If they are the same, it means that the data is successfully transmitted and the communication link between the root complex and the converter can be restored. This means that the device can work normally and exchange data.

[0154] If not, the configuration failure information is fed back to the above processor.

[0155] That is, if they are different, it indicates that there may be a problem with data transmission, and the system needs to feedback configuration failure information to the processor for troubleshooting and repair.

[0156] The method provided in this embodiment updates the first extensible interface address space of multiple types of the first device, and the converter simulates the root complex to generate the second address request information and the second data, finds the corresponding third extensible interface address space of the second target type according to the same method as above, and writes the third data. Then, the first actual data in the third extensible interface address space is read, and by comparing the read second actual data with the third data, it is checked whether the third data is correctly stored in the second extensible interface address space. If it is, the communication link between the root complex and the converter is restored, and if not, the configuration failure information is fed back to the processor. In this way, after the first extensible interface address space is updated, the updated first extensible interface address space is verified to ensure the correctness and effectiveness of the update of the first extensible interface address space.

[0157] In an optional implementation, in order to further realize automatic mapping between the extensible interface address spaces of multiple devices, each extensible interface address space includes: a starting address and a space size.

[0158] An extensible interface address space includes multiple extensible interface addresses, the start address may be the first address therein, and the size may be the number of addresses in the address space, or the size of data that can be accommodated.

[0159] The above step S204 includes:

[0160] The starting address of the second extensible interface address space of the first target type is determined according to the identifier of the first target device, the starting address of the first extensible interface address space of the first target type, the space size of the first extensible interface address space of the first target type, and a preset relationship.

[0161] That is, the starting address of the second extensible interface address space of the same type as the first target device is determined according to the starting address of the first extensible interface address space and the identifier of the device.

[0162] The space size of the second extensible interface address space of the first target type is the same as the space size of the first extensible interface address space of the first target type.

[0163] The above preset relationship is:

[0164]

[0165] Among them, VF v BAR b For the above target type is BAR b The corresponding identifier is the starting address of the second scalable interface address space of the first target device, VF0BAR bFor the above target type is BAR b and the corresponding identifier is the starting address of the first extensible interface address space 0, For the above target type is BAR b And the corresponding identifier is 0, and the space size of the first extensible interface address space.

[0166] Among them, VF v That is, the virtual device under test is identified as v, VF0 is the first device, and its identification is 0. Therefore, if the first target PCIe address is to request the first device, the first data can be written directly in the first extensible interface address space of the target type corresponding to the first device, or it can be determined by the above-mentioned preset relationship, that is, v=0.

[0167] The method provided in this embodiment represents an extensible interface address space through a starting address and a space size. Then, through the identifier of the first target device, the starting address of the first extensible interface address space of the first target type, the space size of the first extensible interface address space of the first target type, and the preset relationship, the starting address of the second extensible interface address space of the first target type is determined, and the space size of the first extensible interface address space of the first target type is used as the space size of the second extensible interface address space. In this way, the mapping relationship between the extensible interface address spaces of multiple devices is dynamically adjusted, the complexity of the user-side configuration is reduced, and the operating efficiency and management flexibility of the system are improved.

[0168] Further, after the second extensible interface address space is determined, a corresponding extensible interface address in the second extensible interface address space may be determined based on the PCIe address. Figure 4 Schematic diagram of address conversion in an embodiment of the present invention. Figure 4 As shown, it includes: the address space corresponding to the PCIe address passed in by the RC end, whose starting address is 64`h0000_0000_1000_0000, and whose space size is 1M, 20 bits. The converted extensible interface address space, whose starting address is 64`h0000_0000_3000_0000, and whose space size is 1M, 20 bits.

[0169] The scalable interface address corresponding to the position of the corresponding scalable interface address space may be determined according to the position of the PCIe address in the corresponding PCIe address space.

[0170] Figure 5 Schematic diagram of address space conversion in an embodiment of the present invention. Figure 5As shown, it includes: multiple types of PCIe address spaces of multiple devices, which are input into the above converter and converted into corresponding scalable interface address spaces. Each device has at least one set of PCIe address spaces and scalable interface address spaces of the same type. The address space of device 0 in the scalable interface address space is pre-configured and recorded in the converter, and the scalable interface address spaces of other devices are configured according to their identification and type and the corresponding scalable interface address space of device 0.

[0171] In an optional implementation manner, in order to avoid a system failure caused by a failure to update the address classification table or the first extensible interface address spaces of multiple types of the first device, after the above step S201, the method further includes:

[0172] The address classification table and a plurality of types of first extensible interface address spaces of the first device are stored in the converter.

[0173] Specifically, the address classification table and multiple types of first extensible interface address spaces of the first device may be stored in the backup register.

[0174] After feeding back the configuration failure information to the processor, the following further includes:

[0175] Use the above address classification table to replace the above updated address classification table.

[0176] Alternatively, the first extensible interface address spaces of multiple types of the first device are used to replace the first extensible interface address spaces of multiple types of the updated first device.

[0177] Specifically, after feeding back the configuration failure information to the above-mentioned processor, the address classification table and the first extensible interface address space of multiple types of the first device are retrieved from the backup register, the configuration register is cleared, and the retrieved address classification table and the first extensible interface address space of multiple types of the first device are written.

[0178] A communication link between the root complex and the switch is restored.

[0179] Restoring a communication link typically involves reinitializing the devices or reconfiguring communication parameters to ensure they can interact properly. Ensuring that the root complex and the switch are in the same state may require updating related registers or settings to prepare for subsequent data transfers. After restoring communication, the system may need to record this state or send a signal to other components that the communication link has been restored.

[0180] The method provided in this embodiment backs up the address classification table and the first extensible interface address space of multiple types of the first device, and after feeding back the configuration failure information to the processor, the backed-up address classification table and the first extensible interface address space of multiple types of the first device are used to back up and replace the updated address classification table and the first extensible interface address space of multiple types of the first device, and then the communication link between the root complex and the above-mentioned converter is restored. This avoids the problem that the root complex cannot normally access the extensible interface address space due to configuration failure, which in turn causes data transmission errors, and achieves the technical effect of improving system stability.

[0181] In an optional implementation, after determining the second extensible interface address space of the first target type of the first target device, the method further includes: receiving status feedback information from the root complex, wherein the status feedback information indicates a current working status of the first target device.

[0182] Based on the above status feedback information, determine whether the above first target device is in an available state, if yes, continue to perform the write operation; if no, pause or retry the write operation, and record the status information for subsequent analysis. When recording the status information, it also includes:

[0183] A log file is generated, including the identification, timestamp, status feedback information of the first target device and detailed information of the first data.

[0184] Regularly upload log files to a central monitoring system for performance analysis and troubleshooting.

[0185] The method provided in this embodiment helps to provide detailed historical records when a problem occurs in the system, which is convenient for subsequent maintenance and optimization. This can enhance the traceability and management capabilities of the system. It can ensure that the system can make corresponding adjustments when a device is unavailable, thereby improving overall stability and reliability.

[0186] The embodiment of the present invention further provides an access device capable of expanding the interface address space, the device being applied to a converter, Figure 6 is a schematic diagram of the structure of an access device for an expandable interface address space according to an embodiment of the present invention, such as Figure 6 As shown, the device comprises:

[0187] The acquisition module 601 is used to acquire an address classification table and multiple types of first extensible interface address spaces of a first device.

[0188] The first device is one of the multiple devices, and the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device. The number and type of the multiple types of each device are the same, and each PCIe address corresponds to an extensible interface address space of a device.

[0189] The receiving module 602 is configured to receive the first address request information and the first data sent by the root complex.

[0190] The first address request information includes: a first target PCIe address and an identifier of a first target device among the multiple devices.

[0191] The search module 603 is used to search for a type corresponding to the first target PCIe address from the multiple types of the multiple devices in the address classification table to obtain a first target type.

[0192] The first target PCIe address corresponds to the first extensible interface address space of the first target type.

[0193] The determination module 604 is configured to determine a second extensible interface address space of the first target type of the first target device according to the identifier of the first target device and the first extensible interface address space of the first target type.

[0194] The writing module 605 is configured to write the first data into the second extensible interface address space of the first target type.

[0195] The device provided in this embodiment searches the first target type corresponding to the target PCIe address sent by the root complex from the address classification table, thereby determining the first scalable interface address space of the first target type of the first device, and determining the second scalable interface address space of the first target type of the first target device according to the identifier of the first target device and the first scalable interface address space of the first target type, and then writes the first data into the second scalable interface address space. Thus, the technical effect of accessing the scalable interface address space through the PCIe address according to the address classification table and the first scalable interface address spaces of multiple types of the first device is achieved, so that the address classification table and the first scalable interface address spaces of multiple types of the first device can be dynamically modified later, and the mapping relationship between the PCIe address and the scalable interface address space can be flexibly adjusted. At the same time, the second scalable interface address space of the first target type of the first target device is temporarily determined, which reduces the pre-configuration work of the scalable interface address space, reduces the conditions for accessing the scalable interface address space, further optimizes resource allocation and utilization, and improves the overall operation efficiency of the system.

[0196] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0197] The access device of the expandable interface address space in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0198] The embodiment of the present invention also provides a computer device having the above Figure 6 The access device of the extensible interface address space is shown.

[0199] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0200] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit. The integrated circuit may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0201] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0202] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0203] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0204] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0205] Figure 8 is a schematic diagram of an access system for an extensible interface address space according to an embodiment of the present invention, such as Figure 8 As shown, the system includes: a root complex, a converter, and multiple devices. The converter is respectively connected to the root complex and multiple devices, such as device 0 to device 6, and the multiple devices can be multiple devices to be tested under virtual functions.

[0206] The converter can be Figure 1 As shown, it includes: a configuration register, a manager, a NIC bridge, and at least one interface, such as a first interface and a second interface, wherein the first interface may be a PCIe interface and the second interface may be an extensible interface. In addition, it should be understood that other more or fewer interfaces may also be included, and this embodiment does not limit this.

[0207] The manager connects the NIC bridge and the configuration registers respectively. The NIC bridge connects the root complex RC through the PCIe interface, and the NIC bridge also connects other devices through the extensible interface.

[0208] In addition, in a possible implementation manner, the converter further includes a backup register for backing up data in the configuration register.

[0209] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0210] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for accessing an extensible interface address space, characterized in that: The method is applied to a converter, the converter is respectively connected to a root complex and a plurality of devices, and the method comprises: Obtain an address classification table and a first extensible interface address space of multiple types of a first device, wherein the first device is one of the multiple devices, and the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device; the number and type of the multiple types of each device are the same, and each PCIe address corresponds to an extensible interface address space of a device; receiving first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and an identifier of a first target device among the multiple devices; From the multiple types of the multiple devices in the address classification table, searching for a type corresponding to the first target PCIe address to obtain a first target type; the first target PCIe address corresponds to a first scalable interface address space of the first target type; determining, according to the identifier of the first target device and the first extensible interface address space of the first target type, a second extensible interface address space of the first target device of the first target type; The first data is written in a second extensible interface address space of the first target type.

2. The method according to claim 1, characterized in that: After acquiring the address classification table and the first extensible interface address spaces of multiple types of the first device, the method further includes: receiving a first configuration instruction sent by a processor; Parsing the first configuration instruction to obtain a correspondence between a second target PCIe address and a plurality of types of the plurality of devices; According to the correspondence between the second target PCIe address and the multiple types of the multiple devices, the device and type corresponding to the second target PCIe address in the address classification table are modified to obtain an updated address classification table.

3. The method according to claim 2, characterized in that After modifying the device and type corresponding to the second target PCIe address in the address classification table according to the correspondence between the second target PCIe address and the multiple types of the multiple devices to obtain an updated address classification table, the method further includes: Generate second address request information and second data, wherein the second address request information includes: the second target PCIe address and an identifier of a second target device among the multiple devices; Searching for a type corresponding to the second target PCIe address from among the multiple types of the multiple devices in the updated address classification table to obtain a second target type; determining, according to the identifier of the second target device and the first extensible interface address space of the second target type, a second extensible interface address space of the second target device of the second target type; writing the second data in a second extensible interface address space of the second target type; reading first actual data in a second extensible interface address space of the second target type; determining whether the second data is the same as the first actual data; If yes, restoring the communication link between the root complex and the switch; If not, configuration failure information is fed back to the processor.

4. The method according to claim 1, characterized in that: After acquiring the address classification table and the first extensible interface address spaces of multiple types of the first device, the method further includes: receiving a second configuration instruction sent by the processor; Parsing the second configuration instruction to obtain a modified first extensible interface address space; According to the modified first extensible interface address space, the multiple types of first extensible interface address spaces of the first device are modified to obtain updated first extensible interface address spaces of the first device.

5. The method according to claim 4, characterized in that After modifying the first extensible interface address spaces of multiple types of the first device according to the modified first extensible interface address space to obtain updated first extensible interface address spaces of multiple types of the first device, the method further includes: Generate third address request information and third data, wherein the third address request information includes: a third target PCIe address and an identifier of a third target device among the multiple devices; Searching for a type corresponding to the third target PCIe address from among the multiple types of the multiple devices in the address classification table to obtain a third target type; determining a second extensible interface address space of the third target type of the third target device according to the identifier of the third target device and the updated first extensible interface address space of the third target type; Writing the third data in a second extensible interface address space of the third target type; Reading second actual data in a second extensible interface address space of the third target type; determining whether the third data is the same as the second actual data; If yes, restoring the communication link between the root complex and the switch; If not, configuration failure information is fed back to the processor.

6. The method according to any one of claims 1 to 5, characterized in that: Each extensible interface address space includes: a starting address and a space size; Determining, according to the identifier of the first target device and the first extensible interface address space of the first target type, a second extensible interface address space of the first target device of the first target type, comprises: Determine a starting address of a second extensible interface address space of the first target type according to an identifier of the first target device, a starting address of a first extensible interface address space of the first target type, a space size of the first extensible interface address space of the first target type, and a preset relationship; The space size of the second extensible interface address space of the first target type is the same as the space size of the first extensible interface address space of the first target type; The preset relationship is: Among them, VF v BAR b For the target type BAR b The corresponding identifier is the starting address of the second scalable interface address space of the first target device, VF0BAR b For the target type BAR b and the corresponding identifier is the starting address of the first extensible interface address space 0, For the target type BAR b And the corresponding identifier is 0, and the space size of the first extensible interface address space.

7. The method according to claim 3 or 5, characterized in that: After acquiring the address classification table and the first extensible interface address spaces of multiple types of the first device, the method further includes: storing the address classification table and a plurality of types of first extensible interface address spaces of the first device in the converter; After feeding back the configuration failure information to the processor, the method further includes: replacing the updated address classification table with the address classification table; Alternatively, using the first extensible interface address spaces of the first device of the multiple types to replace the updated first extensible interface address spaces of the first device of the multiple types; A communication link between the root complex and the switch is restored.

8. An access device capable of expanding an interface address space, characterized in that: The device is applied to a converter, the converter is respectively connected to a root complex and a plurality of devices, and the device comprises: an acquisition module, configured to acquire an address classification table and a first extensible interface address space of a plurality of types of a first device, wherein the first device is one of the plurality of devices, and the address classification table comprises: a plurality of types of the plurality of devices, and at least one PCIe address corresponding to each type of each device; the number of types and the type kind of the plurality of types of each of the devices are the same, and each PCIe address corresponds to an extensible interface address space of a device; A receiving module, configured to receive first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and an identifier of a first target device among the multiple devices; a search module, configured to search for a type corresponding to the first target PCIe address from among the multiple types of the multiple devices in the address classification table, and obtain a first target type; the first target PCIe address corresponds to a first extensible interface address space of the first target type; a determining module, configured to determine a second extensible interface address space of the first target type of the first target device according to an identifier of the first target device and a first extensible interface address space of the first target type; A writing module is used to write the first data in a second extensible interface address space of the first target type.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method for accessing the extensible interface address space according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method for accessing the extensible interface address space according to any one of claims 1 to 7.

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