A method, apparatus, device and medium for extending access to an interface address space

Abstract

The application relates to the technical field of computers and discloses an access method and device for extensible interface address space, equipment and a medium, the method comprising the following steps: acquiring an address classification table and a plurality of types of first extensible interface address spaces of a first device; receiving first address request information and first data sent by a root complex; searching for a type corresponding to a first target PCIe address from a plurality of types of a plurality of devices of the address classification table to obtain a first target type; determining a second extensible interface address space of the first target type of a first target device according to an identifier of the first target device and the first extensible interface address space of the first target type; and writing the first data into the second extensible interface address space of the first target type. Therefore, the technical effect of accessing the extensible interface address space through a PCIe address according to the address classification table and the first extensible interface address spaces of the plurality of types of the first device is achieved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to methods, apparatus, devices, and media for accessing scalable interface address spaces. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial expansion bus standard widely used in high-performance computing and storage systems. To achieve efficient data transmission and resource management, especially in complex systems involving multiple devices and different address spaces, address translation and management between PCIe and AXI (Advanced eXtensible Interface) are crucial. Summary of the Invention

[0003] In view of this, the present invention provides a method, apparatus, device and medium for accessing a scalable interface address space, in order to solve the problem of how to access a scalable interface address space in a complex system with multiple devices and different address spaces.

[0004] In a first aspect, the present invention provides a method for accessing an extensible interface address space, wherein the method is applied to a converter, the converter being connected to a root complex and multiple devices respectively, and the method includes:

[0005] Obtain an address classification table and a first scalable interface address space for multiple types of a first device, wherein the first device is one of the multiple devices, and the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device; the number and types of the multiple types of each device are the same, and each PCIe address corresponds to the scalable interface address space of a device;

[0006] Receive the first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and the identifier of the first target device among the plurality of devices;

[0007] From the multiple types of the multiple devices in the above address classification table, find the type corresponding to the first target PCIe address to obtain the first target type; the first target PCIe address corresponds to the first scalable interface address space of the first target type.

[0008] Based on the identifier of the first target device and the first scalable interface address space of the first target type, the second scalable interface address space of the first target device of the first target type is determined;

[0009] Write the first data into the address space of the second extensible interface of the first target type.

[0010] The present invention provides a method for accessing an extensible interface address space, which has the following advantages:

[0011] By looking up the first target type corresponding to the target PCIe address sent by the root complex in the address classification table, the first scalable interface address space of the first target type of the first device is determined. Based on the identifier of the first target device and the first scalable interface address space of the first target type, the second scalable interface address space of the first target device for the first target type is determined, and then the first data is written into the second scalable interface address space. This achieves the technical effect of accessing the scalable interface address space via PCIe address based on the address classification table and the first scalable interface address spaces of multiple types of the first device. This allows for dynamic modification of the address classification table and the first scalable interface address spaces of multiple types of the first device, flexibly adjusting the mapping relationship between PCIe address and scalable interface address space. Simultaneously, temporarily determining the second scalable interface address space of the first target type of the first target device reduces the pre-configuration work of the scalable interface address space, lowers the conditions for accessing the scalable interface address space, further optimizes resource allocation and utilization, and improves the overall operating efficiency of the system.

[0012] In one alternative implementation, after obtaining the address classification table and the address spaces of multiple types of the first scalable interface of the first device, the method further includes:

[0013] Receive the first configuration instruction sent by the processor;

[0014] Parse the first configuration instruction to obtain the correspondence between the second target PCIe address and the multiple types of the multiple devices;

[0015] Based on the correspondence between the second target PCIe address and the various types of the multiple devices, the devices and types corresponding to the second target PCIe address in the address classification table are modified to obtain an updated address classification table.

[0016] Specifically, in this method, the device and type corresponding to the second target PCIe address in the address classification table are modified according to the first configuration instruction sent by the processor, and the address classification table is updated. This achieves dynamic adjustment of the mapping relationship between PCIe addresses and the scalable interface address space, thereby achieving the technical effect of real-time adjustment of resource allocation. This allows the system to adapt more flexibly to various application scenarios and improves the overall resource utilization.

[0017] In an optional implementation, after modifying the device and type corresponding to the second target PCIe address in the address classification table according to the correspondence between the second target PCIe address and the multiple types of the multiple devices, and obtaining an updated address classification table, the method further includes:

[0018] Generate second address request information and second data, wherein the second address request information includes: the second target PCIe address and the identifier of the second target device among the plurality of devices;

[0019] From the multiple types of the multiple devices in the updated address classification table, find the type corresponding to the second target PCIe address to obtain the second target type;

[0020] Based on the identifier of the second target device and the first scalable interface address space of the second target type, the second scalable interface address space of the second target device of the second target type is determined.

[0021] Write the second data into the address space of the second extensible interface of the second target type;

[0022] Read the first actual data from the address space of the second extensible interface of the second target type mentioned above;

[0023] Determine whether the second data mentioned above is the same as the first actual data mentioned above;

[0024] If so, then restore the communication link between the root complex and the converter.

[0025] If not, then report a configuration failure message to the aforementioned processor.

[0026] Specifically, in this method, after updating the address classification table, the converter simulates the root complex to generate second address request information and second data. Following the same method described above, it finds the second scalable interface address space corresponding to the second target type and writes the second data. Then, it reads the first actual data from this second scalable interface address space. By comparing the read first actual data with the second data, it verifies whether the first data is correctly stored in the second scalable interface address space. If so, the communication link between the root complex and the converter is restored; otherwise, a configuration failure message is sent to the processor. This achieves the goal of verifying the updated address classification table after updating it, ensuring the correctness and effectiveness of the address classification table update.

[0027] In one alternative implementation, after obtaining the address classification table and the address spaces of multiple types of the first scalable interface of the first device, the method further includes:

[0028] Receive the second configuration instruction sent by the processor;

[0029] Parse the second configuration instruction to obtain the modified first extensible interface address space;

[0030] Based on the modified first scalable interface address space described above, the first scalable interface address spaces of multiple types of the first device are modified to obtain the updated first scalable interface address spaces of multiple types of the first device.

[0031] Specifically, in this method, the address spaces of multiple types of the first scalable interface of the first device are modified according to the second configuration instructions sent by the processor, thereby achieving dynamic adjustment of the scalable interface address space and realizing the technical effect of real-time adjustment of resource allocation. This allows the system to adapt more flexibly to various application scenarios and improve overall resource utilization.

[0032] In an optional implementation, after modifying the first scalable interface address spaces of multiple types of the first device according to the modified first scalable interface address space described above to obtain updated first scalable interface address spaces of multiple types of the first device, the method further includes:

[0033] Generate third address request information and third data. The third address request information includes: the third target PCIe address and the identifier of the third target device among the multiple devices.

[0034] From the multiple types of the above-mentioned devices in the above address classification table, find the type corresponding to the above-mentioned third target PCIe address to obtain the third target type;

[0035] Based on the identifier of the third target device and the updated first scalable interface address space of the third target type, the second scalable interface address space of the third target device of the third target type is determined.

[0036] Write the aforementioned third data into the address space of the second extensible interface of the aforementioned third target type;

[0037] Read the second actual data from the address space of the second extensible interface of the third target type mentioned above;

[0038] Determine whether the third data mentioned above is the same as the second actual data mentioned above;

[0039] If so, then restore the communication link between the root complex and the converter.

[0040] If not, then report a configuration failure message to the aforementioned processor.

[0041] Specifically, in this method, after updating the first scalable interface address space of multiple types of the first device, the converter simulates the root complex to generate second address request information and second data. Following the same method, it finds the corresponding third scalable interface address space of the second target type and writes the third data. Then, it reads the first actual data from the third scalable interface address space. By comparing the read second actual data with the third data, it verifies whether the third data is correctly stored in the second scalable interface address space. If so, the communication link between the root complex and the converter is restored; otherwise, a configuration failure message is sent to the processor. This achieves the goal of verifying the updated first scalable interface address space after updating it, ensuring the correctness and effectiveness of the update.

[0042] In one alternative implementation, each scalable interface address space includes: a starting address and a space size;

[0043] Based on the identifier of the first target device and the first scalable interface address space of the first target type, the second scalable interface address space of the first target device of the first target type is determined, including:

[0044] Based on the identifier of the first target device, the starting address of the first scalable interface address space of the first target type, the size of the first scalable interface address space of the first target type, and the preset formula, the starting address of the second scalable interface address space of the first target type is determined.

[0045] The size of the address space of the second scalable interface of the first target type is the same as that of the address space of the first scalable interface of the first target type.

[0046] The above-mentioned pre-defined relation is:

[0047]

[0048] Among them, VF v BAR b The target type mentioned above is BAR b And the corresponding identifier is the starting address of the second expandable interface address space of the first target device, VF0BAR. b The target type mentioned above is BAR b And the starting address of the first expandable interface address space, which is identified as 0. The target type mentioned above is BAR b And the size of the address space of the first scalable interface with the corresponding identifier of 0.

[0049] Specifically, in this method, a scalable interface address space is represented by a starting address and a space size. Then, using the identifier of the first target device, the starting address of the first scalable interface address space of the first target type, the space size of the first scalable interface address space of the first target type, and a preset relationship, the starting address of the second scalable interface address space of the first target type is determined, and the space size of the first scalable interface address space of the first target type is used as the space size of the second scalable interface address space. This achieves dynamic adjustment of the mapping relationship between the scalable interface address spaces of multiple devices, reducing the complexity of user-end configuration and improving system operating efficiency and management flexibility.

[0050] In one alternative implementation, after obtaining the address classification table and the address spaces of multiple types of the first scalable interface of the first device, the method further includes:

[0051] The converter stores the address classification table and the first scalable interface address space of multiple types of the first device.

[0052] After reporting the configuration failure information to the aforementioned processor, the process also includes:

[0053] Replace the updated address classification table with the address classification table described above;

[0054] Alternatively, the updated first scalable interface address space of the first device of the multiple types described above may be replaced with the first scalable interface address space of the first device of the multiple types described above.

[0055] Restore the communication link between the root complex and the converter.

[0056] Specifically, in this method, by backing up the address classification table and the address spaces of multiple types of the first scalable interface of the first device, after reporting a configuration failure to the processor, the backed-up address classification table and the backed-up address spaces of multiple types of the first scalable interface of the first device are used to replace the updated address classification table and the backed-up address spaces of multiple types of the first scalable interface of the first device. Then, the communication link between the root complex and the aforementioned converter is restored. This avoids the problem of the root complex being unable to access the scalable interface address space normally due to configuration failure, thus preventing data transmission errors and achieving the technical effect of improving system stability.

[0057] In a second aspect, the present invention provides an access device for an extensible interface address space, the device being applied to a converter, the converter being connected to a root complex and multiple devices respectively, the device comprising:

[0058] The acquisition module is used to acquire an address classification table and a first scalable interface address space of multiple types of the first device, wherein the first device is one of the multiple devices, the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device; the number and types of the multiple types of each device are the same, and each PCIe address corresponds to the scalable interface address space of one device;

[0059] The receiving module is configured to receive first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and the identifier of the first target device among the plurality of devices;

[0060] The lookup module is used to look up the type corresponding to the first target PCIe address from the multiple types of the multiple devices in the address classification table to obtain the first target type; the first target PCIe address corresponds to the first scalable interface address space of the first target type.

[0061] The determining module is configured to determine the second expandable interface address space of the first target type of the first target device based on the identifier of the first target device and the first expandable interface address space of the first target type.

[0062] The writing module is used to write the first data into the address space of the second extensible interface of the first target type.

[0063] The present invention provides an access device for an extensible interface address space, which has the following advantages:

[0064] By looking up the first target type corresponding to the target PCIe address sent by the root complex in the address classification table, the first scalable interface address space of the first target type of the first device is determined. Based on the identifier of the first target device and the first scalable interface address space of the first target type, the second scalable interface address space of the first target device for the first target type is determined, and then the first data is written into the second scalable interface address space. This achieves the technical effect of accessing the scalable interface address space via PCIe address based on the address classification table and the first scalable interface address spaces of multiple types of the first device. This allows for dynamic modification of the address classification table and the first scalable interface address spaces of multiple types of the first device, flexibly adjusting the mapping relationship between PCIe address and scalable interface address space. Simultaneously, temporarily determining the second scalable interface address space of the first target type of the first target device reduces the pre-configuration work of the scalable interface address space, lowers the conditions for accessing the scalable interface address space, further optimizes resource allocation and utilization, and improves the overall operating efficiency of the system.

[0065] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the scalable interface address space access method of the first aspect or any corresponding embodiment described above.

[0066] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the method for accessing the extensible interface address space of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0067] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0068] Figure 1 This is a schematic diagram of a converter according to an embodiment of the present invention;

[0069] Figure 2 This is one of the flowcharts for accessing the scalable interface address space according to an embodiment of the present invention;

[0070] Figure 3This is a second flowchart of a method for accessing the address space of an extensible interface according to an embodiment of the present invention;

[0071] Figure 4 This is a schematic diagram of address translation according to an embodiment of the present invention;

[0072] Figure 5 This is a schematic diagram of address space translation according to an embodiment of the present invention;

[0073] Figure 6 This is a schematic diagram of the structure of an access device for an extensible interface address space according to an embodiment of the present invention;

[0074] Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention;

[0075] Figure 8 This is a schematic diagram of an access system for the scalable interface address space according to an embodiment of the present invention. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0077] According to an embodiment of the present invention, an embodiment of a method for accessing an extensible interface address space is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0078] Figure 1 This is a schematic diagram of a converter according to an embodiment of the present invention, such as... Figure 1 As shown, the converter connects to the root complex (RC) and multiple devices, such as devices 0 to 6. The multiple devices can be multiple DUTs (Device Under Test) under a virtual function (VF).

[0079] The converter includes: a configuration register, a manager, a NIC bridge (Network Interface Controller Bridge), and at least one interface, such as a first interface and a second interface, wherein the first interface can be a PCIe interface and the second interface can be an expandable interface. Furthermore, it should be understood that it may include other, more or fewer, interfaces, and this embodiment does not impose any limitations on this.

[0080] The manager connects to the NIC bridge and the configuration register. The NIC bridge connects to the root complex RC via a PCIe interface, and also connects to other devices via an AXI interface.

[0081] In addition, in one possible implementation, the converter also includes a backup register for backing up the data in the configuration register.

[0082] This embodiment provides a method for accessing an extensible interface address space, which can be used in the aforementioned converter. Figure 2 This is one of the flowcharts for a method of accessing the address space of an extensible interface according to an embodiment of the present invention, the method comprising:

[0083] Step S201: Obtain the address classification table and the first scalable interface address space of multiple types of the first device.

[0084] The first device is one of the aforementioned devices. The address space of the first extensible interface of the first device of various types can be a user-configured address space.

[0085] The address classification table includes: multiple types for multiple devices, and at least one PCIe address corresponding to each type for each device. The number and types of each type are the same for all devices, and each PCIe address corresponds to the scalable interface address space of one device.

[0086] Multiple types can correspond to multiple BARs (Base Address Registers). For example, there could be six types, from BAR0 to BAR5. The address classification table can record at least one PCIe address corresponding to each device's BAR0 to BAR5.

[0087] One implementation of obtaining the address classification table is as follows: the manager retrieves the address classification table from a configuration register, where the address allocation table is pre-stored in the configuration register. Similarly, the manager can also retrieve the first scalable interface address space of multiple types of the first device from the register.

[0088] Step S202: Receive the first address request information and first data sent by the root complex.

[0089] The first address request information includes: the first target PCIe address and the identifier of the first target device among the aforementioned multiple devices.

[0090] The first target PCIe address can be any one of at least one PCIe address corresponding to the scalable interface address space of a first device.

[0091] The first data can be the data that needs to be written into the scalable interface address space corresponding to the first target PCIe address.

[0092] The identifier of the first target device can be a unique identification code for multiple devices, for example, 0 to 10.

[0093] In step S202, one specific implementation is as follows: the root complex first obtains the first address request information and the first data, then converts this information and data into TLP (Transaction Layer Packet) format, and finally sends the TLP format packet to the converter.

[0094] Step S203: From the multiple types of the above-mentioned multiple devices in the address classification table, find the type corresponding to the first target PCIe address to obtain the first target type.

[0095] The first target PCIe address corresponds to the first scalable interface address space of the first target type.

[0096] Specifically, all PCIe addresses are scanned from the address classification table to find the first target PCIe address and its corresponding type, which is designated as the first target type. Under this first target type, there are at least one PCIe address of the first target type, the first scalable interface address space of the first target type, and the scalable interface address spaces of the first target type of other devices (e.g., the second scalable interface address space of the first type of the first target device).

[0097] Step S204: Determine the second expandable interface address space of the first target type of the first target device based on the identifier of the first target device and the first expandable interface address space of the first target type.

[0098] Each device has multiple types of scalable interface address spaces, each corresponding to different functions or resources. Determining the second scalable interface address space from the first scalable interface address space can be based on the target type and combined with the identifier of the first target device to determine the interval between address spaces. Then, the first scalable interface address space is shifted to determine the second scalable interface address space.

[0099] Step S205: Write the first data into the address space of the second scalable interface of the first target type.

[0100] It is possible to initiate a write request to the second scalable interface address space of the first target type through the aforementioned NIC bridge using the scalable interface protocol, and transmit the first data to the second scalable interface address space of the first target type through the scalable interface bus.

[0101] The method provided in this embodiment determines the first scalable interface address space of the first target type of the first device by looking up the first target type corresponding to the target PCIe address sent by the root complex in the address classification table. Based on the identifier of the first target device and the first scalable interface address space of the first target type, a second scalable interface address space of the first target device is determined. Then, first data is written into this second scalable interface address space. This achieves the technical effect of accessing the scalable interface address space via PCIe address based on the address classification table and the first scalable interface address spaces of multiple types of the first device. This allows for subsequent dynamic modification of the address classification table and the first scalable interface address spaces of multiple types of the first device, flexibly adjusting the mapping relationship between PCIe address and scalable interface address space.

[0102] In addition, this method can also determine the second scalable interface address space of the first target type of the first target device in real time, which reduces the pre-configuration work of the scalable interface address space, lowers the conditions for accessing the scalable interface address space, further optimizes resource allocation and utilization, and improves the overall operating efficiency of the system.

[0103] In one alternative implementation, to further dynamically adjust the mapping relationship between PCIe addresses and the scalable interface address space, Figure 3 This is a second flowchart of a method for accessing the scalable interface address space according to an embodiment of the present invention, such as... Figure 3 As shown, after step S201 above, the following is also included:

[0104] Step S301: Receive the first configuration instruction sent by the processor.

[0105] The first configuration instruction can be a TLP message used to modify the data in the aforementioned configuration register. The processor can be a CPU (Central Processing Unit).

[0106] Specifically, the converter can be connected to the processor via the PCIe bus to receive the first configuration instruction.

[0107] Step S302: Parse the first configuration instruction to obtain the correspondence between the second target PCIe address and the multiple types of the multiple devices.

[0108] Specifically, the converter parses the TLP message to obtain the correspondence between the second target PCIe address and the various types of the aforementioned devices.

[0109] Step S303: Based on the correspondence between the second target PCIe address and the multiple types of the multiple devices, modify the device and type corresponding to the second target PCIe address in the address classification table to obtain an updated address classification table.

[0110] Specifically, it can involve traversing the address classification table, finding the second target PCIe address, and modifying the corresponding device and type.

[0111] The method provided in this embodiment modifies the device and type corresponding to the second target PCIe address in the address classification table according to the first configuration instruction sent by the processor, and updates the address classification table, thereby realizing the dynamic adjustment of the mapping relationship between PCIe addresses and the scalable interface address space. This achieves the technical effect of real-time adjustment of resource allocation, enabling the system to adapt more flexibly to various application scenarios and improve the overall resource utilization.

[0112] In an optional implementation, to further verify whether the dynamic adjustment of the mapping relationship between the PCIe address and the scalable interface address space has been successfully achieved, after step S303 above, the following is also included:

[0113] Generate second address request information and second data. The second address request information includes: the second target PCIe address and the identifier of the second target device among the plurality of devices.

[0114] The second address request information and the second data can be a TLP message generated by the converter.

[0115] From the multiple types of the aforementioned multiple devices in the updated address classification table, find the type corresponding to the aforementioned second target PCIe address to obtain the second target type.

[0116] From the updated address classification table, find the corresponding device type based on the second target PCIe address and output the second target type.

[0117] Based on the identifier of the second target device and the first scalable interface address space of the second target type, the second scalable interface address space of the second target device is determined.

[0118] The second extensible interface address space of the second target type can be determined based on the identifier of the second target device and its corresponding first extensible interface address space.

[0119] Write the second data into the address space of the second extensible interface of the second target type.

[0120] It can be that a write operation is sent to a defined second scalable interface address space to write the second data.

[0121] Read the first actual data from the address space of the second extensible interface of the second target type mentioned above.

[0122] It can be that a read operation is sent to a defined second scalable interface address space to obtain the first actual data.

[0123] Determine whether the second data mentioned above is the same as the first actual data mentioned above.

[0124] This could involve comparing the second set of data with the first set of actual data to determine if they are the same.

[0125] If so, then restore the communication link between the root complex and the converter.

[0126] If the results are the same: it means the data was successfully transmitted and the communication link between the root complex and the converter can be restored. This means the device can function normally and exchange data.

[0127] If not, then report a configuration failure message to the aforementioned processor.

[0128] If they are different, it indicates that there may be a problem with data transmission, and the system needs to report the configuration failure to the processor in order to troubleshoot and repair the problem.

[0129] The method provided in this embodiment involves updating the address classification table. The converter simulates the root complex to generate second address request information and second data. Following the same method described above, it locates the second scalable interface address space corresponding to the second target type and writes the second data. Then, it reads the first actual data from this second scalable interface address space. By comparing the read first actual data with the second data, it verifies whether the first data is correctly stored in the second scalable interface address space. If so, the communication link between the root complex and the converter is restored; otherwise, a configuration failure message is sent to the processor. This achieves the goal of verifying the updated address classification table after updating it, ensuring the correctness and effectiveness of the address classification table update.

[0130] In an optional implementation, to further dynamically adjust the scalable interface address space, after step S201 above, the following is also included:

[0131] Receive the second configuration instruction sent by the processor.

[0132] The second configuration instruction can be a TLP message used to modify the data in the aforementioned configuration register. The processor can be a CPU.

[0133] Specifically, the aforementioned converter can be connected to the processor via a PCIe bus to receive a second configuration instruction.

[0134] Parse the second configuration instruction to obtain the modified first extensible interface address space.

[0135] Specifically, the converter parses the TLP message to obtain the modified first scalable interface address space and its type.

[0136] Based on the modified first scalable interface address space described above, the first scalable interface address spaces of multiple types of the first device are modified to obtain the updated first scalable interface address spaces of multiple types of the first device.

[0137] Specifically, it can involve traversing the configuration registers, finding a first scalable interface address space of the same type as the modified first scalable interface address space, and replacing it with the modified first scalable interface address space.

[0138] The method provided in this embodiment modifies the address space of multiple types of the first scalable interface of the first device according to the second configuration instruction sent by the processor, thereby realizing the dynamic adjustment of the scalable interface address space and achieving the technical effect of real-time adjustment of resource allocation. This allows the system to adapt more flexibly to various application scenarios and improve the overall resource utilization.

[0139] In an optional implementation, to further verify whether the dynamic adjustment of the scalable interface address space was successful, after modifying the first scalable interface address spaces of multiple types of the first device according to the modified first scalable interface address space to obtain the updated first scalable interface address spaces of multiple types of the first device, the method further includes:

[0140] Generate third address request information and third data. The third address request information includes: the third target PCIe address and the identifier of the third target device among the multiple devices.

[0141] The third address request information and the third data can be a TLP message generated by the converter.

[0142] From the multiple types of the above-mentioned devices in the address classification table, find the type corresponding to the above-mentioned third target PCIe address to obtain the third target type.

[0143] From the address classification table, find the corresponding device type based on the third target PCIe address and output the third target type.

[0144] Based on the identifier of the third target device and the updated first scalable interface address space of the third target type, the second scalable interface address space of the third target device of the third target type is determined.

[0145] The second scalable interface address space of the third target type can be determined based on the identifier of the target device and its corresponding first scalable interface address space.

[0146] Write the aforementioned third data into the address space of the second extensible interface of the aforementioned third target type.

[0147] It could be sending a write operation to a defined second scalable interface address space to write third data.

[0148] Read the second actual data from the address space of the second extensible interface of the third target type mentioned above.

[0149] It can be that a read operation is sent to a defined second scalable interface address space to obtain the second actual data.

[0150] Determine whether the third data mentioned above is the same as the second actual data mentioned above.

[0151] One could compare the third data with the second actual data mentioned above to determine if they are the same.

[0152] If so, then restore the communication link between the root complex and the converter.

[0153] If the results are the same: it means the data was successfully transmitted and the communication link between the root complex and the converter can be restored. This means the device can function normally and exchange data.

[0154] If not, then report a configuration failure message to the aforementioned processor.

[0155] If they are different, it indicates that there may be a problem with data transmission, and the system needs to report the configuration failure to the processor in order to troubleshoot and repair the problem.

[0156] The method provided in this embodiment involves updating the first scalable interface address space of multiple types of the first device. The converter simulates the root complex to generate second address request information and second data. Following the same method described above, it finds the corresponding third scalable interface address space of the second target type and writes the third data. Then, it reads the first actual data from the third scalable interface address space. By comparing the read second actual data with the third data, it verifies whether the third data is correctly stored in the second scalable interface address space. If so, the communication link between the root complex and the converter is restored; otherwise, a configuration failure message is sent to the processor. This achieves the goal of verifying the updated first scalable interface address space after updating it, ensuring the correctness and effectiveness of the update.

[0157] In one alternative implementation, to further enable automatic mapping between the scalable interface address spaces of multiple devices, each scalable interface address space includes: a starting address and a space size.

[0158] An extensible interface address space includes multiple extensible interface addresses. The starting address can be the first address in the space, and the size can be the number of addresses in the address space or the amount of data it can hold.

[0159] Step S204 above includes:

[0160] Based on the identifier of the first target device, the starting address of the first scalable interface address space of the first target type, the size of the first scalable interface address space of the first target type, and a preset formula, the starting address of the second scalable interface address space of the first target type is determined.

[0161] That is, based on the starting address of the first scalable interface address space and the device identifier, the starting address of the second scalable interface address space of the same type of the first target device is determined.

[0162] The size of the address space of the second extensible interface of the first target type is the same as that of the address space of the first extensible interface of the first target type.

[0163] The above-mentioned pre-defined relation is:

[0164]

[0165] Among them, VF v BAR b The target type mentioned above is BAR b And the corresponding identifier is the starting address of the second expandable interface address space of the first target device, VF0BAR. bThe target type mentioned above is BAR b And the starting address of the first expandable interface address space, which is identified as 0. The target type mentioned above is BAR b And the size of the address space of the first scalable interface with the corresponding identifier of 0.

[0166] VF v The virtual device under test is identified as v. VF0 is the first device, which is identified as 0. Therefore, if the first target PCIe address requests the first device, the first data can be written directly into the first scalable interface address space of the target type corresponding to the first device, or it can be determined by the above preset relationship, i.e., v = 0.

[0167] The method provided in this embodiment represents a scalable interface address space using a starting address and a space size. Then, using the identifier of the first target device, the starting address of the first scalable interface address space of the first target type, the space size of the first scalable interface address space of the first target type, and a preset relationship, the starting address of the second scalable interface address space of the first target type is determined, and the space size of the first scalable interface address space of the first target type is used as the space size of the second scalable interface address space. This achieves dynamic adjustment of the mapping relationship between the scalable interface address spaces of multiple devices, reducing the complexity of user-end configuration and improving system operating efficiency and management flexibility.

[0168] Furthermore, after determining the second scalable interface address space, the corresponding scalable interface address in the second scalable interface address space can also be determined based on the PCIe address. Figure 4 This is a schematic diagram of address translation according to an embodiment of the present invention, such as... Figure 4 As shown, this includes: the address space corresponding to the PCIe address passed from the RC end, with a starting address of 64`h0000_0000_1000_0000 and a size of 1M (20 bits); and the converted scalable interface address space, with a starting address of 64`h0000_0000_3000_0000 and a size of 1M (20 bits).

[0169] The location of the corresponding expandable interface address in the address space can be determined based on the location of the PCIe address in the corresponding PCIe address space.

[0170] Figure 5 This is a schematic diagram of address space translation according to an embodiment of the present invention, as shown below. Figure 5As shown, this includes multiple types of PCIe address spaces from multiple devices. After being input into the converter, these spaces are converted to their corresponding expandable interface address spaces. Each device has at least one set of PCIe address spaces and expandable interface address spaces of the same type. The address space of device 0 in the expandable interface address space is pre-configured and recorded in the converter. The expandable interface address spaces of other devices are configured according to their identifiers and types, as well as the corresponding expandable interface address space of device 0.

[0171] In an optional implementation, to avoid system failure caused by failure to update the address classification table or the address space of multiple types of the first scalable interface of the first device, after step S201 above, the method further includes:

[0172] The aforementioned address classification table and the first scalable interface address space of multiple types of the first device are stored in the aforementioned converter.

[0173] Specifically, the address classification table and the address spaces of the first scalable interfaces of the first device of multiple types can be stored in the aforementioned backup register.

[0174] After reporting the configuration failure information to the aforementioned processor, the process also includes:

[0175] Replace the updated address classification table with the address classification table described above.

[0176] Alternatively, the first scalable interface address space of the first device of the above-mentioned multiple types may be replaced with the first scalable interface address space of the first device of the above-mentioned multiple types.

[0177] Specifically, after reporting the configuration failure information to the processor, the address classification table and the address spaces of the first scalable interfaces of the first device of multiple types can be retrieved from the backup register. The configuration register is then cleared and written to the retrieved address classification table and the address spaces of the first scalable interfaces of the first device of multiple types.

[0178] Restore the communication link between the root complex and the converter.

[0179] Yes, restoring a communication link typically involves reinitializing devices or reconfiguring communication parameters to ensure they can interact properly. Ensuring the root complex and converters are in the same state may require updating relevant registers or settings to prepare for subsequent data transfers. After communication is restored, the system may need to record this state or send a signal to other components indicating that the communication link has been restored.

[0180] The method provided in this embodiment backs up the address classification table and the address spaces of multiple types of the first scalable interface of the first device. After reporting a configuration failure to the processor, the backed-up address classification table and the backed-up address spaces of multiple types of the first scalable interface of the first device are used to replace the updated address classification table and the backed-up address spaces of multiple types of the first scalable interface of the first device. Then, the communication link between the root complex and the aforementioned converter is restored. This avoids the problem of the root complex being unable to access the scalable interface address space normally due to configuration failure, which leads to data transmission errors, thus achieving the technical effect of improving system stability.

[0181] In one optional implementation, after determining the second scalable interface address space of the first target type of the first target device, the method further includes: receiving status feedback information from the root complex, wherein the status feedback information indicates the current operating status of the first target device.

[0182] Based on the aforementioned status feedback information, it is determined whether the first target device is in an available state. If so, the write operation continues; if not, the write operation is paused or retried, and the status information is recorded for subsequent analysis. Recording the status information also includes:

[0183] Generate a log file containing the identifier, timestamp, status feedback information, and detailed information of the first target device and the first data.

[0184] Log files are regularly uploaded to the central monitoring system for performance analysis and fault diagnosis.

[0185] The method provided in this embodiment helps to provide detailed historical records when system problems occur, facilitating subsequent maintenance and optimization. This enhances the system's traceability and management capabilities. It ensures that the system can make appropriate adjustments when equipment is unavailable, thereby improving overall stability and reliability.

[0186] This invention also provides an access device for an scalable interface address space, which is applied to a converter. Figure 6 This is a schematic diagram of the structure of an access device for an extensible interface address space according to an embodiment of the present invention, such as... Figure 6 As shown, the device includes:

[0187] The acquisition module 601 is used to acquire the address classification table and the first scalable interface address space of multiple types of the first device.

[0188] The first device mentioned above is one of the aforementioned multiple devices. The address classification table includes multiple types of the aforementioned multiple devices, and at least one PCIe address corresponding to each type of each device. The number and types of the multiple types of each of the aforementioned devices are the same, and each PCIe address corresponds to the scalable interface address space of one device.

[0189] The receiving module 602 is used to receive the first address request information and the first data sent by the root complex.

[0190] The aforementioned first address request information includes: the first target PCIe address and the identifier of the first target device among the aforementioned multiple devices.

[0191] The lookup module 603 is used to look up the type corresponding to the first target PCIe address from the multiple types of the multiple devices in the address classification table, and obtain the first target type.

[0192] The aforementioned first target PCIe address corresponds to the first scalable interface address space of the aforementioned first target type.

[0193] The determining module 604 is used to determine the second expandable interface address space of the first target type of the first target device based on the identifier of the first target device and the first expandable interface address space of the first target type.

[0194] The writing module 605 is used to write the first data into the address space of the second extensible interface of the first target type.

[0195] The apparatus provided in this embodiment determines the first scalable interface address space of the first target type of the first device by looking up the first target type corresponding to the target PCIe address sent by the root complex in the address classification table. Based on the identifier of the first target device and the first scalable interface address space of the first target type, it determines the second scalable interface address space of the first target device for the first target type, and then writes first data into the second scalable interface address space. This achieves the technical effect of accessing the scalable interface address space via PCIe address based on the address classification table and the first scalable interface address spaces of multiple types of the first device. This allows for dynamic modification of the address classification table and the first scalable interface address spaces of multiple types of the first device, flexibly adjusting the mapping relationship between PCIe address and scalable interface address space. Simultaneously, temporarily determining the second scalable interface address space of the first target type of the first target device reduces the pre-configuration work of the scalable interface address space, lowers the conditions for accessing the scalable interface address space, further optimizes resource allocation and utilization, and improves the overall operating efficiency of the system.

[0196] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0197] In this embodiment, the access device for the scalable interface address space is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0198] This invention also provides a computer device having the above-described features. Figure 6 The illustrated device is an access device for the scalable interface address space.

[0199] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0200] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include an integrated circuit. The integrated circuit may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPRS), or any combination thereof.

[0201] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiment.

[0202] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0203] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0204] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0205] Figure 8 This is a schematic diagram of an access system for the scalable interface address space according to an embodiment of the present invention, such as... Figure 8 As shown, the system includes: a root complex, converters, and multiple devices. The converters are connected to the root complex and the multiple devices, such as devices 0 to 6. The multiple devices can be multiple devices under test in a virtual function.

[0206] This converter can include, for example Figure 1 As shown, it includes: a configuration register, a manager, a NIC bridge, and at least one interface, such as a first interface and a second interface, wherein the first interface can be a PCIe interface and the second interface can be an expandable interface. Furthermore, it should be understood that it may include other, more or fewer, interfaces, and this embodiment does not limit this.

[0207] The manager connects to the NIC bridge and the configuration register. The NIC bridge connects to the root complex RC via a PCIe interface, and also connects to other devices via an expandable interface.

[0208] In addition, in one possible implementation, the converter also includes a backup register for backing up the data in the configuration register.

[0209] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0210] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for accessing an extensible interface address space, characterized in that, The method is applied to a converter, which is connected to a root complex and multiple devices, and the method includes: Obtain an address classification table and a first scalable interface address space for multiple types of a first device, wherein the first device is one of the multiple devices, and the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device; the number and types of the multiple types of each device are the same, and each PCIe address corresponds to the scalable interface address space of a device; Receive first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and the identifier of the first target device among the plurality of devices; From the multiple types of the multiple devices in the address classification table, the type corresponding to the first target PCIe address is searched to obtain the first target type; the first target PCIe address corresponds to the first scalable interface address space of the first target type; Based on the identifier of the first target device and the first scalable interface address space of the first target type, determine the second scalable interface address space of the first target device for the first target type; Write the first data into the address space of the second extensible interface of the first target type.

2. The method according to claim 1, characterized in that, After obtaining the address classification table and the address spaces of the first extensible interfaces for multiple types of the first device, the process also includes: Receive the first configuration instruction sent by the processor; Parse the first configuration instruction to obtain the correspondence between the second target PCIe address and the multiple types of the multiple devices; Based on the correspondence between the second target PCIe address and the multiple types of the multiple devices, the device and type corresponding to the second target PCIe address in the address classification table are modified to obtain an updated address classification table.

3. The method according to claim 2, characterized in that, After modifying the device and type corresponding to the second target PCIe address in the address classification table according to the correspondence between the second target PCIe address and the multiple types of the multiple devices, and obtaining an updated address classification table, the method further includes: Generate second address request information and second data, wherein the second address request information includes: the second target PCIe address and the identifier of the second target device among the plurality of devices; From the multiple types of the multiple devices in the updated address classification table, find the type corresponding to the second target PCIe address to obtain the second target type; Based on the identifier of the second target device and the first scalable interface address space of the second target type, determine the second scalable interface address space of the second target device for the second target type; Write the second data into the address space of the second extensible interface of the second target type; Read the first actual data from the address space of the second extensible interface of the second target type; Determine whether the second data is the same as the first actual data; If so, then restore the communication link between the root complex and the converter; If not, a configuration failure message is sent back to the processor.

4. The method according to claim 1, characterized in that, After obtaining the address classification table and the address spaces of the first extensible interfaces for multiple types of the first device, the process also includes: Receive the second configuration instruction sent by the processor; Parse the second configuration instruction to obtain the modified first extensible interface address space; Based on the modified first scalable interface address space, the first scalable interface address spaces of multiple types of the first device are modified to obtain the updated first scalable interface address spaces of multiple types of the first device.

5. The method according to claim 4, characterized in that, After modifying the first scalable interface address spaces of multiple types of the first device according to the modified first scalable interface address space to obtain the updated first scalable interface address spaces of multiple types of the first device, the method further includes: Generate third address request information and third data, wherein the third address request information includes: a third target PCIe address and the identifier of the third target device among the plurality of devices; From the multiple types of the multiple devices in the address classification table, find the type corresponding to the third target PCIe address to obtain the third target type; Based on the identifier of the third target device and the updated first scalable interface address space of the third target type, the second scalable interface address space of the third target device is determined. The third data is written into the address space of the second extensible interface of the third target type; Read the second actual data from the address space of the second extensible interface of the third target type; Determine whether the third data is the same as the second actual data; If so, then restore the communication link between the root complex and the converter; If not, a configuration failure message is sent back to the processor.

6. The method according to any one of claims 1 to 5, characterized in that, Each scalable interface address space includes: a starting address and a space size; Based on the identifier of the first target device and the first extensible interface address space of the first target type, determine the second extensible interface address space of the first target device, including: Based on the identifier of the first target device, the starting address of the first scalable interface address space of the first target type, the size of the first scalable interface address space of the first target type, and a preset formula, determine the starting address of the second scalable interface address space of the first target type. The size of the address space of the second extensible interface of the first target type is the same as the address space of the first extensible interface of the first target type. The preset relation is: Among them, VF v BAR b The target type is BAR b And the corresponding identifier is the starting address of the second expandable interface address space of the first target device, VF0BAR. b The target type is BAR b And the starting address of the first expandable interface address space, which is identified as 0. The target type is BAR b And the size of the address space of the first scalable interface with the corresponding identifier of 0.

7. The method according to claim 3 or 5, characterized in that, After obtaining the address classification table and the address spaces of the first extensible interfaces for multiple types of the first device, the process also includes: The converter stores the address classification table and the first scalable interface address space of multiple types of the first device; After reporting the configuration failure information to the processor, the process also includes: Replace the updated address classification table with the address classification table; Alternatively, the updated first scalable interface address space of the first device of multiple types may be replaced with the first scalable interface address space of the first device of multiple types. Restore the communication link between the root complex and the converter.

8. A device for accessing an scalable interface address space, characterized in that, The apparatus is used in a converter, which is connected to a root complex and multiple devices, and the apparatus includes: The acquisition module is used to acquire an address classification table and a first scalable interface address space of multiple types of a first device, wherein the first device is one of the multiple devices, the address classification table includes: multiple types of the multiple devices, and at least one PCIe address corresponding to each type of each device; the number and types of the multiple types of each device are the same, and each PCIe address corresponds to the scalable interface address space of a device; The receiving module is configured to receive first address request information and first data sent by the root complex, wherein the first address request information includes: a first target PCIe address and the identifier of the first target device among the plurality of devices; The lookup module is used to look up the type corresponding to the first target PCIe address from the multiple types of the multiple devices in the address classification table to obtain the first target type; the first target PCIe address corresponds to the first scalable interface address space of the first target type; The determining module is configured to determine the second expandable interface address space of the first target type of the first target device based on the identifier of the first target device and the first expandable interface address space of the first target type; The writing module is used to write the first data into the address space of the second extensible interface of the first target type.

9. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method for accessing the scalable interface address space as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method for accessing the scalable interface address space according to any one of claims 1 to 7.

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