FPGA-based SPI-flexray communication conversion module

Abstract

The application provides an FPGA-based SPI-FlexRay communication conversion module and relates to the technical field of communication, which comprises an FPGA processing unit, a bus isolation unit and a FlexRay communication unit; the bus isolation unit is connected with an external interface, the FPGA processing unit and the FlexRay communication unit; the bus isolation unit completes the buffering and isolation between high-speed data and the external interface; the FlexRay communication unit completes the FlexRay bus data transceiving, data flow control and data conversion; the FPGA processing unit receives SPI bus data or FlexRay bus data, and performs data analysis and buffering; the standard SPI and FlexRay protocols are adopted to perform data frame encapsulation; the data conversion between the SPI and the FlexRay high-speed bus is completed and outputted. The application realizes the data communication and conversion between the high-speed SPI bus and the high-speed FlexRay bus.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an FPGA-based SPI-FlexRay communication conversion module for realizing data communication and conversion between a high-speed SPI bus and a high-speed FlexRay bus. Background Art

[0002] With the rapid development of industrial bus technology, the complexity and connectivity of avionics systems are increasing. To meet increasingly stringent safety and performance requirements, various communication protocols and standards are widely used in avionics system internal networks. Among them, SPI and FlexRay are two very important communication protocols.

[0003] SPI is a synchronous serial data transmission protocol with advantages such as a simple interface, high communication speed, and low power consumption. It is commonly used for communication between microcontrollers and external devices. However, the SPI protocol is not suitable for high-speed and high-reliability communication requirements, especially in applications involving avionics systems, automotive electronics systems, and other high-security applications.

[0004] On the other hand, FlexRay, a high-speed communication protocol for the automotive sector, boasts determinism, fault tolerance, and scalability. In recent years, it has become increasingly suitable for communication in avionics systems and safety-related functions. However, due to its complexity and cost, FlexRay is not the preferred communication protocol for all avionics equipment.

[0005] Therefore, in the internal network of avionics systems, SPI and FlexRay often coexist. In order to achieve seamless connection and data exchange between different protocols, a module that can convert communication between SPI and FlexRay is needed.

[0006] While some SPI-to-FlexRay conversion solutions exist on the market, these suffer from low conversion efficiency, low reliability, complex principles, and high costs. Especially when processing large amounts of data and high-frequency communications, existing conversion solutions often struggle to meet the high-performance requirements of internal system networks. Summary of the Invention

[0007] To address the problems of low conversion efficiency, low reliability, and high cost between the SPI interface and FlexRay node devices in existing high-speed buses, the present invention provides an FPGA-based SPI-FlexRay communication conversion module, which is efficient, reliable, simple in principle, and cost-effective. This module enables data communication and conversion between SPI devices and FlexRay node devices, meeting the growing communication needs of the internal network of the avionics system.

[0008] The embodiment of the present application provides the following technical solution: an FPGA-based SPI-FlexRay communication conversion module, comprising: an FPGA processing unit, a bus isolation unit, and a FlexRay communication unit;

[0009] The bus isolation unit is connected to the external interface and is respectively connected to the FPGA processing unit and the FlexRay communication unit, and the FPGA processing unit and the FlexRay communication unit are communicatively connected with each other; the bus isolation unit is used to complete buffering and isolation between high-speed data and the external interface, the FlexRay communication unit is used to complete FlexRay bus data reception and transmission and data flow control, and complete data conversion between external high-speed data and FPGA interface data; the FPGA processing unit is used to receive SPI bus data from the bus isolation unit or FlexRay bus data from the FlexRay communication unit, and perform data parsing and caching internally, use standard SPI and FlexRay protocols for data frame encapsulation, complete data conversion between the two high-speed buses SPI and FlexRay, so as to convert the SPI bus data from the bus isolation unit into FlexRay bus data and then output it to the FlexRay communication unit, or convert the FlexRay bus data from the FlexRay communication unit into SPI bus data and then output it to the bus isolation unit.

[0010] According to an embodiment of the present application, a power conversion unit is further included, which is connected to the FPGA processing unit, the bus isolation unit and the FlexRay communication unit respectively, and is used to supply power to each component unit.

[0011] According to one embodiment of the present application, the FlexRay communication unit includes a FlexRay bus communication controller and a FlexRay bus transceiver, the FlexRay bus transceiver is connected to the bus isolation unit and the FlexRay bus communication controller respectively, the FPGA processing unit includes an FPGA main control chip, and the FlexRay bus communication controller is connected to the FPGA main control chip.

[0012] According to one embodiment of the present application, the bus isolation unit includes an SPI bus isolation unit and a FlexRay bus isolation unit. The FPGA main control chip is connected to the SPI bus isolation unit to interact with the external interface through the SPI bus isolation unit. The FlexRay bus transceiver is connected to the FlexRay bus isolation unit to provide a path for FlexRay bus communication through the external interface.

[0013] According to one embodiment of the present application, the FPGA master control chip includes an SPI data encapsulation module, an SPI frame driver module, an SPI data parsing module, a cache module, a clock control module, a FlexRay data encapsulation module, and a FlexRay frame driver module, wherein the FPGA system clock signal is provided by an external clock circuit, and the clock control module generates a bus reference clock signal inside the FPGA master control chip, and the cache module includes a data receiving cache module and a data sending cache module;

[0014] When SPI bus data is used as input and FlexRay bus data is used as output, the SPI bus isolation unit inputs the SPI bus data into the FPGA main control chip. The SPI bus data includes a data signal and a clock signal. The SPI data parsing module performs data parsing according to the standard protocol inside the FPGA main control chip, inputs the parallel data results into the cache module for storage, and then sequentially processes the data through the FlexRay data encapsulation module and the FlexRay frame driver module, and finally sends the data to the FlexRay communication unit.

[0015] When FlexRay bus data is used as input and SPI bus data is used as output, external FlexRay bus data enters the FlexRay bus transceiver through the logic output port of the FlexRay bus isolation unit, and the bus signal is input into the FPGA main control chip through the FlexRay bus communication controller. Inside the FPGA main control chip, the FlexRay frame driver module puts the data into the cache module for storage, and processes it in turn through the SPI data encapsulation module and the SPI frame driver module, and finally outputs it to the external interface through the logic port of the SPI bus isolation unit.

[0016] According to one embodiment of the present application, the FPGA processing unit further includes a maintenance circuit, a reset circuit and a clock circuit, and the maintenance circuit, reset circuit and clock circuit are respectively connected to the FPGA main control chip.

[0017] According to an embodiment of the present application, the FlexRay communication unit is connected to the FPGA processing unit via an asynchronous communication bus, a control line, and a status feedback signal.

[0018] According to one embodiment of the present application, the FPGA processing unit is internally integrated with an asynchronous high-speed cache hard core, which can set the cache area width and depth according to the actual bus data width and rate. The FPGA processing unit is internally integrated with a clock management hard core, which can set the system clock and reference clock according to the SPI and FlexRay bus rates.

[0019] Compared to the prior art, the beneficial effects achieved by at least one of the above-mentioned technical solutions employed in the embodiments of this specification include at least the following: The embodiments of the present invention utilize standard SPI bus and FlexRay bus interfaces, enabling direct connection to external SPI / FlexRay devices, addressing the inflexible development and testing issues inherent in single-bus environments. A bus isolation unit is employed to isolate the transmission of internal module data from external data, ensuring stable and reliable bus data. FPGA-based data protocol conversion allows for flexible design and development within the FPGA chip based on bus characteristics. FlexRay network data interaction is accomplished using a bus controller and transceiver. Internal module power supply design is implemented using a DC / DC and LDO chip, resulting in an FPGA-based SPI-FlexRay communication conversion module. The present invention eliminates the need for additional processors and completely eliminates the potential impact of software issues. Through its unique design, the present invention can easily achieve seamless conversion between SPI bus data and FlexRay bus data. Its principle is concise and clear, reducing costs while improving data transmission efficiency and stability, providing a more convenient and efficient data conversion solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a schematic diagram of an FPGA-based SPI-FlexRay communication conversion module according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the SPI-FlexRay bus conversion principle according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the FlexRay-SPI bus conversion principle according to an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the SPI encapsulation module state machine according to an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram showing the interconnection principle of the FlexRay communication unit and other units according to an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of a power conversion unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0028] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0029] An embodiment of the present invention proposes an FPGA-based SPI-to-FlexRay communication conversion module. As a programmable logic device, FPGAs offer a high degree of flexibility and configurability, enabling customization and optimization based on diverse application requirements. By leveraging these advantages, an embodiment of the present invention implements an efficient, reliable, simple, and cost-effective SPI-to-FlexRay communication conversion module to meet the growing communication needs of avionics system internal networks.

[0030] The embodiment of the present invention provides an FPGA-based SPI-FlexRay communication conversion module, comprising: an FPGA processing unit, a bus isolation unit, and a FlexRay communication unit;

[0031] The bus isolation unit is connected to the external interface and is respectively connected to the FPGA processing unit and the FlexRay communication unit, and the FPGA processing unit and the FlexRay communication unit are communicatively connected with each other; the bus isolation unit is used to complete buffering and isolation between high-speed data and the external interface to prevent the spread of circuit or other interference; the FlexRay communication unit is used to complete FlexRay bus data reception and transmission and data flow control, and complete data conversion between external high-speed data and FPGA interface data; the FPGA processing unit is used to receive SPI bus data from the bus isolation unit or FlexRay bus data from the FlexRay communication unit, and internally perform data parsing and caching, use standard SPI and FlexRay protocols for data frame encapsulation, complete data conversion between the two high-speed buses SPI and FlexRay, so as to convert the SPI bus data from the bus isolation unit into FlexRay bus data and output it to the FlexRay communication unit, or convert the FlexRay bus data from the FlexRay communication unit into SPI bus data and output it to the bus isolation unit.

[0032] In some embodiments, the FlexRay communication unit includes a FlexRay bus communication controller and two FlexRay bus transceivers, the FlexRay bus transceivers are connected to the bus isolation unit and the FlexRay bus communication controller respectively, the FPGA processing unit includes an FPGA main control chip, and the FlexRay bus communication controller is connected to the FPGA main control chip.

[0033] In this embodiment, the FlexRay bus communication controller is implemented using the MFR4310 chip of NXP, and the FlexRay bus transceiver is implemented using the TJA1080 chip of NXP.

[0034] In some embodiments, the bus isolation unit includes an SPI bus isolation unit and a FlexRay bus isolation unit. The FPGA master control chip is connected to the SPI bus isolation unit to interact with an external interface through the SPI bus isolation unit. The FlexRay bus transceiver is connected to the FlexRay bus isolation unit to provide a path for FlexRay bus communication through the external interface.

[0035] In this embodiment, the bus isolation unit completes the signal isolation protection between the internal bus data and the external interface. The SPI bus isolation chip is implemented using the ADuM1201 magnetic isolation chip of ADI Company, and the ADuM1201 magnetic isolation chip is used to isolate the bus data signal, clock signal, bus control signal, and external feedback signal; the FlexRay bus isolation chip is implemented using the Si8420 chip of NXP Company.

[0036] In some embodiments, the FPGA master control chip includes an SPI data encapsulation module, an SPI frame driver module, an SPI data parsing module, a cache module, a clock control module, a FlexRay data encapsulation module, and a FlexRay frame driver module, wherein the FPGA system clock signal is provided by an external clock circuit, and the clock control module generates a bus reference clock signal inside the FPGA master control chip, and the cache module includes a data receiving cache module and a data sending cache module;

[0037] When SPI bus data is used as input and FlexRay bus data is used as output, the SPI bus isolation unit inputs the SPI bus data into the FPGA main control chip. The SPI bus data includes a data signal and a clock signal. The SPI data parsing module performs data parsing according to the standard protocol inside the FPGA main control chip, inputs the parallel data results into the cache module for storage, and then sequentially processes the data through the FlexRay data encapsulation module and the FlexRay frame driver module, and finally sends the data to the FlexRay communication unit.

[0038] When FlexRay bus data is used as input and SPI bus data is used as output, external FlexRay bus data enters the FlexRay bus transceiver through the logic output port of the FlexRay bus isolation unit, and the bus signal is input into the FPGA main control chip through the FlexRay bus communication controller. Inside the FPGA main control chip, the FlexRay frame driver module puts the data into the cache module for storage, and processes it in turn through the SPI data encapsulation module and the SPI frame driver module, and finally outputs it to the external interface through the logic port of the SPI bus isolation unit.

[0039] In some embodiments, the FPGA processing unit further includes a maintenance circuit, a reset circuit, and a clock circuit, and the maintenance circuit, reset circuit, and clock circuit are respectively connected to the FPGA main control chip.

[0040] In some embodiments, the maintenance circuit and the reset circuit may be connected to an external interface respectively.

[0041] In some embodiments, the FlexRay communication unit is connected to the FPGA processing unit via an asynchronous communication bus, a control line, and a status feedback signal.

[0042] In some embodiments, the FPGA processing unit has an internal integrated asynchronous high-speed cache hard core, which can set the cache area width and depth according to the actual bus data width and rate. The FPGA processing unit has an internal integrated clock management hard core, which can set the system clock and reference clock according to the SPI and FlexRay bus rates.

[0043] In some embodiments, the FPGA master chip is implemented using the Xilinx XC7S15-1CPGA196I chip. This chip has an internal FLASH memory for program storage. The internal modules of the FPGA are implemented using the Verilog language for logic coding.

[0044] In some embodiments, a power conversion unit is further included, and the power conversion unit is connected to the FPGA processing unit, the bus isolation unit and the FlexRay communication unit respectively, and is used to supply power to each component unit.

[0045] In this embodiment, the power conversion unit provides power to each internal functional unit and includes an isolation protection chip, a voltage regulator chip, a DC / DC chip, and an LDO chip. The isolation protection chip is implemented using the TPS26625 chip from TI; the voltage regulator chip is implemented using the BZV55C12 Zener diode from HY. The DC / DC chip uses the multi-channel output LTM4622 chip, generating 3.3V to power the MFR4310 and ADuM1201 chips, and 5V to power the TJA1080 and Si8420 chips. The LDO chip uses the TPS70345 chip, generating 3.3V to power only the FPGA chip.

[0046] In some embodiments, the internal power supply of the module is: FPGA main control chip is 3.3V, ADuM1201 chip (SPI bus isolation chip) is 3.3V, Si8420 chip (FlexRay bus isolation chip) is 5V, MFR4310 chip (FlexRay bus communication controller chip) is 3.3V, and TJA1080 chip (FlexRay bus transceiver chip) is 5V.

[0047] In the communication conversion module of the embodiment of the present invention, the address signal, data signal, reset signal, control signal, and interrupt feedback signal of the MFR4310 chip are connected to the peripheral GPIO port of the FPGA main control chip, and the control signal is controlled by the FPGA processing unit.

[0048] According to a specific embodiment, Figure 1 As shown, the FPGA-based SPI-FlexRay communication conversion module described in this embodiment includes an FPGA processing unit, a bus isolation unit, a FlexRay communication unit and a power conversion unit. The data input and output interface of the conversion module is one or more standard SPI or FlexRay bus interfaces.

[0049] In this embodiment, the programmable logic chip in the FPGA processing unit adopts Xilinx's XC7S15-1CPGA196I, the bus isolation unit adopts ADI's ADuM1201 magnetic isolation chip for SPI bus isolation, and the Si8420 chip for FlexRay bus isolation. The FlexRay bus controller in the FlexRay communication unit adopts NXP's MFR4310 chip, and the FlexRay bus transceiver adopts NXP's TJA1080 chip. The power conversion unit adopts TI's TPS26625 chip for isolation protection, HY's BZV55C12 voltage regulator diode is used for voltage regulation protection, and Linear's LTM4622 chip and TI's TPS70345 are used to complete power supply step-down conversion.

[0050] In this embodiment, the FPGA master control chip connects to the logic port of the bus isolation unit via its own peripheral GPIO port. This allows data processed by the SPI encapsulation module to be sent to external devices via the SPI interface, or SPI data from external devices is input into the FPGA chip's internal functional modules for parsing and conversion. The FlexRay communication unit communicates with the FPGA chip's peripheral GPIO port via the bus controller's address, data, reset, control, and interrupt feedback signals. The FlexRay bus controller connects to the bus transceiver via data and enable control signals.

[0051] The FPGA processing unit is used to handle interface interrupts, bus protocol conversion, and driver operations. It includes a programmable logic master chip, a maintenance circuit, a reset circuit, and a clock circuit. The maintenance circuit enables logic file loading and storage, as well as external signal testing. The reset circuit performs hardware initialization and external reset of the master chip. The clock circuit uses an external passive crystal oscillator to provide a normal clock signal for the master chip.

[0052] The FPGA processing unit uses multiple general GPIO ports on the periphery of the main control chip as one or more control signal interfaces, SPI data signal interfaces, FlexRay data signal interfaces and status feedback interfaces.

[0053] The bus isolation unit is used to isolate the external bus signal from the module's internal bus, and includes one or more isolation chips to achieve level isolation of control signals and data signals.

[0054] The FPGA-based SPI-FlexRay communication conversion module of this embodiment only includes a function block execution part in the FPGA chip, and other parts are directly implemented by hardware circuits.

[0055] In this embodiment, the function execution module in the FPGA chip is divided into three parts, including an initialization submodule, an event service submodule, and a clock management submodule. The initialization submodule includes an SPI communication initialization module and a FlexRay network configuration initialization module. The event service submodule includes an SPI data parsing module, an SPI data encapsulation module, an asynchronous buffer module (FIFO module), a FlexRay frame parsing module, and a FlexRay frame driver module. The clock management submodule implements clock management based on the IP core and provides a clock reference for the internal processing modules. The FIFO module is implemented based on the IP core and completes bus data caching.

[0056] The SPI communication initialization submodule and the FlexRay network configuration initialization submodule in the initialization submodule execute simultaneously. The SPI communication initialization submodule configures the SPI data packet frame length and operating mode. The FlexRay network configuration initialization module configures various characteristic parameters of FlexRay network communication.

[0057] The working modes include four modes in the SPI standard.

[0058] The relationship between the reference clock f1 used in the SPI data analysis module and the SPI bus clock f2 is: f1 = 8*f2.

[0059] The specific execution process of the event service submodule is as follows:

[0060] like Figure 2 As shown in the figure, when the module converts SPI bus data into FlexRay bus data, the external SPI device inputs the data to the FPGA processing unit through the logic port of the SPI bus isolation unit. After receiving the SPI data information, the FPGA enables the SPI data parsing module and calls it to complete the SPI data parsing. The parsed data is then placed into the asynchronous FIFO. Based on the external bus status feedback, the FlexRay data encapsulation module is called to package the FIFO data into FlexRay network data. Finally, the FlexRay driver module is called to complete the communication with the FlexRay communication unit through the GPIO port.

[0061] like Figure 3As shown, when the module converts FlexRay bus data into SPI bus data, the external FlexRay node device inputs the data into the FlexRay communication unit through the logic port of the FlexRay bus isolation unit. The FlexRay communication unit then sends the FlexRay data to the FPGA processing unit. The FlexRay frame driver module in the FPGA processing unit inputs the network data into the FIFO unit for buffering. The SPI data encapsulation module reads the FIFO data and encapsulates it into an SPI data packet according to the standard SPI protocol. When the SPI send flag and various status control bits are enabled, the SPI driver module outputs the SPI data packet through the GPIO port to the SPI bus isolation unit.

[0062] like Figure 4 As shown in the figure, the execution process of the SPI data encapsulation module inside the FPGA chip is as follows:

[0063] After completing the SPI communication initialization, the SPI encapsulation module enters the idle standby state - State 0. In this state, the source data collected by GPIO is latched and waits for the state machine to jump. When the bus polarity and phase state are consistent with the initialization configuration conditions, the SPI encapsulation module jumps to the frame-by-frame encapsulation state - State 1. In State 1, the parallel data taken out of the FIFO unit is encapsulated bit by bit into the SPI transmit register. When the bit width reaches the predefined length, the module jumps to the transmit enable state - State 2. In State 2, the SPI transmit flag and various status control bits are enabled, and the module enters the idle loop state - State 3 in the next cycle. In the idle loop state, the module does not execute any instructions and returns to State 0 again after 2 clock cycles.

[0064] like Figure 5 As shown, the FlexRay communication unit includes a FlexRay bus controller and a FlexRay bus transceiver.

[0065] like Figure 6 As shown, the power conversion unit is used to power all internal units of the module. It includes power isolation protection, voltage regulation protection, and power conversion circuitry. A multi-output DC / DC chip is used to power the bus isolation unit and FlexRay communication unit, and an LDO chip is used to independently power the FPGA main control chip. The input power is isolated and short-circuit protected. The SPI-FlexRay communication conversion module involves 3.3V and 5V voltages.

[0066] Compared with the existing invention, the beneficial effects of the present invention are as follows:

[0067] The present invention adopts standard SPI bus and FlexRay bus interfaces, which can be directly plugged into external SPI / FlexRay devices, solving the problem of inflexible development and testing in a single bus environment and expanding the application scenarios of the SPI bus and FlexRay bus. A bus isolation unit is used to achieve transmission isolation between internal module data and external data, ensuring stable and reliable bus data. Based on FPGA, data protocol conversion can be achieved. Flexible design and development can be carried out within the FPGA chip based on bus characteristics. FlexRay network data interaction is completed based on the bus controller and transceiver. The internal power supply design of the module is completed based on DC / DC and LDO chips, resulting in an FPGA-based SPI-FlexRay communication conversion module. The present invention does not require the use of other processors and is completely free from the potential impact of software problems. Through its unique design, the present invention can easily achieve seamless conversion between SPI bus data and FlexRay bus data, realizing the expansion of communication methods of each node device in the SPI bus network and the FlexRay bus network. Its principle is simple and clear, reducing costs while improving the efficiency and stability of data transmission, providing a more convenient and efficient data conversion solution.

[0068] Those skilled in the art will recognize that the embodiments of the present invention can be implemented in a variety of ways, whether as a module, method, system, or computer program product, all of which effectively reflect the innovation. Therefore, the implementation of the present invention is not limited to pure hardware, software, or a combination of hardware and software. Furthermore, the present invention can also take the form of a computer program product, which can be stored in a computer-accessible storage medium, such as a disk, ROM, memory, etc., and implement its functions through the executable code therein.

[0069] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An FPGA-based SPI-FlexRay communication conversion module, characterized in that: include: FPGA processing unit, bus isolation unit and FlexRay communication unit; The bus isolation unit is connected to the external interface and is respectively connected to the FPGA processing unit and the FlexRay communication unit, and the FPGA processing unit and the FlexRay communication unit are communicatively connected with each other; the bus isolation unit is used to complete buffering and isolation between high-speed data and the external interface, the FlexRay communication unit is used to complete FlexRay bus data reception and transmission and data flow control, and complete data conversion between external high-speed data and FPGA interface data; the FPGA processing unit is used to receive SPI bus data from the bus isolation unit or FlexRay bus data from the FlexRay communication unit, and perform data parsing and caching internally, use standard SPI and FlexRay protocols for data frame encapsulation, complete data conversion between the two high-speed buses SPI and FlexRay, so as to convert the SPI bus data from the bus isolation unit into FlexRay bus data and then output it to the FlexRay communication unit, or convert the FlexRay bus data from the FlexRay communication unit into SPI bus data and then output it to the bus isolation unit.

2. The FPGA-based SPI-FlexRay communication conversion module according to claim 1, characterized in that: It also includes a power conversion unit, which is connected to the FPGA processing unit, the bus isolation unit and the FlexRay communication unit respectively, and is used to supply power to each component unit.

3. The FPGA-based SPI-FlexRay communication conversion module according to claim 1, wherein: The FlexRay communication unit includes a FlexRay bus communication controller and a FlexRay bus transceiver, the FlexRay bus transceiver is connected to the bus isolation unit and the FlexRay bus communication controller respectively, the FPGA processing unit includes an FPGA main control chip, and the FlexRay bus communication controller is connected to the FPGA main control chip.

4. The FPGA-based SPI-FlexRay communication conversion module according to claim 3, characterized in that: The bus isolation unit includes an SPI bus isolation unit and a FlexRay bus isolation unit. The FPGA main control chip is connected to the SPI bus isolation unit to interact with the external interface through the SPI bus isolation unit. The FlexRay bus transceiver is connected to the FlexRay bus isolation unit to provide a path for FlexRay bus communication through the external interface.

5. The FPGA-based SPI-FlexRay communication conversion module according to claim 4, characterized in that: The FPGA master control chip includes an SPI data encapsulation module, an SPI frame driver module, an SPI data parsing module, a cache module, a clock control module, a FlexRay data encapsulation module, and a FlexRay frame driver module. The FPGA system clock signal is provided by an external clock circuit, and the clock control module generates a bus reference clock signal inside the FPGA master control chip. The cache module includes a data receiving cache module and a data sending cache module. When SPI bus data is used as input and FlexRay bus data is used as output, the SPI bus isolation unit inputs the SPI bus data into the FPGA main control chip. The SPI bus data includes a data signal and a clock signal. The SPI data parsing module performs data parsing according to the standard protocol inside the FPGA main control chip, inputs the parallel data results into the cache module for storage, and then sequentially processes the data through the FlexRay data encapsulation module and the FlexRay frame driver module, and finally sends the data to the FlexRay communication unit. When FlexRay bus data is used as input and SPI bus data is used as output, external FlexRay bus data enters the FlexRay bus transceiver through the logic output port of the FlexRay bus isolation unit, and the bus signal is input into the FPGA main control chip through the FlexRay bus communication controller. Inside the FPGA main control chip, the FlexRay frame driver module puts the data into the cache module for storage, and processes it in turn through the SPI data encapsulation module and the SPI frame driver module, and finally outputs it to the external interface through the logic port of the SPI bus isolation unit.

6. The FPGA-based SPI-FlexRay communication conversion module according to claim 5, characterized in that: The FPGA processing unit also includes a maintenance circuit, a reset circuit and a clock circuit, and the maintenance circuit, reset circuit and clock circuit are respectively connected to the FPGA main control chip.

7. The FPGA-based SPI-FlexRay communication conversion module according to claim 1, characterized in that: The FlexRay communication unit is connected to the FPGA processing unit via an asynchronous communication bus, a control line, and a state feedback signal.

8. The FPGA-based SPI-FlexRay communication conversion module according to claim 1, characterized in that: The FPGA processing unit integrates an asynchronous high-speed cache hard core to set the cache area width and depth according to the actual bus data width and rate. The FPGA processing unit integrates a clock management hard core to set the system clock and reference clock according to the SPI and FlexRay bus rates.

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