Method and device for simultaneous dynamic global reconstruction of DSP and FPGA, medium and program product

Abstract

The invention provides a DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) simultaneous dynamic global reconstruction method, equipment, a medium and a program product. The method comprises the following steps of: designing starting configuration of the DSP and the FPGA as well as a connection relation and a mapping relation of the DSP, the FPGA and FLASH by hardware; and in combination with a software logic process, simultaneous dynamic global reconstruction of the DSP and the FPGA is completed through cooperation of software and hardware. According to the method, the simultaneous dynamic global reconstruction of the DSP and the FPGA can be realized without modifying or adding any Bootloader starting file or flow or adding any hardware overhead in a mode of combining software and hardware, and compared with other dynamic reconstruction methods, the method is simple, stable and reliable.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a method, device, medium and program product for simultaneous dynamic global reconfiguration of DSP and FPGA. Background Art

[0002] In the electronic information industry, the main functions of equipment are mostly defined by software. Software solutions can support the storage, input / output, signal processing and data processing capabilities required for various functions of the equipment. When new tasks need to be completed or new functions need to be added, as long as the current hardware resources are sufficient to complete the task, then only new software components need to be installed; when resources are upgraded or new resources are added, there is no need to redesign the entire system or rewrite a large amount of software. Among them, the DSP+FPGA architecture is the most common digital signal processing architecture. Under this architecture, the more software functions there are, the higher the resource occupancy rate, the higher the operating power consumption of DSP and FPGA, and the chip resources are also limited, and the software functions that can be realized are also limited. Then, through software componentization, the method of dynamically loading and reconstructing when a certain function is needed can solve the resource problem well and reduce power consumption.

[0003] At present, more and more devices are tending to be integrated and miniaturized. The devices are getting smaller and smaller, but they have more and more functions. At this time, dynamic software reconstruction based on software radio is particularly important. There are many existing methods for dynamic software reconstruction. Most of them are implemented by increasing hardware resources or by modifying the official burning tool or Bootloader startup program, which is complicated and increases the cost. Summary of the invention

[0004] The present invention aims to provide a method, device, medium and program product for simultaneous dynamic global reconfiguration of DSP and FPGA to solve the above-mentioned problems.

[0005] In a first aspect, the present invention provides a method for simultaneous dynamic global reconfiguration of a DSP and an FPGA, comprising:

[0006] Hardware design: DSP and FPGA startup configuration, as well as the connection and mapping relationship between DSP, FPGA and FLASH;

[0007] Combined with the software logic flow, the dynamic global reconstruction of DSP and FPGA is completed simultaneously through the cooperation of software and hardware.

[0008] In some embodiments, in the software logic flow, the DSP controls the FPGA reconstruction through switching instruction judgment, and the FPGA controls the DSP reconstruction through high-order addresses and reset signals.

[0009] In some embodiments, the connection relationship between the DSP, FPGA and FLASH includes:

[0010] The DSP and FPGA are connected via the EMIF bus, and the FPGA and FLASH are connected via a parallel bus.

[0011] In some embodiments, the mapping relationship between the DSP, FPGA and FLASH includes:

[0012] There are multiple sectors in FLASH, and the high-order addresses corresponding to each sector map the functional software of DSP and FPGA.

[0013] In some embodiments, the startup configuration of the DSP is determined by the states of the EMIFB address lines BEA18 and BEA19 when they are powered on.

[0014] In some embodiments, the DSP is powered on in EMIFB 8-bit ROM boot mode.

[0015] In some embodiments, the startup configuration of the FPFA is a main BPI mode.

[0016] In a second aspect, the present invention further provides an electronic device, comprising:

[0017] at least one processor; and a memory communicatively coupled to the at least one processor;

[0018] The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the software logic flow in the above method by executing the instructions stored in the memory.

[0019] In a third aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store instructions, and when the instructions are executed, the software logic flow in the above method is implemented.

[0020] In a fourth aspect, the present invention further provides a computer program product, which, when called by a computer, enables the computer to execute the software logic flow in the above method.

[0021] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0022] 1. The present invention can realize simultaneous dynamic global reconstruction of DSP and FPGA by combining software and hardware, without modifying or adding any Bootloader startup file or process, and without increasing any hardware overhead. Compared with other dynamic reconstruction methods, the present invention is simple, stable and reliable.

[0023] 2. For the most common digital signal processing architecture (DSP+FPGA architecture), it can realize the integration of multiple functions without increasing any hardware overhead, dynamically reconstruct according to real-time functional requirements, reduce software real-time overhead, and also reduce chip heat consumption to a certain extent, which is of great significance in equipment miniaturization, multi-functional integration and low-power design. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of FPGA startup configuration in an embodiment of the present invention.

[0025] Figure 2 It is a schematic diagram of DSP startup configuration in an embodiment of the present invention.

[0026] Figure 3 Schematic diagram of the connection relationship among DSP, FPGA and FLASH in an embodiment of the present invention.

[0027] Figure 4 Schematic diagram of the mapping relationship when DSP accesses FLASH in an embodiment of the present invention.

[0028] Figure 5 It is a software logic diagram when the DSP and FPGA are reconstructed simultaneously in an embodiment of the present invention.

[0029] Figure 6 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The embodiment of the present invention provides a method for simultaneous dynamic global reconfiguration of DSP and FPGA, comprising:

[0033] Hardware design: DSP and FPGA startup configuration, as well as the connection relationship between DSP, FPGA and FLASH;

[0034] Combined with the software logic flow, the dynamic global reconstruction of DSP and FPGA is completed simultaneously through the cooperation of software and hardware.

[0035] Therefore, through the combination of software and hardware, there is no need to modify or add any Bootloader startup files or processes, nor to increase any hardware overhead, to achieve simultaneous dynamic global reconstruction of DSP and FPGA. Compared with other dynamic reconstruction methods, it is simple, stable and reliable.

[0036] A method for simultaneous dynamic global reconfiguration of DSP and FPGA provided by an embodiment of the present invention is described below based on DSP (model DSP6416), FPGA (model SMQ7K410T) and 1G parallel port FLASH (model SM29GL01G).

[0037] Figure 1 The FPFA startup configuration in the embodiment of the present invention is shown. Among them, MO_0, M1_0, and M2_0 are FPGA startup configuration pins. In this embodiment, the FPGA startup needs to be configured as the main BPI mode, so MO_0, M1_0, and M2_0 need to be configured to 0, 1, and 0 respectively.

[0038] Figure 2 The DSP startup configuration in the embodiment of the present invention is shown. The DSP startup configuration is determined by the state of the EMIFB address lines BEA18 and BEA19 when they are powered on. In this embodiment, the DSP needs to be powered on in the EMIFB 8-bit ROM boot mode, and BEA18 and BEA19 are connected to the FPGA, and the FPGA controls the power-on state of BEA18 and BEA19.

[0039] Figure 3 The connection relationship among DSP, FPGA and FLASH in a method for simultaneous dynamic global reconfiguration of DSP and FPGA provided by an embodiment of the present invention is shown. DSP and FPGA are connected via an EMIF bus, and FPGA and FLASH are connected via a parallel bus.

[0040] Figure 4 The mapping relationship among DSP, FPGA and FLASH in a method for simultaneous dynamic global reconfiguration of DSP and FPGA provided by an embodiment of the present invention is shown. There are multiple sectors in FLASH, and the high-order address corresponding to each sector maps the functional software of DSP and FPGA.

[0041] DSP controls FLASH through FPGA software wiring. The principle is as follows: when DSP needs to access FLASH, DSP directly operates EMIFB CE1 and EMIFB CE1 space, and at the same time writes the high 7-bit address control data corresponding to the FLASH sector to FPGA through EMIFB CE0 space and is controlled by FPGA.

[0042] Figure 5 The flowchart of the simultaneous dynamic global reconfiguration of DSP and FPGA in a method for simultaneous dynamic global reconfiguration of DSP and FPGA provided by an embodiment of the present invention is shown. In the software logic flow, DSP controls FPGA reconfiguration by switching instruction judgment, and FPGA controls DSP reconfiguration by high-order address and reset signal, which specifically includes the following steps:

[0043] Step S01: Since the FPGA hardware has been configured in the master BPIM mode, after power-on, the FPGA will address the FPGA program header from the corresponding FLASH, load the FPGA execution file, and run the FPGA function software 1;

[0044] Step S02: After the FPGA function software 1 is running, the external IO is initialized, the DSP is powered on and the configuration pin BEA[19:18] is set to 0x2, and the FLASH high 7-bit address A[26:20] is set to (Sn1AddrL>>20)&0x7F;

[0045] Step S03: FPGA function software 1 outputs a DSP reset signal to reset the DSP;

[0046] Step S04: After the DSP is reset, the EMIFB 8-bit ROM boot mode will be adopted according to the BEA[19:18] status. According to the value of the FLASH high 7-bit address A[26:20], the DSP will directly access and read the FLASH sector n+1 and run the DSP function software 1.

[0047] Step S05: After receiving the switching command, the DSP function software 1 makes a judgment. If it needs to switch to the function software 2, the DSP writes the switching instruction to the FPGA through EMIFB CE0;

[0048] Step S06: After receiving the switching command, the FPGA function software 1 sets the FPGA self-start address bus to the first address S2AddrL of the FLASH sector 2;

[0049] Step S07: FPGA function software 1 starts dynamic configuration, begins reconstruction, and loads FPGA execution file from FLASH sector 2;

[0050] Step S08: running FPGA function software 2;

[0051] Step S09: After the FPGA function software 2 is running, the external IO is initialized, the DSP is powered on and the configuration pin BEA[19:18] is set to 0x2, and the FLASH high 7-bit address A[26:20] is set to (Sn2AddrL>>20)&0x7F;

[0052] Step S10: FPGA function software 2 outputs a DSP reset signal to reset the DSP;

[0053] Step S11: After the DSP is reset, the EMIFB 8-bit ROM boot mode will be adopted according to the BEA[19:18] status. According to the value of the FLASH high 7-bit address A[26:20], the DSP will directly access and read the FLASH sector n+2 and run the DSP function software 2.

[0054] Step S12: If it is necessary to switch to the function software 3, the DSP writes the switching instruction to the FPGA through EMIFB CE0;

[0055] Step S13: After receiving the switching command, the FPGA function software 1 sets the FPGA self-start address bus to the first address S3AddrL of the FLASH sector 3;

[0056] Step S14: FPGA function software 1 starts dynamic configuration, begins reconstruction, and loads FPGA execution file from FLASH sector 3;

[0057] Step S15: running FPGA function software 3;

[0058] Step S16: After the FPGA function software 3 is running, the external IO is initialized, the DSP is powered on and the configuration pin BEA[19:18] is set to 0x2, and the FLASH high 7-bit address A[26:20] is set to (Sn3AddrL>>20)&0x7F;

[0059] Step S17: FPGA function software 3 outputs a DSP reset signal to reset the DSP;

[0060] Step S18: After the DSP is reset, it will adopt the EMIFB 8-bit ROM boot mode according to the BEA[19:18] status. According to the value of the FLASH high 7-bit address A[26:20], the DSP will directly access and read the FLASH sector n+3 and run the DSP function software 3.

[0061] Here we only demonstrate the simultaneous reconstruction and switching of FPGA function software 1 and DSP function software 1 to FPGA function software 2 and DSP function software 2 and FPGA function software 3 and DSP function software 3. Through the same principle operation, each function software can be switched to each other.

[0062] Based on the same technical concept, an embodiment of the present invention further provides an electronic device, which can implement the software logic flow in the DSP and FPGA simultaneous dynamic global reconfiguration method provided in the above embodiment of the present application. In one embodiment, the electronic device can be a server, or a terminal device or other electronic device. Figure 6 As shown, the electronic device may include:

[0063] At least one processor, and a memory connected to the at least one processor. The specific connection medium between the processor and the memory is not limited in the embodiment of the present invention. Figure 6 The example in this article is that the processor and memory are connected through a bus. Figure 6 The connections between other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus can be divided into address bus, data bus, control bus, etc. Figure 6 In the diagram, only one thick line is used, but this does not mean that there is only one bus or only one type of bus. Alternatively, a processor can also be called a controller, and there is no limitation on the name.

[0064] In an embodiment of the present invention, the memory stores instructions that can be executed by at least one processor. By executing the instructions stored in the memory, the at least one processor can execute the software logic flow in the method for simultaneous dynamic global reconfiguration of DSP and FPGA discussed above. The processor can implement Figure 6 The functions of each module in the device shown.

[0065] Among them, the processor is the control center of the device, which can use various interfaces and lines to connect the various parts of the entire control device, and monitor the device as a whole by running or executing instructions stored in the memory and calling data stored in the memory, various functions of the device and processing data.

[0066] In an optional design, the processor may include one or more processing units, and the processor may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor. In some embodiments, the processor and the memory may be implemented on the same chip, and in some embodiments, they may also be implemented separately on separate chips.

[0067] The processor may be a general-purpose processor, such as a CPU, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the software logic flow in the method for simultaneous dynamic global reconstruction of a DSP and an FPGA disclosed in the embodiments of the present invention may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0068] As a non-volatile computer-readable storage medium, the memory can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access Memory, RAM), static random access memory (Static Random Access Memory, SRAM), programmable read-only memory (Programmable Read Only Memory, PROM), read-only memory (Read Only Memory, ROM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic memory, disk, optical disk, etc. The memory is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiment of the present invention can also be a circuit or any other device that can realize a storage function, used to store program instructions and / or data.

[0069] By designing and programming the processor, the code corresponding to the software logic flow in the method for simultaneous dynamic global reconfiguration of a DSP and FPGA introduced in the above embodiment can be fixed into the chip, so that the chip can perform the steps of the software logic flow in the method for simultaneous dynamic global reconfiguration of a DSP and FPGA in the above embodiment when running. How to design and program the processor is a technology well known to those skilled in the art and will not be described in detail here.

[0070] Based on the same inventive concept, an embodiment of the present invention further provides a storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer executes the software logic flow in the method for simultaneous dynamic global reconstruction of a DSP and FPGA discussed above.

[0071] In some optional embodiments, the present application also provides various aspects of the software logic flow in a method for simultaneous dynamic global reconstruction of a DSP and FPGA, which can also be implemented in the form of a program product, which includes program code. When the program product is run on an apparatus, the program code is used to enable the control device to execute the steps of the software logic flow in a method for simultaneous dynamic global reconstruction of a DSP and FPGA according to various exemplary embodiments of the present application described above in this specification.

[0072] It should be noted that, although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of a unit described above can be further divided into multiple units to be embodied. In addition, although the operation of the method of the present application is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution.

[0073] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0074] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a server, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0075] Program code for performing the operations of the present application may be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0076] Where a remote computing device is involved, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for simultaneous dynamic global reconfiguration of DSP and FPGA, characterized in that: include: Hardware design: DSP and FPGA startup configuration, as well as the connection and mapping relationship between DSP, FPGA and FLASH; Combined with the software logic flow, the dynamic global reconstruction of DSP and FPGA is completed simultaneously through the cooperation of software and hardware.

2. The method for simultaneous dynamic global reconfiguration of DSP and FPGA according to claim 1, characterized in that: In the software logic flow, the DSP controls the FPGA reconstruction through switching instruction judgment, and the FPGA controls the DSP reconstruction through high-order addresses and reset signals.

3. The method for simultaneous dynamic global reconfiguration of DSP and FPGA according to claim 1, characterized in that: The connection relationship between the DSP, FPGA and FLASH includes: The DSP and FPGA are connected via the EMIF bus, and the FPGA and FLASH are connected via a parallel bus.

4. The method for simultaneous dynamic global reconfiguration of DSP and FPGA according to claim 3, characterized in that: The mapping relationship between the DSP, FPGA and FLASH includes: There are multiple sectors in FLASH, and the high-order addresses corresponding to each sector map the functional software of DSP and FPGA.

5. The method for simultaneous dynamic global reconfiguration of DSP and FPGA according to claim 1, characterized in that: The startup configuration of the DSP is determined by the states of the EMIFB address lines BEA18 and BEA19 when they are powered on.

6. The method for simultaneous dynamic global reconfiguration of DSP and FPGA according to claim 5, characterized in that: The DSP is powered on in EMIFB 8-bit ROM boot mode.

7. The method for simultaneous dynamic global reconfiguration of DSP and FPGA according to claim 1, characterized in that: The startup configuration of the FPFA is the main BPI mode.

8. An electronic device, characterized in that: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, and the at least one processor executes the software logic flow in the method as described in any one of claims 1 to 7 by executing the instructions stored in the memory.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store instructions, and when the instructions are executed, the software logic flow in any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that When the computer program product is called by a computer, the computer executes the software logic flow in the method according to any one of claims 1 to 7.

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