Parallel computing core caching method and device based on multi-compression scheme and medium

Abstract

The invention relates to the technical field of parallel computing core caching, and discloses a parallel computing core caching method and device based on a multi-compression scheme and a medium. The method comprises the following steps: receiving a high-concurrency memory access signal of a parallel computing core, performing adaptability arbitration according to internal capacity performance parameters of a cache, and determining a memory access request sequence; setting a plurality of data compression schemes, determining data characteristics of the memory access request by analyzing the memory access data, optimizing a compression effect according to the plurality of data compression schemes, and determining whether to perform data compression on the memory access data and the compression scheme adopted; compressed data is fully associated with a multi-path group association mechanism in the cache system, each path of cache group association module stores a compression result of a compression scheme, and the plurality of group association modules can perform data exchange, so that the data can be continuously updated along with the continuous refreshing of the data. And the most matched data compression scheme is continuously and dynamically used for the data characteristics, so that the utilization efficiency of the on-chip cache resources is improved.

Description

Technical Field

[0001] The present invention relates to the field of parallel computing core cache technology, and in particular to a parallel computing core cache based on a multi-compression scheme Background Art In modern high-performance computing scenarios, the application of parallel computing cores is becoming more and more extensive, and its requirements for data storage and processing capabilities are becoming increasingly stringent. The traditional parallel computing core cache architecture has gradually exposed many drawbacks when dealing with the large-scale, high-concurrency data reading and writing needs of parallel computing cores. From the perspective of concurrent processing mechanism, given the high concurrency characteristics of parallel computing cores, the cache architecture often needs to synchronously respond to memory read and write requests from multiple threads. However, most of the current parallel computing core cache architectures adopt a processing strategy that decomposes concurrent access into serial access. Although this solution has the advantage of being simple and fast in the implementation process, the negative effect it causes is that it significantly increases the memory access latency of the parallel computing core, which becomes a key performance bottleneck in computing tasks with extremely high performance requirements. In terms of on-chip resource allocation, due to the inherent limitations of on-chip resources, in the resource allocation process of parallel computing cores, computing resources often have a higher tendency to be allocated in priority than storage resources. In this case, how to maximize the storage efficiency of the parallel computing core architecture under the constraints of limited on-chip storage resources has also become a key problem that needs to be overcome.

[0002] At present, cache compression technology is widely studied as an effective means to improve cache performance. However, existing cache compression technologies usually use a single compression scheme to process the entire cache, which cannot fully utilize the characteristics of different data, resulting in limited compression effect and performance improvement. For example, different application data has different characteristics. Some data is suitable for a certain compression method, while other data may be more suitable for other compression methods. Therefore, it is necessary to develop a parallel computing core cache system implementation based on multiple compression schemes to improve the adaptability and overall performance of the parallel computing core cache.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] In view of the defects of the prior art, the present invention provides a parallel computing core caching method, device and medium based on a multi-compression scheme, which is used to solve the problems that the existing parallel computing core caching scheme is difficult to handle high-concurrency memory access requests and has low on-chip storage resource utilization.

[0006] In some embodiments, the parallel computing core caching method based on multiple compression schemes includes: Step A, receiving n-way concurrent memory access requests from the parallel computing core; Step B: performing adaptability arbitration according to the internal capacity performance parameters of the cache to determine the memory access request sequence; First, according to the depth and bit width of the internal storage unit of the read cache, the word_sel size in the memory access request is determined according to the bit width of the internal storage unit of the cache, the index size in the memory access request is determined according to the depth of the internal storage unit of the cache, and the tag size in the memory access request is determined according to the bit width of the processor; then, the index data in the n-way memory access request sent to the cache by the parallel computing core is read, and the n-way memory access requests are grouped and merged according to the index data. The grouping and merging method is to merge the memory access requests with the same index into one group, and the indexes between groups are arranged in sequence, and m groups of n-way concurrent memory access requests are formed through grouping and merging; m and n are both positive integers, and m≤n; Step C, execute the memory access request adapted to the multi-cache data compression scheme, the m groups of n-way concurrent memory access requests formed in step B are sent to the cache, the cache adopts a multi-way group associative cache construction mechanism, each cache group associative module stores a data compression scheme, and determines whether the memory access request is hit or missed by label comparison. If the request is hit, the request hit execution mechanism is triggered, and if the request is missed, the request miss execution mechanism is triggered; during the execution of the request hit execution mechanism and the request miss execution mechanism, if it is data reading, the data compression method stored in the request hit cache group associative module is executed, and if it is data updating, the compression algorithm is selected according to the input data characteristics, data compression is executed, and the storage group associative module is associated.

[0007] As a further improvement, in step B, the sizes of word_sel, index, and tag are determined as follows: , in , , Respectively represent the size of word_sel, index, tag, Width, Depth and SIZE core They represent the cache internal storage unit bit width, cache internal storage unit depth and processor bit width respectively.

[0008] As a further improvement, when step B performs grouping, if the total number of memory access requests with the same index does not reach n, an invalid signal is filled in so that each group of memory access requests reaches n. The m groups of n-way concurrent memory access requests formed by grouping all include a TAG signal bit, an Index signal bit, a WORD_SEL signal bit and an identification bit. The TAG signal bit and the WORD_SEL signal bit are directly filled with the TAG signal and the WORD_SEL signal in the n-way concurrent memory access request sent by the parallel computing core. The Index signal bit is filled with the Index signal after grouping. The memory access request of the Index signal after grouping is stored, and the identification position is valid. The memory access request filled with the invalid signal has an identification position that is invalid.

[0009] As a further improvement, in step C, the request hit includes a read data request hit, and the request miss includes a read data request miss; When a read data request is missing, the request missing execution mechanism is as follows: if one or more read data requests do not hit in the valid signals of the n-way memory access requests sent, the read data request missing execution mechanism is triggered, and the missed memory access requests are extracted line by line from the n-way memory access requests executed concurrently and sent to the next-level cache; after receiving the request signal from the cache at this level, the cache at the next level performs a memory access request hit judgment. If the request of the next-level cache hits, a response signal is fed back to the cache at this level. The response signal includes a response address signal and a response data signal. The response data signal first enters the compression and decompression algorithm way judgment module to perform input data feature analysis, and completes compression algorithm selection, data compression execution, and group associative module selection according to the input data features. Then, the response address signal is split into tag, index, and word_sel signals. The corresponding cache line in the group associative module is determined according to the index signal, and the compressed response data is written into the cache line corresponding to the group associative module corresponding to the cache data, and the split tag data is written into the cache line corresponding to the group associative module corresponding to the cache tag; When a read data request hits, the request hit execution mechanism is: if there is one or more read data request hits in the valid signals of the n-way memory access request sent, the read data request hit execution mechanism is triggered, and the response data is obtained from the cache line corresponding to the group associative module of the cache data according to the hit group associative module and index data, and the obtained response data and the group associative module are sent to the compression and decompression algorithm way judgment module for processing. The compression and decompression algorithm way judgment module determines the data compression algorithm to be executed according to the received group associative module, and then completes the reverse decompression operation of the data according to the data compression algorithm, and feeds the decompressed data back to the parallel computing core module.

[0010] As a further improvement, the request hit includes a write data request hit, and the request miss includes a write data request miss; When a write data request hits, the request hit execution mechanism is as follows: if one or more write data request hits exist in the valid signals of the n-way memory access request sent, the write data request hit execution mechanism is triggered, and storage data is obtained from the cache line corresponding to the group associative module corresponding to the cache address according to the hit group associative module and index data, and the storage data is sent to the compression and decompression algorithm way judgment module for decompression processing to obtain decompressed storage data, and then the decompressed storage data is combined with the write data sent by the parallel computing core to obtain complete write data, and the complete write data is resent to the compression and decompression algorithm way judgment module for data feature The compression and decompression algorithm way judgment module re-judges the data compression scheme according to the characteristics of the complete written data. If the judgment result is the original data compression scheme, the compression and decompression algorithm way judgment module completes the compression of the complete written data and continues to store the compressed data in the index cache line corresponding to the original group associative module; if the judgment result is a new data compression scheme, the compression and decompression algorithm way judgment module completes the data compression according to the new data compression scheme and writes the compressed data into the index cache line corresponding to the new group associative module, and invalidates the data of the index cache line corresponding to the original group associative module on the other hand; When a write data request is missing, the request missing execution mechanism is: if there is a valid signal in the n-way memory access request sent and one or more write data requests are not hit, the write data request missing execution mechanism is triggered. This mechanism does not trigger the data cache action in the current level cache and the compression and decompression algorithm way judgment module action, but directly extracts the missed memory access requests line by line from the concurrently executed n-way memory access requests and sends them to the next level cache.

[0011] As a further improvement, four compression schemes are stored in the compression and decompression algorithm way judgment module as the default data compression scheme. When input data enters, the compression and decompression algorithm way judgment module first performs the default data compression scheme matching work, and selects the corresponding compression scheme according to the data characteristics and compression scheme priority. Each data compression scheme is configured with a group associative storage module associated with it. If a certain data compression algorithm is matched, the compressed data will be stored in the corresponding group associative storage module.

[0012] As a further improvement, the four compression schemes stored in the way judgment module of the compression and decompression algorithm are: BDI(2,0), BDI(4,0), BDI(4,2) in the BDI compression algorithm and DIC(8) in the DIC compression algorithm. The default data compression scheme based on these four compression schemes matches the following workflow: slice the entire cache line data by 2 bytes to form (k+1)*2 bytes of distributed data. The first data 0 is used as the reference data, and the following k data are subtracted from the reference data to obtain the difference data 1 to k. Compare whether the difference data 1 to k are all 0. If they are all 0, it meets BDI(2,0). Compression algorithm rules, store 2-byte reference data 0 in group associative storage module 0, if the difference data is not all 0, re-slice the data; the re-sliced ​​data is based on 4 bytes, and also forms (k / 2+1)*4 bytes of distributed data, and also uses the first data 0 as the reference data, and the following k / 2 data are subtracted from the reference data to obtain difference data 1 to k / 2, and compare whether the difference data 1 to k / 2 are all 0. If they are all 0, it meets the BDI (4,0) compression algorithm rules, and store the 4-byte reference data 0 in group associative storage module 1; if the difference is not all 0 but the difference bit width is within 2 bytes, it meets According to the BDI (4, 2) compression algorithm rules, the 4-byte reference data 0 and the k-byte difference data are stored in the group associative storage module 2; if the difference bit width is greater than 2 bytes, it does not meet the BDI compression algorithm rules, and the DIC compression algorithm is judged. The judgment process is: slice the data according to 4 bytes to form (k / 2+1)*4 bytes of distributed data, and store the distributed data [0, k / 2] in the data storage dictionary in sequence. The data storage dictionary is composed of content-addressable memory. The storage of the same data will only feedback one dictionary index. While the dictionary index is continuously generated, the dictionary depth judgment is performed. When the dictionary index of all distributed data is After all the indexes are generated and the depth does not exceed the dictionary depth, it indicates that the repetition rate of the distributed data is good, and the DIC data compression algorithm is adapted, and the dictionary index is stored as data in the group associative storage module 3. If the depth of the dictionary index generated by the distributed data exceeds the dictionary depth, it indicates that the repetition rate of the distributed data is poor, and the DIC data compression algorithm cannot be used. When the adaptation work results of the BDI compression algorithm and the adaptation work results of the DIC compression algorithm are both consistent, the BDI compression algorithm is used to compress the data; when the adaptation work results of the BDI compression algorithm are inconsistent and the adaptation work results of the DIC compression algorithm are consistent, the DIC compression algorithm is used to compress the data.

[0013] As a further improvement, the compression and decompression algorithm way judgment module reserves an extensible compression scheme interface. When the results of the default data compression scheme adaptation work are all incompatible, the extensible data compression scheme adaptation work is started. If there is no extensible data compression scheme or the results of the extensible data compression scheme adaptation work are also incompatible, the data will not be compressed. The reserved extensible data compression scheme also has a corresponding group associative storage module associated with it. When there is no extensible data compression scheme, the data stored in the corresponding group associative storage module stores uncompressed cache data.

[0014] In some embodiments, the device includes a processor and a memory storing program instructions, and the processor is configured to execute the aforementioned parallel computing core caching method based on multiple compression schemes when running the program instructions.

[0015] In some embodiments, the storage medium stores program instructions, and when the program instructions are run, they execute the aforementioned parallel computing core caching method based on multiple compression schemes.

[0016] The parallel computing core cache method, device and medium based on multiple compression schemes provided in the embodiments of the present disclosure can achieve the following technical effects: The scheme of the present invention addresses the problems that traditional parallel computing core cache schemes are difficult to handle high-concurrency memory access requests and low on-chip storage resource utilization, and proposes a parallel computing core cache system and method based on multiple compression schemes. First, the upper layer interface of the present invention fully accommodates the high-concurrency memory access signals of the parallel computing core, and implements adaptive arbitration according to the internal capacity performance parameters of the parallel computing core cache to determine the memory access request sequence; secondly, the present invention fully accommodates a variety of data compression schemes, determines the characteristics of the memory access request data by receiving and analyzing the memory access data in the memory access request sequence, and optimizes the compression effect according to the accommodated multiple data compression schemes, determines whether to compress the memory access data and the compression scheme to be used when compressing the data; finally, the present invention fully associates the data compressed by multiple compression schemes with the multi-way group associative mechanism in the classic cache system, each cache group associative module stores the compression result of a compression scheme, and multiple group associative modules can fully exchange data, thereby ensuring that the cache system scheme of the present invention can dynamically use the most suitable data compression scheme according to the data characteristics as the data is continuously refreshed, so as to improve the utilization efficiency of on-chip cache resources.

[0017] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein: Figure 1 This is a schematic diagram of the overall architecture of the parallel computing core cache system; Figure 2 This is a flow chart of the method described in Example 1; Figure 3 A flowchart of the adaptive arbitration strategy for memory access requests; Figure 4 A flow chart of the memory access request execution mechanism for adapting the multi-cache data compression scheme; Figure 5 This is a schematic diagram of the internal architecture of the compression and decompression algorithm way judgment module; Figure 6 Adapt the compression process diagram for the BDI data compression algorithm; Figure 7 Schematic diagram of compression process for DIC data compression algorithm adaptation; Figure 8 This is a functional block diagram of the device described in Example 2. DETAILED DESCRIPTION

[0019] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0020] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0021] Unless otherwise stated, the term "plurality" means two or more.

[0022] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0023] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0024] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0025] Example 1 This embodiment discloses a parallel computing core cache method based on a multi-compression scheme. The overall architecture of the parallel computing core cache system is as follows: Figure 1 As shown, the parallel computing core is the computing upper layer of the cache architecture of the solution of the present invention, and is responsible for completing specific computing and storage instructions. In order to ensure the upward compatibility of the solution of the present invention with the original parallel computing core, the present invention does not change the external interface of the original parallel computing core, and fully accepts high-concurrency memory access requests from the parallel computing core.

[0026] The cache architecture of the solution of the present invention adopts Harvard storage architecture as a whole. The L1 cache is divided into instruction cache and data cache. The instruction cache is specifically used to process instruction data, and the overall cache structure is read-only and not write-only. The data cache is specifically used to process computing data, and the overall cache structure is readable and writable. There is no direct path between the instruction cache and the data cache, but data is exchanged through the L2 cache. At the same time, in order to further improve the performance of multiple computing cores in the parallel computing core and make full use of the temporal locality and spatial locality characteristics of cached data, the cache structure of the present invention allocates private instruction cache and data cache to each parallel computing core. The private L1 cache of multiple computing cores cannot directly exchange data, and can only transfer data exchange through the L2 cache.

[0027] The cache architecture of the present invention adopts a write-through non-memory allocation cache mechanism as a whole. The memory access process is specifically explained by taking parallel computing core 1 as an example: First, when the program starts running, parallel computing core 1 sends an instruction fetch signal to the private instruction cache according to the program PC. Since the instruction cache is empty at this time, a cache miss occurs in the private instruction cache of parallel computing core 1, so the private instruction cache sends an instruction fetch signal to the L2 cache. The L2 cache receives the instruction fetch signal sent from computing core 1 and performs data memory access. Assuming that the data is stored in the L2 cache, the L2 cache sends a data response signal to the private instruction cache of computing core 1. After receiving the data response sent by L2, the private cache of computing core 1 stores it in its own cache line and sends a data response signal to computing core 1, which is the instruction information requested by the computing core earliest. After receiving the instruction information, computing core 1 enters the decoding-execution logic. Assuming that the instruction is also a memory access instruction and is used to read data from a certain address, computing core 1 sends a data request to the private data cache, and the overall execution process is consistent with the private instruction cache reading data; assuming that the instruction is a memory access instruction and is used to write data to a certain address, computing core 1 sends a write data request to the private data cache. After the private data cache corresponding to computing core 1 receives the data write request, it completes the cache hit judgment internally: if the cache hits, the data is written to the private data cache corresponding to computing core 1, and a write data request is sent to the L2 cache simultaneously. If the cache misses, only a write data request is sent to the L2 cache.

[0028] In order to improve the portability of the project, the scheme of the present invention integrates multiple data compression schemes synchronously in the private L1 cache and L2 cache of each parallel computing core. The overall computing unit and storage transmission bus of the parallel computing core are not changed, but data compression and cache performance improvement are achieved by changing the internal components of the cache.

[0029] Combination Figure 2 As shown, the embodiment of the present disclosure provides a parallel computing core cache method based on a multi-compression scheme, including: Step A, receiving n-way concurrent memory access requests from the parallel computing core; Step B: performing adaptability arbitration according to the internal capacity performance parameters of the cache to determine the memory access request sequence; Step C: executing a memory access request adapted to the multi-cache data compression scheme.

[0030] Step B performs adaptability arbitration based on the cache internal capacity performance parameters to determine the memory access request sequence mechanism such as Figure 3As shown: First read the depth and width of the internal storage unit of the cache, determine the word_sel size in the memory access request according to the storage width, determine the index size in the memory access request according to the storage depth, and determine the tag size in the memory access request according to the processor width. The specific formula is as follows, where Width, Depth and SIZE core Respectively represent cache width, cache depth and processor width: , in , , Respectively represent the sizes of word_sel, index, and tag.

[0031] Subsequently, the parallel computing core sends n-way memory access requests to the cache, reads the index data according to the calibrated index position, and groups and merges the n-way memory access requests sent by the parallel computing core according to the index data. The specific grouping and merging scheme is to merge the memory access requests with the same index into one group, and arrange the indexes in order between groups. If the total number of memory access requests with the same index does not reach n-way, then fill in invalid signals to make each group of memory access requests reach n-way. The m groups of n-way concurrent memory access requests formed by grouping all include TAG signal bits, Index signal bits, WORD_SEL signal bits and identification bits. The TAG signal bits and WORD_SEL signal bits directly fill in the TAG signals and WORD_SEL signals in the n-way concurrent memory access requests sent by the parallel computing core, and the Index signal bits fill in the Index signal after grouping. At the same time, in order to ensure the stability of the internal communication bit width of the cache, a 1-bit identification bit is added to the memory access signal within the group to indicate whether the memory access signal is valid, and the number of concurrent memory access paths within the group remains unchanged. For the memory access request of the Index signal after the storage grouping, the mark position is valid, and the memory access request filled with the invalid signal, the mark position is invalid.

[0032] The specific implementation process is as follows Figure 3 In the example shown, the parallel computing core sends n-way memory access request signals to the cache ( Figure 3In the example, Addr 0 to Addr n are used to represent the cache. The cache internal adaptive arbitration mechanism first slices the data of the n-way memory access request according to the cache capacity parameter, and divides it into n-way TAG signals, n-way index signals, and n-way word_sel signals. Then, the values ​​of the n-way index signals are compared, and the index values ​​are arranged in order into addr_C0 to addr_Cm, a total of m memory access requests. Each memory access request contains n-way concurrent signals, of which the tag signal and word_sel signal completely fill the tag and word_sel signals sent by the parallel computing core. The index signal uniformly uses the sorted index signal, and the identification signal is used to indicate that only the paths with the same index among the n-way concurrent signals are valid. By grouping and merging, m groups of n-way concurrent memory access requests are formed ( Figure 3 denoted by Addr_C0 to Addr_Cn in the diagram).

[0033] After the above adaptive arbitration mechanism completes its work, m times n-way concurrent memory access requests will be sent to the specific data unit inside the cache in sequence to complete the data read and write operations, such as Figure 4 shown.

[0034] First, the cache data module reads the cache_tag data of the group-associative quantity from the multi-way group-associated cache tag storage at the same time according to the common access index of the n-way access request sent. That is, Figure 4cache_tag0-cache_tagc in the memory. Then compare the TAG data with valid identification bits in the n-way memory access request sent and the cache_tag0-cache_tagc data obtained by memory access to see if they match (tag comparison), and assign the n-bit wide cache hit register corresponding to each group associative module. Specifically, if there is a valid identification bit in a certain group associativity and TAG=cache_tag, then the identification bit in the n-bit wide cache hit register corresponding to the group associativity is pulled high. In this way, the memory access hit / miss situation of the valid signal in the n-way memory access request sent and the group associative position of the cache hit can be obtained. At the same time, since the cache request is divided into read data request and write data request, the overall cache hit situation is divided into four types: read data request hit, read data request miss, write data request hit, and write data request miss. Among them, a read data request hit belongs to data reading, a read data request miss and a write data request hit belong to data updating. When a read data request hits, the input is the address. After judging that a certain cache group-associative module is hit according to the address, the corresponding data decompression scheme stored therein can be executed. When a read data request is missed, the core inputs the address. After there is no data in the cache at this level, a request is sent to the cache at the next level. The cache at the next level responds to the request and gives data. This data needs to be updated to the cache at this level, so the corresponding compression algorithm needs to be selected according to the response data characteristics given by the cache at the next level, and stored in the corresponding group-associative module; when a write data hits, the input is the address and data. The corresponding compression algorithm needs to be selected first according to the hit group-associative module, the data in the cache is read out, and then combined with the write data, and the corresponding compression algorithm is further selected according to the characteristics of the combined data, and stored in the corresponding group-associative module.

[0035] The specific implementation process is described in detail below: (1) Read data request missing execution mechanism: If one or more read data requests do not hit the valid signal in the n-way memory access request sent, the read data request missing execution mechanism is triggered, and the missed memory access requests are extracted line by line from the n-way memory access requests executed concurrently, and stored in the MEM_READ_QUEUE (storage read queue) in sequence, and finally the memory access requests are sent to the next level cache in sequence. After receiving the request signal from the cache at this level, the next level cache will also perform a memory access request hit judgment. Assuming that the request of the next level cache hits, a response signal will be fed back to the cache at this level. In the present invention, the response signal fed back by the lower-level cache is divided into a response address signal and a response data signal. The response data signal will first enter the compression and decompression algorithm way judgment module for judgment. This module is a unique module in the scheme of the present invention, which is responsible for completing the functions of selecting the compression algorithm according to the input data characteristics, executing data compression, and determining the data storage group associative module according to the selected compression algorithm. After the compression and decompression algorithm way judgment module completes the data compression and group associative module selection according to the input response data signal, the read data request missing execution mechanism will also complete the splitting of the response address signal. This module reuses the adaptive arbitration mechanism in the cache module according to the internal capacity performance parameters of the cache, and splits the response address signal into tag, index and word_sel signals according to the same formula. Then the cache module will determine the group associative module according to the obtained group associative selection result, determine the corresponding cache line in the group associative module according to the index, and write the compressed response data into the corresponding cache line of the group associative module corresponding to the cache data (cache_data), and write the split tag data into the corresponding cache line of the group associative module corresponding to the cache tag (cache_tag). At the same time, in order to ensure that the parallel computing core obtains the response data with the lowest possible latency, the response signal fed back by the lower-level cache will be directly fed back to the parallel computing core while compressing and storing the data.

[0036] (2) Read data request hit execution mechanism: If one or more read data request hits exist in the valid signals of the n memory access requests sent, the read data request hit execution mechanism is triggered, and the response data is obtained from the cache line corresponding to the group associative module of the cache data (cache_data) according to the hit group associative module and the cut index data, and the obtained response data and the group associative module are sent to the compression and decompression algorithm way judgment module for processing. Since each group associative module of the cache data (cache_data) stores data after data compression, the compression and decompression algorithm way judgment module is responsible for completing the data decompression operation in the read data request hit execution mechanism. Specifically, the compression and decompression algorithm way judgment module is responsible for completing the data compression algorithm determined to be executed according to the received group associative module, and then completing the reverse decompression operation of the data according to the data compression algorithm, and feeding the decompressed data back to the parallel computing core module.

[0037] (3) Write data request hit execution mechanism: If one or more write data requests are hit in the valid signals of the n memory access requests sent, the write data request hit execution mechanism is triggered, and the storage data is obtained from the cache line corresponding to the group associative module corresponding to the cache data (cache_data) according to the hit group associative module and the cut index data, and the storage data is sent to the compression and decompression algorithm way judgment module for decompression processing to obtain decompressed storage data. Subsequently, the decompressed storage data is combined with the write data sent by the parallel computing core to obtain the complete write data, and the complete write data is resent to the compression and decompression algorithm way judgment module for data judgment. Since the complete write data is replaced with the original compressed storage data, the original data compression scheme may not be adapted to the characteristics of the replaced data, and the compression and decompression algorithm way judgment module needs to re-judge the data compression scheme. If the judgment result is the original data compression scheme, the compression and decompression algorithm way judgment module will continue to store the compressed data in the index cache row corresponding to the original group associative module after completing the compression of the changed data; if the judgment result is a new data compression scheme, the compression and decompression algorithm way judgment module will complete the data compression according to the new data compression scheme on the one hand, and write the compressed data into the index cache row corresponding to the new group associative module, and on the other hand, it needs to invalidate the index cache row data corresponding to the original group associative module.

[0038] (4) Write data request missing execution mechanism: If one or more write data requests do not hit the valid signal in the n-way memory access request sent, the write data request missing execution mechanism is triggered. This mechanism does not trigger the cache data (cache_data) and compression and decompression algorithm way judgment module action in the cache at this level, but directly extracts the missed memory access requests from the concurrently executed n-way memory access requests line by line, and stores them in MEM_WRITE_QUEUE (storage write queue) in sequence, and finally sends the memory access requests to the next level cache in sequence. It is worth noting that due to the port width limit of sending data requests from the cache at this level to the next level cache, if both MEM_WRITE_QUEUE and MEM_REQ_QUEUE have data requests waiting to be transmitted, the requests in the MEM_READ_QUEUE queue will be transmitted first.

[0039] The compression and decompression algorithm way judgment module is a unique module of the solution of the present invention, which is mainly responsible for completing the functions of selecting the compression algorithm according to the characteristics of the input data, executing data compression, and associating the storage group association module. Figure 5 As shown, the scheme of the present invention selects four cases of two data compression schemes as the default compression schemes by statistically analyzing the data characteristics of existing parallel computing core applications and integrating the industry's leading cache data compression schemes. At the same time, sufficient extended compression scheme interfaces are reserved as reserved compression schemes. The overall implementation scheme is as follows: The scheme of the present invention first counts the compression effects and applicability probabilities of various data compression schemes, and finds that BDI(2,0), BDI(4,0), BDI(4,2) in the BDI compression algorithm and DIC(8) in the DIC compression algorithm have data compression applicability frequencies of 11.4%, 15.6%, 10.9% and 9.1% respectively in the parallel computing core multiple application program tests, which are much higher than other data compression algorithms. Therefore, they are set as the four default data compression schemes of the parallel computing core cache system and method based on multiple compression schemes of the scheme of the present invention.

[0040] When a cache line containing a large amount of data enters the compression and decompression algorithm way judgment module, the default data compression scheme will be matched first, and the BDI compression algorithm adaptation work has a higher priority than the DIC compression algorithm adaptation work. The BDI compression algorithm adaptation workflow is shown in the figure below: Figure 6As shown, firstly, the entire cache line data is sliced ​​into 2 bytes to form (k+1)*2 bytes of distributed data, and the first data 0 is used as the reference data. The following k data are subtracted from the reference data to obtain difference data 1 to k, and the difference data 1 to k are compared to see if they are all 0. If they are all 0, it complies with the BDI (2,0) compression algorithm rule, and only the 2-byte reference data 0 needs to be stored in the group associative storage module 0 to represent the entire data. Therefore, the 2-byte reference data 0 is stored in the group associative storage module 0. If the difference data is not all 0, the data is re-sliced; the re-sliced ​​data is based on 4 bytes, and the distributed data of (k / 2+1)*4 bytes is also formed. The first data 0 is also used as the reference data, and the following k / 2 data are subtracted from the reference data to obtain the difference data 1 to k / 2. The difference data 1 to k / 2 are compared to see if they are all 0. If they are all 0, it complies with the BDI (4,0) compression algorithm rule, and only the 4-byte reference data 0 needs to be stored in the group-associative storage module 1 to represent the entire data. Therefore, the 4-byte reference data 0 is stored in the group-associative storage module 1. If the difference is not all 0 but the difference bit width is within 2 bytes, it complies with the BDI (4,2) compression algorithm rule, and the 4-byte reference data 0 and the k-byte difference data are stored in the group-associative storage module 2. If the difference bit width is greater than 2 bytes, it does not comply with the BDI compression algorithm rule, and the DIC compression algorithm judgment is performed.

[0041] The DIC compression algorithm adaptation workflow is shown in the figure below: Figure 7 As shown, the data is sliced ​​according to 4 bytes to form (k / 2+1)*4 bytes of distributed data, and the distributed data [0, k / 2] is stored in the data storage dictionary in sequence. The data storage dictionary is composed of a content-addressable memory (CAM) to ensure that the storage of the same data will only feedback one dictionary index, thereby realizing the work of converting actual data into a dictionary index. While the dictionary index is continuously generated, the dictionary depth is judged. When the dictionary indexes of all distributed data are generated and the depth does not exceed the dictionary depth, it means that the repetition rate of the distributed data is good, and the DIC data compression algorithm is adapted. The dictionary index is stored as data in the group associative storage module 3. If the depth of the dictionary index generated by the distributed data exceeds the dictionary depth, it means that the repetition rate of the distributed data is poor and the DIC data compression algorithm cannot be used. In this embodiment, the dictionary depth is set to 2 bytes to achieve the best data compression effect.

[0042] When the adaptation results of the BDI compression algorithm and the DIC compression algorithm are both consistent, the BDI compression algorithm is used first to compress the data; when the adaptation results of the BDI compression algorithm are inconsistent and the DIC compression algorithm is consistent, the DIC compression algorithm is used to compress the data. When the adaptation results of the default data compression scheme are inconsistent, the scalable data compression scheme adaptation work is started. If there is no scalable data compression scheme or the adaptation results of the scalable data compression scheme are also inconsistent, the data will not be compressed.

[0043] The present invention configures a group associative storage module associated with each data compression scheme, and configures a group associative storage module for storing uncompressed data at the last level. If a certain data compression algorithm is suitable, the compressed data is stored in the corresponding group associative storage module. At the same time, the reserved scalable data compression scheme also has a corresponding group associative storage module associated with it. When there is no scalable data compression scheme, the data stored in the corresponding group associative storage module will be the same as the last level group associative storage module, storing uncompressed cache data.

[0044] Example 2 Combination Figure 8 As shown, an embodiment of the present disclosure provides a parallel computing core cache device 300 based on a multiple compression scheme, including a processor (processor) 304 and a memory (memory) 301. Optionally, the device may also include a communication interface (Communication Interface) 302 and a bus 303. Among them, the processor 304, the communication interface 302, and the memory 301 can communicate with each other through the bus 303. The communication interface 302 can be used for information transmission. The processor 304 can call the logic instructions in the memory 301 to execute the parallel computing core cache method based on the multiple compression scheme of the above embodiment.

[0045] In addition, the logic instructions in the memory 301 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0046] The memory 301 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes the function application and data processing by running the program instructions / modules stored in the memory 301, that is, the parallel computing core cache method based on the multi-compression scheme in the above embodiment is implemented.

[0047] The memory 301 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 301 may include a high-speed random access memory and may also include a non-volatile memory.

[0048] Example 3 An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned parallel computing core caching method based on multiple compression schemes.

[0049] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0050] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0051] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0052] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0053] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit.

Claims

1. A parallel computing core caching method based on multiple compression schemes, characterized in that: include: Step A, receiving n-way concurrent memory access requests from the parallel computing core; Step B: performing adaptability arbitration according to the internal capacity performance parameters of the cache to determine the memory access request sequence; First, according to the depth and bit width of the internal storage unit of the read cache, the word_sel size in the memory access request is determined according to the bit width of the internal storage unit of the cache, the index size in the memory access request is determined according to the depth of the internal storage unit of the cache, and the tag size in the memory access request is determined according to the bit width of the processor; Then read the index data in the n-way memory access request sent by the parallel computing core to the cache, and group and merge the n-way memory access requests according to the index data. The grouping and merging method is to merge the memory access requests with the same index into one group, and arrange the indexes in order between the groups. Through grouping and merging, m groups of n-way concurrent memory access requests are formed; m and n are both positive integers, and m≤n; Step C, execute the memory access request adapted to the multi-cache data compression scheme, the m groups of n-way concurrent memory access requests formed in step B are sent to the cache, the cache adopts a multi-way group associative cache construction mechanism, each cache group associative module stores a data compression scheme, and determines whether the memory access request is hit or missed by label comparison. If the request is hit, the request hit execution mechanism is triggered, and if the request is missed, the request miss execution mechanism is triggered; during the execution of the request hit execution mechanism and the request miss execution mechanism, if it is data reading, the data compression method stored in the request hit cache group associative module is executed, and if it is data updating, the compression algorithm is selected according to the input data characteristics, data compression is executed, and the storage group associative module is associated.

2. The parallel computing core cache method based on multiple compression schemes according to claim 1, characterized in that: In step B, the size of word_sel, index, and tag is determined as follows: ， in , , Respectively represent the size of word_sel, index, tag, Width, Depth and SIZE core They represent the cache internal storage unit width, cache internal storage unit depth, and processor width respectively.

3. The parallel computing core cache method based on multiple compression schemes according to claim 1, characterized in that: When performing grouping in step B, if the total number of memory access requests with the same index does not reach n-way, an invalid signal is filled in so that each group of memory access requests reaches n-way. The m groups of n-way concurrent memory access requests formed by grouping all include a TAG signal bit, an Index signal bit, a WORD_SEL signal bit and an identification bit. The TAG signal bit and the WORD_SEL signal bit are directly filled with the TAG signal and the WORD_SEL signal in the n-way concurrent memory access request sent by the parallel computing core. The Index signal bit is filled with the Index signal after grouping. The memory access request of the Index signal after grouping is stored, and the identification position is valid. The memory access request filled with the invalid signal has the identification position invalid.

4. The parallel computing core cache method based on multiple compression schemes according to claim 1, characterized in that: In step C, the request hit includes a read data request hit, and the request miss includes a read data request miss; When a read data request is missed, the request missing execution mechanism is as follows: if one or more read data requests do not hit the valid signal in the n-way memory access request sent, the read data request missing execution mechanism is triggered, and the missed memory access requests are extracted row by row from the concurrently executed n-way memory access requests and sent to the next level cache; After receiving the request signal from the cache at this level, the next level cache performs a memory access request hit judgment. If the next level cache request hits, a response signal is fed back to the cache at this level. The response signal includes a response address signal and a response data signal. The response data signal first enters the compression and decompression algorithm way judgment module to perform input data feature analysis, and completes compression algorithm selection, data compression execution, and group associative module selection based on the input data features. Then, the response address signal is split into tag, index, and word_sel signals. The corresponding cache line in the group associative module is determined based on the index signal, and the compressed response data is written into the cache line corresponding to the group associative module corresponding to the cache data, and the split tag data is written into the cache line corresponding to the group associative module corresponding to the cache tag. When a read data request hits, the request hit execution mechanism is: if there is one or more read data request hits in the valid signals of the n-way memory access request sent, the read data request hit execution mechanism is triggered, and the response data is obtained from the cache line corresponding to the group associative module of the cache data according to the hit group associative module and index data, and the obtained response data and the group associative module are sent to the compression and decompression algorithm way judgment module for processing. The compression and decompression algorithm way judgment module determines the data compression algorithm to be executed according to the received group associative module, and then completes the reverse decompression operation of the data according to the data compression algorithm, and feeds the decompressed data back to the parallel computing core module.

5. The parallel computing core cache method based on multiple compression schemes according to claim 1, characterized in that: A request hit includes a write data request hit, and a request miss includes a write data request miss; When a write data request hits, the request hit execution mechanism is as follows: if one or more write data request hits exist in the valid signals of the n-way memory access request sent, the write data request hit execution mechanism is triggered, and storage data is obtained from the cache line corresponding to the group associative module corresponding to the cache address according to the hit group associative module and index data, and the storage data is sent to the compression and decompression algorithm way judgment module for decompression processing to obtain decompressed storage data, and then the decompressed storage data is combined with the write data sent by the parallel computing core to obtain complete write data, and the complete write data is resent to the compression and decompression algorithm way judgment module for data feature The compression and decompression algorithm way judgment module re-judges the data compression scheme according to the characteristics of the complete written data. If the judgment result is the original data compression scheme, the compression and decompression algorithm way judgment module completes the compression of the complete written data and continues to store the compressed data in the index cache line corresponding to the original group associative module; if the judgment result is a new data compression scheme, the compression and decompression algorithm way judgment module completes the data compression according to the new data compression scheme and writes the compressed data into the index cache line corresponding to the new group associative module, and invalidates the data of the index cache line corresponding to the original group associative module on the other hand; When a write data request is missing, the request missing execution mechanism is: if there is a valid signal in the n-way memory access request sent and one or more write data requests are not hit, the write data request missing execution mechanism is triggered. This mechanism does not trigger the data cache action in the current level cache and the compression and decompression algorithm way judgment module action, but directly extracts the missed memory access requests line by line from the concurrently executed n-way memory access requests and sends them to the next level cache.

6. The parallel computing core cache method based on multiple compression schemes according to claim 4 or 5, characterized in that: The compression and decompression algorithm way judgment module stores four compression schemes as the default data compression scheme. When input data enters, the compression and decompression algorithm way judgment module first performs the default data compression scheme matching work, and selects the corresponding compression scheme according to the data characteristics and compression scheme priority. Each data compression scheme is configured with a group associative storage module associated with it. If a data compression algorithm matches, the compressed data will be stored in the corresponding group associative storage module.

7. The parallel computing core cache method based on multiple compression schemes according to claim 6 is characterized in that: The four compression schemes stored in the compression and decompression algorithm way judgment module are: BDI(2,0), BDI(4,0), BDI(4,2) in the BDI compression algorithm and DIC(8) in the DIC compression algorithm. The default data compression scheme based on these four compression schemes matches the following workflow: slice the entire cache line data by 2 bytes to form (k+1)*2 bytes of distributed data. The first data 0 is used as the reference data, and the following k data are subtracted from the reference data to obtain the difference data 1 to k. Compare whether the difference data 1 to k are all 0. If they are all 0, it complies with the BDI(2,0) compression algorithm rules. , store the 2-byte reference data 0 in the group associative storage module 0. If the difference data is not all 0, re-slice the data; the re-sliced ​​data is based on 4 bytes, and the distributed data of (k / 2+1)*4 bytes is also formed. The first data 0 is also used as the reference data. The following k / 2 data are subtracted from the reference data to obtain the difference data 1 to k / 2. Compare whether the difference data 1 to k / 2 are all 0. If they are all 0, it complies with the BDI (4,0) compression algorithm rules, and store the 4-byte reference data 0 in the group associative storage module 1; if the difference is not all 0 but the difference bit width is within 2 bytes, it complies with BDI (4,2) compression algorithm rules, the 4-byte reference data 0 and the k-byte difference data are stored in the group associative storage module 2; if the difference bit width is greater than 2 bytes, it does not meet the BDI compression algorithm rules, and the DIC compression algorithm is judged. The judgment process is: slice the data according to 4 bytes to form (k / 2+1)*4 bytes of distributed data, and store the distributed data [0,k / 2] in the data storage dictionary in sequence. The data storage dictionary is composed of content-addressable memory. The storage of the same data will only feedback one dictionary index. While the dictionary index is continuously generated, the dictionary depth judgment is performed. When the dictionary indexes of all distributed data are After the generation is completed and the depth does not exceed the dictionary depth, it means that the repetition rate of the distributed data is good, and the DIC data compression algorithm is adapted, and the dictionary index is stored as data in the group associative storage module 3. If the dictionary index depth generated by the distributed data exceeds the dictionary depth, it means that the repetition rate of the distributed data is poor, and the DIC data compression algorithm cannot be used. When the BDI compression algorithm adaptation work result and the DIC compression algorithm adaptation work result are both consistent, the BDI compression algorithm is used to compress the data; when the BDI compression algorithm adaptation work result is inconsistent and the DIC compression algorithm adaptation work result is consistent, the DIC compression algorithm is used to compress the data.

8. The parallel computing core cache method based on multiple compression schemes according to claim 7, characterized in that: The compression and decompression algorithm way judgment module reserves an extensible compression scheme interface. When the default data compression scheme adaptation work results are all incompatible, the extensible data compression scheme adaptation work is started. If there is no extensible data compression scheme or the extensible data compression scheme adaptation work results are also incompatible, the data will not be compressed. The reserved extensible data compression scheme also has a corresponding group associative storage module associated with it. When there is no extensible data compression scheme, the data stored in the corresponding group associative storage module stores uncompressed cache data.

9. A parallel computing core cache device based on multiple compression schemes, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the parallel computing core cache method based on multiple compression schemes as described in any one of claims 1 to 8 when running the program instructions.

10. A storage medium storing program instructions, characterized in that: When the program instructions are run, they execute the parallel computing core cache method based on multiple compression schemes as described in any one of claims 1 to 8.

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