Data processing method, data analysis method and data processing device
By implementing data acquisition and preprocessing in FPGA, the problem of low testing efficiency of FPGA in automatic testing equipment is solved, and a more efficient data processing and testing process is achieved.
Patent Information
- Application Number
- CN202411947975.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, when FPGA is used in automatic testing equipment to control data acquisition, the test efficiency is low, mainly due to frequent start-up and stop and data reading delay caused by multiple startup storage and data processing.
By implementing a data processing method in the FPGA, data acquisition is initiated using the trigger signal or the start signal, single-point data is collected during the acquisition period, and pre-processed in the FPGA, including statistical data statistics in the acquisition period, and pre-processing is stored for subsequent analysis.
This method improves testing efficiency, reduces the number of start and stops of FPGAs, avoids data reading delays, and completes data preprocessing within FPGAs, reduces dependence on the host computer software, and improves overall testing efficiency and data traceability.
Smart Images
Figure CN119884620A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of testing technology, and in particular to a data processing method, a data analysis method and a data processing device. Background Art
[0002] FPGA (Field Programmable Gate Array) has important applications in automatic test equipment (ATE). For example, FPGA can control data acquisition devices to collect data. The main function of data acquisition devices is to convert continuous analog signals into discrete digital signals. This process is very important for the analog quantity collection and analysis of analog devices. With the advancement of electronic technology, the devices under test are becoming more and more complex, and the number of test items involved is also increasing, which puts more stringent requirements on the test efficiency and performance of analog boards.
[0003] However, the related art requires the use of FPGA to control the data acquisition device to collect data in the test process, which has the problem of low efficiency during testing, limiting the further application of FPGA. Summary of the invention
[0004] The present invention provides a data processing method, a data analysis method and a data processing device to improve the test efficiency when using FPGA testing.
[0005] According to one aspect of the present invention, a data processing method is provided, the method being applied to an FPGA, the method comprising:
[0006] Initiate data collection according to a trigger signal or a start signal; wherein the method includes N trigger signals or N start signals, and each time control starts data collection until a stop condition is met, control the collection of single-point data; N is greater than 1;
[0007] Storing the single-point data collected during each collection period;
[0008] Preprocessing the single point data collected in each of the collection time periods to obtain preprocessed data corresponding to the single point data in each of the collection time periods, wherein the preprocessing at least includes collecting statistical information of the single point data collected in each of the collection time periods;
[0009] The pre-processed data is stored.
[0010] Optionally, storing the single-point data collected in each collection period includes:
[0011] Control and collect single-point data;
[0012] After a single point of data is collected each time, the single point of data is stored in sequence in the first storage space of the FPGA.
[0013] Optionally, the statistical information of the single-point data collected in each of the collection time periods includes at least: the number of single-point data collected in each of the collection time periods, the storage location pointer of the single-point data collected in each of the collection time periods, the maximum value of the single-point data collected in each of the collection time periods, the location corresponding to the maximum value, the minimum value of the single-point data collected in each of the collection time periods, the location corresponding to the minimum value and the measurement range information;
[0014] The preprocessing of the single point data collected in each collection period includes:
[0015] After completing the control acquisition of a single point of data each time, the single point of data is sequentially stored in the first storage space of the FPGA.
[0016] Update the number, maximum value, position corresponding to the maximum value, minimum value and position corresponding to the minimum value of the single point data in the statistical information according to the currently collected single point data;
[0017] Determine whether the first stop condition is met; if so, determine the preprocessed data; if not, return to execute the step of controlling the acquisition of single-point data; the first stop condition is that the number of the single-point data is a preset number.
[0018] Optionally, the preprocessed data further includes an average value of single-point data during the acquisition period;
[0019] After the first stop condition is met, the following steps are also included:
[0020] Determine the average value of the single-point data collected during the collection period corresponding to the current startup data collection.
[0021] Optionally, after determining the preprocessing data, the step further includes:
[0022] storing the preprocessed data in a second storage space;
[0023] Wherein, storing the preprocessed data in the second storage space at least includes:
[0024] Storing the number of the single point data and the storage location pointer in the first sub-storage space;
[0025] storing the average value and the measurement range information in a second sub-storage space;
[0026] storing the maximum value and the position corresponding to the maximum value in a third sub-storage space;
[0027] storing the minimum value and the position corresponding to the minimum value in a fourth sub-storage space;
[0028] The storage addresses in each sub-storage space are continuous.
[0029] Optionally, after completing the control acquisition of a single point of data each time, storing the single point of data in sequence in the first storage space of the FPGA further includes:
[0030] Determining whether the first storage space overflows, and if the first storage space overflows, outputting an alarm message and not starting data collection;
[0031] If the first storage space does not overflow, the step of updating the number, maximum value, position corresponding to the maximum value, minimum value and position corresponding to the minimum value of the single point data in the statistical information according to the currently collected single point data is performed.
[0032] Optionally, after storing the preprocessed data in the second storage space, the method further includes:
[0033] Determine whether the second storage space overflows. If the second storage space overflows, output an alarm message and do not start data collection. If the second storage space does not overflow, return to the step of starting data collection according to a trigger signal or a start signal.
[0034] Optionally, the controlling and collecting each single point of data each time before storing the single point of data in sequence in the first storage space of the FPGA further includes:
[0035] Determine whether a second stop condition is met; wherein the second stop condition is detection of a stop signal;
[0036] If the stop signal is detected, the step of determining the average value of the single-point data collected in the collection period corresponding to the start of data collection is executed; if the stop signal is not detected, the step of storing the single-point data in sequence in the first storage space of the FPGA is executed.
[0037] According to another aspect of the present invention, there is provided a data analysis method, comprising:
[0038] FPGA starts data acquisition according to the trigger signal or start signal;
[0039] The method includes N trigger signals or N start signals, and each time after controlling the start of data collection, the single point data is collected in the collection period until the stop condition is met; N is greater than 1; the single point data collected in each collection period is stored; the single point data collected in each collection period is preprocessed to obtain preprocessed data corresponding to the single point data in each collection period, wherein the preprocessing at least includes statistical information of the single point data collected in each collection period; and the preprocessed data is stored;
[0040] The data reading and analyzing device reads and analyzes the corresponding single-point data according to the preprocessed data.
[0041] According to another aspect of the present invention, there is provided a data processing device for executing the above-mentioned data processing method, the data processing device comprising:
[0042] A start control module, wherein the start control module is used to start data acquisition according to a trigger signal or a start signal;
[0043] A processing module, used for preprocessing the single point data collected in each of the collection time periods to obtain preprocessed data corresponding to the single point data in each of the collection time periods, wherein the preprocessing at least includes collecting statistical information of the single point data collected in each of the collection time periods;
[0044] A first storage space, used to store the single point data;
[0045] The second storage space is used to store the pre-processed data.
[0046] The technical solution of the embodiment of the present invention adopts a data processing method including controlling the start of data acquisition according to a trigger signal or a start signal; wherein the method includes N trigger signals or N start signals, and each time after controlling the start of data acquisition, the single point data is controlled to be collected in the acquisition period until the stop condition is met; N is greater than 1; the single point data collected in each acquisition period is stored; the single point data collected in each acquisition period is preprocessed to obtain the preprocessed data corresponding to the single point data in each acquisition period, wherein the preprocessing at least includes statistical information of the single point data collected in each acquisition period; and the preprocessing data is stored. After receiving the trigger signal or the start signal, the data acquisition is started, and the data output by the device under test under multiple test conditions can be collected in one test process, and there is no need to read out the data collected in the FPGA at the end of each acquisition period, thereby greatly improving the test efficiency. In addition, since the preprocessing of the data collected by multiple starts is completed in the FPGA, there is no need to process the collected data after reading it out, thereby further improving the test efficiency. In addition, the single point data and preprocessed data collected by multiple starts are stored, and the preprocessed data and the single point data are corresponded to ensure the accuracy of the data, and the data is traceable.
[0047] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0049] Figure 1 A flowchart of a data processing method provided by an embodiment of the present invention;
[0050] Figure 2 A flowchart of another data processing method provided by an embodiment of the present invention;
[0051] Figure 3 A flow chart of a data analysis method provided by an embodiment of the present invention;
[0052] Figure 4 A schematic diagram of a single-point data storage process provided by an embodiment of the present invention;
[0053] Figure 5 A schematic diagram of a second storage space storing pre-processed data provided by an embodiment of the present invention;
[0054] Figure 6 A schematic diagram of the structure of a data processing device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0057] In the related art, the test process of using FPGA to control the data acquisition device to collect data has the problem of low test efficiency. After a lot of research, the inventor found that the reason for this technical problem is that in some test scenarios, FPGA needs to have the ability to start storage multiple times to cope with more and more analog measurement tasks. For the test process that requires multiple startups of FPGA to collect analog data, after each startup test, before the next startup test, the FPGA needs to read the data collected by the FPGA through the software, and then perform the next test; if the data is not read out in time, the original data will be overwritten at the next startup, so repeated start and stop make the test inefficient. In addition, the data in the FPGA depends on the host computer processing, and the host computer software needs to be used to perform data processing tasks, that is, in the scenario where multiple measurements are required, the data needs to be read by the software after each test, and then analyzed, which makes the data processing time longer, thereby making the test efficiency low.
[0058] In view of the above technical problems, the present invention proposes the following solutions:
[0059] Figure 1A flowchart of a data processing method provided by an embodiment of the present invention, the data processing method is applied to FPGA, reference Figure 1 , the data processing methods include:
[0060] Step S110, starting data collection according to a trigger signal or a start signal; wherein the method includes N trigger signals or N start signals, and each time after data collection is started, single-point data is collected during a collection period until a stop condition is met; N is greater than 1;
[0061] Specifically, during the test of the device under test (DUT), data collection can be started according to the received trigger signal, and the data collection task can also be started according to the start signal generated by the pre-configured start time. The data processing method provided in this embodiment may include N trigger signals, or N start signals, which can be applied to application scenarios in which data collection is started multiple times, such as pre-configured multiple start times, specifically the first start time, the second start time, the third start time...N start times, and the corresponding start signals are generated in sequence according to the set start times. After the FPGA receives the start signal, data collection is started in sequence according to the set start times.
[0062] If the trigger signal for starting data acquisition comes from a test vector, the test data is output to the device under test by executing a preset test vector, and the acquisition trigger mark in the test vector is used to trigger the data acquisition device to collect the data output by the device under test; that is, the FPGA controls the data acquisition device to start data acquisition according to the acquisition trigger mark; the data acquisition device is, for example, an ADC (Analog to Digital Converter). The acquisition trigger mark can be in the form of a pulse, and can also be in other forms in other embodiments, which are not specifically limited. For example, data acquisition can be defined as outputting an acquisition trigger mark to the FPGA after a preset time of outputting test data to the device under test, thereby allowing data acquisition to be performed after the output data of the device under test is stable. When the stop condition is met, the FPGA controls the data acquisition device to stop data acquisition, that is, one data acquisition is completed.
[0063] It should be noted that when starting data collection based on a test vector, an acquisition trigger mark is required. When based on other trigger signal sources or start signals, it can be determined whether to set the trigger mark as needed, and there is no specific limitation on this.
[0064] It should be noted that the data acquisition described in this embodiment means the completion of a continuous data acquisition, and multiple single-point data may be collected during a continuous data acquisition process. Among them, the data acquisition frequency of the data acquisition device can be pre-defined and stored in the data acquisition device, and the number of single-point data collected each time the data acquisition is started can be controlled by controlling the duration of the vector row corresponding to the acquisition trigger mark. In addition, it should be noted that the data acquisition device sends the single-point data to the FPGA immediately after collecting it. In other words, the single-point data in the FPGA is obtained by the FPGA from the data acquisition device. In this embodiment, when data acquisition is started by a test vector, multiple acquisition trigger marks are set in the test vector, and one test vector can be used to complete the data acquisition work after multiple groups of test data are input into the device under test. There is no need to read data from the FPGA after each group of test data is tested before the next group of test data can be input into the device under test. Data collection work, thereby greatly improving the test efficiency.
[0065] Step S120, storing the single point data collected in each collection period;
[0066] Specifically, in this embodiment, a data storage space is provided in the FPGA, and each time the data acquisition device acquires single-point data and sends it to the FPGA, the FPGA will store the single-point data. When a test vector is used to start data acquisition, in the process of using multiple sets of test data to test the device under test, since multiple sets of test data are synthesized into one test vector, and a collection trigger mark is provided in the test vector, all single-point data corresponding to the multiple sets of test data will be stored in the data storage space in the FPGA, and will not be refreshed and overwritten, so there is no need to read out the single-point data corresponding to a set of test data after the test is completed, thereby greatly improving the test efficiency.
[0067] It should be noted that the data storage space can be set inside the FPGA or outside the FPGA. The specific setting can be set according to actual needs and is not specifically limited here.
[0068] Step S130 , preprocessing the single point data collected in each collection period to obtain preprocessed data corresponding to the single point data in each collection period, wherein the preprocessing at least includes counting statistical information of the single point data collected in each collection period.
[0069] Specifically, the single-point data collected in each collection period is defined as a single-point data group, and each group of test data corresponds to a single-point test data group. The statistical information of the single-point data group is processed in the FPGA, and there is no need for subsequent reading and analysis preprocessing using software, which greatly shortens the data processing time and further improves the test efficiency.
[0070] It should be noted that the order of step S120 and step S130 in this embodiment is not limited. There are various specific implementation methods, such as storing a single point data after collecting a single point data, or storing a single point data group uniformly after collecting it; FPGA preprocessing after each data processing device collects single point data, or preprocessing a single point data group uniformly after being acquired by FPGA, etc. The present invention will focus on introducing the more preferred implementation methods later.
[0071] Step S140, storing preprocessed data;
[0072] Specifically, after determining the preprocessed data corresponding to each acquisition period, the preprocessed data is stored in the FPGA, and the preprocessed data can be directly read from the FPGA later, without the need to use software to preprocess and analyze the single-point data. The single-point data and preprocessed data collected multiple times are stored, and the preprocessed data and the single-point data are matched to ensure the accuracy of the data, and the data can also be traced.
[0073] The technical solution of this embodiment adopts a data processing method including controlling the start of data acquisition according to a trigger signal or a start signal; wherein the method includes N trigger signals or N start signals, and each time after controlling the start of data acquisition, the single point data is controlled to be collected in the acquisition period until the stop condition is met; N is greater than 1; the single point data collected in each acquisition period is stored; the single point data collected in each acquisition period is preprocessed to obtain the preprocessed data corresponding to the single point data in each acquisition period, wherein the preprocessing at least includes statistical information of the single point data collected in each acquisition period; and the preprocessing data is stored. According to N trigger signals or N start signals, N data acquisitions are started, and the data output by the device under test under multiple test conditions can be collected in the test process of one trigger signal, and it is not necessary to read out the data collected in the FPGA at the end of each acquisition period, which greatly improves the test efficiency. In addition, since the preprocessing of the data collected by multiple starts is completed in the FPGA, it is not necessary to process the collected data after reading it out, thereby further improving the test efficiency. In addition, the single point data and preprocessed data collected by multiple starts are stored, and the preprocessed data are corresponded to the single point data to ensure the accuracy of the data, and the data is traceable.
[0074] Optionally, Figure 2 A flowchart of another data processing method provided by an embodiment of the present invention, referring to Figure 2 .
[0075] Storing the single point data collected during each collection period includes:
[0076] Step S213, controlling the collection of single-point data.
[0077] Specifically, before step S213, starting N data acquisitions according to a trigger signal or a start signal includes: when the test starts, the FPGA enters step S211, that is, enters an idle state. After the FPGA is in an idle state for a certain period of time, it enters step S212, that is, it continuously detects whether a trigger signal or a start signal is received; if a trigger signal or a start signal is received, it enters step S213; if a trigger signal or a start signal is not received, it returns to step S211. Single-point data is the data output by the data acquisition device at a certain moment. The FPGA controls the data acquisition device to collect data output by the device under test, and the FPGA receives digital data output by the data acquisition device.
[0078] It should be noted that after the test starts, the FPGA clears all previous single-point data and pre-processed data to ensure that each process starts with a new round of data collection. If a storage space overflow occurs before, the abnormal state will be automatically resolved.
[0079] Step S215, after each control is completed to collect a single point of data, the single point of data is stored in sequence in the first storage space of the FPGA.
[0080] Specifically, in this embodiment, a first storage space dedicated to storing single-point data is provided in the data storage space of the FPGA. The first storage space can be an on-chip storage resource or an off-chip storage space, for example, a storage structure of a ring buff, which is not specifically limited. After each single-point data is collected by the data acquisition device and read by the FPGA, the FPGA stores it in the first storage space in sequence, thereby avoiding the loss of the single-point data. Among them, storing in the first storage space in sequence means storing the single-point data according to the address of the first storage space, such as the single-point data collected for the first time is stored in the address 0 of the first storage space, the single-point data collected for the second time is stored in the address 1 of the first storage space, and the single-point data collected for the third time is stored in the address 2 of the first storage space, and so on, to ensure the integrity of the data.
[0081] Optionally, continue to refer to Figure 2 , the statistical information of the single-point data collected in each collection period includes at least: the number of single-point data collected in each collection period, the storage location pointer of the single-point data collected in each collection period, the maximum value of the single-point data collected in each collection period, the location corresponding to the maximum value, the minimum value of the single-point data collected in each collection period, the location corresponding to the minimum value and the measurement range information;
[0082] Specifically, after each control starts data collection, all single-point data are continuously stored in the first storage space. After the storage of all single-point data collected in each collection period is completed, the storage position pointer is recorded. When reading data later, the data collected at any time when data collection is started can be read through the storage position pointer as needed. There is no need to read all the single-point data, which can further improve the test efficiency. In addition, the statistical information also includes the maximum value and the position corresponding to the maximum value, wherein the position corresponding to the maximum value can be the position in the first storage space, or the relative position or absolute position in the preset number of single-point data; similarly, the position corresponding to the minimum value can also be the position in the first storage space, or the relative position or absolute position in the preset number of single-point data.
[0083] The preprocessing of the single-point data collected in each collection period includes:
[0084] After the single-point data is sequentially stored in the first storage space of the FPGA after each control acquisition is completed, that is, after step S215, step S217 is executed, that is, the number of single-point data, the maximum value, the position corresponding to the maximum value, the minimum value, the position corresponding to the minimum value, and the measurement range information in the statistical information are updated according to the single-point data currently acquired;
[0085] Specifically, in FPGA, a register n can be defined, and register n is used to count the number of sampling points, that is, the number of single-point data corresponding to each acquisition period. The initial value of register n can be set to 0, and the value of register n is accumulated by 1 each time a data is sampled. That is, when a single-point data is collected for the first time, the value of register n is 1. When all single-point data corresponding to a single start data collection are sampled, the final result of register n is the final number of sampling points, that is, the final result of register n is the number of single-point data corresponding to the end of a single data collection.
[0086] In addition, in FPGA, a register a can be defined, and register a is used to record the current storage location pointer. Register a represents the first address in the first storage space that can be used to store single-point data. For example, the initial value of register a is 0; register a is not updated during a single data acquisition process, and is updated after the single data acquisition is completed.
[0087] In addition, in this embodiment, N data collections are started. For the extreme value (maximum value and minimum value) processing in the single data collection process, after the FPGA obtains the single-point data collected by the data collection device for the first time, the maximum data and the minimum data in the single-point data collected for the first time are determined as the maximum value and the minimum value. In the subsequent process of continuously collecting single-point data, the collected single-point data is compared with the current maximum value and the minimum value. If the single-point data collected currently is greater than the current maximum value, the single-point data collected currently is updated to the maximum value; if the single-point data collected currently is less than or equal to the current maximum value, the current maximum value is kept unchanged. Similarly, if the single-point data collected currently is less than the current minimum value, the single-point data collected currently is updated to the minimum value; if the single-point data collected currently is greater than or equal to the current maximum value, the current minimum value is kept unchanged. At the same time, when the maximum value or the minimum value is updated, the corresponding position is also updated synchronously.
[0088] In addition, step S217 may also include accumulating single-point data, that is, defining a register s, and adding the current value of the register s to the single-point data every time a single-point data is collected, so as to facilitate subsequent calculation of the average value.
[0089] In addition, step S217 may also include recording the measurement range information corresponding to the current startup data collection, wherein the measurement range information includes the voltage range and the current range.
[0090] It should be noted that the measurement range information in this embodiment refers to the acquisition range information of voltage and current. Generally, during the sampling process, the measurement range information is related to the actual acquired data. Selecting appropriate measurement range information can ensure the test accuracy. Each time the data acquisition is triggered, the measurement range information of each trigger needs to be saved to ensure the correspondence between the actual acquired data and the measurement range information. The subsequent data reading and analysis device can calculate the correct conversion coefficient based on the measurement range information and calculate the actual analog value. The specific calculation process adopts a conventional calculation method, which will not be described in detail here.
[0091] Step S218, determine whether the first stop condition is met. That is, determine whether the collected single-point data reaches the corresponding preset number. If so, it means that the data collection is completed and step S220 can be executed; if not, return to step S213. Among them, the stop condition in this embodiment includes the first stop condition, that is, when the first stop condition is met, the collection period ends. The first stop condition is to stop after the preset number of single-point data is collected, which includes all the single-point data required for the test data set by the user.
[0092] Step S220 is to determine the pre-processed data.
[0093] Specifically, when all single-point data collection in a single start-up data collection is completed, the final statistical information reflects the statistical information corresponding to all single-point data in the sampling period. In this embodiment, after each single-point data collection, the corresponding statistical information is counted, and after all single-point data statistics are completed, the corresponding statistical information can be obtained in time. Compared with statistics after all single-point data collection is completed, it has higher real-time performance, can further shorten the time required to obtain pre-processed data, and can further improve the test efficiency. Among them, determining the statistical information includes updating the storage location pointer, and the storage location pointer represents the first address in the first storage space that can be used to store data.
[0094] It should be noted that the storage location pointer cooperates with the actual collected data to implement the indexing of the first address and the last address of a single start of data collection, and distinguish each data collection.
[0095] Optionally, continue to refer to Figure 2 The pre-processed data also includes the average value of the single-point data during the acquisition period. In step S218, after the first stop condition is met, the following is also included:
[0096] Step S219, determining the average value of the single-point data collected in the collection period corresponding to the control startup data collection. Specifically, after the single-point data in the collection period corresponding to the control startup data collection are collected, the cumulative value of all single-point data is also calculated, and the average value can be obtained by dividing the cumulative value by the preset number. In this embodiment, step S219 is executed before step S220. In step S220, determining the pre-processed data includes determining the number of collections in each collection period, the storage location pointer of the single-point data, the maximum value, the location corresponding to the maximum value, the minimum value, the location corresponding to the minimum value and the measurement range information, and also includes determining the average value. It should be noted that the pre-processed data may also include other data besides the above-mentioned statistical information and the average value, without specific limitation.
[0097] Optionally, after determining the preprocessed data, the following further comprises:
[0098] Step S221, storing the preprocessed data, that is, storing the preprocessed data in the second storage space of the FPGA.
[0099] Specifically, in this embodiment, the data storage space in the FPGA includes a second storage space in addition to the first storage space. The second storage space is different from the first storage space. The second storage space is provided with a plurality of sub-storage spaces for storing different types of pre-processed data. However, the addresses in the first storage space are continuous, and the addresses in the second storage space are also continuous, thereby ensuring the integrity and traceability of the data.
[0100] Preferably, storing the preprocessed data in the second storage space comprises at least:
[0101] storing the number of single-point data and the storage location pointer in the first sub-storage space;
[0102] storing the average value and the measurement range information in the second sub-storage space;
[0103] The maximum value and the position corresponding to the maximum value are stored in the third sub-storage space;
[0104] The minimum value and the position corresponding to the minimum value are stored in the fourth sub-storage space, wherein the storage addresses in each sub-storage space are continuous.
[0105] Specifically, in this embodiment, the second storage space is divided into four sub-storage spaces. In other embodiments, the second storage space may also be divided into other numbers of sub-storage spaces, which are not specifically limited here. The addresses in each sub-storage space are continuous, and the addresses of two adjacent sub-storage spaces may also be set to be continuous. The data stored in each sub-storage space is of the same category, that is, the pre-processed data of the same category is stored in the same sub-storage space, which facilitates data retrieval and processing by category and ensures the reading rate of the same type of information.
[0106] For example, by analyzing the number of single-point data in the collection period corresponding to a certain start-up data collection and the storage location pointer, the single-point data corresponding to the data collection can be read. More specifically, the first address of the single-point data corresponding to the data collection is the storage location pointer minus the number of sampling points (i.e., the number of single-point data), and the last address is the storage location pointer minus 1. Similarly, if only the maximum value needs to be read, the data stored in the third sub-storage space corresponding to the data collection can be read.
[0107] In some other implementations, the data categories stored in each sub-storage space may also be different. Various types of information triggered at the same time (such as single-point data and pre-processed data) can be stored in one sub-storage space to facilitate obtaining sampling data according to the number of startups. The specific storage method can be set according to actual needs.
[0108] Furthermore, in some implementations, the size of each sub-storage space may be set to be the same or different.
[0109] Optionally, continue to refer to Figure 2 After each acquisition of a single point of data is completed, the single point of data is stored in the first storage space of the FPGA in sequence, and then the following steps are further included:
[0110] Step S216, determine whether the first storage space overflows; if the first storage space overflows, execute step S224. Step S224 is an overflow alarm, that is, outputs an alarm message and does not start data collection. If the first storage space does not overflow, execute step S217.
[0111] Specifically, in this embodiment, after each single-point data is stored, it is first determined whether the first storage space overflows. If data overflow is detected, data collection and data processing are automatically stopped, and further data storage is stopped. Such a setting effectively prevents test data errors caused by insufficient storage space, ensures that the single-point data obtained after each data collection is started is valid, ensures data reliability, and avoids the generation of erroneous data.
[0112] Optionally, continue to refer to Figure 2 After storing the preprocessed data in the second storage space, that is, after step S221, the method further includes: step S222, determining whether the second storage space overflows; if the second storage space overflows, executing step S224, generating an overflow alarm, and ending the test. If the second storage space does not overflow, returning to the step of executing the trigger signal or the start signal to start data acquisition. More specifically, the method may return to step S211.
[0113] Specifically, in this embodiment, after each storage of the pre-processed data, it is first determined whether the second storage space overflows. If data overflow is detected, data collection and data processing are automatically stopped, and further data storage is stopped. Such a setting effectively prevents test data errors caused by insufficient storage space, ensures that the pre-processed data obtained after each data collection is started is valid, ensures data reliability, and avoids the generation of erroneous data.
[0114] Optionally, after a single point of data is collected each time, before the single point of data is sequentially stored in the first storage space of the FPGA, the method further includes:
[0115] Step S214, determining whether the second stop condition is met; wherein the second stop condition is the detection of a stop signal; if a stop signal is detected, executing step S219, i.e., executing the step of determining the average value of the single-point data collected during the collection period corresponding to the control start data collection. If no stop signal is detected, executing step S215, i.e., the step of storing the single-point data in sequence in the first storage space of the FPGA after completing the control collection of a single-point data each time.
[0116] Specifically, in this embodiment, in addition to performing preprocessing after completing a data collection, the FPGA can also perform preprocessing directly after receiving a stop signal. The stop signal can be generated by a digital board and sent to the FPGA. By setting the FPGA to stop data collection in response to the stop signal, the flexibility of the test can be further improved. It can be understood that the second stop condition in this embodiment includes a stop signal. When the FPGA stops in response to the stop signal, the number of single-point data collected in the corresponding collection period may not reach the above-mentioned preset number.
[0117] Optionally, continue to refer to Figure 2 After the judgment result of step S222 is no, the method further includes: step S223, judging whether the total number of startup times is satisfied, if not, returning to step S211; if yes, the test ends. The total number of startup times is N, that is, the number of times the FPGA needs to start data collection under one test vector.
[0118] Based on the same inventive concept, the present invention also provides a data analysis method, such as Figure 3 As shown, Figure 3 A flow chart of a data analysis method provided by an embodiment of the present invention. The data analysis method comprises:
[0119] Step S311, FPGA starts data acquisition according to a trigger signal or a start signal; wherein, the method includes N trigger signals or N start signals, and each time after controlling the start of data acquisition, controls the acquisition of single-point data within an acquisition period until a stop condition is met; N is greater than 1; stores the single-point data collected in each acquisition period; pre-processes the single-point data collected in each acquisition period to obtain pre-processed data corresponding to the single-point data in each acquisition period, wherein the pre-processing at least includes statistical information of the single-point data collected in each acquisition period; stores the pre-processed data.
[0120] Specifically, the specific working process of FPGA can refer to the description of the data processing method of FPGA in the present invention, which will not be repeated here.
[0121] Step S312: the data reading and analyzing device reads and analyzes the corresponding single-point data according to the preprocessed data.
[0122] Specifically, the data reading and analyzing device is, for example, a host computer, and the data reading and analyzing device can correspond the preset number of single-point data collected after each data collection is started with the pre-processed data. The data reading and analyzing device can read the single-point data and pre-processed data after any one of the data collection is started. Of course, it can also be to obtain all the single-point data after the entire test process is completed. More specifically, the data reading and analyzing device reads the storage location pointer and the preset number from the second storage space to determine the corresponding single-point data to be read. Of course, other corresponding pre-processed data can also be read from the second storage space. The data processing and analyzing device can also correspond the single-point data with the pre-processed data. In addition, the data reading and analyzing device can also interact with the user so that the user can obtain the data stored in the FPGA. Of course, in some embodiments, the data reading and analyzing device can also have an access number restriction function, that is, if the user needs to access the single-point data and pre-processed data corresponding to the N+1th start of data collection, since the FPGA has started data collection N times in total, at this time, the data reading and analyzing device will prompt and alarm. In some embodiments, analyzing the single-point data can be drawing a waveform chart based on the single-point data.
[0123] The technical solution of this embodiment adopts the FPGA data analysis method, which greatly improves the test efficiency because it does not need to read and analyze data after each data collection is started, but reads data after multiple data collections are started. In addition, the data has been preprocessed in the FPGA, thereby further improving the test efficiency.
[0124] It should also be noted that the data processing methods provided in the embodiments of the present invention can all be executed by the FPGA in the FPGA data analysis method provided in the embodiments of the present invention.
[0125] The specific implementation modes and related technologies of the present invention are described below by way of examples.
[0126] For example, to start data acquisition with a test vector, and test the quiescent current (IDDQ, short for Quiescent IDD, Quiescent Supply Current) of a two-input IC (Integrated Circuit) device under different input combinations, four input combinations (00, 01, 10, 11) need to be tested separately. Each time a digital board outputs an input combination, it triggers the FPGA to measure the corresponding IDDQ value.
[0127] The test steps in the related technology are as follows:
[0128] The first step is to write a test vector.
[0129] Define test vectors: Create a test vector for each input combination, for example:
[0130] Test vector 1: A=0, B=0;
[0131] Test vector 2: A=0, B=1;
[0132] Test vector 3: A=1, B=0;
[0133] Test vector 4: A=1, B=1;
[0134] In the second step, test vector 1 is applied and the IDDQ test is triggered.
[0135] Load the first test vector: Use the digital board to output the first test vector (A=0, B=0);
[0136] Waiting for the current to stabilize: Give the IC device a certain amount of time to reach a stable working state, usually ranging from a few microseconds to tens of microseconds;
[0137] Trigger IDDQ test: Once the IC device is stable, immediately trigger the analog-to-digital acquisition card to start measuring IDDQ;
[0138] Record data: FPGA will automatically record the IDDQ current value under this input combination;
[0139] Read data: The software reads the sampled IDDQ current value of the analog-to-digital acquisition card in this input state;
[0140] Save data: Save the IDDQ current value obtained from each test segment to the specified data storage space.
[0141] Step 3: Repeat the above process.
[0142] Perform IDDQ tests on the other three input combinations (A=0, B=1; A=1, B=0; A=1, B=1) in turn, and repeat the above steps.
[0143] Step 4: data analysis.
[0144] After the test is completed, the software calculates and processes the mean, maximum, and minimum values based on the saved IDDQ data to determine whether the IC device has defects.
[0145] From the above analysis, it can be seen that this test method needs to load test vectors four times, read test data four times, and after the test is completed, the software needs a lot of time to process the data, which reduces the test efficiency.
[0146] The specific test steps of this solution are as follows:
[0147] The first step is to write a test vector.
[0148] The four input combinations (00, 01, 10, 11) are synthesized into a test vector. After each segment outputs a combination to the IC device, a delay of 10us is made to wait for the IC current to stabilize, and then the FPGA is triggered to collect the IDDQ current. Assuming that 100 points need to be collected for each startup, the sampling interval is 1us, that is, a delay of 100us. After waiting for the current state test to be completed, the IDDQ test of the next input combination is continued until all four combinations of IDDQ current tests are completed.
[0149] Test vector:
[0150] A=0, B=0, delay 10us, start IDDQ sampling, delay 100us,
[0151] A=0, B=1, delay 10us, start IDDQ sampling, delay 100us,
[0152] A=1, B=0, delay 10us, start IDDQ sampling, delay 100us,
[0153] A=1, B=1, delay 10us, start IDDQ sampling, delay 100us;
[0154] The second step is to trigger the start of the IDDQ test.
[0155] After the IDDQ current under each input combination is stable, the FPGA is triggered to start the current test. In one test process, four start signals will be received, and the FPGA will perform four IDDQ tests.
[0156] The third step is the IDDQ current single point value storage process.
[0157] After receiving the start signal, the analog-to-digital acquisition card will collect the IDDQ current and store the collected current value in the single-point data storage space (i.e., the first storage space). Figure 4 As shown, Figure 4 A schematic diagram of a single-point data storage process provided by an embodiment of the present invention.
[0158] The first trigger starts, and the IDDQ single-point data (i.e., the first sampling data) is written into the first area of the first storage space, with data size = 100 and position pointer = 100;
[0159] The second trigger starts, and the IDDQ single-point data (second sampling data) is written into the second area, with data size = 100 and position pointer = 200;
[0160] The third trigger starts, and the IDDQ single-point data is written (the third sampling data) into the third area, with data size = 100 and position pointer = 300;
[0161] The fourth trigger starts, and IDDQ single-point data is written (the 4th sampling data) into the fourth area, data size = 100, position pointer = 400.
[0162] The fourth step is the preprocessing data storage process.
[0163] like Figure 5 As shown, Figure 5 A schematic diagram of a second storage space for storing pre-processed data provided by an embodiment of the present invention. During the acquisition process, the FPGA pre-processes the single-point data in real time, and writes the statistical information into the pre-processed data storage space in sequence after each sampling, including the actual number of sampling points, average value, maximum value, minimum value and other information. It should be noted that Figure 5 The specific data are only examples.
[0164] Step 5: After the test is completed, all the data in the first storage space and the second storage space are read out through the software, and the single-point data and the pre-processed data are matched to draw the test waveform for subsequent analysis;
[0165] It should be noted that the correspondence between the preprocessed data and the single-point data is achieved by querying the storage position pointer of the second storage space and the actual number of sampling points. The first address of the single-point data storage space = storage position pointer - the number of single-point data, and the end address of the single-point data storage space = position pointer - 1.
[0166] For example, Figure 5 In the first single-point current value storage space address range: 0-99;
[0167] The second single-point current value storage space address range: 100-199;
[0168] The third single-point current value storage space address range: 200-299;
[0169] The fourth single-point current value storage space address range: 300-399;
[0170] After the single-point data and preprocessing are completed, they are displayed together in the software oscilloscope, including the single-point value, average value, maximum value and minimum value of each sampling.
[0171] Based on the same inventive concept, the present invention also provides a data processing device, such as Figure 6 As shown, Figure 6 A schematic diagram of the structure of a data processing device provided in an embodiment of the present invention. The data processing device is used to execute the data processing method provided in any embodiment of the present invention. The data processing device includes:
[0172] A start control module 41, which is used to control the start of data acquisition according to a trigger signal or a start signal;
[0173] A processing module, used for preprocessing the single point data collected in each collection period to obtain preprocessed data corresponding to the single point data in each collection period, wherein the preprocessing at least includes statistical information of the single point data collected in each collection period;
[0174] The first storage space 431 is used to store single point data;
[0175] The second storage space 432 is used to store pre-processed data.
[0176] Specifically, the data processing device of this embodiment is, for example, an FPGA, and the startup control module 41 continuously detects whether there is a trigger signal or a startup signal. If a trigger signal or a startup signal is detected, the data acquisition device is controlled to collect single-point data. Figure 2 , the control module 41 is started to execute step S212. The processing module is used to execute step S215 and step S217. The data storage space 43 of the data processing device includes a first storage space 431, and the first storage space 431 can be used to store single point data.
[0177] The technical solution of this embodiment does not need to read and analyze data after each data collection is started, but reads data after multiple data collections are started, which greatly improves the test efficiency. In addition, the data processing device has preprocessed the data, which further improves the test efficiency.
[0178] Optionally, continue to refer to Figure 2 and Figure 6 The data processing device further includes an ADC control module 46, the data storage space 43 of the data processing device further includes a second storage space 432, and the data processing device further includes an overflow management module 45. The processing module includes a sampling information statistics and storage control module 42 and a data preprocessing and storage control module 44.
[0179] Specifically, the data processing device is in an idle state after being powered on, that is, it enters step S211. And the startup control module 41 executes step S212, that is, waits for a trigger signal or a startup signal. If a trigger signal or a startup signal is detected, the startup control module 41 controls the ADC control module 46, so that the ADC control module 46 starts the external analog-to-digital conversion module (i.e., the data acquisition device) for sampling according to the set sampling frequency. That is, the ADC control module 46 executes step S213, and the ADC control module 46 also executes step S214, that is, continuously detects whether the second stop condition is met. If the stop signal is not detected, the sampling information statistics and storage control module 42 executes step S215, that is, after each single point data is acquired, the single point data is stored in the first storage space of the FPGA in sequence. In addition, the sampling information statistics and storage control module 42 executes step S216, that is, detects whether the first storage space overflows, and if overflows, an overflow flag is issued, and the overflow flag is sent to the overflow management module 45. The sampling information statistics and storage control module 42 is also used to execute the part of updating the number of single-point data in the statistical information according to the currently sampled single-point data in step S217, and step S218. In addition, in some embodiments, the sampling information statistics and storage control module 42 is also used to count the total number of startups collected by the statistical data, and the total number of startups can be sent to the data preprocessing and storage control module 44. In addition, the data preprocessing and storage control module 44 is used to execute the part of updating the maximum value, the position corresponding to the maximum value, the minimum value and the position corresponding to the minimum value of the statistical information according to the currently sampled single-point data in step S217. After step S218, the data preprocessing and storage control module 44 executes steps S219, S220, S221 and S222. If the judgment result of step S222 is yes, a preprocessing data overflow flag is generated and sent to the overflow management module 45. In addition, the data preprocessing and storage control module 44 is also used to store the total number of startups in the second storage space 432. It should be noted that when the second storage space overflows, it means that the total number of startups exceeds the maximum number of startups supported. It should be noted that after the overflow management module 45 receives the overflow flag, it controls the data processing device to immediately stop the storage of the single point data and the pre-processed data, and stops the operation of the data acquisition device. The overflow management module 45 can control the data processing device to immediately stop the storage of the single point data and the pre-processed data after receiving any one of the overflow flags of the first storage space and the overflow flags of the second storage space, and receive a trigger start command after the current test round stops, and restart the next round of testing after receiving the trigger start command. It is understandable that after each round of restarting the test, if there is an overflow flag in the overflow management module 45, the overflow flag will be reset.
[0180] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0181] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A data processing method, characterized in that: The method is applied to FPGA, and the method comprises: Initiate data collection according to a trigger signal or a start signal; wherein the method includes N trigger signals or N start signals, and each time control starts data collection until a stop condition is met, control the collection of single-point data; N is greater than 1; Storing the single-point data collected during each collection period; Preprocessing the single point data collected in each of the collection time periods to obtain preprocessed data corresponding to the single point data in each of the collection time periods, wherein the preprocessing at least includes collecting statistical information of the single point data collected in each of the collection time periods; The pre-processed data is stored.
2. The data processing method according to claim 1, characterized in that: The storing of the single point data collected in each collection period includes: Control and collect single-point data; After a single point of data is collected each time, the single point of data is stored in sequence in the first storage space of the FPGA.
3. The data processing method according to claim 2, characterized in that: The statistical information of the single-point data collected in each of the collection time periods includes at least: the number of single-point data collected in each of the collection time periods, the storage location pointer of the single-point data collected in each of the collection time periods, the maximum value of the single-point data collected in each of the collection time periods, the location corresponding to the maximum value, the minimum value of the single-point data collected in each of the collection time periods, the location corresponding to the minimum value and the measurement range information; The preprocessing of the single point data collected in each collection period includes: After completing the control acquisition of a single point of data each time, the single point of data is sequentially stored in the first storage space of the FPGA. Update the number, maximum value, position corresponding to the maximum value, minimum value and position corresponding to the minimum value of the single point data in the statistical information according to the currently collected single point data; Determine whether the first stop condition is met; if so, determine the preprocessed data; if not, return to execute the step of controlling the acquisition of single-point data; the first stop condition is that the number of the single-point data is a preset number.
4. The data processing method according to claim 3, characterized in that: The pre-processed data also includes the average value of the single-point data in the acquisition period; After the first stop condition is met, the following steps are also included: Determine the average value of the single-point data collected during the collection period corresponding to the current startup data collection.
5. The data processing method according to claim 4, characterized in that: After determining the preprocessing data, the method further includes: storing the preprocessed data in a second storage space; Wherein, storing the preprocessed data in the second storage space at least includes: Storing the number of the single point data and the storage location pointer in the first sub-storage space; storing the average value and the measurement range information in a second sub-storage space; storing the maximum value and the position corresponding to the maximum value in a third sub-storage space; storing the minimum value and the position corresponding to the minimum value in a fourth sub-storage space; The storage addresses in each sub-storage space are continuous.
6. The data processing method according to claim 3, characterized in that: After completing the control acquisition of a single point of data each time, the single point of data is sequentially stored in the first storage space of the FPGA, and the method further includes: Determining whether the first storage space overflows, and if the first storage space overflows, outputting an alarm message and not starting data collection; If the first storage space does not overflow, the step of updating the number, maximum value, position corresponding to the maximum value, minimum value and position corresponding to the minimum value of the single point data in the statistical information according to the currently collected single point data is performed.
7. The data processing method according to claim 5, characterized in that: After storing the pre-processed data in the second storage space, the method further includes: Determine whether the second storage space overflows. If the second storage space overflows, output an alarm message and do not start data collection. If the second storage space does not overflow, return to the step of starting data collection according to a trigger signal or a start signal.
8. The data processing method according to claim 4, characterized in that: The control acquisition of a single point of data each time before storing the single point of data in sequence in the first storage space of the FPGA also includes: Determine whether a second stop condition is met; wherein the second stop condition is detection of a stop signal; If the stop signal is detected, the step of determining the average value of the single-point data collected in the collection period corresponding to the start of data collection is executed; if the stop signal is not detected, the step of storing the single-point data in sequence in the first storage space of the FPGA is executed.
9. A data analysis method, characterized in that: include: FPGA starts data acquisition according to the test trigger signal or start signal; The method includes N trigger signals or N start signals, and each time after controlling the start of data collection, the single point data is collected in the collection period until the stop condition is met; N is greater than 1; the single point data collected in each collection period is stored; the single point data collected in each collection period is preprocessed to obtain preprocessed data corresponding to the single point data in each collection period, wherein the preprocessing at least includes statistical information of the single point data collected in each collection period; and the preprocessed data is stored; The data reading and analyzing device reads and analyzes the corresponding single-point data according to the preprocessed data.
10. A data processing device, used to execute the data processing method according to any one of claims 1 to 8, characterized in that: The data processing device comprises: A start control module, wherein the start control module is used to start data acquisition according to a trigger signal or a start signal; A processing module, used for preprocessing the single point data collected in each of the collection time periods to obtain preprocessed data corresponding to the single point data in each of the collection time periods, wherein the preprocessing at least includes collecting statistical information of the single point data collected in each of the collection time periods; A first storage space, used to store the single point data; The second storage space is used to store the pre-processed data.