Circuit delay calculation method based on genetic-particle swarm hybrid algorithm

Abstract

The invention discloses a circuit delay calculation method based on a genetic-particle swarm hybrid algorithm, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a circuit structure and converting the circuit structure into a weighted graph; traversing the weighted graph by using a genetic algorithm, and selecting nodes according to fitness; performing crossover and mutation operation of the genetic algorithm, and introducing an updating mechanism of particles in a particle swarm algorithm to select nodes and paths to obtain a path with the maximum sum of weights in a group, namely a path with the longest delay; iterations are repeated until iteration termination conditions are met, and a path with the maximum weight sum is obtained. According to the method, the optimal solution in the weighted graph is searched by utilizing the genetic algorithm, and meanwhile, the particle swarm optimization is introduced to optimize the search process of the genetic algorithm, so that the convergence speed is improved, namely, the search speed of the path corresponding to the circuit delay value is improved, and the delay calculation efficiency and precision are remarkably improved.

Description

Technical Field

[0001] The invention relates to a circuit delay calculation method based on a genetic-particle swarm hybrid algorithm, and belongs to the technical field of integrated circuit design automation. Background Art

[0002] As one of the mid-range design processes, logic synthesis plays an important role in digital integrated circuit design. The purpose of logic synthesis is to ensure that the designed circuit can accurately implement the required functions. Its main goal is to convert high-level logic descriptions into gate-level or lower-level circuit implementations. In this conversion process, there are several common methods, including logical expressions, truth tables, and graphical representations. Among the above methods, the graphical representation method is intuitive, efficient, and clear, which improves the efficiency and accuracy of the design. Therefore, the graphical representation method is becoming the mainstream representation method in the logic synthesis process.

[0003] In circuit systems, circuit delay is an important indicator that can show the synchronization of circuit signals and help understand circuit performance optimization effects and reliability.

[0004] By converting the circuit into a graph, the complexity of the circuit can be simplified, the efficiency of calculating the delay can be improved, and the accuracy of the calculation can be increased. When calculating the delay of the converted graph, the commonly used methods are depth-first search (DFS) and breadth-first search (BFS). When these two methods perform graph traversal, they traverse and search each node one by one and finally obtain the traversal result. However, this traversal method is inefficient and not very accurate. When the circuit complexity is high, it takes a long time to calculate the delay.

[0005] Therefore, in the face of the defects of the above methods, it is very important to choose a method to improve the efficiency and accuracy of circuit delay calculation. Summary of the invention

[0006] In order to improve the efficiency and accuracy of calculating circuit delay, the present invention provides a circuit delay calculation method based on a genetic-particle swarm hybrid algorithm, and the technical solution is as follows:

[0007] The circuit delay calculation method of the present invention comprises:

[0008] Step 1: Obtain the circuit structure and convert it into a weighted graph;

[0009] Step 2: Number the nodes in the weighted graph and initialize the delay and path of the source node;

[0010] Step 3: Use a genetic algorithm to traverse the weighted graph, calculate the fitness of the nodes, and select the nodes according to the fitness;

[0011] Step 4: Perform crossover and mutation operations of the genetic algorithm on the node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay;

[0012] Step 5: Repeat steps 3 to 5 until the iteration termination condition is met, and obtain the path with the largest sum of weights in the weighted graph, where the sum of the weights of the path is the circuit delay value.

[0013] Optionally, step 3 includes:

[0014] Step 21: Randomly select a source node as the initial node, start traversing from the initial node, and perform traversal selection level by level. During the selection process, calculate the path fitness size;

[0015] Step 22: Select nodes level by level. The node with greater fitness has greater weight. Select nodes with greater fitness as new node groups in each level, and select nodes from the new node groups according to probability.

[0016] Optionally, the fitness calculation formula of the node is:

[0017] Fitness(v)=max u→v (Fitness(u)+ω(u,v))

[0018] Among them, u→v represents the edge from node u to node v, and ω(u,v) represents the weight of the edge.

[0019] Optionally, the probability of node selection in step 22 is:

[0020]

[0021] Among them, P(i) represents the selection probability of the i-th node, and N represents the number of nodes.

[0022] The present invention provides a circuit delay calculation system, comprising:

[0023] A weighted graph conversion module is configured to obtain a circuit structure and convert it into a weighted graph;

[0024] An initialization module, configured to number the nodes in the weighted graph and initialize the delay and path of the source node;

[0025] A node traversal module is configured to traverse the weighted graph using a genetic algorithm, calculate the fitness of the nodes, and select the nodes according to the fitness;

[0026] The local optimal calculation module is configured to perform crossover and mutation operations of the genetic algorithm on the node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay;

[0027] The circuit delay value calculation module is configured to iterate the calculation process using the node traversal module and the local optimal calculation module until the iteration termination condition is met, and obtain the path with the largest sum of weights in the weighted graph, and the sum of the weights of the path is the circuit delay value.

[0028] Optionally, the calculation process of the node traversal module includes:

[0029] Randomly select the source node as the initial node, start traversing from the initial node, and perform traversal selection level by level. During the selection process, calculate the path fitness size.

[0030] The nodes are selected level by level, the nodes with greater fitness have greater weights, and nodes with greater fitness are selected in each level as new node groups, and nodes are selected from the new node groups according to probability.

[0031] Optionally, the fitness calculation formula of the node is:

[0032] Fitness(v)=max u→v (Fitness(u)+ω(u,v))

[0033] Among them, u→v represents the edge from node u to node v, and ω(u,v) represents the weight of the edge.

[0034] Optionally, the probability of each node in the new node group being selected is:

[0035]

[0036] Among them, P(i) represents the selection probability of the i-th node, and N represents the number of nodes.

[0037] The present invention provides a circuit delay calculation device, comprising a memory and a processor;

[0038] The memory is used to store computer programs;

[0039] The processor is used to implement the circuit delay calculation method as described in any one of the above items when executing the computer program.

[0040] The present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the circuit delay calculation method as described in any one of the above items is implemented.

[0041] The beneficial effects of the present invention are:

[0042] The method for calculating circuit delay proposed in the present invention uses software tools such as Visual Paradigm to convert the circuit into a weighted graph, and uses the weight size in the graph to digitize the delay. Converting the circuit into a weighted graph can improve the calculation efficiency of the algorithm.

[0043] In addition, the present invention introduces a heuristic algorithm to search for the optimal solution, uses the powerful global search capability of the genetic algorithm to search for the optimal solution in the weighted graph, and introduces a particle swarm algorithm to optimize the search process of the genetic algorithm, thereby improving the convergence speed, that is, improving the search speed for the path corresponding to the circuit delay value, and significantly improving the calculation efficiency. Therefore, using the genetic algorithm and the particle swarm algorithm to traverse and search the weighted graph can further improve the efficiency and accuracy of the delay calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 This is a flowchart of the overall steps of the method for calculating circuit delay based on the genetic-particle swarm hybrid algorithm in Example 1 of the present invention.

[0046] Figure 2(a)-Figure 2(e) This is an example diagram of the steps for implementing the authorized diagram in Example 3 of the present invention.

[0047] Figure 3 This is a schematic diagram of the genetic algorithm traversing the weighted graph nodes and selecting the node fitness in the second embodiment of the present invention.

[0048] Figure 4 It is a schematic diagram of introducing the particle swarm algorithm to search for nodes after crossover and mutation in the second embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of introducing a particle swarm algorithm to update particle positions in the second embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0051] Embodiment 1:

[0052] This embodiment provides a circuit delay calculation method, see Figure 1 , methods include:

[0053] Step 1: Obtain the circuit structure and convert it into a weighted graph;

[0054] Step 2: Number the nodes in the weighted graph and initialize the delay and path of the source node;

[0055] Step 3: Use the genetic algorithm to traverse the weighted graph, calculate the fitness of the nodes, and select the nodes according to the fitness;

[0056] Step 4: Perform crossover and mutation operations of the genetic algorithm on the node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay;

[0057] Step 5: Repeat steps 3 to 5 until the iteration termination condition is met, and the path with the largest sum of weights in the weighted graph is obtained. The sum of the weights of the path is the circuit delay value.

[0058] Embodiment 2

[0059] This embodiment provides a method for calculating circuit delay based on a particle swarm-genetic hybrid algorithm. Figure 1 , the method comprising:

[0060] Step 1: Obtain the circuit structure and convert it into a weighted graph;

[0061] According to the characteristics of the circuit structure, the circuit is converted into a weighted graph using corresponding software, that is, the circuit is represented as a graph for calculation.

[0062] Step 2: Number the nodes in the weighted graph and initialize the delay and path of the source node;

[0063] A set of source nodes in the weighted graph is randomly encoded as "chromosomes", and this step can be repeated many times. It is defined as: S = {s 1 ,s 2 ,s 3 ...}. Among them, s 1 、s 2 、s 3 etc. represent node 1, node 2, node 3, and so on. Initialize the weights of the source nodes in the weighted graph to facilitate step-by-step calculations.

[0064] Step 3: Use the genetic algorithm to traverse the weighted graph, calculate the fitness of the nodes, and select the nodes according to the fitness;

[0065] Taking the source node as the starting node, the fitness evaluation of the weighted graph is calculated level by level, that is, the fitness of each level of the source node is calculated (here it can be regarded as the weight of the edge between the nodes), and the fitness of the node is calculated using the following formula:

[0066] Fitness(v)=max u→v (Fitness(u)+ω(u,v))

[0067] Among them, u→v represents the edge from node u to node v, and ω(u,v) represents the weight of the edge.

[0068] Nodes are selected level by level according to their fitness. Nodes with larger fitness (with larger weights of edges between nodes) are selected as new "chromosomes" (node ​​groups) in each level, and the following fitness selection formula is used to select nodes:

[0069]

[0070] Among them, P(i) represents the selection probability of the i-th node, and N represents the number of nodes.

[0071] Step 4: Perform crossover and mutation operations of the genetic algorithm on the new node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay; the particle swarm algorithm update mechanism is shown in the following formula:

[0072] v i (t+1)=ωv i (t)+c 1 ·r 1 ·(p i -x i (t))+c 2 ·r 2 ·(g i -x i (t))

[0073] x i (t+1)=x i (t)+v i (t+1)

[0074] Among them, v i (t) is the velocity of the particle at time t; x i (t) is the position of the particle at time t; ω is the inertia weight that controls the influence of the previous iteration on the particle velocity; c 1 and c 2 are learning factors, representing the importance of individual learning and group learning; r 1 and r 2is a random number, usually in the range [0,1]; p i is the individual optimal position of the particle; g i is the global optimal position.

[0075] Step 5: After the above steps, a set of results can be obtained, but the result obtained by a global search is not necessarily the optimal solution. Therefore, steps 3 to 5 are repeated, that is, the method is iterated. After several rounds of algorithm iterations, the optimal solution of the algorithm is finally obtained, that is, the path with the largest sum of weights in the weighted graph, that is, the delay size of the circuit represented by the weighted graph. Among them, the weight size represents the circuit delay. The size represented by the sum of the path weights finally obtained in this step is the delay size of this circuit.

[0076] In order to further prove the technical effect of calculating the weighted graph path of the present invention, a comparative experiment was conducted with the existing depth-first search (DFS), and the comparison results are shown in Table 1 below:

[0077] Table 1: Comparison of the results of the weighted graph path calculated by the present invention and the traditional DFS method

[0078]

[0079] It can be seen from Table 1 that the longest path length obtained by the circuit delay calculation method based on the genetic-particle swarm hybrid algorithm of the present invention is closer to the actual length than the existing method, so the present invention effectively improves the weight calculation accuracy.

[0080] Embodiment three:

[0081] This embodiment introduces a weighted graph traversal method, the basic purpose of which is to find the longest path level by level by comparing weights. The method includes the following steps:

[0082] Step 1: Create a priority queue;

[0083] Step 2: For each node v in the weighted graph:

[0084] (1) Set the initial delay of node v to infinite: delay[v] = ∞;

[0085] (2) Set the initial path weight of node v to 0: path[v] = 0;

[0086] Step 3: Set the delay of source node s to 0: delay[s] = 0;

[0087] Step 4: Enter the queue: enqueue(s,0);

[0088] Step 5: When the priority queue is not empty:

[0089] (1) After dequeueing, point to node v: v←dequeue();

[0090] (2) Construct a set: δ←{u|e vu ∈ε};

[0091] (3) For each node u in the set:

[0092] (a) Update the delay: d new =delay[v]+e vu ;

[0093] (b) Determine the delay: If d new >delay[u], then delay[u]=d new 、path[u]=v、enqueue(u,d new ).

[0094] Embodiment 4:

[0095] This embodiment provides a circuit delay calculation system, including:

[0096] A weighted graph conversion module is configured to obtain a circuit structure and convert it into a weighted graph;

[0097] An initialization module, configured to number the nodes in the weighted graph and initialize the delay and path of the source node;

[0098] The node traversal module is configured to traverse the weighted graph using a genetic algorithm, calculate the fitness of the nodes, and select the nodes according to the fitness;

[0099] The local optimal calculation module is configured to perform crossover and mutation operations of the genetic algorithm on the node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay;

[0100] The circuit delay value calculation module is configured to iterate the calculation process using the node traversal module and the local optimal calculation module until the iteration termination condition is met, and obtain the path with the largest sum of weights in the weighted graph, and the sum of the weights of the path is the circuit delay value.

[0101] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit delay calculation method, characterized in that: The method comprises: Step 1: Obtain the circuit structure and convert it into a weighted graph; Step 2: Number the nodes in the weighted graph and initialize the delay and path of the source node; Step 3: Use a genetic algorithm to traverse the weighted graph, calculate the fitness of the nodes, and select the nodes according to the fitness; Step 4: Perform crossover and mutation operations of the genetic algorithm on the node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay; Step 5: Repeat steps 3 to 5 until the iteration termination condition is met, and obtain the path with the largest sum of weights in the weighted graph, where the sum of the weights of the path is the circuit delay value.

2. The method according to claim 1, characterized in that The step 3 comprises: Step 21: Randomly select a source node as the initial node, start traversing from the initial node, and perform traversal selection level by level. During the selection process, calculate the path fitness size; Step 22: Select nodes level by level. The node with greater fitness has greater weight. Select nodes with greater fitness as new node groups in each level, and select nodes from the new node groups according to probability.

3. The method according to claim 2, characterized in that The fitness calculation formula of the node is: Fitness(v)=max u→v (Fitness(u)+ω(u,v)) Among them, u→v represents the edge from node u to node v, and ω(u,v) represents the weight of the edge.

4. The method according to claim 2, characterized in that: The probability of node selection in step 22 is: Among them, P(i) represents the selection probability of the i-th node, and N represents the number of nodes.

5. A circuit delay calculation system, characterized in that: The system comprises: A weighted graph conversion module is configured to obtain a circuit structure and convert it into a weighted graph; An initialization module, configured to number the nodes in the weighted graph and initialize the delay and path of the source node; A node traversal module is configured to traverse the weighted graph using a genetic algorithm, calculate the fitness of the nodes, and select the nodes according to the fitness; The local optimal calculation module is configured to perform crossover and mutation operations of the genetic algorithm on the node group obtained after selection, and introduce the particle update mechanism of the particle swarm algorithm to select nodes and paths, and obtain the path with the largest sum of weights in the group, that is, the path with the longest delay; The circuit delay value calculation module is configured to iterate the calculation process using the node traversal module and the local optimal calculation module until the iteration termination condition is met, and obtain the path with the largest sum of weights in the weighted graph, and the sum of the weights of the path is the circuit delay value.

6. The circuit delay calculation system according to claim 5, characterized in that: The calculation process of the node traversal module includes: Randomly select the source node as the initial node, start traversing from the initial node, and perform traversal selection level by level. During the selection process, calculate the path fitness size. The nodes are selected level by level, the nodes with greater fitness have greater weights, and nodes with greater fitness are selected in each level as new node groups, and nodes are selected from the new node groups according to probability.

7. The circuit delay calculation system according to claim 6, characterized in that: The fitness calculation formula of the node is: Fitness(v)=max u→v (Fitness(u)+ω(u,v)) Among them, u→v represents the edge from node u to node v, and ω(u,v) represents the weight of the edge.

8. The circuit delay calculation system according to claim 6, characterized in that: The probability of each node being selected in the new node group is: Among them, P(i) represents the selection probability of the i-th node, and N represents the number of nodes.

9. A circuit delay calculation device, characterized in that: including memory and processor; The memory is used to store computer programs; The processor is used to implement the circuit delay calculation method according to any one of claims 1 to 4 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the circuit delay calculation method according to any one of claims 1 to 4 is implemented.

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