Layout optimization evaluation method, test structure, device and storage medium

Abstract

The present application relates to a layout optimization evaluation method, test structure, device and storage medium. The method includes: obtaining a first layout; constructing delay relationships corresponding to multiple types of test capacitor structures; the delay relationship includes a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure; obtaining a layout optimization type; based on the delay relationship corresponding to the layout optimization type, performing delay optimization on the first layout, and / or performing delay evaluation on the second layout; wherein the first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator. By constructing delay relationships corresponding to multiple types of test capacitor structures, and then using the delay relationship to optimize the delay of the first layout and / or perform delay evaluation on the second layout based on the layout optimization type, the performance of the ring oscillator can be evaluated more accurately, thereby improving the performance of the ring oscillator.

Description

Technical Field

[0001] The present application relates to the field of test optimization technology, and in particular to a layout optimization evaluation method, a test structure, a device and a storage medium. Background Art

[0002] In complementary metal oxide semiconductor (CMOS) digital circuits, the operating frequency and performance are strongly correlated: higher frequencies translate to better performance. CMOS refers to a technology used to manufacture large-scale integrated circuit chips, or chips made using this technology. Ring oscillators (ROs), due to their excellent compatibility with CMOS processes, are commonly used to implement frequency control in CMOS digital circuits. The RO frequency is often used to characterize the high-frequency performance of digital CMOS circuits.

[0003] In the related art, the structure of the ring oscillator is as follows: Figure 1 As shown, it consists of an odd number of inverters connected end to end. Once the RO starts oscillating, the potential between stages jumps between high and low, stabilizing at a certain frequency. Because capacitors pass AC but block DC, the interstage equivalent capacitance C (parasitic capacitance) affects the rate of change of the interstage potential during RO operation, thereby affecting the RO's operating frequency. When designing a ring oscillator, current considerations focus solely on the parasitic capacitance of the subsequent wiring. This approach fails to accurately assess the performance of the ring oscillator, resulting in poor performance. Summary of the Invention

[0004] Based on this, it is necessary to provide a layout optimization evaluation method, test structure, device and storage medium for a ring oscillator to address the above technical problems.

[0005] In a first aspect, the present application provides a layout optimization and evaluation method for a ring oscillator, the method comprising: obtaining a first layout; constructing delay relationships corresponding to multiple types of test capacitor structures; the delay relationships comprising data relationships based on the delay, capacitance value and / or structural design parameters of the test capacitor structure; obtaining a layout optimization type; based on the delay relationship corresponding to the layout optimization type, performing delay optimization on the first layout, and / or performing delay evaluation on the second layout; wherein the first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator.

[0006] In one embodiment, constructing the delay relationship corresponding to multiple types of test capacitor structures includes: constructing multiple types of multiple test capacitor structures based on the original ring oscillator, and determining the capacitance value of each of the test capacitor structures; constructing multiple test ring oscillators based on the multiple types of multiple test capacitor structures; obtaining the delay of each of the test capacitor structures based on the delay of the test ring oscillator; and constructing the delay relationship of each type of test capacitor structure based on the delay, capacitance value and / or structural design parameters corresponding to the multiple test capacitor structures of each type.

[0007] In one embodiment, multiple types of test capacitor structures are constructed based on the original ring oscillator, including constructing multiple first-type test capacitor structures based on the front-end CMOS capacitor; the structural design parameters of the first-type test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically including: the first-type test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the first-type test capacitor structure are respectively set on the gate and the metal line; the gate length of the channel in the first-type test capacitor structure is adjusted to generate multiple first-type test capacitor structures.

[0008] In one embodiment, multiple types of test capacitor structures are constructed based on the original ring oscillator, including multiple second-type test capacitor structures based on mid-segment capacitors; the structural design parameters of the second-type test capacitor structure include the number of contact holes in the mid-segment capacitor structure; specifically, the second-type test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the second-type test capacitor structure are respectively provided on the gate and the metal line; the number of contact holes in the second-type test capacitor structure is adjusted to generate multiple second-type test capacitor structures.

[0009] In one embodiment, based on the original ring oscillator, multiple types of test capacitor structures are constructed, including multiple third-type test capacitor structures for constructing back-end capacitors; the structural design parameters of the third-type test capacitor structure include the facing area between metal wires in the back-end capacitor structure; specifically, the third-type test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the first metal wire and the second metal wire are respectively arranged on the first metal wire and the second metal wire as the two ends of the third-type test capacitor structure; the facing area between the first metal wire and the second metal wire in the third-type test capacitor structure is adjusted to generate multiple third-type test capacitor structures.

[0010] In one embodiment, multiple types of test capacitor structures are constructed based on the original ring oscillator, including constructing multiple fourth-type test capacitor structures based on the front-end junction capacitor; the structural design parameters of the fourth-type test capacitor structure include the area of the doped active region in the front-end junction capacitor structure; specifically, the fourth-type test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal wire; the first substrate and the second doped active region form a PN junction, a contact hole is set on the second doped active region, and the contact hole is connected to the metal wire; wherein the first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; the two ends of the fourth-type test capacitor structure are respectively set on the first substrate and the metal wire; the area of the second doped active region in the fourth-type test capacitor structure is adjusted to generate multiple fourth-type test capacitor structures.

[0011] In one embodiment, multiple test ring oscillators are constructed based on the multiple types of test capacitor structures, respectively, including: connecting the same test capacitor structure between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; and constructing the multiple test ring oscillators by adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator. Wherein, connecting the same test capacitor structure between each interstage node of the original ring oscillator includes: connecting both ends of the test capacitor structure to the interstage node and a ground line or a power line, respectively.

[0012] In one embodiment, delay optimization is performed on the first layout based on the delay relationship corresponding to the layout optimization type, including: calculating a delay difference based on the delay of the original ring oscillator and a target delay requirement; determining at least one target delay relationship according to at least one of the layout optimization types; optimizing the structure of the original ring oscillator based on the target delay relationship and the delay difference to obtain a layout of an optimized ring oscillator; wherein the target delay relationship includes a data relationship between the delay and capacitance value of a test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, and / or a data relationship between the delay and structural design parameters of the test capacitor structure.

[0013] In one embodiment, a delay evaluation is performed on the second layout based on the delay relationship corresponding to the layout optimization type, including: determining at least one target delay relationship based on at least one of the layout optimization types; determining at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator based on the first layout and the second layout; and evaluating the delay of the optimized ring oscillator based on the target delay relationship and the structural design parameter difference to complete the delay evaluation of the second layout; wherein the target delay relationship includes a data relationship between the delay and capacitance value of the test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, and / or a data relationship between the delay and structural design parameters of the test capacitor structure.

[0014] In the second aspect, the present application also provides a performance test circuit for a ring oscillator, including multiple types of test capacitor structures; the performance test circuit is applied to the layout optimization evaluation method of the ring oscillator described in any one of the first aspects above; the test capacitor structure is based on the partial structure design of the original ring oscillator, and the partial structure includes at least one of the front-end CMOS structure, the middle-end capacitor structure, the back-end capacitor structure and the front-end junction capacitor structure.

[0015] In one embodiment, it includes a first type of test capacitor structure based on a front-end CMOS capacitor; the structural design parameters of the first type of test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically, the first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal lines; the two ends of the first type of test capacitor structure are respectively provided on the gate and the metal line; different first type of test capacitor structures have different channel gate lengths.

[0016] In one embodiment, it includes a second type of test capacitor structure based on a mid-section capacitor; the structural design parameters of the second type of test capacitor structure include the number of contact holes in the mid-section capacitor structure; specifically, the second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal lines; the two ends of the second type of test capacitor structure are respectively provided on the gate and the metal line; different second type test capacitor structures have different numbers of contact holes.

[0017] In one embodiment, a third type of test capacitor structure includes a back-end capacitor; the structural design parameters of the third type of test capacitor structure include the facing area between metal wires in the back-end capacitor structure; specifically, the third type of test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the two ends of the third type of test capacitor structure are respectively arranged on the first metal wire and the second metal wire; different third type test capacitor structures have different facing areas between the first metal wire and the second metal wire.

[0018] In one embodiment, a fourth type of test capacitor structure based on a front-end junction capacitor is included; the structural design parameters of the fourth type of test capacitor structure include the area of the doped active region in the front-end junction capacitor structure; specifically, the fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal wire; the first substrate and the second doped active region form a PN junction, a contact hole is provided on the second doped active region, and the contact hole is connected to the metal wire; wherein the first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; the two ends of the fourth type of test capacitor structure are respectively provided on the first substrate and the metal wire; different fourth type test capacitor structures have different second doped active region areas.

[0019] In one embodiment, at least one test ring oscillator is included; an identical test capacitor structure is connected between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; different test ring oscillators have different types and / or structural design parameters of the test capacitor structure connected to the original ring oscillator; wherein, connecting the identical test capacitor structure between each interstage node of the original ring oscillator includes: connecting two ends of the test capacitor structure to the interstage node and a ground line or a power line, respectively.

[0020] In the third aspect, the present application also provides a layout optimization and evaluation device for a ring oscillator, the device comprising: a first acquisition module for acquiring a first layout; a construction module for constructing delay relationships corresponding to multiple types of test capacitor structures; the delay relationship includes a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure; a second acquisition module for acquiring a layout optimization type; an optimization module for performing delay optimization on the first layout based on the delay relationship corresponding to the layout optimization type, and / or performing delay evaluation on the second layout; wherein, the first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator.

[0021] In a fourth aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the layout optimization and evaluation method for a ring oscillator according to any one of the first aspects is implemented.

[0022] In a fifth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the layout optimization and evaluation method for a ring oscillator according to any one of the first aspects.

[0023] The layout optimization evaluation method and performance test circuit of the above-mentioned ring oscillator obtains a first layout and constructs delay relationships corresponding to various types of test capacitor structures. Among them, the delay relationship includes a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure. Then, the layout optimization type is obtained, and based on the delay relationship corresponding to the layout optimization type, the first layout is delayed and / or the second layout is delayed. The first layout is the layout of the original ring oscillator, and the second layout is the layout of the optimized ring oscillator. By constructing delay relationships corresponding to various types of test capacitor structures, and then using the delay relationship to optimize the first layout and / or evaluate the delay of the second layout based on the layout optimization type, the performance of the ring oscillator can be evaluated more accurately, thereby improving the performance of the ring oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a ring oscillator in one embodiment;

[0025] Figure 2 1 is a flow chart of a layout optimization and evaluation method for a ring oscillator according to an embodiment;

[0026] Figure 3 A flowchart of a method for establishing a delay relationship in one embodiment is shown;

[0027] Figure 4 A schematic structural diagram of multiple first-type test capacitor structures in one embodiment;

[0028] Figure 5 is a schematic structural diagram of multiple second-type test capacitor structures in one embodiment;

[0029] Figure 6 A schematic structural diagram of multiple third-type test capacitor structures in one embodiment;

[0030] Figure 7 2 is a schematic structural diagram of a plurality of fourth-type test capacitor structures in one embodiment;

[0031] Figure 8 A schematic diagram of the structure of a ring oscillator for testing in one embodiment;

[0032] Figure 9 1 is a flow chart of a first layout delay optimization method according to an embodiment;

[0033] Figure 10 1 is a flow chart of a second layout delay evaluation method in one embodiment;

[0034] Figure 11 A structural block diagram of a layout optimization and evaluation device for a ring oscillator according to an embodiment;

[0035] Figure 12 is a diagram of the internal structure of a computer device in one embodiment;

[0036] Figure 13 FIG. 1 is a diagram showing the relationship between the delay and capacitance values based on four test capacitor structures in one embodiment. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0038] In complementary metal oxide semiconductor (CMOS) digital circuits, the operating frequency and performance are strongly correlated: higher frequencies translate to better performance. CMOS refers to a technology used to manufacture large-scale integrated circuit chips, or chips made using this technology. Ring oscillators (ROs), due to their excellent compatibility with CMOS processes, are commonly used to implement frequency control in CMOS digital circuits. The RO frequency is often used to characterize the high-frequency performance of digital CMOS circuits.

[0039] In the related art, the structure of the ring oscillator is as follows: Figure 1 As shown in the figure, it is composed of an odd number of inverters connected end to end. When the RO starts to oscillate, the potential between the stages will jump between high and low potentials and stabilize at a certain frequency. Due to the characteristics of capacitors passing AC and blocking DC, when the RO is working, the inter-stage equivalent capacitance C will affect the speed of change of the inter-stage potential, thereby affecting the operating frequency of the RO. When designing a ring oscillator, currently only the parasitic capacitance of the back-end connection is concerned. The inter-stage equivalent capacitance C includes not only the parasitic capacitance of the back-end connection, but also the parasitic capacitance of the middle section, the parasitic capacitance of the front section, and the junction capacitance. The parasitic capacitance of the front section, the parasitic capacitance of the middle section, and the junction capacitance also account for a large proportion of the inter-stage equivalent capacitance. Especially with the continuous advancement of process nodes, this part of the parasitic capacitance has become non-negligible.

[0040] The embodiments of the present application construct test capacitor structures corresponding to the parasitic capacitance of the rear-end connection, the parasitic capacitance of the middle section, the parasitic capacitance of the front section, and the junction capacitance, respectively, and then establish a corresponding mapping relationship based on each type of test capacitor structure. Based on this mapping relationship, guidance is provided for process optimization and design optimization of the ring oscillator, which can more accurately evaluate the performance of the ring oscillator and further improve the performance of the ring oscillator.

[0041] In one embodiment, Figure 2 As shown, a layout optimization evaluation method for a ring oscillator is provided, comprising the following steps:

[0042] Step 201: Obtain a first layout.

[0043] When performing delay optimization or delay evaluation on a ring oscillator, it is necessary to first obtain a first layout of the ring oscillator, where the first layout is the original layout of the ring oscillator, that is, the layout that has not been optimized.

[0044] Step 202: construct delay relationships corresponding to various types of test capacitor structures.

[0045] Construct delay relationships corresponding to various types of test capacitor structures, where the delay relationships can be presented in the form of curves, charts, and relationships, which are not specifically limited in this embodiment. The test capacitor structure is designed based on a partial structure of the original ring oscillator. The partial structure includes at least one of: a front-end CMOS structure, a middle-end capacitor structure, a back-end capacitor structure, and a front-end junction capacitor structure. In the semiconductor manufacturing process, the front-end layer (FEOL) involves the manufacture and formation of transistors on the wafer, including processes such as ion implantation, oxidation, thin film deposition, lithography, and etching; the middle-end layer (MOL) involves the metal interconnection connecting the devices in the front-end layer with the back-end layer, including the opening and filling of contact holes; the back-end layer (BEOL) involves the formation of metal interconnects in the chip, including processes such as metal deposition, lithography, etching, and chemical mechanical polishing (CMP). The multiple types of test capacitor structures can include at least one of a front-end CMOS test capacitor structure (i.e., front-end MOS channel parasitic capacitance Cch), a mid-end capacitor test capacitor structure (i.e., mid-end contact hole parasitic capacitance Cco), a back-end capacitor test capacitor structure (i.e., back-end connection parasitic capacitance Cbeol), and a front-end junction capacitor test capacitor structure (i.e., PN junction parasitic capacitance Cj). The delay relationship includes a data relationship based on the delay, capacitance, and / or structural design parameters of the test capacitor structure. The structural design parameters include the gate length of the channel in the front-end CMOS structure, the number of contact holes in the mid-end capacitor structure, the facing area between metal lines in the back-end capacitor structure, and the area of the doped active region in the front-end junction capacitor structure. After constructing the multiple types of test capacitor structures, multiple test ring oscillators can be constructed based on the multiple types of test capacitor structures. The delay of the test ring oscillators can then be determined based on the test ring oscillators, thereby obtaining the delay of each test capacitor structure. The capacitance value and structural design parameters of each test capacitor structure can then be determined to determine the delay relationship between the delay, capacitance, and / or structural design parameters of the test capacitor structure. The delay relationship includes: the delay relationship corresponding to the capacitance structure of the front-end CMOS, the delay relationship corresponding to the capacitance structure of the middle-end capacitor, the delay relationship corresponding to the capacitance structure of the rear-end capacitor, and the delay relationship corresponding to the capacitance structure of the front-end junction capacitor.

[0046] Step 203: Obtain layout optimization type.

[0047] When delay optimization is required for the first layout, the layout optimization type is obtained. Or for the second layout that has been optimized, the layout optimization type corresponding to the optimization is obtained. The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor. That is, the layout optimization type corresponds to the delay relationship. After determining the layout optimization type, the delay relationship corresponding to the corresponding test capacitor structure can be found.

[0048] Step 204 : Based on the delay relationship corresponding to the layout optimization type, perform delay optimization on the first layout and / or perform delay evaluation on the second layout.

[0049] Based on the layout optimization type, the corresponding delay relationship is determined. Delay optimization is performed on the first layout and / or delay evaluation is performed on the second layout based on the delay relationship. When delay optimization is required, delay optimization can be performed on the first layout, and when delay evaluation is required, delay evaluation can be performed on the second layout. Alternatively, delay optimization can be performed on the first layout and delay evaluation can be performed on the second layout simultaneously. The first layout is the layout of the original ring oscillator, and the second layout is the layout of the optimized ring oscillator.

[0050] The above embodiment obtains a first layout and constructs delay relationships corresponding to various types of test capacitor structures. The delay relationship includes a data relationship based on the delay, capacitance value and / or structural design parameters of the test capacitor structure. Then, the layout optimization type is obtained, and based on the delay relationship corresponding to the layout optimization type, the first layout is delayed and / or the second layout is delayed. The first layout is the layout of the original ring oscillator, and the second layout is the layout of the optimized ring oscillator. By constructing delay relationships corresponding to various types of test capacitor structures, and then using the delay relationship to optimize the first layout and / or evaluate the delay of the second layout based on the layout optimization type, the performance of the ring oscillator can be evaluated more accurately, thereby improving the performance of the ring oscillator.

[0051] In one embodiment, Figure 3 As shown, a method for constructing a delay relationship is provided, comprising the following steps:

[0052] Step 301 : construct multiple test capacitor structures of various types based on the original ring oscillator, and determine the capacitance value of each test capacitor structure.

[0053] Based on the above, the multiple types of test capacitor structures include at least one of a front-end CMOS test capacitor structure, a mid-end capacitor test capacitor structure, a back-end capacitor test capacitor structure, and a front-end junction capacitor test capacitor structure. Based on the original ring oscillator, multiple types of test capacitor structures are constructed, with multiple test capacitor structures of each type constructed, and the capacitance value corresponding to each test capacitor structure is determined.

[0054] For the test capacitor structure of the front-end CMOS, multiple first-class test capacitor structures based on the front-end CMOS capacitor are constructed; the structural design parameters of the first-class test capacitor structure include the gate length of the channel in the front-end CMOS structure. Specifically, Figure 4 As shown, the first type of test capacitor structure includes an active area AA, a gate, contact holes, and metal lines, used to characterize the effects of Cch capacitance. The gate partially covers the active area, forming at least one channel. Contact holes are provided at the source and drain regions at either end of the channel, each connected to a metal line. The two ends of the first type of test capacitor structure are connected to the gate and metal line, respectively. The gate length of the channel in the first type of test capacitor structure is adjusted to generate multiple first type test capacitor structures. The gate partially overlaps the active area AA, forming source and drain regions on either side of the gate. Contact holes are provided in the source and drain regions, respectively, and connected to the corresponding metal layer of the metal line. For the first type of test capacitor structure, to characterize the channel capacitance of the MOS structure's gate itself, the gate length of the channel in the first type of test capacitor structure, that is, the overlap area between the gate and AA, can be adjusted to adjust the parasitic capacitance. For the first type of test capacitor structure, multiple first type test capacitor structures are constructed with different channel gate lengths. The capacitance value of each first type test capacitor structure is obtained by testing the multiple first type test capacitor structures.

[0055] For the test capacitor structure of the mid-segment capacitor, multiple second-type test capacitor structures based on the mid-segment capacitor are constructed; the structural design parameters of the second-type test capacitor structure include the number of contact holes in the mid-segment capacitor structure. Figure 5As shown, the second type of test capacitor structure includes an active area AA, a gate, a contact hole, and a metal line, which is used to characterize the impact of Cco capacitance. The gate partially covers the active area to form at least one channel; contact holes are provided in the source and drain regions at both ends of the channel, and the contact holes are connected to metal lines for output. The two ends of the second type of test capacitor structure are provided on the gate and metal line, respectively. The number of contact holes in the second type of test capacitor structure is adjusted to generate multiple second type test capacitor structures. The gate partially overlaps with the active area AA, forming a source region and a drain region on both sides of the gate. Contact holes are provided in the source and drain regions, respectively, and are connected to the metal layer corresponding to the metal line. For the second type of test capacitor structure, a parasitic capacitance will form between the gate and the contact hole. By adjusting the number of contact holes, the magnitude of the parasitic capacitance can be adjusted. For the second type of test capacitor structure, multiple second type test capacitor structures are constructed with different numbers of contact holes. By testing a plurality of second-type test capacitor structures, a capacitance value of each second-type test capacitor structure is obtained.

[0056] For the test capacitor structure of the back-end capacitor, multiple third-type test capacitor structures of the back-end capacitor are constructed; the structural design parameters of the third-type test capacitor structure include the facing area between the metal lines in the back-end capacitor structure. Specifically, Figure 6 As shown, the third type of test capacitor structure includes a first metal line and a second metal line, which are used to characterize the impact of Cbeol capacitance. In this embodiment, the first metal line and the second metal line are two metal lines in the same metal layer. Specifically, the first metal line and the second metal line can be two metal lines in the same metal layer in the original ring oscillator. In some other embodiments, the first metal line and the second metal line can also be two metal lines in two adjacent metal layers in the original ring oscillator, which is not specifically limited in this embodiment. The two ends of the third type of test capacitor structure are respectively arranged on the first metal line and the second metal line. The area of the first metal line and the second metal line in the third type of test capacitor structure is adjusted to generate multiple third type of test capacitor structures. For the third type of test capacitor structure, parasitic capacitance is formed between the first metal line and the second metal line. By adjusting the area of the first metal line and the second metal line, the magnitude of the parasitic capacitance can be adjusted. For the third type of test capacitor structure, in order to characterize the parasitic capacitance of the downstream connection, multiple third type of test capacitor structures are constructed with different areas of the first metal line and the second metal line. By testing the multiple third type of test capacitor structures, the capacitance value of each third type of test capacitor structure is obtained.

[0057] For the test capacitor structure of the front-end junction capacitor, multiple fourth-type test capacitor structures based on the front-end junction capacitor are constructed; the structural design parameters of the fourth-type test capacitor structure include the area of the doped active region in the front-end junction capacitor structure. Specifically, Figure 7 As shown, the fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole (Contact), and a metal line (Metal) to characterize the impact of Cj capacitance. In this embodiment, the first substrate is a P-type substrate (PW pickup region), and the second doped active region is an N-type doped active region (N+ region). In other embodiments, the first substrate and the second doped active region can also be an N-type substrate (NW pickup region) and a P-type doped active region (P+ region), respectively. This application does not impose specific limitations. Generally, the design of the first substrate and the second doped active region matches the structure of the original ring oscillator. The first substrate and the second doped active region form a PN junction, and a contact hole is provided in the second doped active region and connected to the metal line. The ends of the fourth type of test capacitor structure are respectively provided on the first substrate and the metal line. The area of the second doped active region in the fourth type of test capacitor structure is adjusted to generate multiple fourth type test capacitor structures. For the fourth type of test capacitor structure, a parasitic capacitance is formed between the first substrate and the second doped active region. The magnitude of the parasitic capacitance can be adjusted by adjusting the area of the second doped active region. For the fourth type of test capacitor structure, multiple fourth type test capacitor structures are constructed with different areas of the second doped active region. The capacitance value of each fourth type test capacitor structure is obtained by testing the multiple fourth type test capacitor structures.

[0058] When determining the capacitance value of each test capacitor structure, the corresponding test capacitor structure may be input into the simulation software through simulation software, and the capacitance value of the corresponding test capacitor structure may be output.

[0059] Step 302 : constructing a plurality of test ring oscillators based on a plurality of test capacitor structures of a plurality of types.

[0060] In the above steps, a plurality of first-type test capacitor structures, a plurality of second-type test capacitor structures, a plurality of third-type test capacitor structures, and a plurality of fourth-type test capacitor structures are obtained. According to each type of test capacitor structure, a corresponding test ring oscillator is constructed, specifically including the following steps:

[0061] In step 1, the same test capacitor structure is connected between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure. This is achieved by adding external capacitors without changing the original ring oscillator structure, resulting in a simple and reliable test ring oscillator.

[0062] For example, each type includes 4 corresponding test capacitor structures. Figure 4The figure shows four first-class test capacitor structures from left to right: DOE1-DOE4; Figure 5 The following table shows four second-type test capacitor structures from left to right: DOE5-DOE8; Figure 6 The following table shows four third-type test capacitor structures from left to right: DOE9-DOE12; Figure 7 The figure shows four fourth-type test capacitor structures from left to right: DOE13-DOE16. Figure 8 As shown in the figure, the original ring oscillator ring is composed of 5 inverters connected end to end. The first interstage node is between the first inverter and the second inverter, the second interstage node is between the second inverter and the third inverter, the third interstage node is between the third inverter and the fourth inverter, the fourth interstage node is between the fourth inverter and the fifth inverter, and the fifth interstage node is between the fifth inverter and the first inverter. DOE1 can be connected to the 5 interstage nodes respectively. Figure 8 The capacitor structure shown in the dotted box is the equivalent capacitor that characterizes DOE1, forming a test ring oscillator corresponding to the first type of test capacitor structure; DOE12 can be connected to the five inter-stage nodes respectively to form a test ring oscillator corresponding to the third type of test capacitor structure; the test ring oscillators corresponding to the remaining test capacitor structures are constructed in the same way, and will not be repeated in this application.

[0063] When the test capacitor structure is connected to the ring oscillator, the two ends of the test capacitor structure are respectively connected to the interstage node, and the ground wire or the power line. That is, one end of the test capacitor structure is connected to the interstage node, and the other end is grounded or connected to the power supply. For the third type of test capacitor structure, grounding or connecting to the power supply will form different voltage directions, but the third type of test capacitor structure does not need to consider the directionality of the voltage, therefore, it can be grounded or connected to the power supply. For the first type of test capacitor structure, the second type of test capacitor structure and the fourth type of test capacitor structure, grounding or connecting to the power supply will form different voltage directions, which requires the same connection method as the corresponding structure in the original ring oscillator. If the corresponding structure in the original ring oscillator is grounded, the corresponding test capacitor structure is grounded. If the corresponding structure in the original ring oscillator is connected to the power supply, the corresponding test capacitor structure is connected to the power supply.

[0064] Step 2: construct multiple test ring oscillators accordingly by adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator.

[0065] For each type of test capacitor structure, and the multiple test capacitor structures corresponding to each type, the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator ring can be adjusted to construct multiple test ring oscillators accordingly. For example, first, DOE1 of the first type of test capacitor structure is connected to the original ring oscillator to construct the corresponding test ring oscillator; by adjusting the gate length of the channel in the front-end CMOS structure, DOE2 is connected to the original ring oscillator to construct the corresponding test ring oscillator; then, DOE3 and DOE4 are connected to the original ring oscillator in sequence to construct the corresponding test ring oscillator. By adjusting the type of test capacitor structure, DOE5 of the second type of test capacitor structure is connected to the original ring oscillator to construct the corresponding test ring oscillator; by adjusting the number of contact holes in the middle capacitor structure, DOE6 is connected to the original ring oscillator to construct the corresponding test ring oscillator; then, DOE7 and DOE8 are connected to the original ring oscillator in sequence to construct the corresponding test ring oscillator. By adjusting the type of test capacitor structure, DOE9 of the third type of test capacitor structure is connected to the original ring oscillator to construct the corresponding test ring oscillator. By adjusting the area of the metal lines in the rear-end capacitor structure, DOE10 is connected to the original ring oscillator to construct the corresponding test ring oscillator. Then, DOE11 and DOE12 are connected to the original ring oscillator to construct the corresponding test ring oscillator. By adjusting the type of test capacitor structure, DOE13 of the fourth type of test capacitor structure is connected to the original ring oscillator to construct the corresponding test ring oscillator. By adjusting the area of the doped active region in the front-end junction capacitor structure, DOE14 is connected to the original ring oscillator to construct the corresponding test ring oscillator. Then, DOE15 and DOE16 are connected to the original ring oscillator to construct the corresponding test ring oscillator. A total of 16 test ring oscillators were constructed, including: 4 test ring oscillators corresponding to the first type of test capacitor structure; 4 test ring oscillators corresponding to the second type of test capacitor structure; 4 test ring oscillators corresponding to the third type of test capacitor structure; and 4 test ring oscillators corresponding to the fourth type of test capacitor structure.

[0066] Step 303: Obtain the delay of each test capacitor structure according to the delay of the test ring oscillator.

[0067] After obtaining multiple test ring oscillators, the output frequency of each test ring oscillator is detected. Based on the output frequency of each test ring oscillator, the delay of each test ring oscillator is determined. Based on the delay of each test ring oscillator, the delay of each test capacitor structure is determined. For example, the output frequency of the test ring oscillator is detected to obtain the output frequency f. The delay T of the test ring oscillator is determined according to the formula f=1 / 2T. The delay t of each test capacitor structure is determined according to the formula t=T / n, where n is the number of test capacitor structures connected to the test ring oscillator.

[0068] Step 304 : constructing a delay relationship for each type of test capacitor structure based on the delays, capacitance values, and / or structural design parameters corresponding to the multiple test capacitor structures for each type.

[0069] The delay relationship can be a mapping relationship between the delay corresponding to the test capacitor structure and the capacitance value; it can also be a mapping relationship between the delay corresponding to the test capacitor structure and the structural design parameters; it can also be a mapping relationship between the capacitance value corresponding to the test capacitor structure and the structural design parameters; it can also be a mapping relationship between the delay, capacitance value and structural design parameters corresponding to the test capacitor structure. For example, a total of 16 test ring oscillators are constructed, including: 4 test ring oscillators corresponding to the first type of test capacitor structure; 4 test ring oscillators corresponding to the second type of test capacitor structure; 4 test ring oscillators corresponding to the third type of test capacitor structure; and 4 test ring oscillators corresponding to the fourth type of test capacitor structure. According to the delay, capacitance value and structural design parameters corresponding to the four first-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the first-category test capacitor structure; according to the delay, capacitance value and structural design parameters corresponding to the four second-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the second-category test capacitor structure; according to the delay, capacitance value and structural design parameters corresponding to the four third-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the third-category test capacitor structure; according to the delay, capacitance value and structural design parameters corresponding to the four fourth-category test capacitor structures, function fitting is performed to construct the delay relationship corresponding to the fourth-category test capacitor structure.

[0070] In the above embodiment, multiple test ring oscillators are constructed by connecting multiple test capacitor structures of various types to the original ring oscillator. Each test ring oscillator is then tested to determine the delay of each test capacitor structure, ultimately yielding a delay relationship for each type of test capacitor structure. This delay relationship enables a more accurate assessment of the performance of the ring oscillator, thereby improving the performance of the ring oscillator.

[0071] In one embodiment, Figure 9As shown, a first layout delay optimization method is provided, comprising the following steps:

[0072] Step 801 : Calculate a delay difference based on the delay of the original ring oscillator and the target delay requirement.

[0073] When optimizing the first layout, we first need to determine the delay of the original ring oscillator. The method for determining the delay of the original ring oscillator is the same as that for the test ring oscillator, so we won't go into detail here. For details, refer to the method for determining the delay of the test ring oscillator described above. We also need to determine the optimization target, or the target delay requirement. We subtract the delay of the original ring oscillator from the target delay requirement to obtain the delay difference.

[0074] Step 802: Determine at least one target delay relationship according to at least one layout optimization type.

[0075] The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor. The delay relationship includes: the delay relationship corresponding to the capacitor structure of the front-end CMOS, the delay relationship corresponding to the capacitor structure of the middle-end capacitor, the delay relationship corresponding to the capacitor structure of the back-end capacitor, and the delay relationship corresponding to the capacitor structure of the front-end junction capacitor. By using any one of the graph optimization types, the purpose of reducing delay can be achieved. Therefore, when actually optimizing, you can select any one or more layout optimization types according to actual needs, determine the corresponding delay relationship, and obtain the target delay relationship.

[0076] Step 803 : Based on the target delay relationship and the delay difference, the structure of the original ring oscillator is optimized to obtain a layout of the optimized ring oscillator.

[0077] If the target delay relationship is the delay relationship corresponding to the capacitor structure of the front-end CMOS, the gate length of the channel in the front-end CMOS structure is determined according to the delay of the original ring oscillator. Then, the target delay relationship is found according to the gate length of the channel in the front-end CMOS structure and the delay difference, and the gate length of the channel in the front-end CMOS structure is optimized to obtain the layout of the optimized ring oscillator.

[0078] If the target delay relationship is the delay relationship corresponding to the capacitance structure of the mid-section capacitor, the number of contact holes in the mid-section capacitor structure is determined according to the delay of the original ring oscillator. Then, the target delay relationship is found according to the number of contact holes in the mid-section capacitor structure and the delay difference, and the number of contact holes in the mid-section capacitor structure is optimized to obtain the layout of the optimized ring oscillator.

[0079] If the target delay relationship is the facing area between the metal wires in the rear-end capacitor structure, the facing area between the metal wires in the rear-end capacitor structure is determined based on the delay of the original ring oscillator. Then, the target delay relationship is found based on the facing area between the metal wires in the rear-end capacitor structure and the delay difference. The facing area between the metal wires in the rear-end capacitor structure is optimized to obtain the layout of the optimized ring oscillator.

[0080] If the target delay relationship is the area of the doped active region in the front-stage junction capacitor structure, the area of the doped active region in the front-stage junction capacitor structure is determined according to the delay of the original ring oscillator. Then, the target delay relationship is found according to the area of the doped active region in the front-stage junction capacitor structure and the delay difference, and the area of the doped active region in the front-stage junction capacitor structure is optimized to obtain the layout of the optimized ring oscillator.

[0081] The target delay relationship includes a data relationship between the delay and capacitance value of the test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, or a data relationship between the delay and structural design parameters of the test capacitor structure.

[0082] The target delay requirement for the first layout is determined, and a delay difference is determined. A target delay relationship is then determined based on at least one layout optimization type. The original ring oscillator is optimized based on the target delay relationship and the delay difference to obtain an optimized ring oscillator layout, thereby improving the performance of the ring oscillator.

[0083] In one embodiment, Figure 10 As shown, a second layout delay evaluation method is provided, comprising the following steps:

[0084] Step 901: Determine at least one target delay relationship according to at least one layout optimization type.

[0085] The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor. The delay relationship includes: the delay relationship corresponding to the capacitor structure of the front-end CMOS, the delay relationship corresponding to the capacitor structure of the middle-end capacitor, the delay relationship corresponding to the capacitor structure of the back-end capacitor, and the delay relationship corresponding to the capacitor structure of the front-end junction capacitor. By using any one of the graph optimization types, the purpose of reducing delay can be achieved. Therefore, when actually performing delay evaluation, select any one or more layout optimization types, determine the corresponding delay relationship, and obtain the target delay relationship.

[0086] Step 902 : determining, based on the first layout and the second layout, at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator.

[0087] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the gate length of the channel in the front-end CMOS structure, then the gate length of the channel in the front-end CMOS structure corresponding to the first layout and the gate length of the channel in the front-end CMOS structure corresponding to the second layout are determined.

[0088] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the number of contact holes in the mid-segment capacitor structure, then the number of contact holes in the mid-segment capacitor structure corresponding to the first layout and the number of contact holes in the mid-segment capacitor structure corresponding to the second layout are determined.

[0089] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the facing area between the metal wires in the back-end capacitor structure, then the facing area between the metal wires in the back-end capacitor structure corresponding to the first layout and the facing area between the metal wires in the back-end capacitor structure corresponding to the second layout are determined.

[0090] Based on the first layout and the second layout, if the structural design parameter optimized by the second layout relative to the first layout is the area of the doped active region in the front-stage junction capacitor structure, then determine the area of the doped active region in the front-stage junction capacitor structure corresponding to the first layout and the area of the doped active region in the front-stage junction capacitor structure corresponding to the second layout.

[0091] Step 903 : Based on the target delay relationship and the difference in structural design parameters, the delay of the optimized ring oscillator is evaluated to complete the delay evaluation of the second layout.

[0092] If the structural design parameter is the gate length of the channel in the front-end CMOS structure, the target delay relationship is the delay relationship corresponding to the capacitor structure of the front-end CMOS. The target delay relationship is found based on the gate length of the channel in the front-end CMOS structure corresponding to the first layout, and the delay corresponding to the first layout is determined. The target delay relationship is found based on the gate length of the channel in the front-end CMOS structure corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0093] The channel of the MOS structure gate itself in the first type of test capacitor structure will form a parasitic capacitor. Based on the gate length of the channel in the front-end CMOS structure of multiple first-type test capacitor structures, the unit capacitance introduced by the unit gate length is determined. Based on the gate length and unit capacitance of the channel in the front-end CMOS structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined. Based on the capacitance value corresponding to the first layout, the target delay relationship is searched and the delay corresponding to the first layout is determined. Based on the gate length and unit capacitance of the channel in the front-end CMOS structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined. Based on the capacitance value corresponding to the second layout, the target delay relationship is searched and the delay corresponding to the second layout is determined.

[0094] If the structural design parameter is the number of contact holes in the mid-segment capacitor structure, the target delay relationship is the delay relationship corresponding to the capacitor structure of the mid-segment capacitor. The target delay relationship is searched based on the number of contact holes in the mid-segment capacitor structure corresponding to the first layout to determine the delay corresponding to the first layout. The target delay relationship is searched based on the number of contact holes in the mid-segment capacitor structure corresponding to the second layout to determine the delay corresponding to the second layout.

[0095] In the second type of test capacitor structure, parasitic capacitance is formed between the gate and the contact hole. Based on the number of contact holes in the multiple second type test capacitor structures, the unit capacitance introduced by each contact hole is determined. Based on the number of contact holes and unit capacitance in the middle section capacitor structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined. Based on the capacitance value corresponding to the first layout, the target delay relationship is searched to determine the delay corresponding to the first layout. Based on the number of contact holes and unit capacitance in the middle section capacitor structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined. Based on the capacitance value corresponding to the second layout, the target delay relationship is searched to determine the delay corresponding to the second layout.

[0096] If the structural design parameters are for a test capacitor structure of a back-end capacitor, the target delay relationship is the delay relationship corresponding to the capacitor structure of the back-end capacitor. The target delay relationship is found based on the area of facing metal lines in the back-end capacitor structure corresponding to the first layout, and the delay corresponding to the first layout is determined. The target delay relationship is found based on the area of facing metal lines in the back-end capacitor structure corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0097] In the third type of test capacitor structure, parasitic capacitance is formed between the first and second metal wires. The capacitance value corresponding to the first layout is determined based on the facing area between the metal wires in the back-end capacitor structure corresponding to the first layout. The target delay relationship is searched based on the capacitance value corresponding to the first layout to determine the delay corresponding to the first layout. The capacitance value corresponding to the second layout is determined based on the facing area between the metal wires in the back-end capacitor structure corresponding to the second layout. The target delay relationship is searched based on the capacitance value corresponding to the second layout to determine the delay corresponding to the second layout.

[0098] If the structural design parameter is the area of the doped active region in the front-stage junction capacitor structure, the target delay relationship is the delay relationship corresponding to the capacitor structure of the front-stage junction capacitor. The target delay relationship is found based on the area of the doped active region in the front-stage junction capacitor structure corresponding to the first layout, and the delay corresponding to the first layout is determined. The target delay relationship is found based on the area of the doped active region in the front-stage junction capacitor structure corresponding to the second layout, and the delay corresponding to the second layout is determined.

[0099] The PN junction between the first substrate and the second doped active region in the fourth type of test capacitor structure forms a parasitic capacitor. Based on the area of the doped active regions in multiple fourth type test capacitor structures, the unit capacitance introduced per unit area of the doped active region is determined. Based on the area and unit capacitance of the doped active region in the front-end junction capacitor structure corresponding to the first layout, the capacitance value corresponding to the first layout is determined. Based on the capacitance value corresponding to the first layout, the target delay relationship is searched to determine the delay corresponding to the first layout. Based on the area and unit capacitance of the doped active region in the front-end junction capacitor structure corresponding to the second layout, the capacitance value corresponding to the second layout is determined. Based on the capacitance value corresponding to the second layout, the target delay relationship is searched to determine the delay corresponding to the second layout.

[0100] After determining the delay corresponding to the first layout and the delay corresponding to the second layout, the delay of the optimized ring oscillator is evaluated, thereby completing the delay evaluation of the second layout. If the delay corresponding to the second layout is less than the delay corresponding to the first layout, the performance of the optimized ring oscillator is better than the original ring oscillator.

[0101] In one specific embodiment, a layout optimization and evaluation method for a ring oscillator is provided. By disassembling the front-end CMOS structure Cch, the middle-end capacitor structure Cco, the back-end capacitor structure Cbeol, and the front-end junction capacitor structure Cj in the ring oscillator, the impact of each capacitor structure on the ring oscillator RO performance is analyzed, providing guidance for process optimization and design optimization.

[0102] The first type of test capacitor structure is Cch external capacitor. Different sizes of Cch external capacitors are added between the stages of the original ring oscillator to obtain the effect of Cch external capacitor on delay. Figure 4As shown, for the Cch external capacitor, different Cch external capacitor values are designed by changing the gate length of the channel. The same Cch external capacitor is connected to each inter-stage node of the original ring oscillator, without changing the structure of the original ring oscillator, and is achieved by additionally connecting the Cch external capacitor. The two ends of the Cch external capacitor are respectively connected between the inter-stage node (Node) and the ground line (Vss), or between the inter-stage node (Node) and the power line (Vdd). If one end is connected to the ground line (Vss) or the power line (Vdd), different voltage directions will be formed. The Cch external capacitor needs to consider the directionality of the voltage, which involves matching with N / P, and is generally designed to match the original ring oscillator structure.

[0103] The second type of test capacitor structure is Cco external capacitor. Different sizes of Cco external capacitors are added between the stages of the original ring oscillator to obtain the effect of Cco external capacitor on delay. Figure 5 As shown, for the Cco external capacitor, different Cco external capacitor values are designed by changing the number of contact holes. The same Cco external capacitor is connected to each interstage node of the original ring oscillator; without changing the structure of the original ring oscillator, it is achieved by additionally connecting the Cco external capacitor. The two ends of the Cco external capacitor are connected between the interstage node (Node) and the ground line (Vss), or between the interstage node (Node) and the power line (Vdd). If one end is connected to the ground line (Vss) or the power line (Vdd), different voltage directions will be generated. The Cco external capacitor needs to consider the directionality of the voltage and is generally designed to match the original ring oscillator structure.

[0104] The third type of test capacitor structure is Cbeol external capacitor. Different sizes of Cbeol external capacitors are added between the stages of the original ring oscillator to obtain the effect of Cbeol external capacitor on delay. Figure 6 As shown, for the Cbeol external capacitor, the parasitic capacitance value is increased by increasing the facing area between the two metal wires. Any metal layer can be selected to construct the Cbeol external capacitor. The same Cbeol external capacitor is connected to each inter-stage node of the original ring oscillator; without changing the structure of the original ring oscillator, it is achieved by additionally connecting the Cbeol external capacitor. The two ends of the Cbeol external capacitor are respectively connected between the inter-stage node (Node) and the ground line (Vss), or between the inter-stage node (Node) and the power line (Vdd). If one end is connected to the ground line (Vss) or the power line (Vdd), different voltage directions will be formed, but the Cbeol external capacitor does not need to consider the directionality of the voltage.

[0105] The fourth type of test capacitor structure is Cj external capacitor. Different sizes of Cj external capacitors are added between the stages of the original ring oscillator to obtain the effect of Cj external capacitor on delay. Figure 7 As shown, for the Cj external capacitor, the same Cj external capacitor is connected to each interstage node of the original ring oscillator; this is achieved by additionally connecting the Cj external capacitor without changing the structure of the original ring oscillator. The two ends of the Cj external capacitor are connected between the interstage node (Node) and the ground line (Vss), or between the interstage node (Node) and the power line (Vdd). One end is connected to the ground line (Vss) or the power line (Vdd), which will form different voltage directions. The Cj external capacitor needs to consider the directionality of the voltage, involving the combination with N / P, and is generally designed to match the original ring oscillator structure. Its PN junction can be a P-type substrate and an N-type doped active region, or it can be an N-type substrate and a P-type doped active region.

[0106] A total of 16 test capacitor structures were constructed, namely Cbeol1, Cbeol2, Cbeol3, Cbeol4, Cco1, Cco2, Cco3, Cco4, Cch1, Cch2, Cch3, Cch4, Cj1, Cj2, Cj3, and Cj4. First, the capacitance values of the 16 test capacitor structures were tested. Each of the 16 test capacitor structures was individually connected to the original ring oscillator, and the frequencies f of the 16 ring oscillators were determined in sequence. The delay time corresponding to the test capacitor structure was determined based on f = 1 / 2tn. Here, t is the delay time, and n is the number of stages in the ring oscillator. Based on the capacitance values and delay times corresponding to Cbeol1, Cbeol2, Cbeol3, and Cbeol4, the delay relationship corresponding to the capacitor structure of the rear-end capacitor was constructed. Based on the capacitance values and delay times corresponding to Cco1, Cco2, Cco3, and Cco4, the delay relationship corresponding to the capacitor structure of the middle-end capacitor was constructed. Based on the capacitance values and delay times of Cch1, Cch2, Cch3, and Cch4, the delay relationship corresponding to the capacitance structure of the front-end CMOS is constructed. Based on the capacitance values and delay times of Cj1, Cj2, Cj3, and Cj4, the delay relationship corresponding to the capacitance structure of the front-end junction capacitor is constructed.

[0107] For example, the delay relationship corresponding to various types of test capacitor structures is constructed, including the data relationship between the delay and capacitance value of the test capacitor structure, and the fitting line of the correlation between the delay time of each type of test capacitor structure and the capacitance of each part is made. The fitting line reflects the influence of each part of the capacitance on the delay. When fitting, all units are normalized to ps / fF. For details, please refer to Figure 13 The four delay relationships shown can be used as a reference for subsequent ring oscillator delay optimization or delay evaluation. Similarly, other delay relationships can also be constructed, and this application does not make specific limitations.

[0108] When evaluating optimization options for the optimized ring oscillator:

[0109] The impact of the external capacitor Cbeol on the ring oscillator primarily stems from the parasitic capacitance of the downstream wiring. By modifying the layout, the original ring oscillator was optimized to produce the optimized ring oscillator. Simulation software was used to determine the capacitance value Cbeol0 for each inverter in the original ring oscillator and the capacitance value Cbeolx for each inverter in the optimized ring oscillator. Based on Cbeol0 and Cbeolx, the delay relationship corresponding to the capacitance structure of the downstream capacitors was found. The delay of the ring oscillator before and after optimization was determined, allowing evaluation of the optimization solution.

[0110] The impact of the external capacitance Cco on the ring oscillator primarily stems from the parasitic capacitance between the contact and the gate. When optimizing the original ring oscillator by modifying the layout, the number of contacts in the ring oscillator layout or the distance between the contact and the gate can be adjusted to obtain the optimized ring oscillator. The capacitance Cco0 introduced by each contact is calculated based on Cco1, Cco2, Cco3, and Cco4. Based on the number of contacts n and the capacitance Cco0 in the original ring oscillator, the capacitance C1 of each inverter in the original ring oscillator is calculated by n × Cco0. Based on the number of contacts n + Δn and the distance d + Δd between the contact and the gate in the optimized ring oscillator, the capacitance C2 of each inverter in the optimized ring oscillator is calculated by Cco0 × n × [d / (d+Δd)] × [(n+Δn) / n]. The delay relationship corresponding to the capacitance structure of the middle capacitor is found based on C1 and C2, and the delay of the ring oscillator before and after optimization is determined, thereby evaluating the optimization solution.

[0111] The impact of the external Cch capacitor on the ring oscillator primarily stems from the channel capacitance of the MOS gate. When optimizing the original ring oscillator by modifying the layout, the overlap area between the gate and AA in the ring oscillator layout can be adjusted to produce the optimized ring oscillator. The capacitance Cch0 introduced per unit of gate-AA overlap area is calculated based on Cch1, Cch2, Cch3, and Cch4. Based on the overlap area s between the gate and AA in the original ring oscillator and the capacitance Cch0, the capacitance C3 of each inverter in the original ring oscillator is calculated by s×Cch0. Based on the overlap area s+Δs between the gate and AA in the optimized ring oscillator, the capacitance C4 of each inverter in the optimized ring oscillator is calculated by Cch0×s×[(s+Δs) / s]. Using C3 and C4, the delay relationship corresponding to the capacitance structure of the front-end CMOS is determined to determine the delay of the ring oscillator before and after optimization, thereby evaluating the optimization solution.

[0112] The impact of the external capacitor Cj on the ring oscillator primarily comes from the N+ / PW or P+ / NW junction capacitance. When optimizing the original ring oscillator by modifying the layout, the area of N+ or P+ in the ring oscillator layout can be adjusted to obtain the optimized ring oscillator. The capacitance Cj0 introduced per unit area of N+ or P+ can be calculated based on Cj1, Cj2, Cj3, and Cj4. Based on the area z of N+ or P+ and the capacitance Cj0 in the original ring oscillator, the capacitance C5 of each inverter in the original ring oscillator is calculated by z×Cj0. Based on the area z+Δz of N+ or P+ in the optimized ring oscillator, the capacitance C6 of each inverter in the optimized ring oscillator is calculated by Cj0×z×[(z+Δz) / z]. Based on C5 and C6, the delay relationship corresponding to the capacitance structure of the front-end junction capacitance can be found to determine the delay of the ring oscillator before and after optimization, thereby evaluating the optimization solution.

[0113] The above method is applicable to various types of ring oscillators. In addition to being applicable to ring oscillators composed of inverters, it is also applicable to ring oscillators composed of other logic gates. The above-mentioned test capacitor structures of each type are illustrated with four as an example. It is understandable that more test capacitor structures can be constructed according to actual use requirements. The more test capacitor structures of each type, the more accurate the delay relationship. For the four types of test capacitor structures, the four types of test capacitor structures can also be combined to determine the delay relationship corresponding to the combination.

[0114] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0115] Based on the same inventive concept, embodiments of the present application also provide a ring oscillator performance test circuit, which is used to implement the aforementioned ring oscillator layout optimization and evaluation method. The implementation solution provided by the ring oscillator performance test circuit is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of the one or more ring oscillator performance test circuit embodiments provided below can be found in the above-mentioned limitations of the ring oscillator layout optimization and evaluation method, and will not be repeated here.

[0116] In one embodiment, a performance test circuit for a ring oscillator is provided, comprising multiple types of test capacitor structures; the test capacitor structures are designed based on a partial structure of an original ring oscillator, the partial structures comprising at least one of a front-end CMOS structure, a mid-end capacitor structure, a back-end capacitor structure, and a front-end junction capacitor structure.

[0117] In one embodiment, Figure 4 As shown, a first type of test capacitor structure based on a front-end CMOS capacitor; the structural design parameters of the first type of test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically, the first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal lines; the two ends of the first type of test capacitor structure are respectively set on the gate and the metal line; different first type of test capacitor structures have different channel gate lengths.

[0118] In one embodiment, Figure 5As shown, a second type of test capacitor structure based on a mid-section capacitor; the structural design parameters of the second type of test capacitor structure include the number of contact holes in the mid-section capacitor structure; specifically, the second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the second type of test capacitor structure are respectively set on the gate and the metal line; different second type test capacitor structures have different numbers of contact holes.

[0119] In one embodiment, Figure 6 As shown, a third type of test capacitor structure of a back-end capacitor; the structural design parameters of the third type of test capacitor structure include the facing area between the metal wires in the back-end capacitor structure; specifically, the third type of test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the two ends of the third type of test capacitor structure are respectively arranged on the first metal wire and the second metal wire; different third type test capacitor structures have different facing areas between the first metal wire and the second metal wire.

[0120] In one embodiment, Figure 7 As shown, a fourth type of test capacitor structure based on the front-end junction capacitor; the structural design parameters of the fourth type of test capacitor structure include the area of the doped active area in the front-end junction capacitor structure; specifically including: the fourth type of test capacitor structure includes a first substrate, a second doped active area, a contact hole and a metal wire; the first substrate and the second doped active area form a PN junction, a contact hole is set on the second doped active area, and the contact hole is connected to the metal wire; wherein, the first substrate and the second doped active area are a P-type substrate and an N-type doped active area, or an N-type substrate and a P-type doped active area; and the design of the first substrate and the second doped active area matches the structure of the original ring oscillator; the two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal wire; different fourth type test capacitor structures have different second doped active area areas.

[0121] In one embodiment, at least one test ring oscillator is included; an identical test capacitor structure is connected between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; different test ring oscillators have different types and / or structural design parameters of the test capacitor structure connected to the original ring oscillator; wherein, connecting the identical test capacitor structure between each interstage node of the original ring oscillator includes: connecting two ends of the test capacitor structure to the interstage node and a ground line or a power line, respectively.

[0122] In one embodiment, the performance test circuit of the ring oscillator is used in the layout optimization evaluation method of the ring oscillator described in any of the above embodiments.

[0123] Based on the same inventive concept, embodiments of the present application also provide a layout optimization and evaluation device for a ring oscillator for implementing the aforementioned layout optimization and evaluation method for a ring oscillator. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of the embodiments of the layout optimization and evaluation device for one or more ring oscillators provided below can be found in the aforementioned limitations of the layout optimization and evaluation method for a ring oscillator, and will not be repeated here.

[0124] In one embodiment, Figure 11 As shown, a layout optimization and evaluation device for a ring oscillator is provided, comprising: a first acquisition module 100, a construction module 200, a second acquisition module 300 and an optimization module 400, wherein:

[0125] A first acquisition module 100 is used to acquire a first layout;

[0126] A construction module 200 is configured to construct delay relationships corresponding to various types of test capacitor structures; the delay relationships include data relationships based on delays, capacitance values, and / or structural design parameters of the test capacitor structures;

[0127] The second acquisition module 300 is used to obtain the layout optimization type;

[0128] An optimization module 400 is configured to perform delay optimization on the first layout and / or delay evaluation on the second layout based on the delay relationship corresponding to the layout optimization type; wherein the first layout is the layout of the original ring oscillator; and the second layout is the layout of the optimized ring oscillator.

[0129] Construction module 200 is further configured to construct multiple test capacitor structures of various types based on the original ring oscillator, and determine the capacitance value of each test capacitor structure; construct multiple test ring oscillators corresponding to the multiple test capacitor structures of various types; obtain the delay of each test capacitor structure based on the delay of the test ring oscillator; and construct a delay relationship for each type of test capacitor structure based on the delay, capacitance value, and / or structural design parameters corresponding to each type of test capacitor structure.

[0130] Construction module 200 is also used to construct multiple first-class test capacitor structures based on the front-end CMOS capacitor; the structural design parameters of the first-class test capacitor structure include the gate length of the channel in the front-end CMOS structure; specifically including: the first-class test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set at the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the first-class test capacitor structure are respectively set on the gate and the metal line; the gate length of the channel in the first-class test capacitor structure is adjusted to generate multiple first-class test capacitor structures.

[0131] Construction module 200 is also used to construct multiple second-type test capacitor structures based on mid-section capacitors; the structural design parameters of the second-type test capacitor structures include the number of contact holes in the mid-section capacitor structure; specifically including: the second-type test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate portion covers the active area to form at least one channel; contact holes are respectively set in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal wires; the two ends of the second-type test capacitor structure are respectively set on the gate and the metal line; the number of contact holes in the second-type test capacitor structure is adjusted to generate multiple second-type test capacitor structures.

[0132] The construction module 200 is also used to construct multiple third-type test capacitor structures of the back-end capacitor; the structural design parameters of the third-type test capacitor structure include the facing area between the metal wires in the back-end capacitor structure; specifically including: the third-type test capacitor structure includes a first metal wire and a second metal wire; wherein the first metal wire and the second metal wire are two metal wires of a metal layer included in the original ring oscillator, or metal wires of two adjacent metal layers included in the original ring oscillator; the two ends of the third-type test capacitor structure are respectively arranged on the first metal wire and the second metal wire; the facing area between the first metal wire and the second metal wire in the third-type test capacitor structure is adjusted to generate multiple third-type test capacitor structures.

[0133] Construction module 200 is also used to construct multiple fourth-type test capacitor structures based on the front-end junction capacitor; the structural design parameters of the fourth-type test capacitor structure include the area of the doped active area in the front-end junction capacitor structure; specifically including: the fourth-type test capacitor structure includes a first substrate, a second doped active area, a contact hole and a metal wire; the first substrate and the second doped active area form a PN junction, a contact hole is set on the second doped active area, and the contact hole is connected to the metal wire; wherein, the first substrate and the second doped active area are a P-type substrate and an N-type doped active area, or an N-type substrate and a P-type doped active area; and the design of the first substrate and the second doped active area matches the structure of the original ring oscillator; the two ends of the fourth-type test capacitor structure are respectively set on the first substrate and the metal wire; the area of the second doped active area in the fourth-type test capacitor structure is adjusted to generate multiple fourth-type test capacitor structures.

[0134] Construction module 200 is further configured to connect an identical test capacitor structure between each interstage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; and to construct multiple corresponding test ring oscillators by adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator. Connecting an identical test capacitor structure between each interstage node of the original ring oscillator includes connecting two ends of the test capacitor structure to the interstage node and a ground line or a power line, respectively.

[0135] The optimization module 400 is further configured to calculate a delay difference based on the delay of the original ring oscillator and a target delay requirement; determine at least one target delay relationship based on at least one of the layout optimization types; and optimize the structure of the original ring oscillator based on the target delay relationship and the delay difference to obtain a layout of an optimized ring oscillator. The target delay relationship may include a data relationship between the delay and capacitance value of a test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, and / or a data relationship between the delay and structural design parameters of the test capacitor structure.

[0136] Optimization module 400 is further configured to determine at least one target delay relationship based on at least one layout optimization type; determine at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator based on the first layout and the second layout; and evaluate the delay of the optimized ring oscillator based on the target delay relationship and the structural design parameter difference to complete the delay evaluation of the second layout; wherein the target delay relationship includes a data relationship between the delay and capacitance value of the test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, and / or a data relationship between the delay and structural design parameters of the test capacitor structure.

[0137] Each module in the aforementioned ring oscillator layout optimization and evaluation device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0138] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 12 As shown. The computer device includes a processor, memory, communication interface, display screen and input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner. The wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, it implements a layout optimization evaluation method for a ring oscillator.

[0139] Those skilled in the art will understand that Figure 12 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0140] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements any one of the above-mentioned ring oscillator layout optimization evaluation methods.

[0141] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the layout optimization evaluation method for a ring oscillator according to any one of the above embodiments is implemented.

[0142] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0143] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A layout optimization evaluation method for a ring oscillator, characterized in that: The method comprises: Get the first version; Constructing delay relationships corresponding to various types of test capacitor structures; the delay relationships include data relationships based on delay, capacitance value, and / or structural design parameters of the test capacitor structure; Get layout optimization type; Based on the delay relationship corresponding to the layout optimization type, performing delay optimization on the first layout, and / or performing delay evaluation on the second layout; The first layout is the layout of the original ring oscillator; the second layout is the layout of the optimized ring oscillator; The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor.

2. The method according to claim 1, characterized in that The delay relationships corresponding to the various types of test capacitor structures are constructed as follows: constructing a plurality of test capacitor structures of various types based on the original ring oscillator, and determining a capacitance value of each of the test capacitor structures; Based on the multiple types of test capacitor structures, constructing multiple test ring oscillators respectively; Obtaining the delay of each of the test capacitor structures according to the delay of the test ring oscillator; Based on the delays, capacitance values and / or structural design parameters corresponding to the multiple test capacitor structures of each type, a delay relationship of each type of the test capacitor structure is constructed.

3. The method according to claim 2, characterized in that The method comprises constructing a plurality of test capacitor structures of various types based on the original ring oscillator, including constructing a plurality of first-type test capacitor structures based on the front-end CMOS capacitors; the structural design parameters of the first-type test capacitor structures include the gate length of the channel in the front-end CMOS structure; The first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line; The two ends of the first type of test capacitor structure are respectively arranged on the gate and the metal line; The gate length of the channel in the first-type test capacitor structure is adjusted to generate a plurality of the first-type test capacitor structures.

4. The method according to claim 2, characterized in that The method comprises constructing a plurality of test capacitor structures of various types based on the original ring oscillator, including constructing a plurality of second-type test capacitor structures based on the mid-segment capacitor; the structural design parameters of the second-type test capacitor structures include the number of contact holes in the mid-segment capacitor structure; The second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line; The two ends of the second type of test capacitor structure are respectively arranged on the gate and the metal line; The number of contact holes in the second-type test capacitor structure is adjusted to generate a plurality of the second-type test capacitor structures.

5. The method according to claim 2, characterized in that Based on the original ring oscillator, multiple types of test capacitor structures are constructed, including multiple third-type test capacitor structures for back-end capacitors; the structural design parameters of the third-type test capacitor structures include the facing area between metal wires in the back-end capacitor structures; The third type of test capacitor structure includes a first metal line and a second metal line; The first metal wire and the second metal wire are two metal wires in one metal layer included in the original ring oscillator, or metal wires in two adjacent metal layers included in the original ring oscillator; Two ends of the third type test capacitor structure are respectively arranged on the first metal line and the second metal line; The facing area between the first metal line and the second metal line in the third type test capacitor structure is adjusted to generate a plurality of the third type test capacitor structures.

6. The method according to claim 2, characterized in that The method comprises constructing multiple types of test capacitor structures based on the original ring oscillator, including constructing multiple fourth-type test capacitor structures based on the front-end junction capacitor; the structural design parameters of the fourth-type test capacitor structure include the area of the doped active region in the front-end junction capacitor structure; The fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal line; the first substrate and the second doped active region form a PN junction, a contact hole is provided on the second doped active region, and the contact hole is connected to the metal line; The first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; Two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal line; The area of the second doped active region in the fourth type test capacitor structure is adjusted to generate a plurality of the fourth type test capacitor structures.

7. The method according to claim 2, characterized in that Based on the multiple types of test capacitor structures, multiple test ring oscillators are constructed respectively, including: Connecting the same test capacitor structure between each inter-stage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; By adjusting the type and / or structural design parameters of the test capacitor structure connected to the original ring oscillator, a plurality of test ring oscillators are constructed accordingly; The same test capacitor structure is connected between each inter-stage node of the original ring oscillator, including: connecting two ends of the test capacitor structure to the inter-stage node and a ground line or a power line respectively.

8. The method according to claim 1, characterized in that Performing delay optimization on the first layout based on the delay relationship corresponding to the layout optimization type includes: Calculate the delay difference based on the delay of the original ring oscillator and the target delay requirement; Determining at least one target delay relationship according to at least one of the layout optimization types; Based on the target delay relationship and the delay difference, optimizing the structure of the original ring oscillator to obtain a layout of the optimized ring oscillator; Among them, the target delay relationship includes a data relationship between the delay and capacitance value of the test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, and / or a data relationship between the delay and structural design parameters of the test capacitor structure.

9. The method according to claim 1, characterized in that Based on the delay relationship corresponding to the layout optimization type, performing delay evaluation on the second layout includes: Determining at least one target delay relationship according to at least one of the layout optimization types; determining, based on the first layout and the second layout, at least one type of structural design parameter difference between the optimized ring oscillator and the original ring oscillator; Based on the target delay relationship and the difference in structural design parameters, evaluating the delay of the optimized ring oscillator to complete the delay evaluation of the second layout; Among them, the target delay relationship includes a data relationship between the delay and capacitance value of the test capacitor structure, a data relationship between the capacitance value and structural design parameters of the test capacitor structure, and / or a data relationship between the delay and structural design parameters of the test capacitor structure.

10. A performance test circuit for a ring oscillator, characterized in that: Comprising multiple types of test capacitor structures; a layout optimization evaluation method for a ring oscillator as claimed in any one of claims 1 to 9; The test capacitor structure is designed based on a partial structure of the original ring oscillator, and the partial structure includes at least one of a front-end CMOS structure, a middle-end capacitor structure, a back-end capacitor structure, and a front-end junction capacitor structure.

11. The performance test circuit according to claim 10, characterized in that: The invention comprises a first type of test capacitor structure based on a front-end CMOS capacitor; the structural design parameters of the first type of test capacitor structure include a gate length of a channel in the front-end CMOS structure; The first type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line; The two ends of the first type of test capacitor structure are respectively arranged on the gate and the metal line; Different first-type test capacitor structures have different channel gate lengths.

12. The performance test circuit according to claim 10, characterized in that: A second type of test capacitor structure based on a mid-segment capacitor is included; the structural design parameters of the second type of test capacitor structure include the number of contact holes in the mid-segment capacitor structure; The second type of test capacitor structure includes an active area, a gate, a contact hole and a metal line; the gate partially covers the active area to form at least one channel; contact holes are respectively provided in the source region and the drain region at both ends of the channel, and the contact holes are connected to the metal line; The two ends of the second type of test capacitor structure are respectively arranged on the gate and the metal line; Different second-type test capacitor structures have different numbers of contact holes.

13. The performance test circuit according to claim 10, characterized in that: A third type of test capacitor structure including a back-end capacitor; the structural design parameters of the third type of test capacitor structure include the facing area between metal lines in the back-end capacitor structure; The third type of test capacitor structure includes a first metal line and a second metal line; The first metal wire and the second metal wire are two metal wires in one metal layer included in the original ring oscillator, or metal wires in two adjacent metal layers included in the original ring oscillator; Two ends of the third type test capacitor structure are respectively arranged on the first metal line and the second metal line; Different third-type test capacitor structures have different facing areas between the first metal line and the second metal line.

14. The performance test circuit according to claim 10, characterized in that: A fourth type of test capacitor structure based on a front-end junction capacitor is included; the structural design parameters of the fourth type of test capacitor structure include the area of the doped active region in the front-end junction capacitor structure; The fourth type of test capacitor structure includes a first substrate, a second doped active region, a contact hole and a metal line; the first substrate and the second doped active region form a PN junction, a contact hole is provided on the second doped active region, and the contact hole is connected to the metal line; The first substrate and the second doped active region are a P-type substrate and an N-type doped active region, or an N-type substrate and a P-type doped active region; and the design of the first substrate and the second doped active region matches the structure of the original ring oscillator; Two ends of the fourth type of test capacitor structure are respectively arranged on the first substrate and the metal line; Different fourth-type test capacitor structures have different second doped active region areas.

15. The performance test circuit according to claim 10, characterized in that: including at least one test ring oscillator; Connecting the same test capacitor structure between each inter-stage node of the original ring oscillator to form a test ring oscillator corresponding to the test capacitor structure; Different test ring oscillators have different types and / or structural design parameters of the test capacitor structure connected to the original ring oscillator; The same test capacitor structure is connected between each inter-stage node of the original ring oscillator, including: connecting two ends of the test capacitor structure to the inter-stage node and a ground line or a power line respectively.

16. A layout optimization and evaluation device for a ring oscillator, characterized in that: The device comprises: A first acquisition module, used to acquire a first layout; A construction module for constructing delay relationships corresponding to various types of test capacitor structures; the delay relationships include data relationships based on delay, capacitance value, and / or structural design parameters of the test capacitor structure; The second acquisition module is used to obtain the layout optimization type; an optimization module, configured to perform delay optimization on the first layout and / or perform delay evaluation on the second layout based on the delay relationship corresponding to the layout optimization type; wherein the first layout is the layout of the original ring oscillator; and the second layout is the layout of the optimized ring oscillator; The layout optimization types include: layout optimization type for the capacitor structure of the front-end CMOS, layout optimization type for the capacitor structure of the middle-end capacitor, layout optimization type for the capacitor structure of the back-end capacitor, and layout optimization type for the capacitor structure of the front-end junction capacitor.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 9 is implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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