Automatic layout method and device for transistors in standard cell and storage medium

Abstract

The invention belongs to the related technical field of layout design, and discloses an automatic layout method and device for transistors in a standard cell and a storage medium, and the method comprises the steps: obtaining transistor information; the method comprises the following steps of: pairing common-gate NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor), if remaining unpaired transistors exist, arranging virtual transistors to be paired with the remaining unpaired transistors, respectively arranging the NMOS and the PMOS in different sequences, and randomly initializing the sequences but ensuring that the paired transistors are always aligned in positions in the sequences; a hill climbing algorithm is executed, the self-adaptive initial layout of the sequence is obtained, the self-adaptive initial temperature T of the sequence is calculated according to the formula T = 2 * S / U, in the formula, S is the accumulation of the score variation obtained in each hill climbing, U is the hill climbing frequency, and the layout score is the weighted sum of the transistor layout indexes; and executing a simulated annealing algorithm to obtain a final layout of the sequence. According to the method, by conducting transistor pairing and improving the optimization algorithm, the layout success rate can be increased, the layout effect is guaranteed, the algorithm convergence time is shortened, and rapid layout is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field related to layout design, and more specifically, relates to an automatic layout method, device and storage medium for transistors in a standard cell. Background Art

[0002] The standard cell library includes layout library, symbol library, circuit logic library, etc., which is the basic part of the back-end design process of integrated circuit chips. Using pre-designed optimized library cells for automatic logic synthesis and layout layout and routing can greatly improve design efficiency.

[0003] In the layout, the layout of transistors is usually involved, that is, the formation of transistor standard units. Currently, it is generally designed semi-automatically through EDA tools. This process requires manual adjustment, which is time-consuming and labor-intensive.

[0004] Therefore, it is necessary to propose an automatic layout method to achieve fast layout of transistors in standard cells and ensure local effects. Summary of the invention

[0005] In view of the above defects or improvement needs of the prior art, the present invention provides a method, device and storage medium for automatic layout of transistors in a standard cell, the purpose of which is to realize automatic layout of transistors and improve layout efficiency on the basis of satisfying the connection characteristics of transistors.

[0006] To achieve the above object, the present invention provides an automatic layout method of transistors in a standard cell, which comprises: Step S1, obtaining information of each NMOS transistor and PMOS transistor to be laid out; Step S2, pairing the NMOS transistors and PMOS transistors with a common gate, and if there are any unpaired transistors, setting virtual transistors to pair with them, placing the NMOS transistors and PMOS transistors in different sequences respectively, randomly initializing the positions of the transistors in the sequences but ensuring that the positions of the paired transistors in the sequences are always aligned; Step S3, taking the sequence layout as the optimization object and the highest layout score as the optimization goal, executing the hill climbing algorithm to obtain the adaptive initial layout of the sequence, and calculating the adaptive initial temperature of the sequence T=2*S÷U, where S is the accumulation of the score change obtained by each hill climbing, U is the number of hill climbing times, and the layout score is the weighted sum of the transistor layout indicators; Step S4, executing a simulated annealing algorithm based on the adaptive initial layout and the adaptive initial temperature to obtain a final layout of the sequence; Step S5: Using the arrangement of transistors in the sequence as the layout of transistors.

[0007] Optionally, in step S4, several rounds of tentative simulated annealing algorithms are first executed, and the layout with the highest layout score is used as the initial solution and the simulated annealing algorithm is continued to be executed until the end.

[0008] Optionally, five rounds of a heuristic simulated annealing algorithm are performed first.

[0009] Optionally, in step S4, the process of executing the simulated annealing algorithm includes: Step S41: take the current layout of the sequence as the current solution i, and set the optimal solution S=i; Step S42: Perturb the current solution i to obtain a new solution j. If the score f(j)>f(i), accept the new solution j and update S=j. Otherwise, calculate the probability P=e ([f(j)-f(i)] / t) And generate a random number greater than 0 and less than 1. If the random number is less than P, the new solution j is accepted; t is the current temperature; Step S43: lowering the temperature t; Step S44: Repeat steps S42 to S43 until the temperature t is lower than the termination temperature or the solution converges, and output the optimal solution.

[0010] Optionally, the disturbance includes rotating the transistor by 180°, exchanging the position of the transistor, or moving the position of the transistor.

[0011] Optionally, if there are transistors whose width exceeds the standard cell size, their width is folded to fit the standard cell size.

[0012] Optionally, step S5 includes: taking the arrangement of transistors in the sequence as the layout of the transistors to obtain the layout information of the transistors, writing the layout information of the transistors, the transistor connection information and the netlist node connection information into a file in json format to obtain a json format file of the layout.

[0013] Optionally, the layout indicators include area, line length, pin accessibility, layout symmetry, layout regularity, and program running time.

[0014] The present invention also provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0016] In general, compared with the prior art, the above technical solutions conceived by the present invention mainly have the following beneficial effects: 1. The transistor automatic layout method proposed in the present invention, on the one hand, before performing layout optimization through the optimization algorithm, the positions of the transistors with a common gate are always aligned through pairing. This constraint can fully ensure that the transistors with a common gate share the same gate network in the final layout result, meet the requirements of the actual standard unit for transistor layout, and improve the layout success rate. On the other hand, when performing layout optimization, the hill climbing algorithm and the simulated annealing algorithm are combined. The situation of the transistors of the current standard unit to be constructed is first understood through the hill climbing algorithm, and the data in the hill climbing process is recorded. Based on the data of the hill climbing algorithm, an adaptive initial temperature that can adapt to the current transistor situation is calculated and used as the temperature starting point of the simulated annealing algorithm. In particular, the setting of the adaptive temperature starting point can adjust the overall probability of accepting the difference solution in the simulated annealing process to be close to P=e -0.5 Compared with the traditional simulated annealing process, which sets the initial temperature very high and causes the probability of accepting a differential solution to be close to 1, the present invention enhances the randomness of accepting a differential solution and will not be overly biased towards accepting a differential solution. Compared with the traditional algorithm, the present invention has a shorter convergence time when executing the simulated annealing algorithm, a higher efficiency, and a better layout effect; 2. Optionally, the simulated annealing algorithm is executed twice in succession. By exploring the initial solution, the layout score convergence in the iteration process can be made relatively stable, with little or no large fluctuation, thereby further accelerating the convergence speed; 3. Optionally, if there are transistors whose width exceeds the size of the standard cell, their width is folded to fit the size of the standard cell, thereby reducing the area waste of the standard cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flowchart of the steps of an automatic layout method in one embodiment of the present invention.

[0018] Figure 2 is a flow chart of the steps of a simulated annealing algorithm in one embodiment of the present invention.

[0019] Figure 3 This is a disturbance method in one embodiment of the present invention.

[0020] Figure 4 It is the relationship curve between temperature and probability in the simulated annealing algorithm.

[0021] Figure 5 FIG. 4 is a diagram showing the change of the placement score during the simulated annealing algorithm in an embodiment of the present invention.

[0022] Figure 6 FIG. 4 is a visualized image of a standard cell obtained according to an embodiment of the present invention.

[0023] Figure 7 The following is a comparison of the layout results using the method of the present invention and traditional tools. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] The present invention provides an automatic layout method for transistors in a standard cell, such as Figure 1 The figure is a flow chart of the steps of the automatic layout method in one embodiment of the present invention, and the steps are introduced below.

[0026] Step S1, obtaining information of each NMOS transistor and PMOS transistor to be laid out.

[0027] Specifically, before constructing a standard unit of transistors, it is necessary to first clarify the information of each transistor, that is, the number of transistors, the parameters of each transistor, the electrical connection relationship between transistors, etc. After clarifying the above information, all transistors are optimized and laid out to obtain a standard unit of transistors.

[0028] In specific operations, the parser can be used to read the netlist information in the data path and interpret the information of each transistor.

[0029] Step S2, pairing the NMOS transistors and PMOS transistors with a common gate, and if there are any remaining unpaired transistors, setting virtual transistors to pair with them, placing the NMOS transistors and PMOS transistors in different sequences respectively, randomly initializing the position of each transistor in the sequence but ensuring that the positions of the paired transistors in the sequence are always aligned.

[0030] When constructing a transistor standard cell, it is usually arranged in two horizontal rows, with PMOS transistors placed in the first row and NMOS transistors placed in the second row. The horizontal direction is defined as the X direction and the vertical direction is defined as the Y direction. The upper and lower transistors are aligned along the Y direction.

[0031] The key to constructing a standard library is to determine the position of each PMOS transistor in the first row and the position of each NMOS transistor in the second row, that is, to optimize the layout of the transistor positions.

[0032] Therefore, the present invention constructs two sequences, the first sequence is the arrangement order of PMOS transistors, and the second sequence is the arrangement order of NMOS transistors. Before initializing the sequence, the present invention first pairs the transistors according to the electrical connection relationship of the transistors, pairs the NMOS transistors with the PMOS transistors with the common gate, and if there are remaining unpaired transistors, sets virtual transistors to pair with them, even if all transistors are paired, each pair has two transistors. During the subsequent initialization and layout optimization, the positions of the two transistors with a pairing relationship in the two sequences are always aligned. For example, the first PMOS transistor and the first NMOS transistor are in a pairing relationship, then the position of the first PMOS transistor in the first sequence is always the same as the position of the first NMOS transistor in the second sequence, which is called a dual arrangement in the present invention. Since the gate connection relationship of transistors usually appears in pairs, each transistor corresponds to a gate line network. In specific operations, each gate line network can be traversed. If the gate line network is an even number, they are paired in pairs according to the circuit connection relationship and placed in relative positions in the two sequences; if it is an odd number, they are first paired in pairs according to the circuit connection relationship, and the remaining transistors and virtual transistors that have no pairing relationship are paired, and the gate of the virtual transistor is set to the gate of the transistor with which it is paired.

[0033] If the transistors are randomly placed in two sequences at the beginning, and the consistency of the gate lines of the two transistors at the same X coordinate position is added as the optimization target in the subsequent optimization algorithm, there is a high probability that the result of the dual arrangement will not be obtained in the end, and the burden of the subsequent optimization algorithm will be increased. Therefore, the present invention proposes a transistor pairing algorithm and a virtual transistor method, which can improve the quality of the optimization solution and reduce the search space of the optimization algorithm, speed up the efficiency of the subsequent algorithm optimization, and improve the quality of the final solution.

[0034] In one embodiment, the transistor is also pre-processed. Before the physical design, the height of the standard cell (the height direction corresponds to the width direction of the transistor) has been determined. Some transistors with large widths cannot be placed in the standard cell, or standard cells with larger heights are required, resulting in area waste. In this embodiment, these transistors are folded along the width direction to adapt their width to the height of the standard cell. In this way, area waste can be reduced, and all information of the folded transistor is consistent with the original transistor information except for the width information.

[0035] In one embodiment, in order to obtain a layout that shares more active areas and reduce the layout area, when folding transistors, transistors with larger widths will be folded. When folding into n ≥ 3 segments is required, at least n-1 segments have the same width. For example, the height of a standard unit is 240nm, and a 550nm transistor needs to be folded into 3 fingers, where two fingers have the same width, for example, it can be split into two 215nm fingers and one 120nm finger.

[0036] The two sequences are randomly initialized, but the positions of the paired transistors in the sequences are guaranteed to be always aligned, and then enter the subsequent layout optimization algorithm.

[0037] Step S3, taking the sequence layout as the optimization object and the highest layout score as the optimization goal, executing the hill climbing algorithm to obtain the adaptive initial layout of the sequence, and calculating the adaptive initial temperature of the sequence T=2*S÷U, where S is the accumulation of the score change obtained by each hill climbing, U is the number of hill climbing times, and the layout score is the weighted sum of the transistor layout indicators.

[0038] Specifically, before optimizing the layout, it is necessary to determine the indicators for judging the quality of the layout, and to construct the optimization target based on the evaluation indicators. In the present invention, the weighted sum of the optimization indicators based on the transistors is performed to obtain the layout score, and the optimization target is to maximize the layout score. The indicators can be flexibly selected according to the actual situation.

[0039] For example, the indicators that can be selected include: area ws, line length bs, pin accessibility ps, layout symmetric symmetric, layout regularity drc, and program running time rs.

[0040] In this step, the sequence layout is taken as the optimization object, the layout is used to obtain the highest optimization target, the hill climbing algorithm is executed to obtain the adaptive initial layout of the sequence, and the adaptive initial temperature of the sequence is calculated at the same time T=2*S÷U, where S is the cumulative score change of each hill climbing execution, and U is the number of hill climbing times.

[0041] The hill climbing algorithm simulates the process of hill climbing, starting from the initial point and continuously moving to a higher point (i.e., a better solution) until a local maximum point (i.e., a local optimal solution) is reached. In the present invention, the random initialization in step S2 can be optimized by the hill climbing algorithm to obtain a relatively good initial solution. In addition, by recording the hill climbing data, the change in the layout score is calculated each time the hill climbs, and the cumulative change in the score during the entire hill climbing process is calculated. Based on the cumulative change in the score and the number of hill climbing times U, an adaptive initial temperature T=2*S÷U is calculated, and the adaptive initial layout obtained by hill climbing is used as the starting point of the subsequent simulated annealing algorithm, and the adaptive initial temperature is used as the initial temperature of the subsequent simulated annealing algorithm.

[0042] Step S4: Based on the adaptive initial layout and the adaptive initial temperature, a simulated annealing algorithm is executed to obtain a final layout of the sequence.

[0043] The simulated annealing algorithm is a probability-based algorithm derived from the principle of solid annealing. It simulates the process of reaching equilibrium at each temperature and finally reaching the ground state at room temperature, with the internal energy reduced to a minimum, by heating the solid to a sufficiently high temperature and then letting it cool slowly.

[0044] Specifically in this scenario, Figure 2 As shown, the specific process of the simulated annealing algorithm is as follows: Step S41: Take the current layout of the sequence as the current solution i, and let the optimal solution S=i.

[0045] Step S42: Perturb the current solution i to obtain a new solution j. If the score f(j)>f(i), accept the new solution j and update S=j. Otherwise, calculate the probability P=exp([f(j)-f(i)] / t) and generate a random number greater than 0 and less than 1. If the random number is less than P, accept the new solution j. t is the current temperature.

[0046] In one embodiment, the perturbation is to adjust the layout of the sequence, for example, Figure 3 Rotation, exchange, movement, etc. as shown.

[0047] Step S43: lowering the temperature t.

[0048] Step S44: Repeat steps S42 to S43 until the temperature t is lower than the termination temperature or the solution converges, and output the optimal solution.

[0049] In the traditional simulated annealing algorithm, in order to find the optimal solution, the initial temperature of the simulated annealing algorithm is usually set very high, and the probability P is close to 1, and then the temperature is gradually lowered to find the optimal solution. However, since the temperature is very high, the process of gradually lowering the temperature to the termination temperature is very slow, that is, the algorithm convergence process is very slow and the algorithm efficiency is very low. Moreover, in the above step S42, if the score f(j)>f(i) is not satisfied, it means that the current solution is a difference solution, and then the probability P=e is calculated. ([f(j )-f(i)] / t) And generate a random number. If the random number is less than P, the new solution j is accepted. Figure 4 The figure shows the relationship curve between temperature and probability in the simulated annealing algorithm. In this process, the higher the temperature, the greater the probability P, and the higher the probability of accepting the differential solution. If the temperature is very high, the probability is close to 1. At this time, both the differential solution and the better solution are accepted with a probability of 1. Therefore, it can be concluded that the algorithm is making meaningless disturbances when the temperature is high, which will increase the time of the final layout and affect the final layout effect.

[0050] In the present invention, an adaptive initial temperature determination strategy is proposed, that is, a hill climbing algorithm is first executed to understand the current transistor status of the standard unit to be constructed through the hill climbing algorithm, and the data in the hill climbing process is recorded. Based on the data of the hill climbing algorithm, an adaptive initial temperature that can adapt to the current transistor status is calculated and used as the temperature starting point of the simulated annealing algorithm. The temperature starting point is T=2*S÷U. Based on the temperature starting point, the overall probability in the simulated annealing process can be adjusted to be close to P=e -0.5 ≈0.6, thus enhancing the randomness of accepting differential solutions and not being overly biased towards accepting differential solutions. Compared with traditional algorithms, the convergence time of the simulated annealing algorithm executed by the present invention is shorter and more efficient.

[0051] When the initial temperature is set to T = 2* S÷U, the overall probability is close to P = e -0.5 Explain the reasons: ; Taking the average of the fractional changes during the entire climb, we get ; T=2*S÷U; Will Substituting T into the probability calculation formula, we get P=e -0.5 .

[0052] In the present invention, by first executing the hill climbing algorithm to obtain the above-mentioned adaptive initial layout and adaptive initial temperature, the convergence time of the simulated annealing algorithm can be improved and the quality effect of the final solution is also greatly improved.

[0053] In one embodiment, the simulated annealing algorithm can be executed twice in succession. The first time is a trial, that is, the iteration rounds of the simulated annealing algorithm are set to several rounds, that is, several rounds of temperature adjustment are performed, and multiple perturbations can be performed in each round, such as 4 to 7 rounds, specifically 5 rounds, and all layout scores of each round are calculated to determine the layout with the highest layout score and the corresponding temperature, and then the simulated annealing algorithm is executed based on the layout with the highest layout score and the corresponding temperature until it ends. Figure 5 The figure shows the change of the layout score during the simulated annealing algorithm in one embodiment of the present invention. It can be seen that after multiple oscillations, it finally converges to a high score value.

[0054] Since the quality of the solution obtained by the simulated annealing algorithm in the optimization process will fluctuate to a certain extent, some methods to solve these fluctuations are to record the random number seed of the best solution through testing and set the random number seed for this situation. Obviously, this method has poor generalization and wastes manpower in the process of testing and recording, and the final result may not be very good. In this embodiment, by exploring the initial solution, the layout score convergence in the iteration process can be made more stable, and there will be basically no large fluctuations, thereby further accelerating the convergence speed.

[0055] Step S5: Using the arrangement of transistors in the sequence as the layout of transistors.

[0056] In the present invention, the solution output by the simulated annealing algorithm is the arrangement of transistors in the sequence, and the arrangement of transistors in the sequence is used as the layout of the transistors.

[0057] During specific operations, the layout information of the transistor, the connection information of the transistor, and the connection information of the netlist nodes may be written into a file in json format to obtain a json format file of the layout.

[0058] Furthermore, you can also generate visualization results based on json format files. The specific operation process is as follows: First, use the numpy tool to create a white background canvas with an image width of real_x_max; Secondly, a mos_list list is generated to store all MOSFET object instances; Draw the power rails VDD, VSS, and the width of the power rails; The connection relationship of the transistor is obtained through the function cv2.getTextSize(), and the transistor layout is arranged according to the obtained json format file information through the function cv2.putText(); Finally, the result is displayed by the function cv2.imshow() and the visualization result is stored by the function cv2.imwrite().

[0059] like Figure 6 The figure shows a visualization image of a standard cell obtained according to an embodiment of the present invention, where each box represents a transistor and the vertical green lines represent gate lines.

[0060] Take the layout design of multiple transistor standard cells in the standard cell library as an example. Figure 7 The figure shows the comparison of the layout results of the method of the present invention and the traditional Virtuoso tool. The temperature-adaptive transistor automatic layout method proposed by the present invention is compared with the Virtuoso layout. Under the premise of consistent optimization goals, the layout area optimization obtained by the present invention is on average 5% to 10% better than the layout area obtained by the Virtuoso tool, indicating that the present invention improves the optimization efficiency while ensuring the optimization effect, which proves the feasibility and reliability of the method.

[0061] Correspondingly, the present invention also relates to an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0062] The electronic device may be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory may be used to store computer programs and / or modules, and the processor may perform various functions of the electronic device by running or executing computer programs and / or modules stored in the memory, and calling data stored in the memory.

[0063] Accordingly, the present invention also relates to a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above method when executed by a processor.

[0064] Specifically, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0065] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. It should be noted that "in one embodiment", "for example", "for example", etc. of the present invention are intended to illustrate the present invention, rather than to limit the present invention.

[0066] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A method for automatically placing transistors in a standard cell, characterized in that: include: Step S1, obtaining information of each NMOS transistor and PMOS transistor to be laid out; Step S2, pairing the NMOS transistors and PMOS transistors with a common gate, and if there are any unpaired transistors, setting virtual transistors to pair with them, placing the NMOS transistors and PMOS transistors in different sequences respectively, randomly initializing the positions of the transistors in the sequences but ensuring that the positions of the paired transistors in the sequences are always aligned; Step S3, taking the sequence layout as the optimization object and the highest layout score as the optimization goal, executing the hill climbing algorithm to obtain the adaptive initial layout of the sequence, and calculating the adaptive initial temperature of the sequence T=2*S÷U, where S is the accumulation of the score change obtained by each hill climbing, U is the number of hill climbing times, and the layout score is the weighted sum of the transistor layout indicators; Step S4, executing a simulated annealing algorithm based on the adaptive initial layout and the adaptive initial temperature to obtain a final layout of the sequence; Step S5: Using the arrangement of transistors in the sequence as the layout of transistors.

2. The automatic layout method of transistors in a standard cell according to claim 1, characterized in that: In step S4, several rounds of tentative simulated annealing algorithms are first executed, and the layout with the highest layout score is used as the initial solution and the simulated annealing algorithm is continued to be executed until the end.

3. The automatic layout method of transistors in a standard cell according to claim 2, characterized in that: First, five rounds of simulated annealing were performed.

4. The automatic layout method of transistors in a standard cell according to claim 1, characterized in that: In step S4, the process of executing the simulated annealing algorithm includes: Step S41: take the current layout of the sequence as the current solution i, and set the optimal solution S=i; Step S42: Perturb the current solution i to obtain a new solution j. If the score f(j)>f(i), accept the new solution j and update S=j. Otherwise, calculate the probability P=e ([f(j)-f(i)] / t) And generate a random number greater than 0 and less than 1. If the random number is less than P, the new solution j is accepted; t is the current temperature; Step S43: lowering the temperature t; Step S44: Repeat steps S42 to S43 until the temperature t is lower than the termination temperature or the solution converges, and output the optimal solution.

5. The automatic layout method of transistors in a standard cell according to claim 4, characterized in that: The disturbance includes rotating the transistor by 180 degrees, exchanging the position of the transistor, and moving the position of the transistor.

6. The automatic layout method of transistors in a standard cell according to claim 1, characterized in that: If there are transistors whose width exceeds the standard cell size, their width is folded to fit the standard cell size.

7. The automatic layout method of transistors in a standard cell according to claim 1, characterized in that: Step S5 includes: taking the arrangement of transistors in the sequence as the layout of the transistors, obtaining the layout information of the transistors, writing the layout information of the transistors, the transistor connection information and the netlist node connection information into a file in json format, and obtaining a json format file of the layout.

8. The automatic layout method of transistors in a standard cell according to claim 1, characterized in that: The layout indicators include area, line length, pin accessibility, layout symmetry, layout regularity, and program running time.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

Images