Neural signal compression circuit, chip and equipment

Abstract

The invention discloses a neural signal compression circuit, a chip and equipment, and the neural signal compression circuit comprises a signal receiving module which is used for receiving and sampling multi-channel electroencephalogram signals in a time division multiplexing mode; the GZIP compression module is used for completing lossless compression of the pulse waveform data; the signal output module is used for storing and controlling the compressed pulse waveform data, executing parallel-serial conversion and then outputting the pulse waveform data; the RAM is used for providing a data storage function for the signal receiving module, the GZIP compression module and the signal output module; the control unit is used for providing configuration parameters for part or all of the signal receiving module, the GZIP compression module and the signal output module; and the signal receiving module, the GZIP compression module and the signal output module are connected in sequence. The invention aims to realize lossless compression processing of high-throughput electroencephalogram signals so as to reduce the bandwidth requirement of data transmission.

Description

Technical Field

[0001] The present invention relates to electroencephalogram (EEG) signal compression and processing technology in the field of brain-computer interface, and in particular to a neural signal compression circuit, chip and device. Background Art

[0002] Brain Computer Interface (BCI) refers to a technology that establishes a direct connection between human brain nerves and external devices with high biocompatibility to achieve information interaction and functional integration between the nervous system and external devices. Invasive wireless brain-computer interface is a highly invasive and technically complex BCI technology. It records and controls brain activity by implanting electrodes or sensors into the brain and transmitting and receiving signals through wireless communication technology.

[0003] Signal compression is a process that reduces the signal representation by reducing the amount of data or utilizing redundant information in the data while retaining enough information for subsequent analysis and diagnosis. The amount of data collected by multiple electrodes of an invasive wireless brain-computer interface at a high sampling rate is extremely large, but its power budget and transmission bandwidth are limited, and the real-time response requirements are high. Signal compression is an effective solution to the above problems. For the transmission scenario of high-throughput EEG signals at the signal acquisition end, the EEG signals are input into the analog chip in the form of electrical signals through the probe, and are converted into digital signals after amplification. How to use hardware to losslessly compress high-throughput EEG signals to obtain lossless EEG signals (which can be sent to the host computer for further EEG signal processing tasks such as epilepsy detection) is a key technical problem that needs to be solved urgently. Summary of the invention

[0004] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a neural signal compression circuit, chip and device are provided. The present invention aims to realize lossless compression processing of high-throughput EEG signals to reduce the bandwidth requirement for data transmission.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A neural signal compression circuit, comprising: A signal receiving module, used for receiving and sampling multi-channel EEG signals in a time division multiplexing manner; GZIP compression module, used to complete lossless compression of pulse waveform data; The signal output module is used to complete the storage and control of the compressed pulse waveform data and perform parallel-to-serial conversion and output; RAM memory, used to provide data storage function for the signal receiving module, GZIP compression module and signal output module; A control unit, used to provide configuration parameters for part or all of the signal receiving module, the GZIP compression module and the signal output module; The signal receiving module, GZIP compression module and signal output module are connected in sequence, the RAM memory is connected to the signal receiving module, GZIP compression module and signal output module respectively, and the control unit is connected to part or all of the signal receiving module, GZIP compression module and signal output module.

[0006] Optionally, the signal receiving module includes: SPI module, including multiple channels, for performing serial conversion and outputting the EEG signals from the SPI interface; An input control module is used to cache the outputs of multiple SPI modules and select the outputs; A preprocessing module, used for performing IIR bandpass filtering on the gated output EEG signal; and a data frame generation module for performing IIR bandpass filtering on the EEG signal to generate a data frame output; The SPI module, input control module, preprocessing module and data frame generation module are connected in sequence, each SPI module corresponds to multiple channels, and first receives the input signal of the first channel, then receives the input signal of the second channel, and so on, ultimately realizing the collection of EEG signals of multiple channels in a time-division multiplexing manner, and different SPI modules correspond to different channels.

[0007] Optionally, the SPI module includes: an instruction decoding unit, for decoding an input configuration signal CMD and sending the obtained configuration information to the prescaler, the counter comparison unit and the configuration unit respectively; the ninth bit CMD[8] of the configuration signal CMD is used to enable the working mode to be the serial data output mode or the serial data input mode; when it is 1'b1, the serial data output mode is enabled; when it is 1'b1, the serial data input mode is enabled; the first eight bits CMD[7:0] of the configuration signal CMD indicate the data length of each transmission in the serial data input mode; and indicate the number of data transmissions to be executed continuously in the serial data output mode; The prescaler is used to capture the phase and polarity of the input clock clk and further transmit the clock to the counter comparison unit; A counter comparison unit, used to use a counter to realize clock frequency division to generate a trigger signal trigger; Configuration unit, used to store clock phase cpha and clock polarity cpol, cpol=0 means that the clock is in a low level state in idle state; cpol=1 means that the clock is in a high level state in idle state; cpha=0 means that the data is valid when the clock jumps from low level to high level, and the data is sampled on the rising edge of the clock; cpha=1 means that the data is valid when the clock jumps from high level to low level, and the data is sampled on the falling edge of the clock; The data shift register is used to shift based on the trigger signal trigger in each clock cycle. Each time the counter shifts, the counter compares the counting result with the data width DATA_WIDTH of the data shift register. If the counting result is equal to the data width DATA_WIDTH, it is determined that the data shift register has received enough data, and the data is loaded into the data output register sdi_data and then outputs a 16-bit serial data input signal; The clock generation unit is used to generate a divided clock sclk according to the clock phase cpha and the clock polarity cpol and the trigger signal trigger output by the counter comparison unit according to the following formula: f(sclk) = f(clk) / (2(n+1)), In the above formula, f(sclk) is the clock frequency of the divided clock sclk, f(clk) is the clock frequency of the input clock clk corresponding to the clock phase cpha and the clock polarity cpol, n is the value of the clock divided counter, n is specified by the configuration variable DEFAULT_CLK_DIV. At the rising edge of each system clock, if the divided cycle ends or the module is in the idle state or waiting for I / O to be ready, the value of the clock divided counter is loaded as the value of DEFAULT_CLK_DIV. If the above conditions are not met, the value of the clock divided counter decreases. When it decreases to 0, the trigger signal trigger becomes 1, indicating that a serial data input signal transmission can be started, and the divided clock sclk also jumps; The chip select generation unit is used to generate a chip select signal CS according to the result of instruction D and the output of the counter comparison unit. The 13th and 14th bits D [13:12] of instruction D are used to indicate the instruction type. When the chip select instruction is executed, the 9th and 10th bits D [9:8] of instruction D are used to indicate the delay of chip select activation. When the time that the chip select signal represented by the SPI counter value should remain in the activated state has reached the number of cycles specified by the command, and there is no need to repeat the chip select command, the low NUM_OF_CS bit of instruction D is assigned to the chip select signal CS, where NUM_OF_CS is the specified chip select bit.

[0008] Optionally, the input control module includes a channel selector and FIFO buffers corresponding to the SPI modules one by one, the input end of each FIFO buffer is connected to the input end of the channel selector, the FIFO buffer is used to receive the waveform data after the channel is serial-to-parallel converted, and the channel selector takes the data in each FIFO buffer in turn in each cycle, so that the data of all channels are continuously transmitted to the preprocessing module in each clock cycle.

[0009] Optionally, the preprocessing module is divided into a five-stage pipeline, and each stage of the pipeline adopts the following filters with exactly the same structure but different coefficients: , , , In the above formula, ~ is the n~nQth output of the filter, ~ is the n~nPth input of the filter, and is the intermediate variable, ~ as well as ~ is the coefficient of the filter, P and Q are the dimensions of the filter coefficient respectively; the five-stage pipeline filters out part of the noise respectively, and finally achieves the purpose of filtering as a whole. Each stage of the pipeline uses four cycles for filtering. The first cycle is used to store input data, the second cycle is used to read intermediate data from the memory, the third cycle calculates the filtering result, and the fourth cycle is used to store the intermediate data in the memory. After the result is calculated in the third cycle, the filtered result will be passed to the next stage of the pipeline, so that the preprocessing module can complete the filtering of one data every five cycles at the fastest. The preprocessing module stores the intermediate values ​​calculated for each channel independently without affecting each other, so as to realize the filter to filter the data of each channel independently.

[0010] Optionally, the frame header of the structured data frame generated by the data frame generation module includes sampling frequency, channel information, waveform data and frame tail, wherein the sampling frequency and channel information each use one byte to represent the sampling frequency and 256 channels, and the frame tail is coded 0xFF.

[0011] Optionally, the GZIP compression module includes: A data stream partitioning module is used to receive an input data stream and implement flow control, and to partition the input data stream into data blocks of fixed size; LZ77 compressor, used to implement the LZ77 compression algorithm in the Deflate algorithm to compress data blocks; Huffman encoder, used to implement the Huffman coding algorithm in the Deflate algorithm, and encode and output the data compressed by the LZ77 compression algorithm; The output stream merging module is used to organize the encoded output according to the specified compression format specification and then output it; The data stream division module, LZ77 compressor, Huffman encoder and output stream merging module are connected in sequence.

[0012] Optionally, the signal output module includes: The output control module is used to store the received data in the RAM memory, and to fetch the data stored in the RAM memory and send it to the parallel-to-serial module; Parallel-to-serial module, used to perform SPI parallel-to-serial conversion; and a communication module, for outputting the data obtained by the SPI parallel-to-serial conversion through a communication interface; A data path for address signals and data signals is provided between the output control module and the RAM memory, a data path for configuration signals and parallel data is provided between the output control module and the parallel-to-serial module, and a data path for clock signals and serial data is provided between the parallel-to-serial module and the communication module. The compressed data is written into the RAM memory after the address is generated by the output control module, and then read and shifted out according to the read address by the output control module, and then sent to the outside of the chip after passing through the parallel-to-serial module and the communication module; as long as the RAM memory is writable, the output control module continuously receives the compressed data and writes and stores it in the RAM memory. When the parallel-to-serial module is idle, as long as there is still data in the RAM memory, the output control module reads the data and configures the parallel-to-serial module to specify the number of continuous transmissions, and then takes out the data stored in the RAM memory and outputs the data through continuous shifting and sends it to the parallel-to-serial module to perform the data parallel-to-serial operation, and then outputs it through the communication module.

[0013] In addition, the present invention also provides a chip, including a chip body and a signal processing circuit arranged in the chip body, and the signal processing circuit is the neural signal compression circuit.

[0014] In addition, the present invention also provides an electronic device, comprising a microprocessor and a memory connected to each other, wherein the microprocessor includes the neural signal compression circuit.

[0015] Compared with the prior art, the present invention mainly has the following advantages: the neural signal compression circuit of the present invention includes a signal receiving module, which is used to receive sampled multi-channel EEG signals in a time-division multiplexing manner; a GZIP compression module, which is used to complete the lossless compression of pulse waveform data; a signal output module, which is used to complete the storage and control of the compressed pulse waveform data and execute and output it after serial conversion; a RAM memory, which is used to provide data storage function for the signal receiving module, the GZIP compression module and the signal output module; a control unit, which is used to provide configuration parameters for part or all of the signal receiving module, the GZIP compression module and the signal output module; the signal receiving module, the GZIP compression module and the signal output module are connected in sequence, and the present invention can realize lossless compression processing of high-throughput EEG signals to reduce the bandwidth requirement for data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the basic structure of the neural signal compression circuit in an embodiment of the present invention.

[0017] Figure 2 Schematic diagram of the basic structure of the SPI module in an embodiment of the present invention.

[0018] Figure 3 Schematic diagram of the structure of the signal receiving module in an embodiment of the present invention.

[0019] Figure 4 Schematic diagram of the structure of a frame header of a data frame in an embodiment of the present invention.

[0020] Figure 5 Schematic diagram of the signal receiving module working process in an embodiment of the present invention.

[0021] Figure 6 Schematic diagram of the structure of the signal output module in an embodiment of the present invention.

[0022] Figure 7 Schematic diagram of the working process of the signal output module in an embodiment of the present invention.

[0023] Figure 8 Schematic diagram of the structure of the GZIP compression module in an embodiment of the present invention.

[0024] Fig. 9 The figure is a flow chart of the LZ77 compression algorithm adopted in the embodiment of the present invention.

[0025] Fig.10 This is a hash table sample of the LZ77 compression algorithm in an embodiment of the present invention.

[0026] Fig.11 Schematic diagram of the architecture of the LZ77 compressor in an embodiment of the present invention.

[0027] Fig.12 Schematic diagram of the pipeline implementation of the LZ77 compressor in an embodiment of the present invention.

[0028] Fig.13 Schematic diagram of the sliding window of the LZ77 compressor in an embodiment of the present invention.

[0029] Fig.14 1 is an example of Huffman tree construction in an embodiment of the present invention, wherein (a) is the initial Huffman tree; (b) is the Huffman tree after merging 1 and 2; (c) is the Huffman tree after merging 3 and 4; and (d) is the Huffman tree after merging 6 and 7.

[0030] Fig.15 It is a Deflate tree obtained based on the Huffman tree construction example in an embodiment of the present invention.

[0031] Fig.16 Schematic diagram of the architecture of a Huffman encoder in an embodiment of the present invention.

[0032] Fig.17 Schematic diagram of the state transition of the finite state machine FSM in an embodiment of the present invention.

[0033] Fig.18 Schematic diagram of the Huffman encoder data output stream pipeline in an embodiment of the present invention.

[0034] Fig.19 Schematic diagram of the working flow of the lossless compression circuit in an embodiment of the present invention.

[0035] Legend of the numbers: 1. Signal receiving module; 11. SPI module; 111. Instruction decoding unit; 112. Prescaler; 113. Counter comparison unit; 114. Configuration unit; 115. Data shift register; 116. Clock generation unit; 117. Chip select generation unit; 12. Input control module; 121. FIFO buffer; 122. Channel selector; 13. Preprocessing module; 14. Data frame generation module; 2. GZIP compression module; 21. Data stream division module; 22. LZ77 compressor; 23. Huffman encoder; 24. Output stream merging module; 3. Signal output module; 31. Output control module; 32. Parallel-to-serial module; 33. Communication module; 4. RAM memory; 5. Control unit. DETAILED DESCRIPTION

[0036] like Figure 1 As shown, the neural signal compression circuit in this embodiment includes: The signal receiving module 1 is used to receive and sample multi-channel EEG signals in a time-division multiplexing manner; GZIP compression module 2, used to complete the lossless compression of pulse waveform data; Signal output module 3, used to complete the storage and control of compressed pulse waveform data and perform parallel-to-serial conversion and output; RAM memory 4, used to provide data storage function for the signal receiving module 1, the GZIP compression module 2 and the signal output module 3; A control unit 5, used to provide configuration parameters for part or all of the signal receiving module 1, the GZIP compression module 2 and the signal output module 3; The signal receiving module 1, the GZIP compression module 2 and the signal output module 3 are connected in sequence, the RAM memory 4 is connected to the signal receiving module 1, the GZIP compression module 2 and the signal output module 3 respectively, and the control unit 5 is connected to part or all of the signal receiving module 1, the GZIP compression module 2 and the signal output module 3.

[0037] In this embodiment, the main function of the signal receiving module 1 is to receive the sampled 256-channel EEG signals in a time-division multiplexing manner, and transmit them to the GZIP compression module 2 for signal compression after processing. Figure 1 As shown, the signal receiving module 1 in this embodiment includes: The SPI module 11 includes multiple channels for performing serial conversion and outputting the EEG signals from the SPI interface; An input control module 12, used to cache the output of the multi-channel SPI module 11 and select the output; A preprocessing module 13 is used to perform IIR bandpass filtering on the gated output EEG signal; and a data frame generation module 14 for performing IIR bandpass filtering on the EEG signal to generate a data frame output; The SPI module 11, input control module 12, preprocessing module 13 and data frame generation module 14 are connected in sequence, each SPI module 11 corresponds to multiple channels, and first receives the input signal of the first channel, then receives the input signal of the second channel, and so on, ultimately realizing the collection of EEG signals of multiple channels in a time-division multiplexing manner, and different SPI modules 11 correspond to different channels.

[0038] The signal receiving module 1 includes the input data of the 16-channel SPI module 11 to realize serial input and parallel output. After the input control module 12, the preprocessing module 13 and the data frame generation module 14, the input is the EEG signal of 16 channels with 1 bit per cycle, and the output is 8 bits of data in AXI-Stream format.

[0039] The SPI module 11 is responsible for converting the received serial input signal into a 16-bit parallel signal (serialinput parallel output, SIPO) for subsequent processing. Figure 2 As shown, the SPI module 11 in this embodiment includes: The instruction decoding unit 111 is used to decode the input configuration signal CMD and send the obtained configuration information to the prescaler 112, the counter comparison unit 113 and the configuration unit 114 respectively, wherein the configuration signal CMD is a signal for implementing mode configuration. The SPI can support two modes, SDO (serial data output) and SDI (serial data input). The 9th bit CMD[8] of the configuration signal CMD is used to enable the working mode to be SDO (serial data output) mode or SDI (serial data input) mode. When it is 1'b1 (CMD[8]=1'b1), the serial data output mode is enabled, and when it is 1'b1 (CMD[9]=1'b1), the serial data input mode is enabled. The first 8 bits CMD[7:0] of the configuration signal CMD represent the data length of each transmission in the serial data input mode (configured as 16 bits in this design), and represent the number of data transmissions that need to be executed continuously in the serial data output mode; The pre-divider 112 is used to capture the phase and polarity of the input clock clk, and further transmit the clock to the counter comparison unit 113; in this embodiment, cpha and cpol refer to the clock phase cpha and the clock polarity cpol respectively, cpol=0: indicates that the clock is in a low level state in the idle state; cpol=1: indicates that the clock is in a high level state in the idle state; cpha=0: indicates that the data is valid when the clock jumps from a low level to a high level, that is, the data is sampled at the rising edge of the clock; cpha=1: indicates that the data is valid when the clock jumps from a high level to a low level, that is, the data is sampled at the falling edge of the clock. Clock division allows the SPI interface to run at different rates to adapt to different devices and communication conditions; The counter comparison unit 113 is used to use the counter to realize clock frequency division to generate a trigger signal trigger. When the trigger signal trigger counts to 0, it changes to 1, indicating that an SPI transmission can be started, and the corresponding frequency division clock sclk also jumps; Configuration unit 114, used to store clock phase cpha and clock polarity cpol, cpol=0 means that the clock is in a low level state in idle state; cpol=1 means that the clock is in a high level state in idle state; cpha=0 means that the data is valid when the clock jumps from a low level to a high level, and the data is sampled at the rising edge of the clock; cpha=1 means that the data is valid when the clock jumps from a high level to a low level, and the data is sampled at the falling edge of the clock; The data shift register 115 is used for shifting in each clock cycle based on the trigger signal trigger. Each time the data shift register 115 is shifted, the counter compares the counting result with the data width DATA_WIDTH of the data shift register 115. If the counting result is equal to the data width DATA_WIDTH, it is determined that the data shift register 115 has received enough data, and the data is loaded into the data output register sdi_data and then outputs a 16-bit serial data input signal. The clock generating unit 116 is used to generate a divided clock sclk according to the clock phase cpha and the clock polarity cpol and the trigger signal trigger output by the counter comparing unit 113 according to the following formula: f(sclk) = f(clk) / (2(n+1)), In the above formula, f(sclk) is the clock frequency of the divided clock sclk, f(clk) is the clock frequency of the input clock clk corresponding to the clock phase cpha and the clock polarity cpol, n is the value of the clock divided counter, n is specified by the configuration variable DEFAULT_CLK_DIV. At the rising edge of each system clock, if the divided cycle ends or the module is in the idle state or waiting for I / O to be ready, the value of the clock divided counter is loaded as the value of DEFAULT_CLK_DIV. If the above conditions are not met, the value of the clock divided counter decreases. When it decreases to 0, the trigger signal trigger becomes 1, indicating that a serial data input signal transmission can be started, and the divided clock sclk also jumps; The chip select generation unit 117 is used to generate a chip select signal CS according to the result output by the instruction D and the counter comparison unit 113. The 13th and 14th bits D [13:12] of the instruction D are used to indicate the instruction type. When the chip select instruction is executed, the 9th and 10th bits D [9:8] of the instruction D are used to indicate the delay of chip select activation. When the time that the chip select signal represented by the SPI counter value should remain activated has reached the number of cycles specified by the command, and there is no need to repeat the chip select command, the low NUM_OF_CS bit of the instruction D is assigned to the chip select signal CS, where NUM_OF_CS is the specified chip select bit.

[0040] like Figure 3As shown, the input of each SPI module 11 is 1 bit of channel data, and the output is 16 bits. It receives 1 bit of channel data in each cycle and stores it in the shift register. After 16 cycles, a 16-bit parallel data is obtained and the data is transmitted to the input control module. The first SPI module 11 first spends 16 cycles to receive the input signal of channel 0, and then spends 16 cycles to receive the input signal of channel 1, and so on, and finally realizes SPI 0 to collect the signals of channel 0 to channel 15 in a time-division multiplexing manner; similarly, the second SPI collects the signals of channel 16 to channel 31, and so on, SPI 15 collects the signals of channel 240 to channel 255, and finally realizes 16-way SPI to collect 256 channel signals in a time-division multiplexing manner.

[0041] The input control module 12 receives the continuous EEG signal data stream, caches the data into the FIFO array, and adds channel information to distinguish different signal channels in subsequent processing. Figure 3 As shown, the input control module 12 in this embodiment includes a channel selector 122 and FIFO buffers 121 corresponding to the SPI modules 11 one by one, and the input end of each FIFO buffer 121 is connected to the input end of the channel selector 122. The FIFO buffer 121 is used to receive the waveform data after the channel is serial-to-parallel converted. In each cycle, the channel selector 122 takes turns to take the data in each FIFO buffer 121, so that the data of all channels are continuously transmitted to the preprocessing module 13 in each clock cycle. In this embodiment, a 16-bit FIFO buffer 121 is configured for each SPI module 11 to receive the waveform data after the channel is serial-to-parallel converted. In each cycle, the channel selector 122 takes turns to take the data in 16 FIFO buffers 121, wherein the data in the first FIFO corresponds to channels 0 to 15, the data in the second FIFO corresponds to channels 16 to 31, and so on. Finally, the 16-bit width data of 256 channels is continuously transmitted to the preprocessing module 13 in each clock cycle.

[0042] The preprocessing module 13 is mainly used to perform IIR bandpass filtering on the input data, and independently complete the bandpass filtering of the signal for the original signal of each channel to improve the signal quality and reliability. In this embodiment, specifically, the bandpass filtering of the signal is independently completed for 256 channels to reduce or eliminate the noise or unnecessary frequency components in the signal, and the main signal information can be more effectively retained during the compression process. In this embodiment, the filter used in the preprocessing module 13 is a Butterworth bandpass filter, which is characterized by a maximum flat frequency response curve within the passband, without ripples, and gradually decreases to zero in the stopband, and is also called a maximum flat filter. The working principle of the filter is to calculate the following iterative formula: , where n represents the nth data, is the input signal, that is, the input signal of 16 bits per channel, is the signal after filtering, which is transmitted to the data frame generation module after filtering. The filtering coefficient and Determines the characteristics of the filter. By changing the filter coefficients a and b, noise at different frequencies can be filtered out. It is configurable. P and Q represent the dimensions of the filter coefficients b and a respectively.

[0043] As an optional implementation, the preprocessing module 13 in this embodiment is divided into a five-stage pipeline, and each stage of the pipeline adopts the following filters with exactly the same structure but different coefficients: , , , In the above formula, ~ is the n~nQth output of the filter, ~ is the n~nPth input of the filter, and is the intermediate variable, ~ as well as ~ is the coefficient of the filter, P and Q are the filter coefficient dimensions respectively; the five-stage pipeline filters out a part of the noise respectively, and finally achieves the purpose of filtering as a whole. Each stage of the pipeline uses four cycles for filtering, the first cycle is used to store input data, the second cycle is used to read intermediate data from the memory, the third cycle calculates the filtering result, and the fourth cycle is used to store the intermediate data in the memory, wherein the third cycle calculates the result and transmits the filtered result to the next stage of the pipeline, so that the preprocessing module 13 can complete the filtering of one data every five cycles at the fastest, and the preprocessing module 13 stores the intermediate values ​​calculated by each channel independently without affecting each other, so as to realize that the filter independently filters the data of each channel. In this embodiment, the five-stage filter of the preprocessing module 13 respectively filters out a part of the noise, and finally achieves the purpose of filtering as a whole. Each stage of the filter requires four cycles for filtering, the first cycle is used to store input data, the second cycle is used to read intermediate data from the RAM memory 4, the third cycle calculates the filtering result, and the fourth cycle is used to store the intermediate data in the RAM memory 4. wherein the third cycle calculates the result and transmits the filtered result to the next stage of the filter. Theoretically, the fastest filtering of one data can be completed every five cycles. The intermediate values ​​calculated by each channel are stored independently without affecting each other, so that the filter can filter the data of each channel independently.

[0044] In order to distinguish data from different channels at different sampling frequencies and improve the reliability and efficiency of data transmission, in this embodiment, the data frame generation module 14 uses a data frame generation method to organize the data into structured data frames. Figure 3 and Figure 4 As shown, the frame header of the structured data frame generated by the data frame generation module 14 in this embodiment includes sampling frequency, channel information, waveform data and frame tail, wherein the sampling frequency and channel information each use one byte to represent the sampling frequency and 256 channels, and the frame tail is coded 0xFF. The frame header contains sampling frequency and channel information, each using one byte to represent, one byte can just represent 256 channels, and the sampling frequency is also represented by one byte, which is convenient for identifying the frame header after decoding. Followed by the waveform data, the frame tail 0xFF is added after the data of the 256 channels are output.

[0045] like Figure 5As shown, the working process of the signal receiving module 1 in this embodiment is roughly divided into the following stages: (1) 16 SPI modules 11 continuously receive channel signals, and the channel signals are input 1 bit per cycle. The channel signals corresponding to each SPI module 11 are input in turn. For example, SPI0 corresponds to channels 0 to 15. After channel 0 is continuously input for 16 cycles, channel 1 is continuously input for 16 cycles, and so on. (2) After the single channel signal is continuously input for 16 cycles, the SPI module 11 converts it into a parallel signal and stores it in the FIFO buffer 121. At the same time, the channel selector 122 selects the channel parallel data and transmits the data to the preprocessing module 13. (3) The preprocessing module 13 performs IIR bandpass filtering on the channel data. In the best case, one filtering result is obtained every 5 cycles. (4) The data frame generation module 14 generates a data frame for the filtered result. First, the sampling frequency is obtained from the control unit 5, followed by the channel number, then the filtered waveform data, and finally the frame tail is added.

[0046] GZIP compression module 2 mainly completes the lossless compression of pulse waveform data. It is written in accordance with the Deflate algorithm specification (RFC1951) and the GZIP format specification (RFC1952), and supports almost the entire Deflate algorithm. Figure 1 As shown, the GZIP compression module 2 in this embodiment includes: The data stream division module 21 is used to receive the input data stream and implement flow control, and divide the input data stream into data blocks of fixed size to facilitate compression by subsequent modules; LZ77 compressor 22, used to implement LZ77 compression algorithm in Deflate algorithm to compress data blocks; Huffman encoder 23, used to implement the Huffman encoding algorithm in the Deflate algorithm, and encode and output the data compressed by the LZ77 compression algorithm; The output stream merging module 24 is used to organize the encoded output according to the specified compression format (GZIP) specification and then output it; The data stream division module 21, the LZ77 compressor 22, the Huffman encoder 23 and the output stream merging module 24 are connected in sequence.

[0047] The signal output module 3 mainly completes the functions of storing and controlling the compressed pulse waveform data, converting parallel data into serial data and outputting it via WIFI. Figure 6 As shown, the signal output module 3 in this embodiment includes: The output control module 31 is used to store the received data in the RAM memory 4, and to fetch the data stored in the RAM memory 4 and send it to the parallel-to-serial module 32, so as to store and control the parallel data to adapt to the speed difference between the parallel input and the serial output; The parallel-to-serial module 32 is used to perform SPI parallel-to-serial conversion. This module is a core module that performs parallel input serial output (PISO) and can output parallel input data in a serial manner. And the communication module 33 is used to output the data obtained by the SPI parallel-to-serial conversion through the communication interface. In this embodiment, a WIFI module is specifically used. In addition, other types of communication modules can also be used as needed. Figure 6 As shown, the input of the signal output module 3 is compressed data in AXI-Stream format, wherein the width of the compressed data is 32 bits, and the output is a serial signal. The signal output module 3 stores the compressed data in the RAM memory 4, converts the compressed parallel data into serial data using the SPI module, and then sends it through the WIFI module.

[0048] like Figure 6 As shown, a data path for address signals and data signals is provided between the output control module 31 and the RAM memory 4, a data path for configuration signals and parallel data is provided between the output control module 31 and the parallel-to-serial module 32, and a data path for clock signals and serial data is provided between the parallel-to-serial module 32 and the communication module 33. The compressed data is written into the RAM memory 4 after the address is generated by the output control module 31, and then read and shifted out according to the read address by the output control module 31, and then sent to the outside of the chip after passing through the parallel-to-serial module 32 and the communication module 33; as long as the RAM memory 4 is writable, the output control module 31 continuously receives the compressed data and writes and stores it in the RAM memory 4. When the parallel-to-serial module 32 is idle, as long as there is still data in the RAM memory 4, the output control module 31 reads the data and configures the parallel-to-serial module 32 to specify the number of continuous transmissions, and then takes out the data stored in the RAM memory 4 and outputs the data through continuous shifting and sends it to the parallel-to-serial module 32 to perform the data parallel-to-serial operation, and then outputs it through the communication module 33.

[0049] It takes multiple clock cycles for the output control module 31 to convert the 32-bit compressed parallel data into 1-bit serial data. The data receiving speed exceeds the processing data of the parallel-to-serial conversion. Therefore, the output control module 31 needs to store the received data in the RAM memory 4 and take out the data at an appropriate time and send it to the subsequent parallel-to-serial conversion module 32. It mainly includes two processes, data writing and data reading. Data reading can be divided into SPI configuration and shift output. (1) Data writing. When the 32-bit data compressed by the GZIP compression module 2 is output for the last time, not all 4 bytes of data are valid. Therefore, the output signal of the GZIP compression module 2 also includes a 4-bit byte valid signal i_tkeep, which is used to indicate the validity of the 32-bit data in a one-hot code manner. If i_tkeep=4'b1111, it means that all 32 bits of data are valid; i_tkeep=4'b0011 means that only bits [15:0] are valid. Therefore, the i_tkeep signal is 4'b1111 during normal output, and it is different only when the current data block is compressed for the last time. In addition, the data in the Bypass working mode does not need to be compressed and is directly transmitted from the input control module 1 to the output control module 31 of the signal output module 3. Therefore, only the lower 16 bits are valid, and the corresponding o_tkeep signal is 4'b0001. Therefore, when the valid signal in the output AXI-Stream format is high, the input data is written to the RAM memory 4 in the form of {i_tkeep, i_tdata}, and the write address is incremented from 0. The RAM memory 4 uses a cyclic read and write method. Considering the speed difference between writing and reading, the write condition is set to addr_wr +10 != addr_rd. 10 means that there are only 10 write addresses left in the RAM memory 4. It is considered that the RAM memory 4 is full at this time. The next beat notifies the GZIP compression module 2 to stop sending data, that is, in the AXI-Stream, the ready signal of the slave module is set low. (2) SPI configuration. When the SPI parallel input to serial output (PISO) module is idle, it sends an idle signal to the output control module 31. After receiving the signal, the output control module 31 generates a read address and reads data from the RAM memory 4, and then transmits the data to the parallel-to-serial module 32. The data output by the GZIP compression module 2 in the AXI-Stream format is not fully valid for 32 bits when it is output for the last time, so the data width of each PISO of the parallel-to-serial module 32 is configured to be one byte. In addition, the lower 8 bits of the configuration signal CMD of the parallel-to-serial module 32 indicate the number of consecutive PISOs. For example, cmd[7:0]=8'h0f indicates that 16 consecutive PISOs can be performed, and the total amount of data processed by one configuration is 16*8bits=128bits.Taking into account the data width mismatch and the configuration signal, in this embodiment, the configuration signal CMD is configured each time data is read from the RAM memory 4. (3) Shift output. Use the two internal shift registers, the shift register byte_valid and the shift register data, to temporarily store the data taken from the RAM memory 4, including: the tkeep signal read from the RAM memory 4 is placed in the shift register byte_valid, and the tdata signal is placed in the shift register data according to the tkeep signal. For example, tkeep=4'b0011, then tdata is placed in the lower 16 bits of data. After each execution of PISO, byte_valid is shifted right by one bit, indicating that the number of transmissions is reduced by one, and the high bit is filled with zero; data transmits the lower 8 bits to the parallel-to-serial module 32 to perform the PISO operation, and at the same time shifts right by 8 bits and fills the high bit with zero. The parallel-to-serial module 32 performs the SDO function. After receiving the configuration command CMD, the configuration command is decoded, and then the internal shift register is initialized, the number of continuous transmissions is configured, and the chip select signal is generated. When the transmission is triggered, if the current bit is the first bit of the parallel data, the parallel data will be loaded into the internal shift register and shifted left according to the calculated shift value to adapt to the custom data width. In each clock cycle, if the current bit is not the first bit of the data word, the value of the shift register will shift left by one bit, and the least significant bit (LSB) will be filled with zero. The generation of the trigger signal depends on the clock divider, multi-function counter and comparator.

[0050] like Figure 7 As shown, the workflow of the signal output module 3 can be divided into the following steps: (1) As long as the RAM memory 4 can still be written, the compressed data is continuously received; (2) When the parallel-to-serial module 32 is idle, as long as there is still data in the RAM memory 4, the data is read; (3) After reading the data, the SPI is configured to specify the number of continuous transmissions; (4) Continuously shift and output data to the parallel-to-serial module 32 to perform the data parallel-to-serial operation.

[0051] like Figure 1 As shown, the RAM memory 4 is used to provide data storage function for the signal receiving module 1, the GZIP compression module 2 and the signal output module 3. The stored data includes: the intermediate result of IIR filtering when the preprocessing module 13 performs IIR bandpass filtering, the hash and sliding window of the LZ77 compressor 22, the Huffman tree (Huffman) between the Huffman encoder 23 and the output stream merging module 24, and the compressed data of the output control module 31.

[0052] like Figure 1As shown, the control unit 5 is used to provide configuration parameters for part or all of the signal receiving module 1, the GZIP compression module 2 and the signal output module 3, including: filter coefficient, sampling frequency, working mode, and SPI configuration signal, etc. The filter coefficient is the filter coefficient when the preprocessing module 13 performs IIR bandpass filtering; the sampling frequency is the frequency of the prescaler 111 in the SPI module 11 controlling the sampling; the working mode includes a normal working mode and a bypass debugging mode (bypass debugging mode). In the normal working mode, the received signal is filtered and then compressed, and the bypass debugging mode is used to directly send the input signal without compression; 16 SPIs are used in the signal receiving module 1 to realize serial-to-parallel conversion (SIPO), and the signal output module 3 uses SPI to realize parallel-to-serial conversion (PISO). Different usage modes of SPI need to be configured using SPI configuration signals.

[0053] like Figure 8 As shown, the data stream division module 21 of this embodiment includes: an input flow control module, which is used to receive the input data stream and implement flow control; a division module, which is used to divide the input data stream into data blocks of fixed size. Also included between the LZ77 compressor 22 and the Huffman encoder 23: a conversion module, which is used to convert the output of the LZ77 compression algorithm into Huffman encoded symbols; a check module, which is used to receive the input data stream and calculate the length len of the entire data stream and the cyclic redundancy check code. Fig. 9 It is a flowchart of the LZ77 compression algorithm adopted in this embodiment.

[0054] The input flow control module, the division module, and the LZ77 compressor 22 are connected in sequence, the LZ77 compressor 22 is connected to the input ends of the conversion module and the verification module respectively, the output ends of the conversion module and the verification module are connected to the input end of the Huffman encoder 23 respectively, and the output end of the Huffman encoder 23 is connected to the input end of the output stream merging module 24. In this embodiment, the input data stream is a data stream in the AXI-Stream format, the input flow control module receives the data input in the AXI-Stream format for buffering, the division module divides the data stream into blocks and controls the flow of the data stream, the LZ77 compressor 22 implements the LZ77 data compression algorithm, the conversion module converts the LZ77 compressed data into characters, the verification module counts the number of data and calculates the CRC32 check code, the Huffman encoder 23 encodes the data processed by the LZ77 compressor 22, and finally puts the data into the output stream merging module 24 for output flow control and transmits it to the next module in the AXI-Stream format.

[0055] As an optional implementation, the input flow control module in this embodiment includes two 8-bit buffers for receiving data input in AXI-Stream format and implementing flow control, and the two 8-bit buffers are used to receive data input in AXI-Stream format in turn. The input flow control module in this embodiment receives data input in AXI-Stream format in a double buffer structure through the above structure, which can effectively optimize the data processing flow, improve the response speed and data processing capability of the system, and enhance the stability and reliability of the system.

[0056] like Figure 8 As shown, the partitioning module of this embodiment includes a counter and a comparator. The counter is used to count according to the data received in the AXI-Stream format. The output end of the counter and the preset threshold BLK_MIN are used as the input of the comparator. The comparator is used to take out the data of the preset threshold BLK_MIN size from the input flow control module as a data block when the count value of the counter is equal to the preset threshold BLK_MIN and output it. In this embodiment, the data smaller than the preset threshold BLK_MIN bytes is treated as a data block (DBLK) of the Deflate algorithm, and the data larger than the preset threshold BLK_MIN bytes is divided into multiple data blocks DBLK, each of which does not exceed the preset threshold BLK_MIN. The output signal of the partitioning module includes a data signal byte, indicating the end of the data block (eob), and a signal of the end of the data stream (eos). The above design of the partitioning module ensures that the data is processed in an appropriate block size, and compression processing can be effectively performed regardless of the size of the original data stream. It should be noted that although the algorithm of dynamically adjusting the size of the data block DBLK can further improve the compression rate, the hardware implementation needs to consider the benefits and costs. Dynamically adjusting the block size will further increase the complexity of hardware implementation, and the compression rate improvement brought by the increased complexity is unstable. In the EEG signal compression task, the hardware resources are limited and the power consumption is restricted. It is not necessary to dynamically adjust the size of the data block DBLK in pursuit of compression rate.

[0057] The LZ77 compressor 22 is used to implement the LZ77 compression algorithm in the Deflate algorithm to compress the data block. The LZ77 compression algorithm is a classic compression algorithm that uses a dictionary to compress data. It was proposed by two Israeli engineers, Jacob Ziv and Abraham Lempel, in 1977. The core idea is that if the information in the string has appeared before, it only needs to point out the position where it appeared before, and then the relative index can be used to represent these words. Fig. 9As shown in the figure, the steps of the LZ77 compression algorithm include: (1) Calculate the hash value: use the hash function to calculate the hash value of the current byte and the next 2-byte neighboring data byte by byte; (2) Construct and maintain the hash table; (3) Match: search the hash table by the hash value to determine whether there is a repeated string in the sliding window and perform a match; if there are multiple identical strings, perform index calculation: select the string with the longest matching length (denoted as L) and the closest distance (proximity principle), calculate the distance between the starting positions of the two (denoted as D), and finally use the index composed of (original character, matching length L, distance D) to represent the content of the repeated string. If the repeated string is not found in the dictionary (no match), the original character of the current character can be directly output; (4) Output the compression result of the LZ77 compression algorithm. If the compression is completed, it ends, otherwise continue to perform compression until all characters are processed. Fig.10 is a hash table sample of the LZ77 compression algorithm in this embodiment. Figure 3 Taking the sentence shown as an example, for the first appearing character, the original character will be encoded because it cannot be matched. The subsequent "a" can be represented by (2,1), "aba" can be represented by (4,3), and "bac" can be indexed by (6,3). "ba" appears twice in the sliding window. According to the proximity principle, it is indexed by (3,2).

[0058] Fig.11 The micro-architecture of the LZ77 compressor 22 in this embodiment is shown, and its input includes: a byte of data [7:0]byte, a data valid signal en, a stream end signal eos (end of stream) and a data block end signal eob (end of block), and the output includes: the original character [7:0]byte or the index (D, L), the index (D, L) is represented by [7:0]len to indicate the matching length L, [3:0]dist to indicate the distance D, and the original character [7:0]byte or the index (D, L) is distinguished using the type signal nlz (notlz77).

[0059] The pipeline implementation diagram of the LZ77 compressor 22 in this embodiment is shown in FIG. 1 . The use of pipeline design in hardware implementation not only improves the processing speed, but also facilitates design and debugging. Fig.12 As shown, the stages of pipeline design include: The receiving data phase A is used to receive the input signal and determine whether it is in the data block and whether the pipeline should be started; Delay processing stage B is used to introduce delays to balance the speed differences of different operations and ensure the synchronization of data in the pipeline; Hash calculation phase C, used to calculate the hash value of the current data block for fast matching in subsequent phases; Hash table read and write phase D is used to write the information of the current position into the hash table and read the possible matching position from the hash table based on the hash value; Matching phase E is used to prepare the data required for matching search; The search phase F is used to perform the actual match check, including searching the hash table through a sliding window based on the hash value, determining whether there are repeated strings in the sliding window and matching them; if there are multiple identical strings, select the string with the longest matching length L and the closest distance, calculate the distance D between the starting positions of the two, and finally use the index composed of (byte, L, D) to represent the content of the repeated string, where byte is the original character of the current data block; The matching decision stage G is used to make a decision based on the matching search result to determine whether to output the original character in the case of non-matching or output the index information in the case of matching; The original character encoding stages H and J are used to prepare the original characters for output in case of non-matching; The final output stage K is used to integrate the non-matching situation and the matching situation, using the type signal nlz to distinguish between the original character and the index information and generate the final output signal.

[0060] According to the principle of LZ77 compression algorithm, LZ77 compression algorithm has two key components: hash table and fast matching in sliding window, which are implemented in hardware using two separate RAMs. Set the search distance to 16383, the range covers the entire DBLK, use hash table matching search, and the hash table size is 4096; in order to map to the entire data block DBLK, the hash value width should be set to 14 bits. LZ77 compression algorithm looks for repeated patterns in data. In order to find matches effectively, it is necessary to be able to access previous data bytes. The sliding window module supports this search by storing the most recent bytes. At the same time, when looking for matches, it is usually necessary to consider the problem of byte boundary alignment. Figure 3 In the compression process example, the sliding window length is 6. Obviously, the setting of the window length will have a crucial impact on the compression efficiency. From the perspective of spatial compression efficiency, the larger the window, the more possible matches there are for the subsequent unprocessed data, and the higher the spatial compression efficiency. However, as the window becomes larger, the time efficiency will decrease rapidly. In this embodiment, after comprehensively considering the time efficiency and spatial compression rate, the window size of the LZ77 compression algorithm is set to 16384 (2 14). Specifically, in this embodiment, when searching in the hash table through a sliding window based on the hash value, the sliding window size used is 16384, the size of the hash value is 4096, the width of the hash value is 14 bits, the search distance of the search is 16383 to cover the entire data block, and four buffers BUFFER are used to store the lower 2 bits of the storage address of the data for searching. Figure 6 Schematic diagram of the sliding window of the LZ77 compressor in this embodiment. Fig.13 As shown in the figure, using four buffers can ensure that the algorithm can access the correct byte sequence under any given byte alignment. In order to improve the access speed, the data is stored in four buffers (BUFFER0~BUFFER3) in sequence according to the lower 2 bits of the storage address. When searching, matching searches can be performed in parallel in different buffers, and different reading methods of data in the BUFFER can be implemented according to the lower 2 bits of the read address, thereby improving the search speed.

[0061] In this embodiment, the conversion module converts the output of the LZ77 compression algorithm into a Huffman coded symbol, including merging the original character and the matching length len into a symbol [8:0]symbol, and determining the number of additional bits required to encode these symbols according to a preset matching length partition comparison table; or merging the distance D in the index with the matching length len of the matching check to use a distance dist, and determining the number of additional bits required to encode these symbols according to a preset matching length partition comparison table, to form two data streams of distance [8:0]dist and symbol [8:0]symbol. The code value of the original character [7:0]byte is between 0 and 255, and the code value represented by the index is extended by a part of the bytes on this basis to represent the matching length, and 256 is used to represent the end. There is no need to compress short lengths, so the minimum compression length is agreed to be 3, 257 represents a matching length of 3, and so on. The maximum compression length is 258, so the maximum value is 511. Considering the distribution of the matching length, the smaller the value, the higher the probability of occurrence and the higher the secondary compression rate, so the matching length L is grouped. The matching length division comparison table used in this embodiment is shown in Table 1.

[0062] Table 1: Match length classification comparison table

[0063] According to the principle of LZ77 compression algorithm, there are two outputs of LZ77 compression algorithm, original characters or indexes (D, L), and Huffman encoder needs to encode real characters, so the conversion module converts the output of LZ77 compression algorithm into Huffman coded symbols. The conversion process includes merging the original characters and the matching length len into a symbol [8:0] symbol, and calculating the number of additional bits required to encode these symbols (i.e., Bits in Table 1). The distance D is also encoded in the above way. This information is then used in Huffman encoder 23 to generate the final compressed data stream.

[0064] In this embodiment, after receiving the input data stream, the verification module calculates the length of the entire data stream and the cyclic redundancy check code (CRC32), and provides this information as output. CRC32 is a commonly used error detection method that can detect whether the data has changed during transmission or storage. Of course, other verification algorithms can also be used as needed to detect whether the data has changed during transmission or storage.

[0065] The Huffman encoder 23 is used to implement the Huffman coding algorithm in the Deflate algorithm, and encodes and outputs the data compressed by the LZ77 compression algorithm. The Huffman coding algorithm is a variable-length lossless compression coding method proposed by Dr. David A. Huffman in 1952 based on some coding ideas expounded by Shannon and Fano. It is an entropy coding algorithm constructed with minimum redundancy. The core of Huffman coding is the construction of the Huffman tree. The specific process is as follows: Step (1): According to n weight values ​​{W 1 ,W 2 ,…,W n}composes a forest of n binary trees F={T 1 ,T 2 ,…,T n}, where each binary tree T i Only those with weight W i , and its left and right subtrees are empty. Step (2): Select two binary trees T with the smallest root node weight from the forest F. i and T j (i, j are positive integers not greater than n), as the left and right subtrees to construct a new binary tree T o , T o The weight is W i +W j Step (3): Delete the left and right subtrees T of the new binary tree from the forest F. i and T j , and the new binary tree To Join the forest F. Step (4): Repeat steps (2) and (3) until there is only one tree in the forest F. This tree is the Huffman tree.

[0066] Assuming that the given character set is {1,2,4,6}, and its weight set is also {1,2,4,6}, the process of constructing the Huffman tree is as follows: Fig.14 and Fig.15 First, a forest of four binary tree nodes is formed based on these four weight values, as shown in Fig.14 As shown in (a) in the figure, then each time two binary trees 1 and 2 with the smallest node weights are selected from the forest, and a new binary tree is constructed with them as the left and right subtrees. The weight of the new binary tree is the sum of the left and right subtrees, which is 3. Fig.14 As shown in (b) in . Add the new binary tree to the forest F and delete its left and right subtrees from F, as shown in Fig.14 Repeat the above process until there is only one binary tree in F, which is the Huffman tree, as shown in (c). Fig.14 After completing the construction of the leaf node Huffman tree, the left and right branches of each binary tree in the tree are assigned values ​​0 and 1 respectively, and the Deflate tree based on the above Huffman tree construction example is obtained as follows Fig.15 As shown, then traverse the Huffman tree from the root node to each leaf node one by one, and the character code of the corresponding leaf node is the Huffman code of the character. However, in the constructed Huffman tree, swapping the left and right leaf nodes does not affect the optimality of the code. In other words, rotating the left and right branches of any node of the code tree (0 and 1 are swapped), which can also be called the left and right swap of the tree, does not affect the code length. This means that the constructed Huffman tree is not unique. In order to decode correctly, it is necessary to save the structural information of the Huffman tree, which increases the difficulty of storage.

[0067] The central idea of ​​the paradigm Huffman coding is to use certain mandatory conventions to reconstruct the structure of the Huffman coding tree with only a small amount of data. Convention 1: Numerical sequence property, which requires that codewords of the same length are binary descriptions of consecutive integers. Convention 2: In order to make the most of the coding space, the length of the first codeword is i Can be obtained from the last codeword of length i-1 It is concluded that: . Convention 3: The first code with the smallest codeword length starts from 0. Through the above convention, it is possible to restore the structure of the entire Huffman coding tree based on the length of each codeword. Drawing on the idea of ​​paradigm Huffman coding, in order to further reduce the amount of information that needs to be saved, the Deflate algorithm stipulates the use of a special Huffman tree, called the Deflate tree. According to RFC1951, the Deflate tree has the following new features compared to the Huffman tree: (a) The two leaf nodes of the same root node in the last layer, the left node character is smaller than the right node; (b) Except for the last layer, the right subtree cannot be a leaf node, it must be a branch node of the subtree; therefore, a Huffman tree can be uniquely constructed, and further observation shows that each layer has only one leaf node, and the codeword of the character can be obtained by recording the depth (codeword length) of the character.

[0068] There are two types of Huffman coding: dynamic Huffman coding and static Huffman coding. Dynamic Huffman coding is a method that continuously updates the Huffman tree during the data encoding process. This encoding method allows the encoder and decoder to gradually build and adjust the Huffman tree when processing data, thereby adapting to changes in the statistical characteristics of the data. Static Huffman coding is a Huffman tree that is pre-built based on the statistical characteristics of the data before encoding begins. This tree remains unchanged throughout the encoding process. Dynamic Huffman coding has a high compression rate but consumes a lot of resources. Static Huffman coding uses a pre-defined Huffman code table to quickly query the character encoding. The compression rate is not as good as dynamic Huffman coding, but the implementation method is simple.

[0069] The original data stream is compressed by the LZ77 compressor 22 and then processed by the conversion module to form two data streams, distance [8:0] dist and symbol [8:0] symbol. The check module statistically outputs the amount of compressed data and the CRC32 check code of the final data block. The above data are all used as input to the Huffman encoder 23. Fig.16 is a schematic diagram of the architecture of the Huffman encoder 23 in this embodiment, as shown in Fig.16As shown, the Huffman encoder 23 is used to perform Huffman encoding according to the two data streams of distance [8:0] dist and symbol [8:0] symbol output by the conversion module, and the length len and cyclic redundancy check code of the data stream output by the check module, and output the compressed data stream (4 bytes) with a data width of 4 bytes and a total of 32 bits according to the GZIP format requirements. In the implementation of the Huffman encoder 23 in this embodiment, it can be determined whether to use the static Huffman method or the dynamic Huffman method according to the length of the data stream. When the number of data in the data stream is greater than the MIN_LEN of the dynamic Huffman tree, a dynamic Huffman tree is established, including a character coding tree and a distance coding tree. When DBLK is small, a static Huffman tree is used for encoding. For the dynamic Huffman method, it is necessary to count the frequency and construct a deflate tree. In order to facilitate implementation, an array is used to simulate the construction process of the deflate tree, and the characters and distance information of the input stream, the cyclic check code and length of each block, and the Huffman tree are stored in three buffers respectively.

[0070] like Fig.17 As shown, the Huffman encoder 23 in this embodiment uses a finite state machine FSM to manage the data compression process, and the finite state machine FSM includes: Idle state R_IDLE: used to receive data and write into the data buffer buffer_data. If the length len of the data stream exceeds the preset threshold MIN_LEN, the dynamic Huffman flag is set to wait for the end EOB of the block input and start constructing the dynamic Huffman tree r_dynamic until the construction is completed huffman_ed. At this time, the read and write addresses are different and the preparation state R_PREPARE is entered. Preparation state R_PREPARE: used to prepare the GIZP header. If the data stream is a new data stream r_l_sos, it is first initialized to the GIZP header, initializes the first stage of the output stream pipeline, and then jumps to the GZIP header output state R_GZIP_HEADER_2~3; if it is not the latest data stream, first use the output stream pipeline to output a 3-bit data block start identifier, and if the dynamic Huffman method r_dynamic is used, jump to the dynamic Huffman tree header output state R_DYN_HEADER_1~3; if the static Huffman method is used, jump to the dynamic Huffman tree output state R_DYN_OUTTREE; the output stream pipeline is used to output the encoding result in a pipeline manner; in this embodiment, if it is the latest data stream (r_l_sos), it is first initialized to the GIZP header ('h00088B1F, fixed value, where ID1 = 31 (0x1F), ID2 = 139 (0x8B), indicating the GZIP format, CM = 08, indicating the DEFLATE method), and then jump to different states depending on whether the dynamic Huffman tree (s_dynamic) is used; GZIP header output state R_GZIP_HEADER_2~3: used to output the header information required by the GZIP file format. If the dynamic Huffman method is used, it jumps to the dynamic Huffman tree header output state R_DYN_HEADER_1~3, otherwise it jumps to the dynamic Huffman tree output state R_DYN_OUTTREE; Dynamic Huffman tree head output state R_DYN_HEADER_1~3: used to output the description information of the Huffman tree, and after output, jump to the dynamic Huffman tree output state R_DYN_OUTTREE:; Dynamic Huffman tree output state R_DYN_OUTTREE: used to output the constructed Huffman tree, and jump to the Huffman coding output state R_HUFFMAN_OUT after output; Huffman coding output state R_HUFFMAN_OUT: used to read the data buffer buffer_data, take out the LZ77 coded data, convert it into Huffman coding, and output it to the buffer. After output, jump to the end block symbol output state R_EOB_SYMBOL; End block symbol output state R_EOB_SYMBOL: used to output the block end symbol EOB indicating the end of the data block in LZ77 compression, and jump to the post-processing state R_POST_PARE after output; Post-processing state R_POST_PARE: used to adjust the read and write pointers to prepare for the next compression. If the output block ends, it jumps to the GZIP tail output state R_GZIP_FOOTER_1~3, otherwise it jumps to the idle state R_IDLE; GZIP footer output state R_GZIP_FOOTER_1~3: used to output the footer information required by the GZIP file format, including the CRC checksum and the original data length, and jump to the idle state R_IDLE after output.

[0071] In order to improve the data processing speed, for design and debugging considerations, the data output stream of the Huffman encoder 23 in this embodiment uses a pipeline design. Fig.18 FIG. 2 is a schematic diagram of a data output pipeline of the Huffman encoder 23 in this embodiment. Fig.18 As shown, the output stream pipeline in this embodiment includes the following stages: Preliminary processing stage A, reads the raw data from the buffer (buffer_data) and performs preliminary processing according to the data type: sets the output enable signal, determines whether it is the beginning, end or end of the stream, extracts the symbol data and the number of additional bits (Bits in Table 1); Table lookup phase B, querying the Huffman table. If a static Huffman tree is used, this phase will query the static Huffman table to obtain the Huffman code and length of each symbol, and process the dynamic flags related to the dynamic Huffman tree; Coding stage C, obtain Huffman code, according to the results of dynamic Huffman tree or static Huffman table, obtain the Huffman code and code length of each symbol and distance. If it is a dynamic Huffman tree, reverse bit operation will be used to obtain the correct code; High and low bit merging stage D, bit stream merging, merging high and low bit Huffman codes in the same cycle, merging the code and length information from the encoding stage C into a unified bit stream, and calculating the number of merged bits; In the bitstream merging stage E, the bitstream is merged across clock cycles, 32 bits of data are output, the shift register t_bits is used to temporarily store the encoding, and the bit alignment is performed to ensure that the output data is aligned in bytes. If the number of valid bits in the shift register t_bitc is greater than 32, the lower 32 bits of the merged bitstream are output to the register e_data in the manner of low byte to high byte, and the part exceeding 32 bits is right-shifted to the lower bit of the shift register t_bits. At the same time, the byte valid signal byte_cnt is used to indicate that the bytes in the 32 bits are valid, and the stream end signal last is generated to indicate the end of the current block, and the final GZIP compressed AXI-Stream format output stream is generated, which is composed of the output signal e_en, the lower 32 bits of the bitstream of the register e_data, the byte valid signal byte_cnt, and the stream end signal last. So far, the output signals e_en, e_data, byte_cnt, and last of Stage E constitute the output stream in the AXI-Stream format, and the compressed data is transmitted to the signal output module under the control of the output stream merging module.

[0072] In this embodiment, the output stream merging module 24 includes an internal buffer for caching output data, and dynamically controls the input data flow according to the filling condition of the internal buffer based on the output flow control signal i_stall_n. When the internal buffer is close to full, the output flow control signal i_stall_n is set to notify the sender to suspend sending data to achieve elastic flow control. The output stream merging module 24 can dynamically control the input data flow according to the filling condition of the internal buffer by outputting the flow control signal i_stall_n. When the buffer is close to full, the output flow control signal i_stall_n is set to 0, thereby notifying the sender to suspend sending data, achieving elastic flow control, ensuring that data can be smoothly transmitted between components of different rates, and preventing data loss or buffer overflow caused by rate mismatch.

[0073] Fig.19 This is a schematic diagram of the workflow of the GZIP compression module 2 of this embodiment, see Fig.19It can be seen that the lossless compression circuit in this embodiment adopts a pipeline design, wherein the input flow control module constitutes the first stage of the pipeline, the partitioning module constitutes the second stage of the pipeline, the LZ77 compressor 22 constitutes the third stage of the pipeline, the conversion module and the verification module both constitute the fourth stage of the pipeline, the Huffman encoder 23 constitutes the fifth stage of the pipeline, and the output stream merging module 24 constitutes the sixth stage of the pipeline. The work of the GZIP compression module 2 in this embodiment includes: (1) The input flow control module receives data in a double buffer structure to ensure smooth data input; (2) The partitioning module uses a counter to count the data, then divides it into blocks, and adds a block end signal eob; (3) The LZ77 compressor 22 compresses the data in a pipeline form. The first stage receives the data and passes through a 10-stage pipeline. The post-compression data has two forms, the original code or the index pair (D, L); (4) The check module continuously calculates the CRC32 check code and counts the length of the data stream; (5) The conversion module maps the original character + matching length to 0~285 for the LZ77 compressed data according to the rules shown in Table 1, and uses similar rules for the matching distance. After mapping, it is transmitted to the Huffman encoder; (6) The Huffman encoder 23 continues to receive the converted data in the idle state. When the block ends (eob), if the Huffman tree needs to be constructed, the dist and symbol trees are constructed respectively. Only after the construction is completed can the next state be entered. The subsequent states are further processed, and finally the information of the coding tree and the encoded data output stream are output; (7) The output stream merging module 24 performs elastic flow control on the output stream.

[0074] In summary, in order to meet the processing requirements of high-throughput EEG signals, inspired by GZIP compression, a neural signal compression circuit for high-throughput EEG signals transmitted wirelessly is provided in this embodiment, and the key is high-throughput EEG signal streaming processing. 256-channel EEG data requires the system to have sufficient throughput and parallel processing capabilities in hardware design and data processing capabilities to support high-speed data transmission and processing. In order to save hardware resources, the design of this embodiment uses a time-division multiplexing scheme for the SPI interface, and the data stream alternately uses the same channel or interface in time. Therefore, the system must be able to effectively manage and schedule the data inputs of multiple SPI modules 11 to ensure that each interface can correctly transmit data within its time slot and avoid conflicts. Moreover, the parallel input of the 16-way SPI module 11 requires strict synchronization and timing control to ensure the accuracy and integrity of the data, and can achieve lossless compression processing of high-throughput EEG signals to reduce the bandwidth requirements for data transmission. In addition, the GZIP compression module 2 in this embodiment implements a hardware implementation of the Deflate algorithm, so that the Deflate algorithm can be combined with the LZ77 compression algorithm and the Huffman coding algorithm to achieve lossless compression of EEG signals based on hardware. In view of the high complexity of the Deflate algorithm, the implementation process needs to process a large number of bit operations and data flow management requires precise control and optimization, which increases the difficulty of development and verification, and the dependency of LZ77 compression and Huffman coding makes parallelization complicated, in order to maximize the use of hardware resources, the GZIP compression module 2 in this embodiment uses a finite state machine (FSM) combined with a pipeline during implementation. In addition, LZ77 compression requires a sliding window to find repeated string sequences, and an efficient access management strategy needs to be designed to support fast data access. In this embodiment, the GZIP compression module 2 uses a multi-buffer method for fast matching. When the dynamic Huffman coding algorithm is implemented, the GZIP compression module 2 in this embodiment uses an array to construct a deflate tree, which reduces the complexity of address calculation, and can access multiple elements in the array in parallel, while performing comparison and exchange operations, thereby accelerating the construction process of the deflate tree.

[0075] In addition, this embodiment also provides a chip, including a chip body and a signal processing circuit arranged in the chip body, and the signal processing circuit is the neural signal compression circuit.

[0076] In addition, this embodiment also provides an electronic device, including a microprocessor and a memory connected to each other, wherein the microprocessor includes the neural signal compression circuit.

[0077] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A neural signal compression circuit, characterized in that: include: A signal receiving module (1) is used to receive and sample multi-channel EEG signals in a time division multiplexing manner; GZIP compression module (2), used to perform lossless compression of pulse waveform data; A signal output module (3) is used to store and control the compressed pulse waveform data and perform parallel-to-serial conversion for output; A RAM memory (4) for providing a data storage function for the signal receiving module (1), the GZIP compression module (2) and the signal output module (3); A control unit (5) for providing configuration parameters for part or all of the signal receiving module (1), the GZIP compression module (2) and the signal output module (3); The signal receiving module (1), the GZIP compression module (2) and the signal output module (3) are connected in sequence, the RAM memory (4) is connected to the signal receiving module (1), the GZIP compression module (2) and the signal output module (3) respectively, and the control unit (5) is connected to part or all of the signal receiving module (1), the GZIP compression module (2) and the signal output module (3).

2. The neural signal compression circuit according to claim 1, characterized in that: The signal receiving module (1) comprises: The SPI module (11) includes multiple channels for performing serial conversion and outputting the EEG signals from the SPI interface; An input control module (12) is used to cache the outputs of the multi-channel SPI modules (11) and select the outputs; A preprocessing module (13) is used to perform IIR bandpass filtering on the gated output EEG signal; and a data frame generation module (14) for performing IIR bandpass filtering on the EEG signal to generate a data frame output; The SPI module (11), the input control module (12), the preprocessing module (13) and the data frame generation module (14) are connected in sequence, each SPI module (11) corresponds to a plurality of channels, and first receives the input signal of the first channel, then receives the input signal of the second channel, and so on, ultimately realizing the acquisition of electroencephalogram signals of the plurality of channels in a time division multiplexing manner, and different SPI modules (11) correspond to different channels.

3. The neural signal compression circuit according to claim 2, characterized in that: The SPI module (11) comprises: An instruction decoding unit (111) is used to decode an input configuration signal CMD and send the obtained configuration information to a prescaler (112), a counter comparison unit (113) and a configuration unit (114) respectively. The ninth bit CMD[8] of the configuration signal CMD is used to enable the working mode to be a serial data output mode or a serial data input mode. When the bit is 1'b1, the serial data output mode is enabled. When the bit is 1'b1, the serial data input mode is enabled. The first eight bits CMD[7:0] of the configuration signal CMD indicate the data length of each transmission in the serial data input mode and indicate the number of data transmissions to be executed continuously in the serial data output mode. A pre-divider (112) is used to capture the phase and polarity of the input clock clk and further transmit the clock to the counter comparison unit (113); A counter comparison unit (113), used for using a counter to implement clock frequency division to generate a trigger signal trigger; A configuration unit (114) is used to store a clock phase cpha and a clock polarity cpol, where cpol=0 indicates that the clock is in a low level state when in an idle state; cpol=1 indicates that the clock is in a high level state when in an idle state; cpha=0 indicates that the data is valid when the clock jumps from a low level to a high level, and the data is sampled at the rising edge of the clock; cpha=1 indicates that the data is valid when the clock jumps from a high level to a low level, and the data is sampled at the falling edge of the clock; A data shift register (115) is used to shift data in each clock cycle based on a trigger signal trigger. During each shift, a counter compares a count result with a data width DATA_WIDTH of the data shift register (115). If the count result is equal to the data width DATA_WIDTH, it is determined that the data shift register (115) has received enough data, and the data is loaded into a data output register sdi_data and then a 16-bit serial data input signal is output; The clock generating unit (116) is used to generate a divided clock sclk according to the following formula based on the clock phase cpha and the clock polarity cpol and the trigger signal trigger output by the counter comparing unit (113): f(sclk) = f(clk) / (2(n+1)), In the above formula, f(sclk) is the clock frequency of the divided clock sclk, f(clk) is the clock frequency of the input clock clk corresponding to the clock phase cpha and the clock polarity cpol, n is the value of the clock divided counter, n is specified by the configuration variable DEFAULT_CLK_DIV. At the rising edge of each system clock, if the divided cycle ends or the module is in the idle state or waiting for I / O to be ready, the value of the clock divided counter is loaded as the value of DEFAULT_CLK_DIV. If the above conditions are not met, the value of the clock divided counter decreases. When it decreases to 0, the trigger signal trigger becomes 1, indicating that a serial data input signal transmission can be started, and the divided clock sclk also jumps; The chip select generating unit (117) is used to generate a chip select signal CS according to the result output by the instruction D and the counter comparison unit (113), wherein the 13th and 14th bits D [13:12] of the instruction D are used to indicate the instruction type. When the chip select instruction is executed, the 9th and 10th bits D [9:8] of the instruction D are used to indicate the delay of chip select activation. When the time that the chip select signal indicated by the SPI counter value should remain in the activated state has reached the number of cycles specified by the command, and there is no need to repeat the chip select command, the low NUM_OF_CS bit of the instruction D is assigned to the chip select signal CS, wherein NUM_OF_CS is the specified chip select bit.

4. The neural signal compression circuit according to claim 2, characterized in that: The input control module (12) comprises a channel selector (122) and FIFO buffers (121) corresponding to the SPI modules (11) one by one, the input end of each FIFO buffer (121) being connected to the input end of the channel selector (122), the FIFO buffer (121) being used to receive waveform data after the channel is serially converted to parallel, and the channel selector (122) takes turns to fetch data from each FIFO buffer (121) in each cycle, so that data from all channels are continuously transmitted to the pre-processing module (13) in each clock cycle.

5. The neural signal compression circuit according to claim 2, characterized in that: The pre-processing module (13) is divided into five pipeline stages, and each pipeline stage uses the following filters with completely identical structures but different coefficients: ， ， , In the above formula, ~ is the n~nQth output of the filter, ~ is the n~nPth input of the filter, and is the intermediate variable, ~ as well as ~ is the coefficient of the filter, P and Q are the dimensions of the filter coefficient respectively; the five-stage pipeline filters out a part of the noise respectively, and finally achieves the purpose of filtering as a whole. Each stage of the pipeline uses four cycles for filtering, the first cycle is used to store input data, the second cycle is used to read intermediate data from the memory, the third cycle is used to calculate the filtering result, and the fourth cycle is used to store the intermediate data in the memory. After the result is calculated in the third cycle, the filtered result will be passed to the next stage of the pipeline, so that the preprocessing module (13) can complete the filtering of one data every five cycles at the fastest. The preprocessing module (13) stores the intermediate values ​​calculated by each channel independently without affecting each other, so as to realize that the filter independently filters the data of each channel.

6. The neural signal compression circuit according to claim 2, characterized in that: The frame header of the structured data frame generated by the data frame generation module (14) includes sampling frequency, channel information, waveform data and frame tail, wherein the sampling frequency and channel information each use one byte to represent the sampling frequency and 256 channels, and the frame tail is coded 0xFF.

7. The neural signal compression circuit according to claim 2, characterized in that: The GZIP compression module (2) comprises: A data stream division module (21), used for receiving an input data stream and implementing flow control, and dividing the input data stream into data blocks of fixed size; An LZ77 compressor (22) is used to implement the LZ77 compression algorithm in the Deflate algorithm to compress the data block; A Huffman encoder (23) is used to implement the Huffman encoding algorithm in the Deflate algorithm, and encode and output the data compressed by the LZ77 compression algorithm; An output stream merging module (24) is used to organize the encoded output according to the specified compression format specification and then output it; The data stream division module (21), the LZ77 compressor (22), the Huffman encoder (23) and the output stream merging module (24) are connected in sequence.

8. The neural signal compression circuit according to claim 2, characterized in that: The signal output module (3) comprises: An output control module (31) is used to receive data and store it in a RAM memory (4), and to take out the data stored in the RAM memory (4) and send it to a parallel-to-serial module (32); A parallel-to-serial module (32) for performing SPI parallel-to-serial conversion; and a communication module (33) for outputting data obtained by SPI parallel-to-serial conversion through a communication interface; A data path for address signals and data signals is provided between the output control module (31) and the RAM memory (4); a data path for configuration signals and parallel data is provided between the output control module (31) and the parallel-to-serial module (32); and a data path for clock signals and serial data is provided between the parallel-to-serial module (32) and the communication module (33). The compressed data is written into the RAM memory (4) after the address is generated by the output control module (31), and then read and shifted out by the output control module (31) according to the read address. After passing through the parallel-to-serial module (32) and the communication module (33), the data is transmitted to the RAM memory (4). is sent to the outside of the chip; as long as the RAM memory (4) is writable, the output control module (31) continuously receives the compressed data and writes and stores it in the RAM memory (4); when the parallel-to-serial module (32) is idle, as long as there is still data in the RAM memory (4), the output control module (31) reads the data and configures the parallel-to-serial module (32) to specify the number of continuous transmissions, then takes out the data stored in the RAM memory (4) and outputs the data through continuous shifting and sends it to the parallel-to-serial module (32) to perform the data parallel-to-serial operation, and then outputs it through the communication module (33).

9. A chip, comprising a chip body and a signal processing circuit arranged in the chip body, characterized in that: The signal processing circuit is the neural signal compression circuit according to any one of claims 1 to 8.

10. An electronic device comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor comprises the neural signal compression circuit according to any one of claims 1 to 8.

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