Wafer defect mode identification method and device

Abstract

The embodiment of the invention provides a wafer defect mode identification method and device, and the method comprises the steps: carrying out the point cloud conversion of a wafer graph of a to-be-identified wafer, and obtaining an original point cloud set of the to-be-identified wafer; performing normalization processing on each point cloud in the original point cloud set to obtain a normalized target point cloud set; constructing a point cloud feature map of the to-be-identified wafer according to the target point cloud set; and determining a defect mode identification result of the wafer to be identified according to the point cloud feature map and a pre-constructed classification network model. By means of the method, original information and geometric characteristics of the wafer graph are fundamentally reserved based on a normalization mode of the point cloud, meanwhile, the problem that information is lost or false information is introduced in the image size unifying process is solved, and the method is more suitable for defect mode recognition tasks of wafer graphs of multiple sizes. Compared with a traditional image normalization method, the method has the advantages that more stable and real feature representation can be provided, and the wafer defect pattern recognition precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a method and device for identifying a wafer defect mode. Background Art

[0002] With the continuous advancement of semiconductor manufacturing technology, the integration and complexity of chips have increased year by year, which has also put forward higher requirements for chip manufacturing processes. This complexity and high integration are not only reflected in chip design, but also put forward more stringent technical requirements for wafer processing, which is the basis of chips. During the wafer processing process, a variety of defects may occur, which will affect the yield and manufacturing cost of the product. As a two-dimensional image representing the state of the chip in the wafer, the wafer map can effectively help analyze whether there is a defect pattern in the wafer. Each defect is usually related to a specific process problem. The wafer defect pattern can not only track anomalies in production, but also provide an important basis for process optimization. Therefore, the identification of wafer map defect patterns has become a key task in semiconductor production.

[0003] At present, the methods for semiconductor wafer defect pattern recognition, whether traditional machine learning algorithms or deep learning-based algorithms, are essentially directly identified through the two-dimensional image of the wafer image. These image-based methods regard the wafer image and the chips in it as a two-dimensional single-channel image, and each pixel represents the state of a chip. However, in actual production, the resolution and shape of wafer images of different chips may vary significantly. In order to facilitate the unified processing of large amounts of data, the resolution of wafer images is usually normalized. This practice may lose some information or introduce inaccurate information. Due to the limitations of normalizing the resolution of wafer images, when the resolution of the original wafer image is significantly different from the normalized resolution, the recognition effect may be significantly reduced. Summary of the invention

[0004] The present invention provides a method and device for recognizing wafer defect patterns, which can provide more stable and realistic feature representation compared to traditional image normalization methods, thereby improving the accuracy of wafer defect pattern recognition.

[0005] In a first aspect, an embodiment of the present invention provides a method for identifying a wafer defect pattern, comprising:

[0006] Performing point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified;

[0007] Normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set;

[0008] Constructing a point cloud feature map of the wafer to be identified according to the target point cloud set;

[0009] According to the point cloud feature map and the pre-built classification network model, a defect pattern recognition result of the wafer to be identified is determined.

[0010] In a second aspect, an embodiment of the present invention provides a device for identifying a wafer defect pattern, comprising:

[0011] A point cloud conversion module is used to perform point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified;

[0012] A normalization module, used for normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set;

[0013] A feature extraction module, used to construct a point cloud feature map of the wafer to be identified according to the target point cloud set;

[0014] The result determination module is used to determine the defect pattern recognition result of the wafer to be identified based on the point cloud feature map and the pre-built classification network model.

[0015] The embodiment of the present invention provides a method and device for identifying wafer defect patterns, the method comprising: first, performing point cloud conversion on the wafer image of the wafer to be identified to obtain the original point cloud set of the wafer to be identified; secondly, normalizing each point cloud in the original point cloud set to obtain the normalized target point cloud set; then, constructing a point cloud feature map of the wafer to be identified based on the target point cloud set; finally, determining the defect pattern recognition result of the wafer to be identified based on the point cloud feature map and the pre-built classification network model. The above technical scheme first converts the wafer image of the wafer to be identified into a point cloud, and then performs normalization based on the point cloud. The normalization method based on the point cloud fundamentally retains the original information and geometric characteristics of the wafer image, and at the same time solves the problem of information loss or introduction of false information in the process of image unification, and is more suitable for the defect pattern recognition task of multi-size wafer images. Compared with the traditional image normalization method, it can provide a more stable and realistic feature representation, and improve the accuracy of wafer defect pattern recognition.

[0016] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic flow chart of a method for identifying a wafer defect pattern provided in the first embodiment of the present invention;

[0019] Figure 2 A schematic flow chart of another wafer defect pattern recognition method provided in Embodiment 2 of the present invention;

[0020] Figure 3 A schematic diagram of the structure of a wafer defect pattern recognition device provided in Embodiment 3 of the present invention;

[0021] Figure 4 A schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "original", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] It should be clear that automated methods based on image processing and machine learning are gradually emerging, such as defect pattern recognition through texture analysis, morphological processing and classification algorithms. However, these methods usually rely on manually designed features and are difficult to adapt to the diversity and complexity of actual chip manufacturing scenarios. Deep learning technology, especially methods based on convolutional neural networks and attention mechanisms, has brought new opportunities for wafer defect pattern recognition, which can automatically extract defect features and significantly improve recognition accuracy. At the same time, methods based on generative adversarial networks and data enhancement have also been used to deal with complex defects and class imbalance problems. At the same time, contrastive learning has also achieved good results in defect pattern recognition of small sample wafer images.

[0025] At present, the methods for semiconductor wafer defect pattern recognition, whether traditional machine learning algorithms or deep learning-based algorithms, are essentially directly identified through the two-dimensional image of the wafer map. These image-based methods treat the wafer map and the chips in it as a two-dimensional single-channel image, and each pixel represents the state of a chip. However, in actual production, the resolution and shape of wafer maps of different chips may vary significantly. For example, if the chip size is large, the resolution of the wafer map is low; if the chip size is small, the resolution of the wafer map is high; if the length and width of the chip are different, the length and width ratio of the wafer map will also be different. In order to facilitate the unified processing of large amounts of data, the resolution of the wafer map is usually normalized. A common practice is to unify wafer maps of different resolutions to the same resolution (for example, 224×224) through methods such as interpolation.

[0026] However, this approach may lose some information or introduce inaccurate information. When the resolution of the original wafer image is large and needs to be reduced, some chip data will inevitably be lost; and when the resolution of the original wafer image is small and needs to be enlarged, virtual pixels will be added. These virtual pixels do not represent actual chips. Due to the limitations of normalizing wafer image resolution, when the resolution of the original wafer image differs greatly from the normalized resolution, the recognition effect may be significantly reduced. To put it more intuitively, when the resolution of the original wafer image differs greatly from the normalized resolution, the recognition effect is more likely to be worse. Therefore, there is an urgent need for a method to solve the problem of poor recognition effect caused by excessive differences in wafer image resolution.

[0027] Embodiment 1

[0028] Figure 1 The present invention provides a flowchart of a wafer defect pattern recognition method provided in the first embodiment of the present invention. The method is applicable to the case of wafer defect pattern recognition. The method can be performed by a wafer defect pattern recognition device, which can be implemented in the form of hardware and / or software and can be configured in an electronic device. Figure 1As shown, the wafer defect pattern recognition method provided in the first embodiment may specifically include the following steps:

[0029] S101 , performing point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified.

[0030] In this embodiment, the wafer map can be specifically understood as a two-dimensional image representing the state of the chips in the wafer. A two-dimensional wafer map I is represented as: , where i and j represent the row and column indices of the pixel, Represents the grayscale value of the pixel, H and Respectively represent the height and width of the wafer image. Each pixel in the wafer image represents a chip, and the pixel grayscale value represents the state of the chip. There are three states: 0 means there is no chip at this location, 1 means there is a chip at this location and it has passed the test, and 2 means there is a chip at this location but it has not passed the test. The area composed of pixels with values ​​1 and 2 is usually circular or elliptical.

[0031] In the prior art, defect pattern recognition is performed directly through the two-dimensional image of the wafer image. The large difference between the original resolution of the wafer image and the resolution after normalization will lead to a decrease in the defect pattern recognition effect. Therefore, it is necessary to ensure how to solve the problem of decreased wafer defect pattern recognition effect caused by the large difference in wafer image resolution without losing the original wafer image information and introducing additional false information, thereby improving the accuracy and robustness of wafer defect pattern recognition. Considering that the point cloud is discretely distributed in space, while the image is densely distributed in space. This discrete distribution characteristic means that when normalizing wafer images of different sizes, the point cloud method will not introduce additional information or lose any existing information. Therefore, using point clouds for normalization can retain the characteristics of the original data to the greatest extent.

[0032] Based on the above description, in this embodiment, the wafer image of the wafer to be identified is converted into a point cloud, and each pixel contained in the wafer image is converted into a point cloud, and a point cloud set of the wafer to be identified is obtained, which is recorded as the original point cloud set. Exemplarily, the coordinates of each pixel of the wafer image can be converted into point cloud coordinates in a Cartesian coordinate system, and the chip state of each chip is used as the value of the point cloud to obtain a point cloud in a Cartesian coordinate system. Alternatively, each pixel in the wafer image is converted into a point cloud in polar coordinates.

[0033] S102 , normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set.

[0034] In this embodiment, since the point cloud contours converted from different wafer images have different sizes, the point clouds in the original point cloud set need to be normalized. Normalizing the point cloud means changing the coordinates of all points in the original point cloud set in equal proportion. Specifically, each point cloud in the original point cloud set is normalized, and the normalized point cloud set is recorded as the target point cloud set.

[0035] S103: construct a point cloud feature map of the wafer to be identified based on the target point cloud set.

[0036] In this embodiment, feature extraction is performed on the point cloud in the target point cloud set to construct a point cloud feature map of the wafer to be identified. In this embodiment, the point cloud in the target point cloud set is divided into regions for the purpose of more effectively extracting local features. According to manual experience in wafer defect pattern recognition, in many cases, the defect pattern of the wafer can be determined by judging a specific area without comprehensively analyzing the entire wafer. The point cloud in the target point cloud set is divided into regions, which can be divided into multiple regions recorded as point cloud regions.

[0037] Continuing with the above description, after dividing the point cloud into various point cloud areas, feature extraction can be performed based on the statistics of the chips that have passed the test and the chips that have not passed the test contained in the point cloud area. It is also possible to obtain a feature map by performing some other feature extraction operations on the points in the point cloud area. Since many defect modes can be judged based on chips that have not passed the test, only the data of chips that have not passed the test can be retained for feature extraction. This is equivalent to constructing a point cloud feature map of the wafer to be identified based on the chip status of each chip contained in each point cloud area.

[0038] S104, determining a defect pattern recognition result of the wafer to be identified according to the point cloud feature map and the pre-built classification network model.

[0039] Among them, the classification network model can be specifically understood as a model for identifying the defect pattern of the wafer to be identified, and its input is a point cloud feature map, and its output is a defect pattern recognition result. In this embodiment, the obtained point cloud feature map is input into the classification network model to classify and identify the defect pattern of the wafer. As a defect pattern recognition method for a wafer, the point cloud feature map can be directly input into a classification network model, and then the classification result is directly output, which is recorded as the defect pattern recognition result of the wafer to be identified. For example, the classification network model can adopt a deep residual network (ResNet50) or a convolutional neural network (DenseNet121), etc., which is not specifically limited here. Since there may be multiple different defect modes in the same wafer, it is preferred to use a network for multi-label classification tasks. It has been experimentally verified that the effect of this method is better than directly inputting the wafer map into the same network. It should be noted that there may be one or more defect modes in the wafer to be identified.

[0040] The above technical solution first converts the wafer image of the wafer to be identified into a point cloud, and then performs normalization based on the point cloud. The point cloud-based normalization method fundamentally retains the original information and geometric characteristics of the wafer image, while solving the problem of information loss or introduction of false information during the image unification process, and is more suitable for defect pattern recognition tasks of multi-size wafer images. Compared with traditional image normalization methods, it can provide more stable and realistic feature representation, and improve the accuracy of wafer defect pattern recognition.

[0041] As an optional embodiment of the embodiment of the present invention, on the basis of the above embodiment, after determining the defect pattern recognition result of the wafer to be recognized, the method further includes: post-processing the defect pattern recognition result to obtain a verified defect pattern recognition result.

[0042] In this embodiment, after performing pattern recognition on the point cloud feature map based on the classification network model to obtain the defect pattern recognition result, the defect pattern recognition result can be further verified based on the characteristics of different defect patterns on the wafer image to determine whether the recognition result is correct and obtain a verified defect pattern recognition result.

[0043] As a specific implementation method, the steps of post-processing the defect pattern recognition result to obtain the verified defect pattern recognition result can be optimized, including:

[0044] 1) If the defect pattern recognition result includes at least one of an edge position defect (Edge-Loc), an edge ring defect (Edge-Ring) and a local defect (Loc), then for each defect, a first maximum connected domain is determined according to a set first connectivity rule;

[0045] 2) For the local defect, if the number of continuous pixels included in the first maximum connected domain is greater than a first number threshold, determining that the wafer to be identified includes the local defect is a verified defect pattern recognition result;

[0046] 3) For the edge position defect, if the number of continuous pixels contained in the first largest connected domain adjacent to the edge of the wafer to be identified is greater than the first number threshold, then determining that the wafer to be identified contains an edge position defect is a verified defect pattern recognition result;

[0047] 4) For the edge ring defect, if the number of continuous pixels contained in the first largest connected domain adjacent to the edge of the wafer to be identified is greater than a second number threshold, then determining that the wafer to be identified contains an edge ring defect is a verified defect pattern recognition result;

[0048] Specifically, if the defect pattern recognition result includes at least one of edge position defect, edge ring defect and local defect, the maximum connected domain of the wafer map can be determined according to the set first connected rule. The first connected rule can be an eight-connected rule, and the eight-connected region means that starting from each pixel in the region, it can reach any pixel in the region through a combination of eight directions, namely, up, down, left, right, upper left, upper right, lower left and lower right, without going beyond the region.

[0049] In this embodiment, post-identification can be performed simultaneously for each defect included in the defect pattern recognition result. For local defects, if the number of continuous pixels included in the first largest connected domain of the wafer image is greater than the first number threshold, the wafer to be identified contains a local defect as a verified defect pattern recognition result.

[0050] For edge ring defects and edge position defects, if it is detected that there are not enough continuous pixels representing failed chips at the boundary of the original wafer image, it is considered that these two types of defects do not actually exist. For edge position defects, if the number of continuous pixels contained in the first largest connected domain adjacent to the edge of the wafer to be identified is greater than the first quantity threshold, the wafer to be identified is determined to contain an edge position defect as a verified defect pattern recognition result. For edge ring defects, if the number of continuous pixels is greater than the second quantity threshold, the wafer to be identified is determined to contain an edge ring defect as a verified defect pattern recognition result. Among them, the first quantity threshold may be different from the second quantity threshold, such as the second quantity threshold may be greater than the first quantity threshold,

[0051] It should be noted that the thresholds corresponding to these two types of defects are usually different. The number of pixels corresponding to the Edge-Ring defect is larger than that of the Edge-Loc defect. Therefore, the threshold corresponding to the Edge-Ring defect can be recorded as the second quantity threshold, and the threshold corresponding to the Edge-Loc defect can be recorded as the first quantity threshold. The threshold can be a fixed size or dynamically adjusted according to the wafer image resolution.

[0052] As another specific implementation manner, the step of post-processing the defect pattern recognition result to obtain the verified defect pattern recognition result may be optimized, including:

[0053] 1) If the defect pattern recognition result includes a scratch defect, determining a second maximum connected domain in the wafer map according to a set second connectivity rule;

[0054] 2) If the length of the farthest line segment corresponding to the two pixels farthest from each other in the second maximum connected domain is greater than a set distance threshold, and the ratio of the length of the farthest line segment to the projection length is greater than a set ratio threshold, then the scratch defect pattern contained in the wafer to be identified is taken as a verified defect pattern recognition result, wherein the projection length is the length of the projection of the target line segment in the vertical direction of the farthest line segment, and the two endpoints of the target line segment are the two pixel points farthest apart in the vertical direction of the farthest line segment.

[0055] In this embodiment, if the defect pattern recognition result includes a scratch defect, the second largest connected domain in the wafer image can be determined according to the set second connectivity rule. For scratch defects, the connectivity rule can be a custom twelve-connectivity rule, which can better extract curves. Among them, the custom twelve-connectivity rule includes pixels in the eight directions of the eight-connectivity rule in addition to pixels in the four directions of up, down, left and right outside the area determined by the eight-connectivity rule.

[0056] Exemplarily, if the two pixels with the farthest distance in the second largest connected domain are found, and the length of the farthest distance is calculated. Then the two farthest pixels are formed into a line segment, and the two pixels with the farthest distance in the direction perpendicular to the line segment in the second largest connected domain are found, and the projection length of the line segment composed of these two pixels in the direction perpendicular to the farthest line segment is determined. If the length of the farthest distance is large and the ratio of the length to the projection length is large enough, it is considered that the sample actually has a Scratch mode. In layman's terms, it is to determine whether the maximum connected domain is "slender" enough. If it is "slender" enough, it is considered that the wafer to be identified has a Scratch defect. If the ratio is less than or equal to the set ratio threshold, the wafer to be identified can be considered to contain no scratch defects as a verified defect pattern recognition result.

[0057] The above technical solution specifies the steps of post-processing the model recognition results, and improves the accuracy of defect recognition by further verifying the defect pattern recognition results.

[0058] Embodiment 2

[0059] Figure 2A flow chart of another method for identifying a wafer defect pattern provided in Embodiment 2 of the present invention. This embodiment is a further optimization of the above-mentioned embodiment. In this embodiment, “performing point cloud conversion on the wafer image of the wafer to be identified to obtain the original point cloud set of the wafer to be identified” is further limited and optimized, and “performing normalization on each point cloud in the original point cloud set to obtain a normalized target point cloud set” is further limited and optimized, and “constructing a point cloud feature map of the wafer to be identified based on the target point cloud set” is further limited and optimized, and “determining the defect pattern recognition result of the wafer to be identified based on the point cloud feature map and a pre-constructed classification network model” is further limited and optimized.

[0060] like Figure 2 As shown, this embodiment 2 provides a method for identifying a wafer defect pattern, which specifically includes the following steps:

[0061] S201, according to the coordinates of each pixel in the wafer image and the center coordinates of the wafer to be identified in the wafer image, combined with the state of each chip in the wafer to be identified, convert each pixel into a point cloud in a Cartesian coordinate system.

[0062] In this embodiment, the two-dimensional wafer image is converted into a point cloud in a Cartesian coordinate system. The coordinates of the point cloud (x, y) correspond to the position of each pixel in the image, and the value v of the point cloud represents the state of the corresponding chip.

[0063] Convert the wafer image I into a point cloud in the Cartesian coordinate system. Define the point cloud as a set P:

[0064] , where i and j are the horizontal and vertical coordinates of the current pixel in the image, represents the coordinates of the point cloud, Indicates the state of the chip. Traverse all pixels. If the current pixel value is 0, skip it; if the current pixel value is 1 or 2, convert the pixel into a point p. The calculation formula is:

[0065] ;

[0066] in, are the coordinates of the wafer center in the wafer image, is the gray value of the pixel, indicating the chip status. According to this formula, all pixels are converted into points, and a point cloud in the Cartesian coordinate system is obtained, with the origin of the coordinate system being the center of the wafer. , then the point cloud P can be expressed as:

[0067] ;

[0068] Based on the above formula, each pixel can be converted into a point cloud in a Cartesian coordinate system.

[0069] S202 , converting the point cloud in the Cartesian coordinate system into a point cloud in the polar coordinate system to form an original point cloud set of the wafer to be identified.

[0070] The polar coordinate system takes the center of the wafer to be identified in the wafer image as the pole and the positive direction of the horizontal axis of the Cartesian coordinate system as the polar axis.

[0071] In this embodiment, the point cloud in the Cartesian coordinate system is converted to the point cloud in the polar coordinate system. The pole of the polar coordinate system is the center of the wafer, and the positive direction of the x-axis of the Cartesian coordinate system is the polar axis. The point cloud in the Cartesian coordinate system is converted to the point cloud in the polar coordinate system to fit the distribution characteristics of wafer defects. In the polar coordinate system, the center of the wafer is the pole, and the positive direction of the axis of the wafer image is the polar axis. For each point in the point cloud , calculate its corresponding polar coordinates The conversion formula is as follows:

[0072] ;

[0073] Among them, after converting all points, we get the point cloud in the polar coordinate system :

[0074] ;

[0075] Based on the above formula, the point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system to form an original point cloud set of the wafer to be identified.

[0076] S203 : Determine a scaling ratio according to the original point cloud radius of the original point cloud set and a set normalized radius.

[0077] The radius of the original point cloud is the distance between the farthest point of the center point of the original point cloud and the center point.

[0078] In this embodiment, since the point cloud contours converted from different wafer images have different sizes, the point clouds in the original point cloud set need to be normalized. For example, let the radius of the wafer to be identified (i.e., the radius of the original point cloud) be , let the radius be normalized to R, then R can be divided by The resulting value can be used as the scaling factor.

[0079] It should be noted that wafer defects are usually caused by process problems, some of which are distributed in a circular or ring shape on the wafer, such as defective cores distributed in a ring shape at the edge of the wafer, most of the defective cores located near the center of the wafer, and the spatial distribution of defective cores similar to a donut. One possible cause of the Edge-Ring defect is the coating problem of the photoresist during the photolithography process. In the photolithography process, the photoresist is first dripped on the center of the wafer and then evenly coated on the surface of the wafer by high-speed rotation. However, due to problems such as inappropriate temperature, improper rotation parameter settings, or the photoresist itself, the photoresist may be unevenly distributed at the edge of the wafer, resulting in an Edge-Ring defect.

[0080] Through the analysis of Edge-Ring defects, it can be found that using a polar coordinate system with the wafer center as the pole to represent data can in principle better fit the root causes of various wafer defect patterns. Therefore, the use of a polar coordinate system helps improve the accuracy and performance of defect identification algorithms.

[0081] S204 , scaling the coordinates of each point cloud in the original point cloud set according to the scaling ratio to obtain a normalized target point cloud set.

[0082] In this embodiment, the coordinates of all point clouds in the original point cloud set are changed proportionally at the same time, so as to obtain a normalized point cloud set, which is recorded as the target point cloud set. This point cloud-based normalization method fundamentally retains the original information and geometric characteristics of the wafer image, while solving the problem of information loss or introduction of false information during the image unification process, and is more suitable for defect pattern recognition tasks of multi-size wafer images. Compared with traditional image normalization methods, it can provide more stable and realistic feature representation.

[0083] S205 , dividing the point cloud in the target point cloud set into regions to obtain multiple point cloud regions.

[0084] In this embodiment, the point cloud under polar coordinates is divided into regions in order to extract local features more effectively. According to the manual experience of wafer defect pattern recognition, in many cases, the defect pattern of the wafer can be determined by judging a specific area without comprehensively analyzing the entire wafer. For example, for Loc and Edge-Loc defect modes, it is only necessary to focus on the characteristics of these specific areas to conclude that the defect exists in the entire wafer. Through this regional division, areas with obvious defects can be processed intensively, improving the efficiency and accuracy of defect recognition.

[0085] Continuing with the above description, in this embodiment, the point cloud in the target point cloud set is divided into regions, which can be divided into multiple regions recorded as point cloud regions. Exemplarily, the point cloud can be divided into several annular regions, or the point cloud can be divided into several sector regions.

[0086] As a specific implementation method, the step of optimizing the region division of the point cloud in the target point cloud set to obtain multiple point cloud regions includes:

[0087] 1) Divide the radius of the point cloud in the target point cloud set into equal parts according to a first number to obtain a first number of annular regions.

[0088] In this embodiment, the point cloud in the normalized target point cloud set is divided into regions. The first number can be set according to the actual situation, and the radius of the normalized point cloud is divided equally according to the first number. Specifically, let the radius of the normalized wafer be R, and divide the circular area C with a radius less than R. First, divide the radius R into p parts to obtain p concentric circles. ,in , and set Corresponding to the center point. Through these concentric circles, we get p annular areas , where i=1,2,…,p, thus the circular area C is divided into p annular areas.

[0089] 2) The polar angle range of each annular area is equally divided according to the second quantity to obtain a third quantity of point cloud areas.

[0090] The third number is equal to the first number multiplied by the second number.

[0091] In this embodiment, the radius of the normalized point cloud is equally divided according to the first number to obtain the first number of annular regions, and the polar angle range is equally divided according to the second data, so that the entire point cloud is divided into multiple annular regions according to the radius and multiple sector regions according to the polar angle, thereby obtaining multiple point cloud regions. The second number is set according to actual conditions.

[0092] Specifically, the polar angle range [0,2π] is divided into parts, each part has an angle of 2π / k, so that each annular area is further divided into k sectors of equal area. Divided into regions, each of which belongs to both a concentric annular region and a sectoral region divided by a polar angle. To express this regions, where i=1,2,…,p, j=1,2,…,k.

[0093] S206 , constructing a point cloud feature map of the wafer to be identified according to the chip status of each chip contained in each point cloud area.

[0094] In this embodiment, after the point cloud is divided into various point cloud areas, feature extraction can be performed based on the statistics of the chips that have passed the test and the chips that have not passed the test contained in the point cloud area. It is also possible to obtain a feature map by performing some other feature extraction operations on the points in the point cloud area. Since many defect modes can be judged only based on the chips that have not passed the test, only the data of the chips that have not passed the test can be retained for feature extraction. In this embodiment, feature extraction is performed based on the chip status of each chip contained in each point cloud area to obtain the features of each point cloud area. The features of all point cloud areas are spliced ​​into a feature map, which is recorded as the point cloud feature map of the wafer to be identified.

[0095] As an implementation method, the steps of constructing a point cloud feature map of a wafer to be identified according to the chip status of the chip contained in each point cloud area can be optimized, including:

[0096] 1) For each point cloud region, according to the chips that have passed the test and the chips that have failed the test contained in the point cloud region, feature extraction is performed according to the first feature extraction method to construct a first feature map of the wafer to be identified.

[0097] In this embodiment, after dividing the point cloud into various point cloud regions, feature extraction can be performed based on the statistics of the chips that have passed the test and the chips that have failed the test contained in the point cloud region. This method is recorded as the first feature extraction method, and the extracted feature results are recorded as the first feature map. Exemplarily, the first feature extraction method can be to count the proportion of chips in different states in each point cloud region, or the center of gravity of the chips that have passed the test and the chips that have failed the test, or the degree of discreteness of the point cloud, etc. The first feature extraction method is not specifically limited here, and a suitable extraction method can be selected according to actual conditions.

[0098] For example, the proportion of chips in different states in each point cloud area can be counted. Specifically, the point cloud area is calculated. The number of chips that passed the test The number of chips that failed the test , and calculate the proportion of chips that pass the test in this area to all chips ,use Indicates area The percentage of chips that pass the test. After calculating the ratio of the point cloud area, a feature map of size [p, k, 1] can be obtained, where p and k represent the size of the feature map, and 1 represents the number of feature channels, that is, the feature of one channel is extracted. At the same time, other statistical methods can also be used to calculate some statistics to describe the characteristics of the area. Here are a few common statistics: the centroid of the points with values ​​1 and 2, the degree of discreteness of the point cloud, and a feature map of size [p, k, 1] can be obtained. The first feature map ,in Indicates the number of feature channels, i.e., extraction The characteristics of a channel.

[0099] It should be noted that the purpose of dividing the point cloud into regions and calculating the proportion of chips in different states in each region is to solve the problem of feature map differences caused by differences in the number of chips in the region after the wafer images of different sizes are converted into point clouds. Directly using the number of chips for analysis will result in a large difference in the feature maps between wafers with more chips and wafers with fewer chips. Therefore, it is hoped to find a variable that is not affected by the number of chips to characterize the characteristics of the region, and the proportion just meets this requirement. Regardless of the number of chips, if there is a defect on the wafer, the proportion of chips in different states will be highly similar in the area where the defect is located. In this way, the defect characteristics of the wafer can be reflected more objectively and consistently.

[0100] 2) Alternatively, for each point cloud region, according to the chips that have failed the test and are contained in the point cloud region, feature extraction is performed according to the second feature extraction method to construct a second feature map of the wafer to be identified.

[0101] In addition, in this embodiment, a feature map can also be obtained by performing other feature extraction operations on the points in the point cloud area. The feature map obtained in this step is recorded as the second feature map, which is expressed as , the shape is Since many defect modes can be judged only based on chips that have not passed the test, only the data of chips that have not passed the test can be retained. Specifically, the points with v=1 are removed and only the points with v=2 are retained. The second feature extraction method can be a point-based network PointNet, maximum pooling, or average pooling.

[0102] For example, only the point cloud area of ​​the chip data that failed the test will be retained The points are input into a point-based network PointNet, and a feature vector with adjustable depth can be obtained. After extracting features from all regions using the PointNet, a shape of The second feature map of . If you want to simplify, you can replace the PointNet network with some simple operations, such as maximum pooling and average pooling.

[0103] 3) Using the first feature map and / or the second feature map as a point cloud feature map.

[0104] In this embodiment, the first feature map or the second feature map can be used alone as the final point cloud feature map, or the first feature map and the second feature map can be concatenated together as the point cloud feature map. For example, assuming that the first feature map is , the second feature map is , you can directly As a point cloud feature map of size [p, k, C] , or you can directly As point cloud feature map , or you can and Splice them together as point cloud feature maps .

[0105] S207, input the point cloud feature map into the classification network model to obtain the defect pattern recognition result of the wafer to be identified. Alternatively, the wafer image is normalized and convolved to obtain an image feature map of the wafer image; the image feature map and the point cloud feature map are spliced ​​to obtain a spliced ​​fusion feature map; the fusion feature map is input into the classification network model to obtain the defect pattern recognition result of the wafer to be identified.

[0106] As a method of wafer defect pattern recognition, the point cloud feature map can be directly input into a classification network model, and then the classification result can be directly output and recorded as the defect pattern recognition result of the wafer to be identified.

[0107] As another way to identify wafer defect patterns, the wafer image and point cloud feature map can be used at the same time. First, since the size of the wafer image is inconsistent with the point cloud feature map, they cannot be directly spliced ​​together and input into the network, so a shape operation needs to be performed on them first. The original wafer images are usually of different sizes, and are normalized to the same shape through interpolation and other methods. The wafer images with unified shapes are convolved. Here, the normalized shape and the parameters of the convolution operation can be set to control the feature map size and point cloud feature map of the wafer image after several convolution operations. Figure 1 Performing a convolution operation on the wafer image is equivalent to extracting features from the wafer image, and the features obtained are recorded as image feature maps.

[0108] Following the above description, we can now stitch the images together to form a feature map, which is called a fused feature map. The fused feature map contains both the features of the image and the features of the point cloud.

[0109] In this embodiment, after the fused feature map is obtained, it can be input into the classification network model to finally obtain the defect pattern recognition result of the wafer to be identified.

[0110] The above technical solution specifies the steps of converting the wafer image into a point cloud, normalizing the point cloud, extracting features from the normalized point cloud, and determining the defect pattern recognition results. By converting the wafer image into a point cloud and normalizing the point cloud, the point cloud method will not introduce additional information or lose any existing information. Using the point cloud for normalization can retain the features of the original data to the greatest extent, thereby improving the accuracy and robustness of wafer defect pattern recognition. In addition, using a polar coordinate system with the center of the wafer as the pole to represent the data can, in principle, be more in line with the root cause of various wafer defect patterns. The use of a polar coordinate system helps to improve the accuracy and performance of the defect recognition algorithm. The point cloud under the polar coordinates is divided into regions in order to more effectively extract local features. Through this regional division, areas with obvious defects can be processed intensively, thereby improving the efficiency and accuracy of defect recognition. In addition, the features of the original wafer image and the features of the point cloud are fused for pattern recognition, which further improves the accuracy of the defect recognition results.

[0111] Embodiment 3

[0112] Figure 3 Schematic diagram of the structure of a wafer defect pattern recognition device provided in Embodiment 3 of the present invention. The device can be applied to the situation of recognizing wafer defect patterns. The wafer defect pattern recognition device can be configured in an electronic device, such as Figure 3 As shown, the device includes: a point cloud conversion module 31, a normalization module 32, a feature extraction module 33 and a result determination module 34; wherein,

[0113] A point cloud conversion module 31 is used to perform point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified;

[0114] A normalization module 32 is used to normalize each point cloud in the original point cloud set to obtain a normalized target point cloud set;

[0115] A feature extraction module 33 is used to construct a point cloud feature map of the wafer to be identified based on the target point cloud set;

[0116] The result determination module 34 is used to determine the defect pattern recognition result of the wafer to be identified based on the point cloud feature map and the pre-built classification network model.

[0117] The above technical solution first converts the wafer image of the identified wafer into a point cloud, and then performs normalization processing based on the point cloud. The point cloud-based normalization method fundamentally retains the original information and geometric characteristics of the wafer image, while solving the problem of information loss or introduction of false information during the image unification process, and is more suitable for defect pattern recognition tasks of multi-size wafer images. Compared with traditional image normalization methods, it can provide more stable and realistic feature representation and improve the accuracy of wafer defect pattern recognition.

[0118] Optionally, the point cloud conversion module 31 is specifically used for:

[0119] According to the coordinates of each pixel in the wafer image and the center coordinates of the wafer to be identified in the wafer image, combined with the status of each chip in the wafer to be identified, each pixel is converted into a point cloud in a Cartesian coordinate system;

[0120] The point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system to form an original point cloud set of the wafer to be identified. The polar coordinate system takes the center of the wafer to be identified in the wafer image as the pole and the positive direction of the horizontal axis of the wafer in the Cartesian coordinate system as the polar axis.

[0121] Optionally, the normalization module 32 is specifically configured to:

[0122] Determine a scaling ratio according to an original point cloud radius of the original point cloud set and a set normalized radius, wherein the original point cloud radius is a distance between the farthest point of the center point of the original point cloud and the center point;

[0123] The coordinates of each point cloud in the original point cloud set are scaled according to the scaling ratio to obtain a normalized target point cloud set.

[0124] Optionally, the feature extraction module 33 includes:

[0125] A region division unit is used to divide the point cloud in the target point cloud set into regions to obtain multiple point cloud regions;

[0126] The feature extraction unit is used to construct a point cloud feature map of the wafer to be identified according to the chip status of each chip contained in each point cloud area.

[0127] Optionally, the area division unit is specifically used to:

[0128] Divide the radius of the point cloud in the target point cloud set into equal parts according to a first number to obtain a first number of annular regions;

[0129] The polar angle range of each annular area is equally divided according to the second number to obtain a third number of point cloud areas, where the third number is equal to the first number multiplied by the second number.

[0130] Optionally, the feature extraction unit is specifically used to:

[0131] For each point cloud region, according to the chips that have passed the test and the chips that have failed the test contained in the point cloud region, feature extraction is performed according to the first feature extraction method to construct a first feature map of the wafer to be identified; or,

[0132] For each point cloud region, according to the chips that failed the test and were contained in the point cloud region, feature extraction was performed according to the second feature extraction method to construct a second feature map of the wafer to be identified;

[0133] The first feature map and / or the second feature map is used as a point cloud feature map.

[0134] Optionally, the result determination module 34 is specifically configured to:

[0135] Input the point cloud feature map into the classification network model to obtain the defect pattern recognition result of the wafer to be identified; or,

[0136] The wafer image is normalized and convolved to obtain an image feature map of the wafer image;

[0137] The image feature map and the point cloud feature map are spliced ​​to obtain a spliced ​​fusion feature map;

[0138] The fused feature map is input into the classification network model to obtain the defect pattern recognition result of the wafer to be identified.

[0139] Optionally, the device further includes a post-processing module, which is used to:

[0140] The defect pattern recognition results are post-processed to obtain verified defect pattern recognition results.

[0141] Optionally, the post-processing module is specifically used for:

[0142] If the defect pattern recognition result includes at least one of an edge position defect, an edge ring defect and a local defect, determining a first maximum connected domain for each defect according to a set first connected rule;

[0143] For the local defect, if the number of continuous pixels included in the first maximum connected domain is greater than a first number threshold, determining that the wafer to be identified includes the local defect is a verified defect pattern recognition result;

[0144] For the edge position defect, if the number of continuous pixels contained in the first maximum connected domain adjacent to the edge of the wafer to be identified is greater than the first number threshold, then it is determined that the wafer to be identified contains the edge position defect as a verified defect pattern recognition result;

[0145] For the edge ring defect, if the number of continuous pixels contained in the first maximum connected domain adjacent to the edge of the wafer to be identified is greater than a second number threshold, then it is determined as a verified defect pattern recognition result that the wafer to be identified contains an edge ring defect.

[0146] Optionally, the post-processing module is specifically used for:

[0147] If the defect pattern recognition result includes a scratch defect, determining a second maximum connected domain in the wafer map according to a set second connectivity rule;

[0148] If the length of the farthest line segment corresponding to the two pixels farthest from each other in the second maximum connected domain is greater than a set distance threshold, and the ratio of the length of the farthest line segment to the projection length is greater than a set ratio threshold, then the scratch defect pattern contained in the wafer to be identified is taken as a verified defect pattern recognition result, wherein the projection length is the length of the projection of the target line segment in the vertical direction of the farthest line segment, and the two endpoints of the target line segment are the two pixel points farthest apart in the vertical direction of the farthest line segment.

[0149] The wafer defect pattern recognition device provided in the embodiment of the present invention can execute the wafer defect pattern recognition method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0150] Embodiment 4

[0151] Figure 4 A schematic diagram of the structure of an electronic device provided for Embodiment 4 of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0152] like Figure 4As shown, the electronic device 40 includes at least one processor 41, and a memory connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 41 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 to the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0153] A number of components in the electronic device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disk, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0154] The processor 41 may be a variety of general and / or dedicated processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 executes the various methods and processes described above, such as a method for identifying a wafer defect pattern.

[0155] In some embodiments, the method for identifying a wafer defect pattern may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the method for identifying a wafer defect pattern described above may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the method for identifying a wafer defect pattern in any other appropriate manner (e.g., by means of firmware).

[0156] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0157] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0158] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0159] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0160] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0161] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0162] An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed by a processor, implements the method for identifying a wafer defect pattern as provided in any embodiment of the present invention.

[0163] In the process of implementation, the computer program product can be written in one or more programming languages ​​or a combination thereof to perform the computer program code for the operation of the present disclosure, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0164] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0165] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for identifying a wafer defect pattern, characterized in that: include: Performing point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified; Normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set; Constructing a point cloud feature map of the wafer to be identified according to the target point cloud set; According to the point cloud feature map and the pre-built classification network model, a defect pattern recognition result of the wafer to be identified is determined.

2. The method according to claim 1, characterized in that The step of performing point cloud conversion on the wafer image of the wafer to be identified to obtain an original point cloud set of the wafer to be identified includes: According to the coordinates of each pixel in the wafer image and the center coordinates of the wafer to be identified in the wafer image, combined with the state of each chip in the wafer to be identified, each pixel is converted into a point cloud in a Cartesian coordinate system; The point cloud in the Cartesian coordinate system is converted into a point cloud in the polar coordinate system to form an original point cloud set of the wafer to be identified, wherein the polar coordinate system takes the center of the wafer to be identified in the wafer image as the pole and takes the positive direction of the horizontal axis of the Cartesian coordinate system as the polar axis.

3. The method according to claim 1, characterized in that The step of normalizing the point cloud included in the original point cloud set to obtain a normalized target point cloud set includes: Determine a scaling ratio according to an original point cloud radius of the original point cloud set and a set normalized radius, wherein the original point cloud radius is a distance between the farthest point of the center point of the original point cloud and the center point; The coordinates of each point cloud in the original point cloud set are scaled according to the scaling ratio to obtain a normalized target point cloud set.

4. The method according to claim 1, characterized in that: The step of constructing a point cloud feature map of the wafer to be identified according to the target point cloud set includes: Dividing the point cloud in the target point cloud set into regions to obtain a plurality of point cloud regions; According to the chip status of each chip contained in each point cloud area, a point cloud feature map of the wafer to be identified is constructed.

5. The method according to claim 4, characterized in that The step of dividing the point cloud in the target point cloud set into regions to obtain a plurality of point cloud regions includes: Divide the radius of the point cloud in the target point cloud set into equal parts according to a first number to obtain a first number of annular regions; The polar angle range of each of the annular areas is equally divided according to a second number to obtain a third number of point cloud areas, where the third number is equal to the first number multiplied by the second number.

6. The method according to claim 4, characterized in that The step of constructing a point cloud feature map of the wafer to be identified according to the chip status of the chip contained in each point cloud area includes: For each of the point cloud regions, according to the chips that have passed the test and the chips that have failed the test contained in the point cloud region, feature extraction is performed according to a first feature extraction method to construct a first feature map of the wafer to be identified; or, For each of the point cloud regions, according to the chips that failed the test and are contained in the point cloud region, feature extraction is performed according to a second feature extraction method to construct a second feature map of the wafer to be identified; The first feature map and / or the second feature map is used as the point cloud feature map.

7. The method according to claim 1, characterized in that Determining the defect pattern recognition result of the wafer to be identified according to the point cloud feature map and the pre-built classification network model includes: Inputting the point cloud feature map into the classification network model to obtain the defect pattern recognition result of the wafer to be identified; or, Performing normalization and convolution processing on the wafer image to obtain an image feature map of the wafer image; Splicing the image feature map and the point cloud feature map to obtain a spliced ​​fusion feature map; The fused feature map is input into the classification network model to obtain the defect pattern recognition result of the wafer to be identified.

8. The method according to claim 1, characterized in that After determining the defect pattern recognition result of the wafer to be recognized, the method further includes: The defect pattern recognition result is post-processed to obtain a verified defect pattern recognition result.

9. The method according to claim 8, characterized in that The post-processing of the defect pattern recognition result to obtain a verified defect pattern recognition result includes: if the defect pattern recognition result includes at least one of an edge position defect, an edge ring defect, and a local defect, determining a first maximum connected domain for each defect according to a set first connectivity rule; For the local defect, if the number of continuous pixels included in the first maximum connected domain is greater than a first number threshold, determining that the wafer to be identified includes the local defect is a verified defect pattern recognition result; For the edge position defect, if the number of continuous pixels contained in the first maximum connected domain adjacent to the edge of the wafer to be identified is greater than the first number threshold, then it is determined that the wafer to be identified contains the edge position defect as a verified defect pattern recognition result; For the edge ring defect, if the number of continuous pixels contained in the first maximum connected domain adjacent to the edge of the wafer to be identified is greater than a second number threshold, then it is determined as a verified defect pattern recognition result that the wafer to be identified contains an edge ring defect.

10. The method according to claim 8, characterized in that The post-processing of the defect pattern recognition result to obtain a verified defect pattern recognition result includes: If the defect pattern recognition result includes a scratch defect, determining a second maximum connected domain in the wafer map according to a set second connectivity rule; If the length of the farthest line segment corresponding to the two pixels farthest from each other in the second maximum connected domain is greater than a set distance threshold, and the ratio of the length of the farthest line segment to the projection length is greater than a set ratio threshold, then the scratch defect pattern contained in the wafer to be identified is taken as a verified defect pattern recognition result, wherein the projection length is the length of the projection of the target line segment in the vertical direction of the farthest line segment, and the two endpoints of the target line segment are the two pixel points farthest apart in the vertical direction of the farthest line segment.

11. A wafer defect pattern recognition device, characterized in that: include: A point cloud conversion module is used to perform point cloud conversion on a wafer image of a wafer to be identified to obtain an original point cloud set of the wafer to be identified; A normalization module, used for normalizing each point cloud in the original point cloud set to obtain a normalized target point cloud set; A feature extraction module, used to construct a point cloud feature map of the wafer to be identified according to the target point cloud set; The result determination module is used to determine the defect pattern recognition result of the wafer to be identified based on the point cloud feature map and the pre-built classification network model.

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