Display module and display device

Abstract

The application provides a display module and a display device. The display module comprises a display panel and a circuit board, and the circuit board is electrically connected with the display panel. The display panel comprises a substrate, a driving circuit and a pixel circuit. The driving circuit and the pixel circuit are located on the substrate. The driving circuit provides a control signal for the pixel circuit. The display panel further comprises a signal line group and a plurality of connection pads. The first signal line group comprises M signal lines for providing signals for the first driving circuit. The second signal line group comprises N signal lines for providing signals for the second driving circuit. M is greater than or equal to 1, and N is greater than or equal to 1. A first pin on the circuit board is connected with the signal lines through the connection pads. A first signal line in the M signal lines and a second signal line in the N signal lines are signal lines for transmitting the same function signal. The first signal line and the second signal line are electrically connected with the same first pin. The application can reduce the number of the first pins occupied on the circuit board, and is beneficial to improving the utilization efficiency of the first pins.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display module and a display device. BACKGROUND

[0002] With the continuous development of display technology, the display panel usually needs to transmit a plurality of scanning signals to the pixel circuit when the pixel circuit works, so as to realize the adjustment of the working state of the pixel circuit. It should be noted that the above-mentioned scanning signals can be generated by a plurality of scanning circuits on the display panel, and the scanning circuits need to rely on a plurality of electrical signals supplied by the circuit board to generate the above-mentioned scanning signals.

[0003] Usually, the scanning circuit can receive the required electrical signals through the path formed by the signal line, the pad, and the pin on the circuit board, and the same scanning circuit often needs to receive the electrical signals transmitted by a plurality of signal lines. In the prior art, different scanning circuits often need to receive the same function signal, but the paths corresponding to the above-mentioned different scanning circuits often correspond to different pins, resulting in unnecessary occupation of the pins on the circuit board, which is not conducive to the rationality of the circuit structure design. SUMMARY

[0004] Therefore, the present application provides a display module and a display device to solve the problem of unnecessary occupation of the pins.

[0005] In a first aspect, an embodiment of the present application provides a display module, comprising a display panel and a circuit board, the circuit board being electrically connected with the display panel; the display panel comprises:

[0006] a substrate;

[0007] a driving circuit and a pixel circuit, the driving circuit and the pixel circuit being located on the substrate, the driving circuit providing a control signal for the pixel circuit;

[0008] a signal line, the signal line providing a signal for the driving circuit;

[0009] the driving circuit comprises a first driving circuit and a second driving circuit;

[0010] a signal line group, the signal line group comprising a first signal line group and a second signal line group, the first signal line group comprising M signal lines providing a signal for the first driving circuit, the second signal line group comprising N signal lines providing a signal for the second driving circuit, M ≥ 1, N ≥ 1;

[0011] the display panel further comprises a plurality of connection pads; the circuit board comprises a plurality of first pins, the first pins being connected with the signal lines through the connection pads;

[0012] The first signal line in the M signal lines and the second signal line in the N signal lines are signal lines for transmitting same function signals; the first signal line and the second signal line are electrically connected with the same first pin.

[0013] In a second aspect, the embodiments of the present application provide a display device, including the display panel provided in the first aspect.

[0014] The setting mode of the embodiments of the present application can reduce the number of the first pins occupied on the circuit board, is beneficial to improve the utilization efficiency of the first pins, and is helpful to enhance the rationality of the circuit connection mode. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of the drawings.

[0016] Figure 1 A schematic diagram of a connection relationship between part structures of a display module provided by the present application;

[0017] Figure 2 A schematic diagram of part structures of a display module provided by the present application;

[0018] Figure 3 A schematic diagram of part structures of a display module provided by the present application;

[0019] Figure 4 An equivalent circuit diagram of a pixel circuit provided by the present application;

[0020] Figure 5 An equivalent circuit diagram of a gate drive circuit provided by the present application;

[0021] Figure 6 An equivalent circuit diagram of another gate drive circuit provided by the present application;

[0022] Figure 7 An equivalent circuit diagram of another gate drive circuit provided by the present application;

[0023] Figure 8 A schematic diagram of part structures of a display module provided by the present application;

[0024] Figure 9 A schematic diagram of part structures of a display module provided by the present application;

[0025] Figure 10 A schematic diagram of part structures of a gate drive circuit group provided by the present application;

[0026] Figure 11 A schematic diagram of a partial structure of a display module is provided in the present application;

[0027] Figure 12 A schematic diagram of the variation of the potential of the electrical signal transmitted by the first type of signal line in a working cycle of the driving circuit is shown;

[0028] Figure 13 A schematic diagram of a partial structure of a display panel is provided in the present application;

[0029] Figure 14 A schematic diagram of a partial structure of a display panel is shown in the figure; Figure 13 A schematic diagram of a partial structure of a display panel is shown in the figure;

[0030] Figure 15 A schematic diagram of a display device is provided in the present application. DETAILED DESCRIPTION

[0031] In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0032] It should be clear that the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0033] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0034] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0035] With the continuous development of display technology, the application scenarios of display devices are becoming more and more diverse, and the working modes of light emitting devices in display devices are also becoming more and more diversified. The main scheme for adjusting the working mode of the light emitting device at present can include: adjusting the light emitting driving current characteristics (such as amplitude size, pulse width size, etc.) provided by the pixel circuit to the light emitting device, so as to adjust the light emitting state of the light emitting device.

[0036] It should be noted that adjusting the scan signal transmitted to the pixel circuit to change the working state of the pixel circuit is a common method for adjusting the above-mentioned characteristics of the light-emitting driving current. The scan signal received by the pixel circuit is usually provided by the scan circuit on the display panel, and the scan circuit often needs to receive the electrical signal (which can be referred to as the circuit board signal) supplied by the circuit board to generate the above-mentioned scan signal.

[0037] Figure 1 A schematic diagram of a connection relationship between a part of a display module and a display panel.

[0038] As Figure 1 shown, the existing display panel 10' can include a plurality of scan circuits 01', which include a first scan circuit 01a' and a second scan circuit 01b'. The scan signal provided by the first scan circuit 01a' to the pixel circuit 02' and the scan signal provided by the second scan circuit 01b' to the pixel circuit can act on different functional modules in the pixel circuit 02', respectively.

[0039] The scan circuit 01' can be electrically connected to the pin 11a' of the circuit board 11' through the via 02' on the display panel 10', and the circuit board 11' can transmit the circuit board signal required by the scan circuit 01' through the via 02', wherein the circuit board 11' can be a flexible circuit board. Generally, the via 02' can be electrically connected to the pin 11a' one by one, and different scan circuits 01' correspond to different pins 11a', respectively. For example, as Figure 1 shown, the first scan circuit 01a' is electrically connected to the first pin 11a1' through the first via 021', and the second scan circuit 01b' is electrically connected to the second pin 11a2' through the second via 022'. At this time, it can be considered that the first scan circuit 01a' and the second scan circuit 01b' share two pins 11a'.

[0040] It should be noted that there are often different scanning circuits 01' that need to receive circuit board signals with the same function. For example, when the first scanning circuit 01a' needs to receive a circuit board signal through the first channel 021' and the second scanning circuit 01b' needs to receive a circuit board signal through the second channel 022', the electrical signal output by the circuit board 11' through the first pin 11a1' and the electrical signal output by the circuit board 11' through the second pin 11a2' can be the same. For two circuit board signals that are the same function signals, the circuit board 11' can output the two circuit board signals through the same pin 11a1'. However, the existing design scheme occupies two pins 11a' for the first scanning circuit 01a' and the second scanning circuit 01b', that is, the circuit board 11' outputs the circuit board signals that are the same function signals through two pins 11a' respectively, which leads to the waste of the number of pins 11a' of the circuit board 11', which is not conducive to the reasonable occupation of the pins 11a'.

[0041] Figure 2 A schematic diagram of part of the structure of a display module is provided for the present application, for the convenience of understanding, Figure 2 Only the connection relationship between part of the structures on the display panel and between the structures on the display panel and the pins of the circuit board is shown, and the specific structure of each circuit is not shown in detail.

[0042] In view of the above problems, as Figure 2 The present application provides a display module 20, which comprises a display panel 10 and a circuit board 11, and the circuit board 11 is electrically connected with the display panel 10.

[0043] The display panel 10 comprises a substrate 01, a driving circuit 02 and a pixel circuit 03, the driving circuit 02 and the pixel circuit 03 are located on the substrate 01, and the driving circuit 02 provides a control signal for the pixel circuit 03. Different control signals provided by different driving circuits 02 can act on different functional modules in the pixel circuit 03.

[0044] The display panel 10 further comprises a signal line 04, the signal line 04 provides a signal for the driving circuit 02, and the signal provided by the signal line 04 for the driving circuit 02 can come from the circuit board 11.

[0045] The driving circuit 02 comprises a first driving circuit 021 and a second driving circuit 022, the control signal output by the first driving circuit 021 and the control signal output by the second driving circuit 022 can act on different structures on the pixel circuit 03, respectively, and the influence of the control signal output by the first driving circuit 021 on the working state of the pixel circuit 03 can be different from the influence of the control signal output by the second driving circuit 022 on the working state of the pixel circuit 03.

[0046] The display panel 10 can further include a signal line group 040, the signal line group 040 including a first signal line group 0401 and a second signal line group 0402, the first signal line group 0401 including M signal lines 04 for providing signals to the first driving circuit 021, and the second signal line group 0402 including N signal lines 04 for providing signals to the second driving circuit 022, M≥1, N≥1.

[0047] The display panel 10 further includes a plurality of connection pads 05, which can be electrically connected with the signal lines 04, that is, the driving circuit 02 can receive the circuit board signals transmitted by the circuit board 11 through the connection pads 05 electrically connected with the signal lines 04. It should be noted that there can be one-to-one electrical connection between the signal lines 04 and the connection pads 05, or multiple signal lines 04 can be electrically connected to the same connection pad 05 (which is not shown in the figure). Figure 2

[0048] The circuit board 11 includes a plurality of first pins 111, which are connected to the signal lines 04 through the connection pads 05. At this time, the circuit board 11 can be a flexible circuit board. The connection pads 05 can be electrically connected with the first pins 111 to achieve electrical connection between the circuit board 11 and the display panel 10.

[0049] The first signal line 041 of the M signal lines 04 and the second signal line 042 of the N signal lines 04 are signal lines for transmitting the same functional signals. For example, the first signal line 041 and the second signal line 042 can both transmit clock signals or power voltage signals.

[0050] The first signal line 041 and the second signal line 042 are both electrically connected with the same first pin 111. Since the signals transmitted by the first signal line 041 and the second signal line 042 are the same functional signals, the circuit board 11 can transmit the required electrical signals of the first signal line 041 and the second signal line 042 through the same first pin 111.

[0051] Compared with the first signal line 041 and the second signal line 042 receiving the required electrical signals through different first pins 111 respectively, the arrangement of the present application can reduce the number of first pins 111 occupied on the circuit board 11, which is conducive to improving the utilization efficiency of the first pins 111 and helping to enhance the rationality of the circuit connection mode.

[0052] Figure 3 For the schematic diagram of part of the structure of the display module provided by the present application, for the convenience of understanding, Figure 3 only the connection relationship between part of the structures on the display panel and between the structures on the display panel and the pins of the circuit board is shown, and the specific structure of each circuit is not shown in detail.

[0053] ​In an embodiment of the present application, as shown in Figure 3 The circuit board 11 further includes second pins 112, and the connection pads 05 are connected to the second pins 112 correspondingly. At this time, the circuit board 11 can be a flexible printed circuit, and the circuit board 11 can include a receiving side 11a and an output side 11b. The first pins 111 can be located on the circuit board 11 near the receiving side 11a, and the second pins 112 can be located on the circuit board 11 near the output side 11b. The first pins 111 can be used to receive electrical signals, and the received electrical signals can be transmitted to the second pins 112. The second pins 112 can transmit the electrical signals received from the first pins 111 to the connection pads 05. There can be a case where some of the first pins 111 are connected to the second pins 112 correspondingly on the circuit board 11, and there can also be a case where multiple second pins 112 are electrically connected to the same first pin 111.

[0054] The connection pads 05 can include first pads 051 and second pads 052, and the first pads 051 are electrically connected to the first signal lines 041, and the second pads 052 are electrically connected to the second signal lines 042. Since the connection pads 05 are connected to the second pins 112 correspondingly, the first signal lines 041 and the second signal lines 042 can receive the required electrical signals through different second pins 112.

[0055] The second pins 112 corresponding to the first pads 051 and the second pins 112 corresponding to the second pads 052 are electrically connected to the same first pin 111. In the circuit board 11, the second pins 112 corresponding to the first pads 051 (which can be referred to as first-type pins) and the second pins 112 corresponding to the second pads 052 (which can be referred to as second-type pins) can be electrically connected to the same first pin 111 through two wiring structures L, respectively. The connection mode of connecting the same structure (such as the first pin 111) through two wiring structures L described above can be referred to as a split connection mode. In the split connection mode, there are multiple wiring structures L transmitting the same electrical signal, and the distribution range of the wiring transmitting the same electrical signal is wide. It should be noted that the wider the distribution range of the wiring transmitting the same electrical signal, the higher the risk of interference of the electrical signal by the external environment. Therefore, when implementing the split connection mode described above, appropriate measures can be taken to reduce the interference with the electrical signal.

[0056] In the embodiments of the present application, the first type of pins and the second type of pins are electrically connected to the same first pin 111, which helps to realize that the first signal line 041 and the second signal line 042 correspond to the same first pin 111, is conducive to reducing the number of occupied first pins 111, and helps to rationalize the connection mode. In addition, compared with the display panel 10, the film layer structure of the circuit board 11 (when it is a flexible circuit board) is simpler, and the electrical signals transmitted by the traces on the circuit board 11 are less affected by external interference. Therefore, by implementing the above-mentioned branch connection mode on the circuit board 11, the number of occupied first pins 111 can be reduced, and at the same time, the interference of the environment on the electrical signals transmitted in the above-mentioned trace structure L can be reduced as much as possible.

[0057] In an embodiment of the present application, the first signal line 041 and the second signal line 042 are both clock signal lines.

[0058] In the embodiments of the present application, the electrical signals transmitted by the clock signal lines can be clock signals, and the potential of the clock signals has fluctuation. Compared with constant potential electrical signals, clock signals are more susceptible to external interference. Considering that the first signal line 041 and the second signal line 042 can be connected to the same first pin 111 on the circuit board 11 in the above-mentioned branch connection mode, the setting mode of the present embodiment can reduce the degree of interference of the environment on the above-mentioned clock signals on the premise of reducing the number of occupied first pins 111.

[0059] Figure 4 An equivalent circuit diagram of a pixel circuit provided by the present application.

[0060] In an embodiment of the present application, as shown in Figure 4 The pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032, and the amplitude modulation sub-circuit 031 can be connected to the pulse width modulation sub-circuit 032. The pixel circuit 03 generates a driving current under the control of the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032. The amplitude modulation sub-circuit 031 can be used to control the amplitude of the driving current, and the pulse width modulation sub-circuit 032 can be used to adjust the pulse width of the voltage applied to the light emitting device 033.

[0061] As shown in Figure 4 The amplitude modulation sub-circuit 031 includes a first drive transistor T11, a first data write transistor T12, a first adjustment transistor T13, a first voltage write transistor T14, a first voltage transmission transistor T15, a first reset transistor T16, a first modulation transistor T17, a first output transistor T18, a second reset transistor T19, a second voltage transmission transistor T20, and a third voltage transmission transistor T10.

[0062] The control end of the first voltage transmission transistor T15 can receive a scanning signal transmitted by the third scanning line S3, and the scanning signal transmitted by the third scanning line S3 can control the power voltage signal transmitted by the first power voltage signal line VDD1 to be written into the input end of the first driving transistor T11. The control end of the second reset transistor T19 can receive a scanning signal transmitted by the fourth scanning line S4, and the scanning signal transmitted by the fourth scanning line S4 can control the electrical signal (which can be referred to as a first reset signal) transmitted by the reset signal line Vset to be written into the control end of the first modulation transistor T17. The input end of the first reset transistor T16 can receive a scanning signal (which can be referred to as a second reset signal) transmitted by the fifth scanning line S5, and when the first reset transistor T16 is turned on, the scanning signal transmitted by the fifth scanning line S5 can be written into the control end of the first driving transistor T11, thereby completing the reset process. The control end of the first output transistor T18 can receive a scanning signal transmitted by the second scanning line S2, and the scanning signal transmitted by the second scanning line S2 can control the driving current to be written into the first electrode of the light emitting device L.

[0063] The pulse width modulation sub-circuit 032 includes a second driving transistor T21, a second data writing transistor T22, a second modulation transistor T23, a second voltage writing transistor T24, a second voltage transmission transistor T25, a third reset transistor T26, and a second output transistor T27.

[0064] As shown in FIG. 1, Figure 4 The control end of the first data writing transistor T12, the control end of the first modulation transistor T13, the control end of the second data writing transistor T22, and the control end of the second modulation transistor T23 can all receive a scanning signal transmitted by the sixth scanning line S6, and the scanning signal transmitted by the sixth scanning line S6 can control the data signal transmitted by the second data signal line Vdata2 to be written into the control end of the first driving transistor T11, and can also control the data signal transmitted by the first data signal line Vdata1 to be written into the control end of the second driving transistor T21, thereby completing the data writing process. The first plate of the second capacitor C2 can receive a scanning signal transmitted by the first scanning line S1, and the second plate of the second capacitor C2 can be electrically connected to the control end of the second driving transistor T21, and the scanning signal transmitted by the first scanning line S1 can be used to control the potential of the control end of the second driving transistor T21.

[0065] It should be noted that all the transistors in the pixel circuit 03 can be P-type transistors.

[0066] Figure 5 An equivalent circuit diagram of a gate drive circuit provided by the present application is shown in FIG. 1, Figure 6 An equivalent circuit diagram of another gate drive circuit provided by the present application is shown in FIG. 2, and it should be noted that, Figure 5The circuit diagram shown can illustrate the circuit structure of the first gate drive circuit, and can also illustrate the circuit structure of the second gate drive circuit.

[0067] In combination Figure 5 and Figure 6 , the display panel 10 further includes a first gate drive circuit 061, a second gate drive circuit 062, and a third gate drive circuit 063.

[0068] The electrical signal output by the first gate drive circuit 061 adjusts the gate potential size of the second drive transistor T21 in the pulse width modulation sub-circuit 032. The output end of the first gate drive circuit 061 can be electrically connected to the first scan line S1, and thus the scan signal output by the first gate drive circuit 061 can be transmitted to the first plate of the second capacitor C2 through the first scan line S1, thereby adjusting the gate potential size of the second drive transistor T21.

[0069] The electrical signal output by the second gate drive circuit 062 controls the light-emitting drive current output by the amplitude modulation sub-circuit 031. The output end of the second gate drive circuit 062 can be electrically connected to the second scan line S2, and thus the scan signal output by the second gate drive circuit 062 can be transmitted to the control end of the first output transistor T18 through the second scan line S2, thereby controlling the light-emitting drive current output to the light-emitting device L.

[0070] The electrical signal output by the third gate drive circuit 063 controls the power voltage signal written into the pulse width modulation sub-circuit 032. The output end of the third gate drive circuit 063 can be electrically connected to the third scan line S3, and thus the scan signal output by the third gate drive circuit 063 can be transmitted to the control end of the first voltage transmission transistor T15 through the third scan line S3, thereby controlling the power voltage signal transmitted by the first power voltage signal line VDD1 to be written into the input end of the first drive transistor T11.

[0071] The first drive circuit 021 and the second drive circuit 022 are respectively two of the first gate drive circuit 061, the second gate drive circuit 062, and the third gate drive circuit 063.

[0072] For example, as Figure 5 shown, the first drive circuit 021 is the first gate drive circuit 061, and the second drive circuit 022 is the second gate drive circuit 062. The second positive clock signal line CK2 in the first gate drive circuit 061 and the second positive clock signal line CK2 in the second gate drive circuit 062 can be commonly connected to the same first pin 111. The first negative clock signal line CKB1 in the first gate drive circuit 061 and the first negative clock signal line CKB1 in the second gate drive circuit 062 can also be commonly connected to the same first pin 111.

[0073] For example, in combinationFigure 5 and Figure 6 The first driving circuit 021 is the first gate driving circuit 061, and the second driving circuit 022 is the third gate driving circuit 063. The second positive clock signal line CK2 in the first gate driving circuit 061 and the third positive clock signal line CK3 in the third gate driving circuit 063 can be connected to the same first pin 111. The first inverted clock signal line CKB1 in the first gate driving circuit 061 and the second inverted clock signal line CKB2 in the third gate driving circuit 063 can also be connected to the same first pin 111.

[0074] like Figure 5 As shown, when the first lower output transistor T41 is turned on, the output terminal of the first gate drive circuit 061 can directly output the electrical signal transmitted by the first positive clock signal line CK1. Therefore, all pixel circuits 03 corresponding to the first gate drive circuit 061 can receive the electrical signal transmitted by the first positive clock signal line CK1 at this time. The number of pixel circuits 03 connected to the output terminal of the first gate drive circuit 061 determines the number of pixel circuits 03 to which the first positive clock signal line CK1 needs to provide electrical signals. In this case, the load on the first positive clock signal line CK1 can be considered relatively large. On the other hand, as... Figure 5 As shown, the output of the first gate drive circuit 061 cannot directly output the electrical signal transmitted by the second positive clock signal line CK2. Therefore, compared with the first positive clock signal line CK1, the load of the second positive clock signal line CK2 is smaller. In this application, a preferred configuration includes connecting the two signal lines with larger loads to different first pins 111, and connecting the two signal lines with smaller loads to the same first pin 111. This avoids the electrical signal transmitted by the same first pin 111 being unable to meet the transmission requirements of the two signal lines with larger loads, while reducing the number of first pins 111 that are occupied.

[0075] In this embodiment, combined with Figure 5 and Figure 6 It is known that neither the first driving circuit 021 nor the second driving circuit 022 directly outputs the electrical signals transmitted by the aforementioned clock signal lines (second positive clock signal line CK2, first negative clock signal line CKB1, and third positive clock signal line CK3), thus the load corresponding to the aforementioned clock signal lines can be relatively small. Therefore, in this embodiment, multiple aforementioned clock signal lines can be electrically connected to the same first pin 111, which helps to reduce the number of times the first pin 111 is occupied.

[0076] Figure 7 An equivalent circuit diagram of another gate drive circuit provided in this application should be noted. Figure 7The circuit diagram shown can illustrate the circuit structure of both the fourth gate drive circuit and the fifth gate drive circuit.

[0077] Alternatively, the display panel 10 may also include a fourth gate drive circuit 064 and a fifth gate drive circuit 065.

[0078] like Figure 7 As shown, the electrical signal output by the fourth gate drive circuit 064 controls the first reset signal to be written into the amplitude modulation sub-circuit 031. The output terminal of the fourth gate drive circuit 064 can be electrically connected to the fourth scan line S4. Then, the scan signal output by the fourth gate drive circuit 064 can be transmitted to the control terminal of the second reset transistor T19 via the fourth scan line S4, thereby controlling the first reset signal transmitted by the reset signal line Vset to be written into the control terminal of the first modulation transistor T17.

[0079] The fifth gate drive circuit 065 controls the writing of the second reset signal into the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032. The output terminal of the fifth gate drive circuit 065 can be electrically connected to the fifth scan line S5, so the second reset signal output by the fifth gate drive circuit 065 can be transmitted to the input terminals of the first reset transistor T16 and the third reset transistor T26 via the fifth scan line S5.

[0080] The first driving circuit 021 and the second driving circuit 022 are respectively the fourth gate driving circuit 064 and the fifth gate driving circuit 065.

[0081] For example, such as Figure 7 As shown, the first driving circuit 021 is the fourth gate driving circuit 064, and the second driving circuit 022 is the fifth gate driving circuit 065. The fourth positive clock signal line CK4 in the fourth gate driving circuit 064 and the fourth positive clock signal line CK4 in the fifth gate driving circuit 065 can be connected to the same first pin 111. The third inverse clock signal line CKB3 in the fourth gate driving circuit 064 and the third inverse clock signal line CKB3 in the fifth gate driving circuit 065 can also be connected to the same first pin 111.

[0082] In this embodiment, as Figure 7 As shown, neither the first driving circuit 021 nor the second driving circuit 022 directly outputs the electrical signals transmitted by the aforementioned clock signal lines (the fourth positive clock signal line CK4 and the third negative clock signal line CKB3), thus the load corresponding to the aforementioned clock signal lines can be relatively small. Therefore, in this embodiment, multiple aforementioned clock signal lines can be electrically connected to the same first pin 111, which helps to reduce the number of times the first pin 111 is occupied.

[0083] like Figure 4As shown, the connection relationship of the circuit structure in the amplitude modulation sub-circuit 031 is as follows: the input end of the first drive transistor T11 is electrically connected with the output end of the first voltage writing transistor T14, the output end of the first drive transistor T11 is electrically connected with the input end of the first modulation transistor T17, and the control end of the first drive transistor T11 is electrically connected with the output end of the first adjustment transistor T13. The input end of the first data writing transistor T12 is electrically connected with the second data signal line Vdata2, the output end of the first data writing transistor T12 is electrically connected with the input end of the first drive transistor T11, and the control end of the first data writing transistor T12 is electrically connected with the sixth scan line S6. The input end of the first adjustment transistor T13 is electrically connected with the output end of the first drive transistor T11, and the control end of the first adjustment transistor T13 is electrically connected with the sixth scan line S6. The input end of the first voltage writing transistor T14 is electrically connected with the first power voltage signal line VDD1, the output end of the first voltage writing transistor T14 is electrically connected with the input end of the first drive transistor T11, and the control end of the first voltage writing transistor T14 is electrically connected with the third scan line S3. The input end of the first voltage transmission transistor T15 is electrically connected with the output end of the first voltage writing transistor T14, the output end of the first voltage transmission transistor T15 is electrically connected with the first plate of the first capacitor C1, and the control end of the first voltage transmission transistor T15 is electrically connected with the third scan line S3. The second plate of the first capacitor C1 is electrically connected with the control end of the first drive transistor T11. The input end of the first reset transistor T16 is electrically connected with the fifth scan line S5, the output end of the first reset transistor T16 is electrically connected with the control end of the first drive transistor T11, and the control end of the first reset transistor T16 is electrically connected with the fifth scan line S5. The output end of the first modulation transistor T17 is electrically connected with the input end of the first output transistor T18, and the control end of the first modulation transistor T17 is electrically connected with the output end of the second reset transistor T19. The output end of the first output transistor T18 is electrically connected with the first pole of the light emitting device L, and the control end of the first output transistor T18 is electrically connected with the second scan line S2. The second pole of the light emitting device L is electrically connected with the third power voltage line VSS. The input end of the second reset transistor T19 is electrically connected with the reset signal line Vset, and the control end of the second reset transistor T19 is electrically connected with the fourth scan line S4. The input end of the second voltage transmission transistor T20 is electrically connected with the second power voltage signal line VDD2, the output end of the second voltage transmission transistor T20 is electrically connected with the first plate of the first capacitor C1, and the control end of the second voltage transmission transistor T20 is electrically connected with the fifth scan line S5. The input end of the third voltage transmission transistor T10 is electrically connected with the second power voltage signal line VDD2, the output end of the third voltage transmission transistor T10 is electrically connected with the first plate of the first capacitor C1, and the control end of the third voltage transmission transistor T10 is electrically connected with the sixth scan line S6.In addition, the amplitude modulation sub-circuit 031 also includes a third capacitor C3. The first plate of the third capacitor C3 is electrically connected to the reset signal line Vset, and the second plate of the third capacitor C3 is electrically connected to the control terminal of the first modulation transistor T17.

[0084] like Figure 4 As shown, the circuit connections in the pulse width modulation sub-circuit 032 are as follows:

[0085] The input terminal of the second driving transistor T21 is electrically connected to the output terminal of the second voltage writing transistor T24. The output terminal of the second driving transistor T21 is electrically connected to the input terminal of the second output transistor T27. The control terminal of the second driving transistor T21 is electrically connected to the output terminal of the second regulating transistor T23. The input terminal of the second data writing transistor T22 is electrically connected to the first data signal line Vdata1. The output terminal of the second data writing transistor T22 is electrically connected to the input terminal of the second driving transistor T21. The control terminal of the second data writing transistor T22 is electrically connected to the sixth scan line S6. The input terminal of the second regulating transistor T23 is electrically connected to the output terminal of the second driving transistor T21. The control terminal of the second regulating transistor T23 is electrically connected to the sixth scan line S6. The input terminal of the second voltage writing transistor T24 is electrically connected to the second power supply voltage signal line VDD2. The output terminal of the second voltage writing transistor T24 is electrically connected to the input terminal of the second driving transistor T21. The control terminal of the second voltage writing transistor T24 is electrically connected to the third scan line S3. The input terminal of the second voltage transfer transistor T25 is electrically connected to the first high-level voltage signal line VGH1, the output terminal of the second voltage transfer transistor T25 is electrically connected to the first plate of the second capacitor C2, and the control terminal of the second voltage transfer transistor T25 is electrically connected to the sixth scan line S6. The input and control terminals of the third reset transistor T26 are both electrically connected to the fifth scan line S5, and the output terminal of the third reset transistor T26 is electrically connected to the control terminal of the second drive transistor T21. The output terminal of the second output transistor T27 is electrically connected to the control terminal of the first modulation transistor T17, and the control terminal of the second output transistor T27 is electrically connected to the third scan line S3.

[0086] like Figure 5 As shown, the connection relationships of the circuit structures in the first gate driving circuit 061 and the second gate driving circuit 062 are as follows:

[0087] The input end of the first upper output transistor T31 is electrically connected with the second high-level voltage signal line VGH2, the output end of the first upper output transistor T31 is electrically connected with the first scan line S1 or the second scan line S2, and the control end of the first upper output transistor T31 is electrically connected with the output end of the third upper transistor T33. The input end of the second upper transistor T32 is electrically connected with the second high-level voltage signal line VGH2, the output end of the second upper transistor T32 is electrically connected with the control end of the first upper output transistor T31, the control end of the second upper transistor T32 is electrically connected with the second plate of the fourth capacitor C4, the first plate of the fourth capacitor C4 is electrically connected with the second positive clock signal line CK2. The input end of the third upper transistor T33 is electrically connected with the output end of the fourth upper transistor T34, and the control end of the third upper transistor T33 is electrically connected with the second positive clock signal line CK2. The input end of the fourth upper transistor T34 is electrically connected with the second positive clock signal line CK2, the output end of the fourth upper transistor T34 is also electrically connected with the second plate of the sixth capacitor C6, the control end of the fourth upper transistor T34 is electrically connected with the output end of the fifth lower transistor T45. The first plate of the sixth capacitor C6 is electrically connected with the output end of the fifth lower transistor T45. The input end of the fifth upper transistor T35 is electrically connected with the output end of the sixth upper transistor T36, the output end of the fifth upper transistor T35 is electrically connected with the control end of the third lower transistor T43, and the control end of the fifth upper transistor T35 is electrically connected with the second positive clock signal line CK2. The input end of the sixth upper transistor T36 is electrically connected with the second high-level voltage signal line VGH2, and the control end of the sixth upper transistor T36 is electrically connected with the output end of the fifth lower transistor T45. The input end of the seventh upper transistor T37 is electrically connected with the second high-level voltage signal line VGH2, the output end of the seventh upper transistor T37 is electrically connected with the control end of the first lower output transistor T41, the control end of the seventh upper transistor T37 is electrically connected with the second plate of the fifth capacitor C5, and the first plate of the fifth capacitor C5 is electrically connected with the second high-level voltage signal line VGH2. The input end of the eighth upper transistor T38 is electrically connected with the second high-level voltage signal line VGH2, the output end of the eighth upper transistor T38 is electrically connected with the control end of the third lower transistor T43, and the control end of the eighth upper transistor T38 is electrically connected with the output end of the second upper transistor T32. The input end of the ninth upper transistor T39 is electrically connected with the third high-level voltage signal line VGH3, the output end of the ninth upper transistor T39 is electrically connected with the control end of the eighth upper transistor T38, the control end of the seventh upper transistor T37, and the control end of the first upper output transistor T31, and the control end of the ninth upper transistor T39 is electrically connected with the first control line L01.

[0088] Furthermore, the input terminal of the first lower transistor T41 is electrically connected to the first positive clock signal line CK1, and the output terminal of the first lower transistor T41 is electrically connected to either the first scan line S1 or the second scan line S2. The input terminal of the second lower transistor T42 is electrically connected to the first low-level voltage signal line VGL1, and the output terminal of the second lower transistor T42 is electrically connected to the control terminal of the first lower transistor T41. The control terminal of the second lower transistor T42 is electrically connected to the output terminal of the third lower transistor T43. The input terminal of the third lower transistor T43 is electrically connected to the first low-level voltage signal line VGL1, and the control terminal of the third lower transistor T43 is electrically connected to the output terminal of the fifth upper transistor T35. The input terminal of the fourth lower transistor T44 is electrically connected to the first inverse clock signal line CKB1, and the output terminal of the fourth lower transistor T44 is electrically connected to the control terminal of the fourth upper transistor T34, the control terminal of the sixth upper transistor T36, and the first plate of the sixth capacitor C6. The control terminal of the fourth lower transistor T44 is electrically connected to the output terminal of the fifth upper transistor T35. The input terminal of the fifth lower transistor T45 is electrically connected to the first low-level voltage signal line VGL1, and the output terminal of the fifth lower transistor T45 is electrically connected to the control terminal of the fourth upper transistor T34. The control terminal of the fifth lower transistor T45 is also electrically connected to the first inverse clock signal line CKB1. The input terminal of the sixth lower transistor T46 is electrically connected to the first upper-level drive line A(n-1), and the output terminal of the sixth lower transistor T46 is electrically connected to the input terminal of the seventh lower transistor T47. The control terminal of the sixth lower transistor T46 is also electrically connected to the first inverse clock signal line CKB1. The aforementioned first upper-level drive line A(n-1) can transmit the electrical signal output by the (n-1)th stage gate drive circuit cascaded with the first gate drive circuit 061, where the first gate drive circuit 061 can be the nth stage gate drive circuit. The first lower-level drive line A(n+1) can transmit the electrical signal output by the (n+1)th stage gate drive circuit cascaded with the first gate drive circuit 061. The output terminal of the seventh lower transistor T47 is electrically connected to the control terminal of the second upper transistor T32, and the control terminal of the seventh lower transistor T47 is electrically connected to the first signal line L1. The input terminal of the eighth lower transistor T48 is electrically connected to the output terminal of the ninth lower transistor T49, the output terminal of the eighth lower transistor T48 is electrically connected to the control terminal of the third lower transistor T43, and the control terminal of the eighth lower transistor T48 is electrically connected to the second signal line L2. The input terminal of the ninth lower transistor T49 is electrically connected to the first lower-stage drive line A(n+1), and the control terminal of the ninth lower transistor T49 is electrically connected to the first inverse clock signal line CKB1.

[0089] like Figure 6 As shown, the connection relationship of the circuit structure in the third gate drive circuit 063 is as follows:

[0090] An input terminal of the first upper-upper output transistor T51 is electrically connected with the fourth high voltage signal line VGH4, an output terminal of the first upper-upper output transistor T51 is electrically connected with the third scan line S3, and a control terminal of the first upper-upper output transistor T51 is electrically connected with an output terminal of the second upper-upper transistor T52. An input terminal of the second upper-upper transistor T52 is electrically connected with the fourth high voltage signal line VGH4, and a control terminal of the second upper-upper transistor T52 is electrically connected with the third clock signal line CK3. An input terminal of the third upper-upper transistor T53 is electrically connected with an output terminal of the fourth upper-upper transistor T54, and a control terminal of the third upper-upper transistor T53 is electrically connected with the third clock signal line CK3. An input terminal of the fourth upper-upper transistor T54 is electrically connected with the third clock signal line CK3, and an output terminal of the fourth upper-upper transistor T54 is further electrically connected with a second plate of the eighth capacitor C8. A control terminal of the fourth upper-upper transistor T54 is electrically connected with an output terminal of the second lower-lower transistor T62. The first plate of the eighth capacitor C8 is electrically connected with the output terminal of the second lower-lower transistor T62. An input terminal of the fifth upper-upper transistor T55 is electrically connected with an output terminal of the sixth upper-upper transistor T56, an output terminal of the fifth upper-upper transistor T55 is electrically connected with a control terminal of the first lower-lower output transistor T61, and a control terminal of the fifth upper-upper transistor T55 is electrically connected with the third clock signal line CK3. An input terminal of the sixth upper-upper transistor T56 is electrically connected with the fourth high voltage signal line VGH4, and a control terminal of the sixth upper-upper transistor T56 is electrically connected with the output terminal of the second lower-lower transistor T62. An input terminal of the seventh upper-upper transistor T57 is electrically connected with the fifth high voltage signal line VGH5, an output terminal of the seventh upper-upper transistor T57 is electrically connected with the control terminal of the first upper-upper output transistor T51, and a control terminal of the seventh upper-upper transistor T57 is electrically connected with the second control line L02.

[0091] Furthermore, the input terminal of the first down-output transistor T61 is electrically connected to the second low-level voltage signal line VGL2, and the output terminal of the first down-output transistor T61 is electrically connected to the third scan line S3. The input terminal of the second down-output transistor T62 is electrically connected to the second low-level voltage signal line VGL2, and the control terminal of the second down-output transistor T62 is electrically connected to the second inverse clock signal line CKB2. The input terminal of the third down-output transistor T63 is electrically connected to the second inverse clock signal line CKB2, and the output terminal of the third down-output transistor T63 is electrically connected to the control terminal of the fourth up-output transistor T54. The control terminal of the third down-output transistor T63 is also electrically connected to the output terminal of the fifth up-output transistor T55. The input terminal of the fourth down-output transistor T64 is electrically connected to the output terminal of the fifth down-output transistor T65, and the output terminal of the fourth down-output transistor T64 is electrically connected to the control terminals of both the first down-output transistor T61 and the second up-output transistor T52. The control terminal of the fourth down-output transistor T64 is also electrically connected to the third signal line L3. The input terminal of the fifth lower transistor T65 is electrically connected to the second upper-stage drive line W(n-1), and the control terminal of the fifth lower transistor T65 is electrically connected to the second inverse clock signal line CKB2. The aforementioned second upper-stage drive line W(n-1) can transmit the electrical signal output by the (n-1)th stage gate drive circuit cascaded with the third gate drive circuit 063, where the third gate drive circuit 063 can be the nth stage gate drive circuit. The second lower-stage drive line W(n+1) can transmit the electrical signal output by the (n+1)th stage gate drive circuit cascaded with the third gate drive circuit 063. The input terminal of the sixth lower transistor T66 is electrically connected to the output terminal of the seventh lower transistor T67, and the output terminal of the sixth lower transistor T66 is electrically connected to the input terminal of the first lower output transistor T61. The control terminal of the sixth lower transistor T66 is electrically connected to the fourth signal line L4. The input terminal of the seventh lower transistor T67 is electrically connected to the second lower stage drive line W(n+1), and the control terminal of the seventh lower transistor T67 is electrically connected to the second inverse clock signal line CKB2.

[0092] like Figure 7 As shown, the connection relationship of the circuit structures in the fourth gate drive circuit 064 and the fifth gate drive circuit 065 is as follows:

[0093] An input terminal of the first upper-upper-upper output transistor T71 is electrically connected with the sixth high-level voltage signal line VGH6, an output terminal of the first upper-upper-upper output transistor T71 is electrically connected with the fourth scan line S4 or the fifth scan line S5 or the sixth scan line S6, and a control terminal of the first upper-upper-upper output transistor T71 is electrically connected with an output terminal of the fourth upper-upper-upper transistor T74. An input terminal of the second upper-upper-upper transistor T72 is electrically connected with the sixth high-level voltage signal line VGH6, an output terminal of the second upper-upper-upper transistor T72 is electrically connected with an input terminal of the third upper-upper-upper transistor T73, and a control terminal of the second upper-upper-upper transistor T72 is electrically connected with the output terminal of the fourth upper-upper-upper transistor T74. An output terminal of the third upper-upper-upper transistor T73 is electrically connected with an input terminal of the second lower-lower-lower transistor T82, and a control terminal of the third upper-upper-upper transistor T73 is electrically connected with the fourth positive clock signal line CK4. An input terminal of the fourth upper-upper-upper transistor T74 is electrically connected with the third negative clock signal line CKB3, and a control terminal of the fourth upper-upper-upper transistor T74 is electrically connected with an output terminal of the sixth lower-lower-lower transistor T86.

[0094] In addition, an input terminal of the first lower-lower-lower output transistor T81 is electrically connected with the fifth positive clock signal line CK5, an output terminal of the first lower-lower-lower output transistor T81 is electrically connected with the fourth scan line S4 or the fifth scan line S5 or the sixth scan line S6, and a control terminal of the first lower-lower-lower output transistor T81 is electrically connected with an output terminal of the second lower-lower-lower transistor T82. A control terminal of the second lower-lower-lower transistor T82 is electrically connected with the third low-level voltage signal line VGL3. An input terminal of the third lower-lower-lower transistor T83 is electrically connected with the third low-level voltage signal line VGL3, an output terminal of the third lower-lower-lower transistor T83 is electrically connected with a control terminal of the second upper-upper-upper transistor T72, and a control terminal of the third lower-lower-lower transistor T83 is electrically connected with the third negative clock signal line CKB3. An input terminal of the fourth lower-lower-lower transistor T84 is electrically connected with the third upper-level driving line S(n-1), an output terminal of the fourth lower-lower-lower transistor T84 is electrically connected with an input terminal of the fifth lower-lower-lower transistor T85, and a control terminal of the fourth lower-lower-lower transistor T84 is electrically connected with the third negative clock signal line CKB3. The third upper-level driving line S(n-1) can transmit an electrical signal output by an n-1th level gate driving circuit cascaded with the fourth gate driving circuit 064, the fourth gate driving circuit 064 can be an nth level gate driving circuit, and the third lower-level driving line S(n+1) can transmit an electrical signal output by an n+1th level gate driving circuit cascaded with the fourth gate driving circuit 064. An output terminal of the fifth lower-lower-lower transistor T85 is electrically connected with a control terminal of the fourth upper-upper-upper transistor T74, and a control terminal of the fifth lower-lower-lower transistor T85 is electrically connected with the sixth signal line L6. An input terminal of the sixth lower-lower-lower transistor T86 is electrically connected with the third lower-level driving line S(n+1), and a control terminal of the sixth lower-lower-lower transistor T86 is electrically connected with the fifth signal line L5.

[0095] Figure 8 This is a schematic diagram of a partial structure of a display module provided in this application, for ease of understanding. Figure 8 The document only shows the connection relationships between some structures on the display panel and between some structures on the display panel and the pins of the circuit board, without showing the specific construction of each circuit structure in detail.

[0096] In one embodiment of this application, such as Figure 8 As shown, the driving circuit 02 also includes a third driving circuit 023. The scanning signal output by the third driving circuit 023 can participate in the data writing process of the pixel circuit 03. To ensure the normal operation of the data writing process, the timing accuracy of the scanning signal output by the third driving circuit 023 needs to meet the expectations, that is, the rising and falling edge durations of the scanning signal when the potential changes need to be less than the threshold.

[0097] Signal line 04 also includes a third signal line 043, which provides a clock signal to the third driving circuit 023. The third signal line 043 and the first signal line 041 are signal lines 04 that transmit signals with the same function. The electrical signal transmitted by the third signal line 043 can participate in the process of the third driving circuit 023 generating a scanning signal. It should be noted that the rising and falling edge durations of the electrical signal transmitted by the third signal line 043 can affect the rising and falling edge durations of the scanning signal generated by the third driving circuit 023.

[0098] Among them, the third signal line 043 and the first signal line 041 are electrically connected to different first pins 111 respectively.

[0099] In this embodiment, although the third signal line 043 and the first signal line 041 are signal lines 04 that transmit signals with the same function, to avoid increasing the rising and falling edge durations of the electrical signal transmitted by the third signal line 043, it is necessary to electrically connect the third signal line 043 and the first signal line 041 to different first pins 111. The reason is that if the third signal line 043, the first signal line 041, and the second signal line 042 are electrically connected to the same first pin 111, the electrical signal transmitted by the first pin 111 will be supplied to all three signal lines simultaneously. Compared to the case where only one signal line is supplied with an electrical signal, the timing accuracy of the electrical signal transmitted by the first pin 111 is lower, and the corresponding rising and falling edge durations are longer. Therefore, by setting the third signal line 043 and the first signal line 041 to different first pins 111, this embodiment helps ensure that the timing accuracy of the third signal line 043 reaches the expected level, avoiding adverse effects on the data writing process of the pixel circuit 03.

[0100] In one embodiment of this application, such as Figure 4As shown, the pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032.

[0101] The display panel 10 further includes a sixth gate drive circuit 066, as shown in Figure 7 As shown, the circuit structure of the sixth gate drive circuit 066 can be the same as that of the fifth gate drive circuit 065 and the fourth gate drive circuit 054.

[0102] In combination with Figure 4 and Figure 7 , the electrical signal output by the sixth gate drive circuit 066 controls the data signal to be written into the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032. The output end of the sixth gate drive circuit 066 can be electrically connected to the control end of the first data write transistor T12, the control end of the first adjusting transistor T13, the control end of the second data write transistor T22 and the control end of the second adjusting transistor T23 through the sixth scan line S6.

[0103] Among them, the third drive circuit 023 is the sixth gate drive circuit 066.

[0104] In the embodiment of the present application, the third signal line 043 providing the electrical signal for the third drive circuit 023 can be connected to the first pin 111 one by one to avoid the time sequence accuracy of the electrical signal transmitted by the third signal line 043 being reduced due to the third signal line 043 and other signal lines 02 corresponding to the same first pin 111. The setting mode of the present embodiment helps to reduce the influence on the data writing process of the pixel circuit 03 on the premise of saving the number of first pins 111.

[0105] Figure 9 A schematic diagram of part of the structure of a display module provided by the present application.

[0106] In an embodiment of the present application, as shown in Figure 9 The circuit board 11 further includes a second pin 112, and the connection pad 05 and the second pin 112 are connected correspondingly. At this time, the circuit board 11 can be a flexible circuit board, and the circuit board 11 can include a receiving side 11a and an output side 11b. The first pin 111 can be located on the circuit board 11 near the area of the receiving side 11a, and the second pin 112 can be located on the circuit board 11 near the area of the output side 11b. The first pin 111 can be used to receive an electrical signal, and the received electrical signal can be transmitted to the second pin 112, and the second pin 112 can transmit the electrical signal received from the first pin 111 to the connection pad 05.

[0107] The connection pad 05 can include a first pad 051, the first signal line 041 and the second signal line 042 are electrically connected to the first pad 051, and the second pin 112 connected to the first pad 051 is correspondingly connected to the first pin 111. Therefore, the first signal line 041 and the second signal line 042 can receive electrical signals through the same second pin 112, and the connection mode between the first signal line 041, the second signal line 042 and the corresponding second pin 112 can constitute the above-mentioned branch connection mode, and the branch connection mode is located on the display panel 10.

[0108] The setting mode of the embodiment of the present application can make different signal lines 04 (the first signal line 041 and the second signal line 042) receive electrical signals through the same first pad 051, thereby reducing the number of required first pads 051. Since the first pad 051 and the second pin 112 can be correspondingly connected, the setting mode of the embodiment is helpful to reduce the number of occupied second pins 112 on the circuit board 11, and is conducive to the rationalization of the connection mode.

[0109] In an embodiment of the present application, the first signal line 041 and the second signal line 042 are both high-level voltage signal lines or low-level voltage signal lines.

[0110] In the above-mentioned branch connection mode, the transmission process of electrical signals on the first signal line 041 and the second signal line 042 is easily affected by external interference. Considering that the branch setting mode is located on the display panel 10 with relatively complex film layer structure, the preferred type of electrical signals transmitted by the first signal line 041 and the second signal line 042 can be constant voltage electrical signals, such as high-level voltage signals or low-level voltage signals. Therefore, the setting mode of the present application can reduce the number of occupied pins on the circuit board 11 while reducing the degree of external interference on the transmission process of electrical signals.

[0111] For example, please refer to Figure 5 , the first signal line 041 and the second signal line 042 can be respectively a first low-level voltage signal line VGL1 connected to the first gate drive circuit 061 and a first low-level voltage signal line VGL1 connected to the second gate drive circuit 062.

[0112] For example, please refer to Figure 7 , the first signal line 041 and the second signal line 042 can be respectively a sixth high-level voltage signal line VGH6 connected to the fourth gate drive circuit 064 and a sixth high-level voltage signal line VGH6 connected to the fifth gate drive circuit 065.

[0113] In an embodiment of the present application, the first signal line 041 and the second signal line 042 are both low-level voltage signal lines.

[0114] The pixel circuit 03 comprises an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032.

[0115] The display panel 10 further comprises a first gate drive circuit 061 and a second gate drive circuit 062. The first gate drive circuit 061 outputs an electrical signal to adjust the gate potential size of the second drive transistor T21 in the pulse width modulation sub-circuit 032. The second gate drive circuit 062 outputs an electrical signal to control the luminous drive current output by the amplitude modulation sub-circuit 031.

[0116] The first drive circuit 021 and the second drive circuit 022 are respectively two of the fourth gate drive circuit 064, the fifth gate drive circuit 065 and the sixth gate drive circuit 066.

[0117] For example, referring to Figure 7 , the first signal line 041 and the second signal line 042 can be respectively any two of the third low-level voltage signal lines VGL3 connected by the fourth gate drive circuit 064, the fifth gate drive circuit 065 and the sixth gate drive circuit 066.

[0118] In the embodiments of the present application, since the first drive circuit 021 and the second drive circuit 022 can not directly output the electrical signal transmitted by the third low-level voltage signal line VGL3, the third low-level voltage signal line VGL3 connected by the first drive circuit 021 and the third low-level voltage signal line VGL3 connected by the second drive circuit 022 can correspond to the same first pin 111, which helps to reduce the number of occupied first pins 111.

[0119] Figure 10 The schematic diagram of part of the structure of part of the gate drive circuit group provided in the present application is provided for the convenience of understanding, Figure 10 only the connection relationship between the gate drive circuits in the gate drive circuit group and part of the signal lines is abstractly shown.

[0120] In an embodiment of the present application, the display panel 10 can comprise a first gate drive circuit group 0601 and a second gate drive circuit group 0602. The first gate drive circuit group 0601 comprises a plurality of cascaded first gate drive circuits 061, and the second gate drive circuit group 0602 comprises a plurality of cascaded second gate drive circuits 062.

[0121] At this time, the first signal line 041 can transmit a start signal to the first-stage first gate drive circuit 061 in the first gate drive circuit group 0601, and the second signal line 042 can transmit a start signal to the first-stage second gate drive circuit 062 in the second gate drive circuit group 0602. When the first-stage first (second) gate drive circuit 061 (062) receives the start signal, the first-stage first (second) gate drive circuit 061 (062) starts to enter a working state, and then outputs an electrical signal to the next-stage gate drive circuit.

[0122] In combination with Figure 2 and Figure 10 , the first signal line 041 and the second signal line 042 correspond to the same first pin 111.

[0123] In the embodiment of the present application, the first signal line 041 and the second signal line 042 can both transmit a start signal, and the electrical signals transmitted by the two have the same function. In addition, it can be known from Figure 5 that the first gate drive circuit 061 and the second gate drive circuit 062 can have the same circuit structure, and the start signals transmitted by the first signal line 041 and the second signal line 042 can be the same. Therefore, the same first pin 111 can be used to transmit the start signal to the first signal line 041 and the second signal line 042, which helps to reduce the number of occupied first pins 111.

[0124] In an embodiment of the present application, the pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032.

[0125] The display panel 10 further includes a fourth gate drive circuit 064, a fifth gate drive circuit 065, and a sixth gate drive circuit 066. The fourth gate drive circuit 064 controls the writing of a first reset signal into the amplitude modulation sub-circuit 031; the fifth gate drive circuit 065 controls the writing of a second reset signal into the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032; and the sixth gate drive circuit 066 controls the writing of a data signal into the amplitude modulation sub-circuit 031 and the pulse width modulation sub-circuit 032.

[0126] The first drive circuit 021 and the second drive circuit 022 are respectively two of the fourth gate drive circuit 064, the fifth gate drive circuit 065, and the sixth gate drive circuit 066.

[0127] For example, the first drive circuit 021 and the second drive circuit 022 can be respectively the fourth gate drive circuit 064 and the fifth gate drive circuit 065.

[0128] For example, the first drive circuit 021 and the second drive circuit 022 can be respectively the fourth gate drive circuit 064 and the sixth gate drive circuit 066.

[0129] For example, the first driving circuit 021 and the second driving circuit 022 can be the fifth gate driving circuit 065 and the sixth gate driving circuit 066 respectively.

[0130] In the embodiment of the present application, the first driving circuit 021 and the second driving circuit 022 can be two of the fourth gate driving circuit 064, the fifth gate driving circuit 065 and the sixth gate driving circuit 066, which means that the part signal lines 04 (for example, the sixth high-level voltage signal line VGH6 or the third low-level voltage signal line VGL3) connected by the fourth gate driving circuit 064, the fifth gate driving circuit 065 and the sixth gate driving circuit 066 respectively can correspond to the same first pin 111, which helps to rationalize the connection relationship between the structures in the display module 20.

[0131] Figure 11 A schematic diagram of part of the structure of the display module provided in the present application.

[0132] In an embodiment of the present application, as shown in Figure 11 The driving circuit 02 further includes a fourth driving circuit 024, and the circuit structure of the fourth driving circuit 024 can be different from the circuit structure of the first driving circuit 021 and the circuit structure of the second driving circuit 022.

[0133] The signal lines 04 further include a fourth signal line 044, which provides a high-level voltage signal or a low-level voltage signal for the fourth driving circuit 024, and the fourth signal line 044 and the first signal line 041 are signal lines for transmitting the same functional signal. It should be noted that the output end of the first driving circuit 021 does not directly output the electrical signal provided by the first signal line 041, while the fourth driving circuit 024 can directly output the electrical signal provided by the fourth signal line 044.

[0134] Among them, the fourth signal line 044 and the first signal line 041 are respectively connected with different first pins 111.

[0135] In the embodiment of the present application, since the fourth driving circuit 024 can directly output the electrical signal provided by the fourth signal line 044, the load of the fourth signal line 044 is larger than that of the first signal line 041. For the signal line 04 with large load, in order to make the voltage size of the electrical signal provided by the signal line 04 meet the working requirement of the circuit structure connected by the signal line 04, the signal line 04 can be set to be connected with the first pin 111 one by one. The setting mode of the present embodiment can ensure that the electrical signal transmitted by the fourth signal line 044 meets the requirement, avoiding the situation that the voltage size of the electrical signal transmitted by the fourth signal line 044 cannot meet the requirement of the pixel circuit 03 due to the connection of the fourth signal line 044 and the first signal line 041 with the same first pin 111.

[0136] In an embodiment of the present application, in combination with Figure 4 , Figure 6 and Figure 11 , the pixel circuit 03 comprises an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032.

[0137] The display panel 10 further comprises a third gate driving circuit 063, and an electric signal output by the third gate driving circuit 063 controls the writing of a power voltage signal into the pulse width modulation sub-circuit 032.

[0138] The fourth driving circuit 024 is the third gate driving circuit 063.

[0139] Please refer to Figure 6 , the fourth signal line 044 can correspond to a fourth high-level voltage signal line VGH4, and when the first upper-upper output transistor T51 is turned on, the electric signal transmitted by the fourth signal line 044 can be transmitted to the pixel circuit 03 through the third signal line S3. The fourth signal line 044 can also correspond to a second low-level voltage signal line VGL2, and when the first lower-lower output transistor T61 is turned on, the electric signal transmitted by the fourth signal line 044 can be transmitted to the pixel circuit 03 through the third signal line S3.

[0140] In an embodiment of the present application, the electric signal transmitted by the fourth signal line 044 can be directly output by the fourth driving circuit 024. In order to avoid the situation that the electric signal output by the fourth driving circuit 024 cannot meet the working requirements of the pixel circuit 03, the fourth high-level voltage signal line VGH4 or the second low-level voltage signal line VGL2 can be set to correspond to different first pins 111, respectively, with the first signal line 041.

[0141] Figure 12 The change of the electric potential of the electric signal transmitted by the first type of signal line in a working cycle of the driving circuit is shown.

[0142] In an embodiment of the present application, in combination with Figure 9 and Figure 12 , the first signal line 041 and the second signal line 042 are both the first type of signal line X, and the first type of signal line X transmits a high-level voltage signal in the first time period T1, and the high-level voltage signal remains unchanged in the first time period T1. The electric signal transmitted by the first type of signal line X becomes a low-level voltage signal in the second time period T2.

[0143] In a working cycle T of the driving circuit 02, the length of the first time period T1 is greater than the length of the second time period T2.

[0144] In the embodiment of the present application, the electrical signal transmitted by the first type of signal line X is a non-constant potential signal, however, in one working period T of the driving circuit 02, the electrical signal transmitted by the first type of signal line X remains unchanged (corresponding to the high potential) for a long time. Therefore, compared with other non-constant potential signals (for example, clock signal), the electrical signal transmitted by the first type of signal line X has stronger ability to resist external interference. At this time, the first signal line 041 and the second signal line 042 which belong to the first type of signal line X can be connected to the same first pad 051, that is, the first signal line 041, the second signal line 042 and the first pad 051 form the above-mentioned branch connection mode on the display panel 10. Under the premise of considering the anti-interference ability of the first type of signal line, the number of occupied first pins 111 is reduced as much as possible.

[0145] In one embodiment of the present application, as shown in Figure 4 The pixel circuit 03 includes an amplitude modulation sub-circuit 031 and a pulse width modulation sub-circuit 032.

[0146] In combination with Figure 5 and Figure 6 , the display panel 10 further includes a first gate driving circuit 061, a second gate driving circuit 062 and a third gate driving circuit 063. The electrical signal output by the first gate driving circuit 061 adjusts the gate potential size of the second driving transistor T21 in the pulse width modulation sub-circuit 032. The electrical signal output by the second gate driving circuit 062 controls the luminous driving current output by the amplitude modulation sub-circuit 031. The electrical signal output by the third gate driving circuit 063 controls the writing of the power voltage signal into the pulse width modulation sub-circuit 032.

[0147] The first driving circuit 021 and the second driving circuit 022 are respectively two of the first gate driving circuit 061, the second gate driving circuit 062 and the third gate driving circuit 063.

[0148] For example, the first driving circuit 021 can be the first gate driving circuit 061, and the first signal line 041 can be a first control line L01 electrically connected to the ninth upper transistor T39 in the first gate driving circuit 061; the second driving circuit 022 can be the second gate driving circuit 062, and the second signal line 042 can be a first control line L01 electrically connected to the ninth upper transistor T39 in the second gate driving circuit 062.

[0149] For example, the first driving circuit 021 can be a first gate driving circuit 061, and the first signal line 041 can be a first control line L01 electrically connected to a ninth upper transistor T39 in the first gate driving circuit 061; the second driving circuit 022 can be a third gate driving circuit 063, and the second signal line 042 can be a second control line L02 electrically connected to a seventh upper transistor T57 in the third gate driving circuit 063.

[0150] In the embodiment of the present application, for the electrical signals transmitted by the first control line L01 and the second control line L02 respectively, in one working cycle of the driving circuit, the time length corresponding to the unchanged potential of the electrical signal is greater than the time length corresponding to the potential change, then the electrical signals transmitted by the first control line L01 and the second control line L02 respectively have stronger anti-interference ability relative to other non-constant potential electrical signals (for example, clock signals). Therefore, in the embodiment, the first control line L01 and the second control line L02 can be correspondingly connected to the same first pin 111, the first control lines L01 respectively corresponding to different driving circuits can be correspondingly connected to the same first pin 111, and the corresponding above branch connection mode can be implemented on the display panel 10, which helps to reduce the number of first pins 111 occupied by the first control line L01 and the second control line L02 on the premise of ensuring the quality of the electrical signals transmitted by the first control line L01 and the second control line L02.

[0151] Figure 13 A schematic view of a partial structure of a display panel provided in the present application is shown in FIG. 1, Figure 14 A schematic view of a partial structure of a display panel provided in the present application is shown in FIG. 1, Figure 13 A schematic view of a partial structure of a display panel provided in the present application is shown in FIG. 1, Figure 14 A schematic view of a partial structure of a display panel provided in the present application is shown in FIG. 1, Figure 13 A schematic view of a partial structure of a display panel provided in the present application is shown in FIG. 1.

[0152] In an embodiment of the present application, in combination with Figure 13 and Figure 14 The substrate 01 includes a first surface 01a and a second surface 01b opposite to each other, and a third surface 01c connecting the first surface 01a and the second surface 01b.

[0153] The signal line 04 includes a first part 04a located on the first surface 01a, and a second part 04b located on the second surface 01b, the first part 04a is electrically connected to the second part 04b through a side edge trace 04c located on the third surface 01c, and the side edge trace 04c is electrically connected to the first part 01a and the second part 04b through an adapter pad m. In addition, the driving circuit 02 can receive the required electrical signal through the first part 04a, and the second part 04b can receive the electrical signal provided by the circuit board 11 through the connection pad 05.

[0154] The first signal line 041 and the second signal line 042 correspond to different side edge traces 04c respectively, and the first signal line 041 and the second signal line 042 can be electrically connected to the different side edge traces 04c through different transfer pads m respectively.

[0155] Figure 15 A schematic diagram of a display device is provided in the present application.

[0156] The present application provides a display device 30, as shown in the figure, the display device 30 comprises the display module 20 described above. The display device 30 can be a mobile phone, in addition, the display device 30 can also be a computer, a television and other electronic equipment. Figure 15

[0157] The rationality of the connection relationship between the display panel 10 and the circuit board 11 in the display device 30 provided by the embodiments of the present application is greatly improved.

[0158] In the present specification, the same or similar parts among various embodiments can be referred to each other. Especially, for the device embodiments and the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the description in the method embodiments.​

Claims

1. A display module, characterized by The display module comprises a display panel and a flexible circuit board, and the flexible circuit board is electrically connected with the display panel; The display panel comprises: a substrate; a driving circuit and a pixel circuit, the driving circuit and the pixel circuit are located on the substrate, and the driving circuit provides a control signal for the pixel circuit; a signal line, the signal line provides a signal for the driving circuit; The driving circuit comprises a first driving circuit and a second driving circuit; a signal line group, the signal line group comprises a first signal line group and a second signal line group, the first signal line group comprises M signal lines for providing a signal for the first driving circuit, and the second signal line group comprises N signal lines for providing a signal for the second driving circuit, M ≥ 1, and N ≥ 1; The display panel further comprises a plurality of connection pads; the flexible circuit board comprises a plurality of first pins, and the first pins are connected with the signal lines through the connection pads; A first signal line in the M signal lines and a second signal line in the N signal lines are signal lines for transmitting the same function signal; the first signal line and the second signal line are both electrically connected with the same first pin.

2. The display module of claim 1, wherein, The flexible circuit board further comprises a second pin, and the connection pads and the second pin are correspondingly connected; The connection pads comprise a first pad and a second pad, the first pad is electrically connected with the first signal line, and the second pad is electrically connected with the second signal line; The second pin corresponding to the first pad and the second pin corresponding to the second pad are electrically connected with the same first pin.

3. The display module of claim 2, wherein, The first signal line and the second signal line are both clock signal lines.

4. The display module of claim 3, wherein, The pixel circuit comprises an amplitude modulation sub-circuit and a pulse width modulation sub-circuit; The display panel further comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit; an electric signal output by the first gate driving circuit adjusts the size of the gate potential of a second driving transistor in the pulse width modulation sub-circuit; an electric signal output by the second gate driving circuit controls the output of a light-emitting driving current by the amplitude modulation sub-circuit; an electric signal output by the third gate driving circuit controls the writing of a power voltage signal into the pulse width modulation sub-circuit; the first driving circuit and the second driving circuit are respectively for two of the first gate driving circuit, the second gate driving circuit and the third gate driving circuit; Alternatively, the display panel further comprises a fourth gate driving circuit and a fifth gate driving circuit, an electric signal output by the fourth gate driving circuit controls the writing of a first reset signal into the amplitude modulation sub-circuit; The fifth gate driving circuit controls the writing of a second reset signal into the amplitude modulation sub-circuit and the pulse width modulation sub-circuit; the first driving circuit and the second driving circuit are respectively for the fourth gate driving circuit and the fifth gate driving circuit.

5. The display module according to claim 3, wherein the driving circuit further comprises a third driving circuit; The signal lines further include a third signal line, the third signal line provides a clock signal for the third driving circuit, and the third signal line and the first signal line are signal lines for transmitting the same function signal; The third signal line and the first signal line are respectively electrically connected with different first pins.

6. The display module according to claim 5, wherein, The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit; The display panel further includes a sixth gate driving circuit, and an electric signal output by the sixth gate driving circuit controls writing of a data signal into the amplitude modulation sub-circuit and the pulse width modulation sub-circuit; The third driving circuit is the sixth gate driving circuit.

7. The display module of claim 1, wherein, The flexible circuit board further includes a second pin, and the connection pad and the second pin are correspondingly connected; The connection pad includes a first pad, the first signal line and the second signal line are electrically connected with the first pad, and the second pin connected with the first pad is correspondingly connected with the first pin.

8. The display module of claim 7, wherein, The first signal line and the second signal line are both high-level voltage signal lines or low-level voltage signal lines.

9. The display module of claim 8, wherein, The first signal line and the second signal line are both low-level voltage signal lines. The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit; The display panel further includes a first gate driving circuit and a second gate driving circuit; an electric signal output by the first gate driving circuit adjusts a gate potential size of a second driving transistor in the pulse width modulation sub-circuit; and an electric signal output by the second gate driving circuit controls an output of an emission driving current by the amplitude modulation sub-circuit. The first driving circuit and the second driving circuit are respectively the first gate driving circuit and the second gate driving circuit.

10. The display module of claim 8, wherein, The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit; The display panel further includes a fourth gate driving circuit, a fifth gate driving circuit and a sixth gate driving circuit; the fourth gate driving circuit controls writing of a first reset signal into the amplitude modulation sub-circuit; the fifth gate driving circuit controls writing of a second reset signal into the amplitude modulation sub-circuit and the pulse width modulation sub-circuit; and the sixth gate driving circuit controls writing of a data signal into the amplitude modulation sub-circuit and the pulse width modulation sub-circuit. The first driving circuit and the second driving circuit are respectively two of the fourth gate driving circuit, the fifth gate driving circuit and the sixth gate driving circuit.

11. The display module according to claim 8, wherein, The driving circuit further includes a fourth driving circuit; The signal lines further include a fourth signal line, the fourth signal line provides a high-level voltage signal or a low-level voltage signal for the fourth driving circuit, and the fourth signal line and the first signal line are signal lines for transmitting the same function signal; The fourth signal line and the first signal line are respectively electrically connected with different first pins.

12. The display module according to claim 11, wherein, The pixel circuit includes an amplitude modulation sub-circuit and a pulse width modulation sub-circuit; The display panel further comprises a third gate driving circuit, and an electric signal output by the third gate driving circuit controls a power voltage signal to be written into the pulse width modulation sub-circuit. The fourth driving circuit is the third gate driving circuit.

13. The display module of claim 7, wherein, The first signal line and the second signal line are both first-type signal lines; the first-type signal lines transmit high-level voltage signals in a first time period, and the high-level voltage signals remain unchanged in the first time period; and the electric signals transmitted by the first-type signal lines become low-level voltage signals in a second time period. In one working cycle of the driving circuit, the length of the first time period is greater than the length of the second time period.

14. The display module according to claim 13, wherein The pixel circuit comprises an amplitude modulation sub-circuit and a pulse width modulation sub-circuit. The display panel further comprises a first gate driving circuit, a second gate driving circuit and a third gate driving circuit; an electric signal output by the first gate driving circuit adjusts the gate potential size of a second driving transistor in the pulse width modulation sub-circuit; an electric signal output by the second gate driving circuit controls the output of a light-emitting driving current by the amplitude modulation sub-circuit; and an electric signal output by the third gate driving circuit controls a power voltage signal to be written into the pulse width modulation sub-circuit. The first driving circuit and the second driving circuit are respectively two of the first gate driving circuit, the second gate driving circuit and the third gate driving circuit.

15. The display module of claim 1, wherein, The substrate substrate comprises opposite first and second surfaces and a third surface connecting the first and second surfaces; The signal line comprises a first part on the first surface and a second part on the second surface; the first part is electrically connected to the second part through a side edge trace on the third surface; the side edge trace is electrically connected to the first part and the second part through a transfer pad; The first signal line and the second signal line correspond to different side edge traces, respectively.

16. A display device comprising: The display module comprises the display module according to any one of claims 1-15.

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