A memory, a test system and a test method

Abstract

The present invention provides a memory, a test system, and a test method, including a memory main control unit and a voltage adjustment unit. The voltage adjustment unit is configured to receive externally provided interface power supplies of varying voltages and core power supplies of varying voltages. The voltage adjustment unit is further configured to determine the operating state of the memory based on the interface power supplies and / or the core power supplies. The voltage adjustment unit and the main control unit adjust the operating state of the memory based on the determination result. The memory, test system, and test method provided by the present invention can maintain the stability of the memory's power supply voltage in the event of power fluctuations and maximize data security when an anomaly occurs.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a memory, a test system and a test method. Background Art

[0002] With the widespread adoption of memory in consumer electronics devices such as smart TVs, set-top boxes, and mobile devices, data reliability and stability have become core requirements. Memory consists of an ARM-based main control unit and NAND Flash memory cells. The main control unit runs firmware to implement key functions for the memory cells, including bad block management, garbage collection (GC), performance optimization, and lifespan maintenance. Furthermore, sensitive data stored in the firmware (such as security keys and digital copyright information) requires protection in a secure enclave, placing even higher demands on the stability of the coordinated operation of hardware and firmware.

[0003] In practical applications, the stability of the memory supply voltage (core power supply voltage (VCC) and interface power supply voltage (VCCQ)) directly impacts the reliability of firmware data processing. Due to the complex operating environments of end devices, abnormal voltage fluctuations can cause firmware logic errors, data read and write failures, or even hardware damage, threatening the security of sensitive information and storage integrity. Therefore, maintaining memory supply voltage stability in the face of power fluctuations and maximizing data security in the event of anomalies are urgent challenges. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory, a test system and a test method, which can maintain the stability of the power supply voltage of the memory in a power supply fluctuation scenario and maximize data security when an abnormality occurs.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory, comprising a main control unit and a voltage adjustment unit, wherein the voltage adjustment unit is used to receive interface power supplies of different voltages and core power supplies of different voltages provided by the outside world;

[0007] The voltage adjustment unit is further configured to determine the working state of the memory based on the interface power supply and / or the core power supply; and the voltage adjustment unit and the main control unit adjust the working state of the memory based on the determination result.

[0008] In one embodiment of the present invention, the voltage adjustment unit includes:

[0009] a judgment subunit, configured to judge the working state of the memory according to the interface power supply and the core power supply, and generate a compensation instruction, an interrupt instruction, and a power-off instruction based on the judgment result;

[0010] A feedback subunit, configured to obtain an interface compensation power supply and a core compensation power supply according to the compensation instruction;

[0011] a regulating subunit, configured to compensate the interface power supply according to the interface compensation power supply to obtain a compensated interface power supply; the regulating subunit is further configured to compensate the core power supply according to the core compensation power supply to obtain a compensated core power supply;

[0012] The output subunit is used to output the compensated interface power supply to the main control unit, and output the compensated core power supply to the flash memory unit of the memory.

[0013] In one embodiment of the present invention, the judgment subunit generates the compensation instruction, the interruption instruction, and the power-off instruction according to the following steps:

[0014] Determine the working status of the memory according to the interface power supply and / or the core power supply:

[0015] When the memory is in the undervoltage mode, a compensation instruction is generated and sent; the feedback subunit and the regulation subunit perform a voltage compensation operation according to the compensation instruction; the voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode;

[0016] When the memory is in a low power consumption mode, an interrupt instruction is generated and sent; the main control unit performs a data backup operation according to the interrupt instruction; the data backup operation means backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory;

[0017] When the memory is in the power-off mode, a power-off instruction is generated and sent; and the main control unit performs a shutdown operation according to the power-off instruction.

[0018] In one embodiment of the present invention, the feedback subunit obtains the interface compensation power supply and the core compensation power supply according to the following steps:

[0019] Acquiring the voltage of the interface power supply and the voltage of the core power supply according to the compensation instruction;

[0020] Calculating the difference between the voltage of the interface power supply and the voltage of the standard interface power supply to obtain an interface compensation voltage, and generating a corresponding interface compensation power supply according to the interface compensation voltage;

[0021] The difference between the voltage of the core power supply and the voltage of the standard core power supply is calculated to obtain a core compensation voltage, and a corresponding core compensation power supply is generated according to the core compensation voltage.

[0022] The present invention also provides a memory testing system, the testing system comprising:

[0023] A processing module, configured to generate and send voltage regulation instructions, and monitor the working status of the memory;

[0024] The power management module is used to output interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction.

[0025] In one embodiment of the present invention, the processing module is further configured to monitor the judgment subunit to determine whether the judgment subunit generates corresponding compensation instructions, interrupt instructions, and power-off instructions after receiving interface power supplies of different voltages and core power supplies of different voltages:

[0026] When the corresponding compensation instruction, the interruption instruction, and the power-off instruction are not generated, it is determined that an abnormality exists in the determination subunit.

[0027] In one embodiment of the present invention, the processing module is further configured to monitor the feedback subunit and the regulating subunit, and determine whether the feedback subunit and the regulating subunit perform a voltage compensation operation after receiving a compensation instruction:

[0028] When the voltage compensation operation is not performed, it is determined that the feedback subunit and the regulation subunit are abnormal; the voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode.

[0029] In one embodiment of the present invention, the processing module is also used to monitor the main control unit and determine whether the main control unit performs a data backup operation after receiving an interrupt instruction: when the data backup operation is not performed, it is determined that there is an abnormality in the firmware of the memory; the data backup operation indicates backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory.

[0030] In one embodiment of the present invention, the processing module is further configured to monitor the main control unit and determine whether the main control unit performs a shutdown operation after receiving a power-off instruction. If the shutdown operation is not performed, it is determined that an abnormality exists in the firmware of the memory.

[0031] The present invention also provides a memory testing method, the testing method comprising:

[0032] Generate and send voltage control instructions;

[0033] Outputting interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction;

[0034] Monitor the working status of the memory and complete the test of the memory.

[0035] As described above, the present invention provides a memory, test system, and test method. By testing the system and firmware during the development phase and combining a rich set of VCC / VCCQ configurations, this significantly improves test coverage, ensuring stable firmware operation in complex terminal environments and reducing the risk of logic errors caused by voltage anomalies. Flexible triggering of differentiated strategies based on the severity of voltage anomalies, including voltage compensation, data backup, and emergency shutdown, prevents system outages caused by overprotection while maximizing data security and hardware integrity.

[0036] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a schematic diagram of a memory according to an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of an adjustment unit according to an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a test system according to an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of inputting different core power supplies to a memory at different times according to an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of inputting power supplies from different interfaces to a memory at different times according to an embodiment of the present invention;

[0043] Figure 6 Flowchart of a testing method in one embodiment of the present invention.

[0044] In the figure: 100, processing module; 200, memory module; 300, storage module; 400, power module; 500, power management module; 600, interface module; 700, memory; 710, main control unit; 720, interface unit; 730, read-only storage unit; 740, random access storage unit; 750, cache unit; 760, flash memory unit; 770, front-end interface processing unit; 780, adjustment unit; 781, sampling subunit; 782, judgment subunit; 783, protection subunit; 784, output subunit; 785, feedback subunit; 786, regulation subunit. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0046] See also Figure 1 The present invention provides a memory, wherein the memory 700 can be an embedded MultiMediaCard (eMMC) or a universal flash storage (UFS). The memory 700 can communicate with the processing module 100 via the CMD line and the DATA0-7 lines, and perform operations such as read, write, and erase by receiving instructions from the processing module 100. The processing module 100 can send instructions via the CMD line and transmit data via the DATA0-7 lines. The communication protocol between the memory 700 and the processing module 100 can comply with the JEDEC protocol. The memory can include a main control unit 710, an interface unit 720, a read-only memory unit 730, a random access memory unit 740, a cache unit 750, a flash memory unit 760, a front-end interface processing unit 770, an adjustment unit 780, and the like.

[0047] See also Figure 1 In some embodiments, the main control unit 710 may be a microcontroller unit (MCU). The main control unit 710 may be used to perform specific control tasks, such as reading data and processing instructions from the processing module 100. The processing core of the main control unit 710 may be designed based on the RISC-V architecture to perform various control and computing tasks.

[0048] See also Figure 1In some embodiments, the interface unit 720 (interface) can serve as a transmission interface and power supply interface between the main control unit 710 and the processing module 100. The interface unit 720 can receive instructions from the processing module 100 and return data or status information to the processing module 100. The interface unit 720 can receive instructions from the processing module 100 via the CMD and DATA lines and return result data or execution status to the processing module 100 via the DATA line. The interface unit 720 can also receive externally provided core power supplies (VCC) and interface power supplies (VCCQ) of varying voltages. The interface unit 720 can be electrically connected to the main control unit 710, which can be electrically connected to the cache unit 750. The main control unit 710, cache unit 750, and the like can operate based on the interface power supply (VCCQ). The interface unit 720 can also be electrically connected to the flash memory unit 760, which can operate based on the interface power supply (VCCQ).

[0049] See also Figure 1 In some embodiments, the read-only storage unit 730 may be a non-volatile memory (ROM) for long-term data storage. The read-only storage unit 730 may store a program, such as firmware. This program may be a set of pre-written instructions that direct the main control unit 710 on how to start up and operate. These instructions include device initialization, peripheral configuration, and possibly a bootloader. The bootloader can be used to load updated programs or an operating system, for example.

[0050] See also Figure 1 In some embodiments, the RAM 740 may be a volatile memory (Random Access Memory, RAM) that temporarily stores data and program code. The RAM 740 may be used to temporarily store data. When the main control unit 710 executes a program, the program code may be loaded from the read-only memory unit 730 into the RAM 740 for execution.

[0051] See also Figure 1 In some embodiments, the cache unit 750 can serve as a high-speed temporary storage area between the main control unit 710 and the flash memory unit 760, storing data and instructions frequently accessed by the main control unit 710 to accelerate data transmission. The cache unit 750 can be further divided into a read buffer and a write buffer. The read buffer is primarily designed to increase data read speed and reduce access to the main storage device; the write buffer is primarily designed to improve data write efficiency and optimize write performance.

[0052] See also Figure 1 In some embodiments, flash memory unit 760 may be a physical unit (NAND) used to store data in memory 700. Flash memory unit 760 may consist of multiple memory blocks. Each memory block may contain multiple pages. Each page is the smallest unit for read / write operations, while a block is the smallest unit for erase operations. Data is typically read and written in pages, while erasing requires erasing the entire block.

[0053] See also Figure 1 In some embodiments, the front-end interface processing unit 770 (FE IP) can receive command data from the processing module 100 via a front-end interface (e.g., UART, SPI, I2C, Ethernet, etc.). It decodes the received command and extracts key information (e.g., operation type, target address, parameters, etc.). It then converts the parsed command into the internal operation instructions required by the main control unit 710 to ensure that the main control unit 710 can execute the command correctly. After processing the command, the main control unit 710 can return the execution result or status information to the processing module 100 via the front-end interface processing unit 770, so that the processing module 100 can determine whether the operation was successful or obtain the required data.

[0054] See also Figure 1 and Figure 2 In some embodiments, the adjustment unit 780 (Voltage Difference Transducer, VDT) can be electrically connected to the interface unit 720, the main control unit 710, and the flash memory unit 760, respectively. The adjustment unit 780 can be used to determine the operating status of the memory 700 based on the core power supply and / or the interface power supply. The adjustment unit 780 and the main control unit 710 can adjust the operating status of the memory 700 based on the determination result. The adjustment unit 780 may include a sampling subunit 781, a determination subunit 782, a protection subunit 783, an output subunit 784, a feedback subunit 785, and a regulation subunit 786.

[0055] See also Figure 2In some embodiments, the sampling sub-unit 781 can be configured to receive the core power supply and the interface power supply from the interface unit 720 and perform real-time sampling of the core power supply voltage (VCC) and the interface power supply voltage (VCCQ), capturing their voltage values and changing trends. The sampling sub-unit 781 can then transmit the sampled VCC and VCCQ values to downstream units (such as the determination sub-unit 782) for subsequent processing and analysis. The sampling sub-unit 781 determines the operating status of the memory 700 by monitoring the changing trends (voltage difference and rate of change) of VCC and VCCQ over a period of time.

[0056] See also Figure 2 In some embodiments, sampling subunit 781 may be a voltage sampling circuit. The voltage sampling circuit may sample VCC and VCCQ using a high-precision ADC (analog-to-digital converter) to ensure data accuracy. The voltage sampling circuit may also calculate the voltage difference between VCC and VCCQ using a differential amplifier or digital calculation circuit. The voltage sampling circuit may also calculate the rate of change of the voltages of VCC and VCCQ using a differential circuit or digital algorithm.

[0057] See also Figure 2 In some embodiments, the primary function of the determination subunit 782 is to determine the operating status of the memory 700 based on the core power supply and interface power supply output by the sampling subunit 781, and to generate a compensation instruction, an interrupt instruction, or a power-down instruction based on the determination result. The determination subunit 782 can determine whether the operating status of the memory 700 is normal based on a comparison between the core power supply voltage and a preset reference core voltage, and a comparison between the interface power supply voltage and a preset reference interface voltage.

[0058] In some embodiments, the reference core voltages may include a normal reference core voltage (VCC1), a brownout reference core voltage (VCC2), an interrupt reference core voltage (VCC3), and a power-down reference core voltage (VCC4). The reference interface voltages may include a normal reference interface voltage (VCCQ1), a brownout reference interface voltage (VCCQ2), an interrupt reference interface voltage (VCCQ3), and a power-down reference interface voltage (VCCQ4). For different memory types, the values of VCC1-VCC4 may vary, for example, VCC1 = 3.3V, VCC2 = 2.7V, VCC3 = 2.1V, and VCC4 = 0.3V. For another example, the values of VCC1-VCC3 may be set proportionally, such that VCC2 / VCC1 may be in the range of 0.75-0.85, and VCC3 / VCC2 may be in the range of 0.75-0.85. The specific setting rules for the values of VCCQ1-VCCQ4 may be similar to those for VCC1-VCC4 and are not limited here. The power-down reference core voltage (VCC4) and the power-down reference interface voltage (VCCQ4) refer to the reference voltages of the memory when it is completely powered off.

[0059] In some embodiments, the normal reference core voltage (VCC1) and the normal reference interface voltage (VCCQ1) may be the minimum voltage thresholds for normal operation of the memory 700. When the core power supply voltage (VCC) is greater than the normal reference core voltage (VCC1) and the interface power supply voltage (VCCQ) is greater than the normal reference interface voltage (VCCQ1), the memory 700 can be considered to be in normal operation. The core power supply can power the core logic circuits of the memory 700, such as the flash memory unit 760. The stability of VCC directly affects the data storage and read performance of the memory 700. The interface power supply can power the main control unit 710 and control logic of the memory 700. The stability of VCCQ directly affects the communication quality between the memory 700 and the processing module 100, as well as the stability of the control logic of the memory 700.

[0060] In some embodiments, when the core power supply voltage (VCC) and the interface power supply voltage (VCCQ) meet specific conditions, for example, when the core power supply voltage (VCC) is less than or equal to the normal reference core voltage (VCC1) and greater than the undervoltage reference core voltage (VCC2), and the interface power supply voltage (VCCQ) is greater than the undervoltage reference interface voltage (VCCQ2), or when the core power supply voltage (VCC) is greater than the undervoltage reference core voltage (VCC2), and the interface power supply voltage (VCCQ) is less than or equal to the normal reference interface voltage (VCCQ1) and greater than the undervoltage reference interface voltage (VCCQ2), the memory 700 may be considered to be in undervoltage mode. In undervoltage mode, the determination subunit 782 generates a compensation instruction, and the feedback subunit 785 and the regulation subunit 786 perform voltage compensation operations until the memory exits undervoltage mode.

[0061] In some embodiments, brownout mode refers to a state in which the core power supply voltage (VCC) or the interface power supply voltage (VCCQ) of the memory 700 is lower than the normal reference voltage (VCC1 or VCCQ1) but higher than the brownout reference voltage (VCC2 or VCCQ2). In this state, while the memory 700 can still operate, it may not achieve optimal performance and may even risk data errors or communication failures.

[0062] In some embodiments, when the core power supply and the interface power supply meet specific conditions, for example, when the core power supply voltage (VCC) is less than or equal to the undervoltage reference core voltage (VCC2) and greater than the interrupt reference core voltage (VCC3), and the interface power supply voltage (VCCQ) is greater than the interrupt reference interface voltage (VCCQ3), or when the core power supply voltage (VCC) is greater than the interrupt reference core voltage (VCC3), and the interface power supply voltage (VCCQ) is less than or equal to the undervoltage reference interface voltage (VCCQ2) and greater than the interrupt reference interface voltage (VCCQ3), the memory 700 can be considered to be in low power mode. In low power mode, the determination subunit 782 generates an interrupt instruction, and the main control unit 710 performs a data backup operation based on the instruction to reduce power consumption and ensure data security.

[0063] In some embodiments, the data backup operation refers to ensuring the safe storage of critical data (such as mapping tables and cache data (CacheFlush)) through a series of firmware internal algorithms and hardware operations when the memory 700 enters low power mode, and shutting down idle modules to reduce power consumption.

[0064] In some embodiments, the mapping table is a key data structure in memory 700 that records the correspondence between logical addresses and physical addresses. The mapping table ensures the correct storage and access of data in memory 700. By initiating a backup algorithm within the firmware, the main control unit 710 can copy the contents of the mapping table to the flash memory unit 760 to prevent loss of the mapping table due to voltage anomalies or power outages, thereby avoiding data read errors or storage confusion. After memory 700 returns to normal, the backup data can be quickly restored, ensuring the normal operation of memory 700 and reducing system interruption time.

[0065] In some embodiments, cache unit 750 is a fast-access area within memory 700 for temporarily storing data. Cache unit 750 can improve data read and write efficiency. A cache flush forcibly writes data from cache unit 750 to flash memory unit 760, ensuring data loss due to power outages. This prevents data loss in cache unit 750 due to voltage anomalies or power outages, ensuring data integrity and consistency. After memory 700 returns to normal operation, backup data can be quickly restored, ensuring normal operation of memory 700 and reducing system downtime.

[0066] In some embodiments, an idle module refers to a portion of the memory 700 that is not currently in use, such as an unused storage unit, interface circuit, or cache unit. The main control unit 710 can shut down unneeded modules based on the current operating state. For example, if the memory 700 is currently only performing read operations, the write cache unit is shut down; if the memory 700 is currently only performing write operations, the read cache unit is shut down. By shutting down idle modules, the memory's power consumption can be significantly reduced.

[0067] In some embodiments, when the core power supply voltage (VCC) is less than or equal to the interrupt reference core voltage (VCC3), or the interface power supply voltage (VCCQ) is less than or equal to the interrupt reference interface voltage (VCCQ3), the memory 700 is considered to be in power-down mode. In power-down mode, the determination subunit 782 generates and sends a power-down instruction, and the main control unit 710 executes a shutdown operation based on the instruction to ensure data security and system stability. Power-down mode refers to a state in which the core power supply voltage (VCC) or the interface power supply voltage (VCCQ) of the memory 700 is less than or equal to the interrupt reference voltage (VCC3 or VCCQ3). At this point, the memory's power supply is insufficient to maintain normal operation, and the system must immediately shut down the device to prevent data loss or hardware damage.

[0068] In some embodiments, in power-down mode, the main control unit 710 immediately halts all ongoing read and write operations to prevent data errors or loss due to insufficient voltage. Simultaneously, the main control unit 710 also forcibly writes data from the cache unit 750 to the flash memory unit 760 to ensure that cached data is not lost due to power outages. Finally, the main control unit 710 copies the contents of the mapping table to the flash memory unit 760 by activating a backup algorithm within the firmware.

[0069] See also Figure 2 In some embodiments, the protection subunit 783 is configured to monitor the core power supply and interface power supply output by the determination subunit 782, as well as the core compensation power supply and interface compensation power supply output by the regulation subunit 786. The protection subunit 783 primarily monitors the core power supply, interface power supply, interface compensation power supply, and core compensation power supply to prevent damage to the chip's internal circuits due to voltage or current anomalies. For example, if VCC or VCCQ exceeds the normal range, a protection mechanism (such as power shutdown or current limiting) is triggered.

[0070] See also Figure 2 In some embodiments, the primary function of the output sub-unit 784 is to transmit the core power supply from the judgment sub-unit 782 to the flash memory unit 760, and to transmit the interface power supply from the judgment sub-unit 782 to the main control unit 710, ensuring a stable power supply for the main control unit 710 and the flash memory unit 760. During the transmission process, the output sub-unit 784 performs filtering and voltage stabilization to ensure that fluctuations in VCC and VCCQ do not affect the performance of the main control unit 710 and the flash memory unit 760.

[0071] See also Figure 2 In some embodiments, the feedback subunit 785 can be used to generate a core compensation power supply and an interface compensation power supply. Specifically, the feedback subunit 785 can obtain VCC and VCCQ output by the output subunit 784 based on the compensation instruction. The feedback subunit 785 can generate a core compensation voltage by calculating the difference between VCC and the standard core voltage, and then generate a corresponding core compensation power supply based on the core compensation voltage. The current of the core compensation power supply can be the same as the current of the core power supply. The feedback subunit 785 can generate an interface compensation voltage by calculating the difference between VCCQ and the standard interface voltage, and then generate a corresponding interface compensation power supply based on the interface compensation voltage. The current of the interface compensation power supply can be the same as the current of the interface power supply. The standard core voltage can be a normal reference core voltage (VCC1), and the standard interface voltage can be a normal reference interface voltage (VCCQ1). By generating the compensation voltages, the actual VCC and VCCQ values are adjusted to approach the standard values, ensuring power supply voltage stability.

[0072] See also Figure 2 In some embodiments, the adjustment subunit 786 may be a key unit in the memory 700 for compensating the core power supply and the interface power supply. Its core function is to adjust the core power supply and the interface power supply output by the sampling subunit 781 based on the core compensation power supply and the interface compensation power supply generated by the feedback subunit 785 to ensure the stability and accuracy of the power supply voltage. This compensation mechanism ensures that the voltage of the compensated core power supply and the voltage of the compensated interface power supply are always close to the standard value, avoiding system instability caused by voltage fluctuations. The main control unit 710 can set a reference core voltage for the sampling subunit 781 through the adjustment subunit 786, and set a standard core voltage and a standard interface voltage for the feedback subunit 785.

[0073] See also Figure 1 and Figure 3 The present invention also provides a memory test system that can test the memory 700 in the above embodiment by providing interface power supplies of different voltages and core power supplies of different voltages to the memory 700 to determine whether the memory 700 can operate normally. The test system can include a processing module 100, a memory module 200, a storage module 300, a power module 400, a power management module 500, an interface module 600, and the like.

[0074] See also Figure 3 In some embodiments, processing module 100 may be a central processing unit (CPU). A CPU is responsible for interpreting and executing program instructions, controlling and processing data. Processing module 100 may be a multi-core processor, with each core processing different data read and write requests in parallel, increasing task parallelism. Processing module 100 may also be used to generate and issue voltage regulation commands and monitor the operating status of memory 700.

[0075] See also Figure 3 In some embodiments, the memory module 200 may be a dynamic random access memory (DRAM). The memory module 200 may be used to store data and program codes so that the processing module 100 can quickly access them.

[0076] See also Figure 3 In some embodiments, the storage module 300 may be a Secure Digital (SD) memory card. The SD card may be used to store an operating system and software programs required for operation.

[0077] See also Figure 3In some embodiments, the power module 400 (POWER) can supply power to the processing module 100 , the memory module 200 , the storage module 300 , the power management module 500 , etc. to complete the test.

[0078] See also Figure 3 In some embodiments, the power management module 500 (Power Management Integrated Circuit, PMIC) can be used to output interface power and core power at different voltage levels to the memory 700 based on voltage control instructions to meet power requirements during testing. Specifically, the power management module 500 can be used to parse the voltage control instructions to determine the required output VCC and VCCQ levels. Subsequently, a voltage regulator within the power management module 500 (such as a DC-DC converter or LDO) generates the required VCC and VCCQ levels.

[0079] See also Figure 3 In some embodiments, the interface module 600 may be a Universal Asynchronous Receiver / Transmitter (UART). The memory 700 may communicate with peripheral devices via serial communication with the interface module 600 to exchange data.

[0080] In some embodiments, after outputting interface power supplies and core power supplies of different voltages to the memory 700, the processing module 100 is further configured to determine whether the judgment subunit 782 can generate corresponding compensation instructions, interrupt instructions, and power-off instructions after receiving the interface power supplies and core power supplies of different voltages, thereby evaluating the working status of the judgment subunit 782 and providing a basis for the optimization of the adjustment unit 780. When the judgment subunit 782 generates the corresponding instructions, it is determined that the judgment subunit 782 can operate normally. When the judgment subunit 782 does not generate the corresponding instructions, it is determined that there is an abnormality in the judgment subunit 782. When there is an abnormality in the judgment subunit 782, it indicates that there may be problems with the voltage abnormality processing design process of the adjustment unit 780, and optimization processing is required, such as improving the voltage judgment logic, adding a fault tolerance mechanism, etc.

[0081] In some embodiments, the processing module 100 can be used to determine whether the feedback subunit 785 and the adjustment subunit 786 perform a voltage compensation operation after receiving a compensation instruction, thereby evaluating the working status of the two subunits. When the feedback subunit 785 and the adjustment subunit 786 perform a voltage compensation operation, it is determined that the two subunits can operate normally. When the feedback subunit 785 and the adjustment subunit 786 do not perform a voltage compensation operation, it is determined that there is an abnormality in the two subunits. The purpose of the voltage compensation operation is to compensate the interface power supply and / or the core power supply until the memory exits the undervoltage mode. When there is an abnormality in the feedback subunit 785 and the adjustment subunit 786, it means that there may be a problem with the voltage abnormality handling design process of the adjustment unit 780, and optimization processing is required, such as improving the voltage compensation logic, adding a fault tolerance mechanism, etc.

[0082] In some embodiments, processing module 100 is further configured to monitor main control unit 710 and determine whether main control unit 710 performs a data backup operation after receiving an interrupt instruction. If the data backup operation is performed, it is determined that the firmware of memory 700 is functioning properly. If the data backup operation is not performed, it is determined that an abnormality exists in the firmware of memory 700. If the firmware fails to perform the data backup operation, it indicates that the firmware's processing strategy is inconsistent and the error cannot be detected, indicating a defect in the firmware's processing flow. Firmware defects can be repaired by updating the firmware.

[0083] In some embodiments, processing module 100 is further configured to determine whether main control unit 710 executes a shutdown operation after receiving a power-off command. If the shutdown operation is executed, the firmware of memory 700 is determined to be functioning properly. If the shutdown operation is not executed, the firmware of memory 700 is determined to be abnormal. If the firmware does not execute the shutdown operation, it indicates that the firmware's processing strategy is inconsistent and the error cannot be detected, indicating a defect in the firmware's processing flow. Firmware defects can be fixed by updating the firmware.

[0084] See also Figure 4 , in some embodiments, Figure 4 The diagram shows the core power supply voltage levels being output to memory 700 at different times, with time plotted on the horizontal axis and voltage plotted on the vertical axis. At times T1, T3, and T9, the core power supply voltage (VCC) falls below the interrupt reference core voltage (VCC3), indicating that memory 700 is in power-down mode. Subsequently, processing module 100 can test memory 700 to determine whether it is capable of shutting down.

[0085] See also Figure 4In some embodiments, at time T7, the core power supply voltage (VCC) is between the undervoltage reference core voltage (VCC2) and the interrupt reference core voltage (VCC3). At this point, the memory 700 can be considered to be in low-power mode. Subsequently, the processing module 100 can test the memory 700 to determine whether the memory 700 is capable of performing data backup operations.

[0086] See also Figure 4 In some embodiments, at times T2, T5, T8, and T10, the core power supply voltage (VCC) is between the normal reference core voltage (VCC1) and the undervoltage reference core voltage (VCC2). At this point, the memory 700 is considered to be in undervoltage mode. Subsequently, the processing module 100 can test the memory 700 to determine whether the memory 700 is capable of performing voltage compensation operations.

[0087] See also Figure 5 , in some embodiments, Figure 5 The diagram shows the voltage (VCCQ) of the interface power supply output to memory 700 at different times, with time on the horizontal axis and voltage on the vertical axis. At times T3, T5, and T9, the interface power supply voltage (VCCQ) falls below the interrupt reference interface voltage (VCCQ3), indicating that memory 700 is in power-down mode. Subsequently, processing module 100 can test memory 700 to determine whether it is capable of shutting down.

[0088] See also Figure 5 In some embodiments, at times T1 and T2, if the interface power supply voltage (VCCQ) is between the undervoltage reference interface voltage (VCCQ2) and the interrupt reference interface voltage (VCCQ3), memory 700 may be considered to be in low-power mode. Subsequently, processing module 100 may test memory 700 to determine whether it is capable of performing data backup operations.

[0089] See also Figure 5 In some embodiments, at times T4 and T7, the interface power supply voltage (VCCQ) is between the normal reference core voltage (VCC1) and the undervoltage reference core voltage (VCC2). At this point, the memory 700 can be considered to be in undervoltage mode. Subsequently, the processing module 100 can test the memory 700 to determine whether the memory 700 is capable of performing voltage compensation operations.

[0090] See also Figure 6The present invention also provides a memory testing method that can be applied to the above-mentioned test system to test the memory 700 in the above-mentioned embodiment. By providing interface power supplies of different voltages and core power supplies of different voltages to the memory 700, it is determined whether the memory 700 can operate normally. The testing method may include the following steps:

[0091] Step S10: generating and sending a voltage control instruction;

[0092] Step S20: outputting interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction;

[0093] Step S30: monitor the working status of the memory and complete the memory test.

[0094] As can be seen, the above solution significantly improves test coverage through system and firmware testing during the development phase, combined with a rich set of VCC / VCCQ configurations. This ensures stable firmware operation in complex terminal environments and reduces the risk of logic errors caused by voltage anomalies. Flexible triggering of differentiated strategies based on the severity of voltage anomalies, including voltage compensation, data backup, and emergency shutdown, prevents system outages caused by overprotection while maximizing data security and hardware integrity.

[0095] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory comprising a main control unit, characterized in that: The memory further includes an adjustment unit, the adjustment unit being configured to receive interface power supplies of different voltages and core power supplies of different voltages provided by the outside world; The adjustment unit is further configured to determine the working state of the memory according to the interface power supply and / or the core power supply; and the adjustment unit and the main control unit adjust the working state of the memory according to the determination result. Wherein, the adjustment unit includes: a judgment subunit, configured to judge the working state of the memory according to the interface power supply and the core power supply, and generate a compensation instruction, an interrupt instruction, and a power-off instruction based on the judgment result; A feedback subunit, configured to obtain an interface compensation power supply and a core compensation power supply according to the compensation instruction; a regulating subunit, configured to compensate the interface power supply according to the interface compensation power supply to obtain a compensated interface power supply; the regulating subunit is further configured to compensate the core power supply according to the core compensation power supply to obtain a compensated core power supply; an output subunit, configured to output the compensated interface power supply to the main control unit, and output the compensated core power supply to the flash memory unit of the memory; The judgment subunit generates a compensation instruction, an interrupt instruction, and a power-off instruction according to the following steps: Determine the working status of the memory according to the interface power supply and / or the core power supply: When the voltage of the core power supply is less than or equal to the normal reference core voltage and greater than the undervoltage reference core voltage, and the voltage of the interface power supply is greater than the normal reference interface voltage, or when the voltage of the core power supply is greater than the undervoltage reference core voltage and the voltage of the interface power supply is less than or equal to the normal reference interface voltage and greater than the undervoltage reference interface voltage, it is determined that the memory is in undervoltage mode, and a compensation instruction is generated and sent; the feedback subunit and the regulation subunit perform a voltage compensation operation according to the compensation instruction; the voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode; wherein the undervoltage mode indicates that the memory has a risk of data error or communication failure; When the voltage of the core power supply is less than or equal to the undervoltage reference core voltage and greater than the interrupt reference core voltage, and the voltage of the interface power supply is greater than the interrupt reference interface voltage, or when the voltage of the core power supply is greater than the interrupt reference core voltage and the voltage of the interface power supply is less than or equal to the undervoltage reference interface voltage and greater than the interrupt reference interface voltage, it is determined that the memory is in a low power consumption mode, and an interrupt instruction is generated and sent; the main control unit performs a data backup operation according to the interrupt instruction; the data backup operation means backing up data in a mapping table and a cache unit, and stopping power supply to idle modules in the memory; When the voltage of the core power supply is less than or equal to the interrupt reference core voltage, or the voltage of the interface power supply is less than or equal to the interrupt reference interface voltage, it is determined that the memory is in power-down mode, and a power-down instruction is generated and sent; the main control unit performs a shutdown operation according to the power-down instruction; Among them, the normal reference core voltage>the undervoltage reference core voltage>the interrupt reference core voltage>the power-down reference core voltage, the normal reference interface voltage>the undervoltage reference interface voltage>the interrupt reference interface voltage>the power-down reference interface voltage, and the normal reference core voltage and the normal reference interface voltage are the minimum voltage thresholds for normal operation of the memory.

2. The memory according to claim 1, wherein The feedback subunit obtains the interface compensation power supply and the core compensation power supply according to the following steps: Acquiring the voltage of the interface power supply and the voltage of the core power supply according to the compensation instruction; Calculating the difference between the voltage of the interface power supply and the voltage of the standard interface power supply to obtain an interface compensation voltage, and generating a corresponding interface compensation power supply according to the interface compensation voltage; The difference between the voltage of the core power supply and the voltage of the standard core power supply is calculated to obtain a core compensation voltage, and a corresponding core compensation power supply is generated according to the core compensation voltage.

3. A memory testing system, characterized in that: The memory is the memory according to any one of claims 1 to 2, and the test system includes: A processing module, configured to generate and send voltage regulation instructions, and monitor the working status of the memory; The power management module is used to output interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction.

4. The memory test system according to claim 3, wherein: The processing module is further configured to monitor the judgment subunit to determine whether the judgment subunit generates corresponding compensation instructions, interrupt instructions, and power-off instructions after receiving interface power supplies of different voltages and core power supplies of different voltages. When the corresponding compensation instruction, the interruption instruction, and the power-off instruction are not generated, it is determined that an abnormality exists in the determination subunit.

5. The memory test system according to claim 4, wherein: The processing module is further configured to monitor the feedback subunit and the regulating subunit, and determine whether the feedback subunit and the regulating subunit perform a voltage compensation operation after receiving a compensation instruction. When the voltage compensation operation is not performed, determining that an abnormality exists in the feedback subunit and the regulation subunit; The voltage compensation operation means compensating the interface power supply and / or the core power supply until the memory exits the undervoltage mode.

6. The memory test system according to claim 4, wherein: The processing module is also used to monitor the main control unit and determine whether the main control unit performs a data backup operation after receiving an interrupt instruction: when the data backup operation is not performed, it is determined that there is an abnormality in the firmware of the memory; the data backup operation indicates backing up the data in the mapping table and the cache unit, and stopping power supply to the idle modules in the memory.

7. The memory test system according to claim 4, wherein: The processing module is further configured to monitor the main control unit and determine whether the main control unit performs a shutdown operation after receiving a power-off instruction; when the shutdown operation is not performed, it is determined that an abnormality exists in the firmware of the memory.

8. A memory testing method, characterized in that: The memory is the memory according to any one of claims 1 to 2, and the testing method comprises: Generate and send voltage control instructions; Outputting interface power supplies of different voltages and core power supplies of different voltages to the memory according to the voltage control instruction; Monitor the working status of the memory and complete the test of the memory.

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