Test method and test device for SPI NAND FLASH memory chip

Abstract

The application provides a test method and test equipment for an SPI NAND FLASH memory chip. The test method comprises: performing corresponding read, write and erase tests on the SPI NAND FLASH memory chip at an initial frequency according to test instructions for reading data, writing data and erasing data input by a user; and adjusting the initial frequency according to a test result and re-performing the test. The application can effectively test the performance of read, write and erase of the NAND FLASH at different operating frequencies, can also completely realize automation, reduces manual participation, reduces costs while ensuring test efficiency, and can well realize small-batch test verification of the variable-frequency SPI NAND FLASH memory chip.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of storage chip testing, and particularly relates to a test method and test equipment for an SPI NAND FLASH storage chip. BACKGROUND

[0002] The SPI NAND FLASH storage chip is a nonvolatile memory widely used in storage devices, and has high-speed reading and writing and large storage capacity. In order to ensure the stability and reliability, a corresponding automatic test device needs to be developed to comprehensively test the performance and quality control of the SPI NAND FLASH storage chip in the production process, so as to meet the use requirements under different conditions.

[0003] At present, some test platforms on the market can perform programming and reading operations on the SPI NAND FLASH storage chip, and can integrate test schemes, adopt a modular design test scheme, can be conveniently connected with various types of memories, and can be tested by setting different parameters. However, the existing test equipment is usually designed for a specific type of memory, lacks compatibility and adaptability for new types of memories (such as SPI NAND FLASH storage chips of different technology nodes), and has insufficient flexibility. Secondly, the current test equipment is mostly controlled by an FPGA, which is suitable for high-performance application scenarios, but the existing test equipment can only test fixed parameters and cannot test more dynamic parameters such as changing frequencies, thereby limiting the comprehensiveness and accuracy of the test. SUMMARY

[0004] The purpose of the present application is to provide a test method and test equipment for an SPI NAND FLASH storage chip, which can complete corresponding reading and writing tests on the SPI NAND FLASH storage chip according to different frequencies.

[0005] In order to achieve the above purpose, the application provides a test method for an SPI NAND FLASH storage chip, which is characterized by comprising the following steps:

[0006] According to the test instructions of the reading data, the writing data and the erasing data input by the user, performing corresponding reading, writing and erasing tests on the SPI NAND FLASH storage chip according to an initial frequency;

[0007] Adjusting the initial frequency according to the test result and re-executing the test.

[0008] Preferably, the step of performing corresponding reading, writing and erasing tests on the SPI NAND FLASH storage chip according to an initial frequency comprises the following steps:

[0009] According to the user input write data automatic test instruction, the preset data is written into the SPI NAND FLASH memory chip at the initial frequency;

[0010] The SPI NAND FLASH memory chip is read to obtain first read data;

[0011] The first read data is compared with the preset data to obtain a write test result;

[0012] The initial frequency is adjusted according to the test result and the test is re-executed, which comprises:

[0013] According to the test result that the first read data is inconsistent with the preset data, the initial frequency is adjusted and the write test is re-executed.

[0014] Preferably, the initial frequency is adjusted according to the test result and the test is re-executed, which comprises:

[0015] According to the user input read data automatic test instruction, data is read from the SPI NAND FLASH memory chip at the initial frequency to obtain second read data;

[0016] The second read data is compared with the original data to obtain a read test result;

[0017] The initial frequency is adjusted according to the test result and the test is re-executed, which comprises:

[0018] According to the test result that the second read data is inconsistent with the original data, the initial frequency is adjusted and the read test is re-executed.

[0019] Preferably, the initial frequency is adjusted according to the test result and the test is re-executed, which comprises:

[0020] According to the user input erase data automatic test instruction, the SPI NAND FLASH memory chip is erased at the initial frequency;

[0021] It is detected whether there is residual data in the SPI NAND FLASH memory chip to obtain an erase test result;

[0022] The initial frequency is adjusted according to the test result and the test is re-executed, which comprises:

[0023] According to the test result that the SPI NAND FLASH memory chip has residual data, the initial frequency is adjusted, the initial frequency is adjusted and the erase test is re-executed.

[0024] Preferably, before performing all steps, further comprising:

[0025] Establishing communication with the multi-channel SPI NAND FLASH memory chip.

[0026] Preferably, the multi-channel comprises a first channel, a second channel, and a third channel, each of which is provided with a plurality of SPI NAND FLASH memory chips, and the performing of the corresponding read, write and erase tests on the SPI NAND FLASH memory chips at the initial frequency comprises:

[0027] Performing tests on the plurality of flash memories of the first channel at a first initial frequency; performing tests on the plurality of flash memories of the second channel at a second initial frequency; and performing tests on the plurality of flash memories of the third channel at a third initial frequency.

[0028] Preferably, the foregoing method can further comprise:

[0029] When the ambient temperature changes, adjusting the initial frequency according to a preset linear relationship between temperature and frequency; and

[0030] When the communication interface voltage changes, adjusting the initial frequency according to a preset linear relationship between voltage and frequency.

[0031] Preferably, further comprising:

[0032] Analyzing the write test results, the read test results and / or the erase test results to obtain performance evaluation results;

[0033] Generating a test report according to the performance evaluation results;

[0034] Uploading the test report to a cloud server.

[0035] Preferably, the performing of the corresponding read, write and erase tests on the SPI NAND FLASH memory chips at the initial frequency comprises:

[0036] Obtaining read, write and erase frequency thresholds of the SPI NAND FLASH memory chip according to model information of the SPI NAND FLASH memory chip;

[0037] Setting the initial frequency according to the thresholds.

[0038] The embodiments of the present application also provide a SPI NAND FLASH memory chip testing device, and the key lies in comprising:

[0039] One or more MCU control units and memories;

[0040] The memory is coupled with the one or more MCU control units, and the memory is configured to store computer program code including computer instructions, which are invoked by the one or more MCU control units to cause the test device to perform the method as described above.

[0041] The application tests the SPI NAND FLASH memory chip by setting an initial frequency, and then adjusts the test frequency according to the test result until the SPI NAND FLASH memory chip works normally at a certain frequency. The performance of the NAND flash memory in reading, writing, erasing and other aspects at different frequencies can be effectively tested, and the automation can be completely realized, reducing the manual participation, reducing the cost while ensuring the test efficiency, and the small batch test verification of the variable frequency SPI NAND FLASH memory chip can be well realized. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The flowchart of the test method of the SPI NAND FLASH memory chip in an embodiment of the application is shown;

[0043] Figure 2 The flowchart of the test method of the SPI NAND FLASH memory chip in an embodiment of the application is shown;

[0044] Figure 3 The flowchart of the test method of the SPI NAND FLASH memory chip in an embodiment of the application is shown;

[0045] Figure 4 The flowchart of the test method of the SPI NAND FLASH memory chip in an embodiment of the application is shown;

[0046] Figure 5 The flowchart of the test method of the SPI NAND FLASH memory chip in an embodiment of the application is shown;

[0047] Figure 6 The structure diagram of the test device of the SPI NAND FLASH memory chip in an embodiment of the application is shown. DETAILED DESCRIPTION

[0048] In the entire description, obviously, the described embodiments are only part of the embodiments in the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0049] It should be noted that all directional indications, such as upper, lower, left, right, front, back, and the like, are merely used for convenience of description and are not intended to limit the application to any particular orientation.

[0050] It should also be noted that when an element is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element or intervening elements can be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can be present.

[0051] In addition, the terms "first", "second", and the like, in the description of the application, are used only for distinguishing between similar elements and are not necessarily used to describe a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive terms "first", "second", etc., are to be interpreted, by those skilled in the art, as a "1st", "2nd", etc. order among at least two elements or steps or concepts, but these can not necessarily be understood as sequential or chronological order among the at least two elements or steps or concepts unless it is clearly indicated by the technical features or the context. Therefore, the scope of the application is not to be interpreted in the limited sense of the sequential or chronological order among the technical features or concepts disclosed in the application description.

[0052] The principle of the application is that: through the input of test instructions by the automatic test equipment, the SPI NAND FLASH memory chip is first tested by reading, writing and erasing at the initial frequency, and when the SPI NAND FLASH memory chip cannot work at the current frequency, the software program in the automatic test equipment automatically adjusts the frequency test until the SPI NAND FLASH memory chip works normally at a certain frequency, and the frequency is used as the standard frequency of some special scene applications, so as to realize the automatic frequency test of the SPI NAND FLASH memory chip.

[0053] The application provides a test method of a SPI NAND FLASH memory chip. Referring to Figure 1 In an embodiment, the test method comprises:

[0054] Step S10, according to the read data, write data and erase data test instruction input by the user, the initial frequency is set to perform the corresponding read, write and erase test on the SPI NAND FLASH memory chip; in the embodiment of the application, the initial frequency can be set to the highest frequency (for example, 133MHz), or the test frequency range of the SPI NAND FLASH memory chip can be obtained according to the model of the SPI NAND FLASH memory chip, so as to determine the initial frequency, after the user inputs the read data, write data and erase data test instruction, the initial frequency is set to perform the corresponding read, write and erase test on the SPI NAND FLASH memory chip.

[0055] Step S20, according to the test result, the initial frequency is adjusted and the test is re-executed; in the embodiment, the initial frequency can be reduced or increased according to the test result of the test failure, until the SPI NAND FLASH memory chip works normally at a certain frequency. For example, if the test result is that the SPI NAND FLASH memory chip fails to pass the test in the read data test process, the initial frequency is reduced and the read test is re-executed, until the chip can pass the test, at this time, the reduced frequency can be used as the standard of the application frequency in some special scenarios.

[0056] In a preferred embodiment, in the step S20, the initial frequency can be adjusted at a preset frequency interval, for example, the initial frequency can be reduced or adjusted at an interval of 1MHz or less.

[0057] In the embodiment of the application, the SPI NAND FLASH memory chip is tested by setting the initial frequency, and then the test frequency is adjusted according to the test result, which can effectively test the performance of the NAND flash in read, write, erase and other aspects at different frequencies, and can also completely realize automation, reduce the manual participation, reduce the cost while ensuring the test efficiency, and can well realize the small batch test verification of the variable frequency SPI NAND FLASH memory chip.

[0058] As described above, the embodiment of the application can automatically perform the corresponding read, write and erase test on the SPI NAND FLASH memory chip. As shown in Figure 2 The flow of testing the write data frequency includes:

[0059] Step S11, according to the write data automatic test instruction input by the user, preset data is written into the SPI NAND FLASH memory chip at the initial frequency;

[0060] Step S12, the SPI NAND FLASH memory chip is read to obtain the first read data;

[0061] Step S13, comparing the first read data with the preset data to obtain a write test result. In the embodiment of the present application, after the test device receives the write data automatic test instruction, the test device can automatically test the write function of the SPI NAND FLASH. The test device extracts the preset data stored in advance from the local according to the write data automatic test instruction, and then writes the preset data into the SPI NAND FLASH. After the writing is completed, the test device reads the SPI NAND FLASH to obtain the first read data.

[0062] After the test device obtains the first read data, the test device judges the first read data. The test device judges whether the first read data is consistent with the preset data. Since the first read data is obtained according to the read preset data written into the SPI NAND FLASH, if the preset data does not have a problem in the process of writing into the SPI NAND FLASH, the first read data should be consistent with the preset data.

[0063] If the test device determines that the first read data is consistent with the preset data, it means that the preset data does not have a problem in the process of writing into the SPI NAND FLASH, which indicates that the write function of the SPI NAND FLASH does not have a problem; and the test device can determine that the write function of the SPI NAND FLASH passes the write test.

[0064] If the test device determines that the first read data is not consistent with the preset data, it means that the preset data has a problem in the process of writing into the SPI NAND FLASH, which indicates that the write function of the SPI NAND FLASH has a problem; and the test device can determine that the write function of the SPI NAND FLASH does not pass the write test.

[0065] If the test device determines that the write function of the SPI NAND FLASH does not pass the write test, the test result can be determined according to that the write function of the SPI NAND FLASH does not pass the write test. The test result can indicate that the write function of the SPI NAND FLASH has a problem. If the test device determines that the write function of the SPI NAND FLASH passes the write test, the test result can be determined according to that the write function of the SPI NAND FLASH passes the write test. The test result can indicate that the write function of the SPI NAND FLASH does not have a problem.

[0066] In the embodiment of the present application, the foregoing step S20 comprises:

[0067] According to the test result that the first read data is inconsistent with the preset data, the initial frequency is adjusted and the write test is re-executed. When the test result shows that the write function of the SPI NAND FLASH has a problem, the initial frequency can be reduced and the write data operation is re-executed until the SPI NAND FLASH storage chip works normally at a certain frequency.

[0068] The foregoing step flow is only exemplary, and the flow can also be reversed. For example, an initial frequency that can pass the test is preset first, and the frequency is continuously increased based on the initial frequency until the write function cannot pass the test. At this time, the frequency is taken as the application frequency standard.

[0069] Figure 3 A flow of testing the read data frequency of the SPI NAND FLASH storage chip in an embodiment of the present application is shown. Referring to Figure 3 In a preferred embodiment, the flow of testing the read data frequency of the SPI NAND FLASH storage chip can include:

[0070] In step S101, the data is read from the SPI NAND FLASH storage chip at an initial frequency according to the read data automatic test instruction input by the user to obtain second read data.

[0071] In step S102, the second read data is compared with the original data to obtain a read test result.

[0072] In the embodiment, the foregoing step S20 can include:

[0073] The test result that the second read data is inconsistent with the original data adjusts the initial frequency and re-executes the read test.

[0074] The embodiment discloses the flow of reading data and testing the read frequency, and the flow is basically the same as the flow and principle of the data write test, which is not described herein.

[0075] Figure 4 A flow of testing the erase data frequency of the SPI NAND FLASH storage chip in an embodiment of the present application is shown. Referring to Figure 4 In a preferred embodiment, the flow of testing the read data frequency of the SPI NAND FLASH storage chip can include:

[0076] In step S110, the SPI NAND FLASH storage chip is erased at an initial frequency according to the erase data automatic test instruction input by the user.

[0077] Step S120, detecting whether the SPI NAND FLASH memory chip has residual data to obtain an erasing test result;

[0078] In the embodiment, the S20 can include:

[0079] According to the test result of the SPI NAND FLASH memory chip having residual data, the initial frequency is adjusted, the initial frequency is adjusted and the erasing test is re-executed.

[0080] The embodiment discloses a flow of erasing data and testing erasing frequency, which is basically the same as the flow and principle of the aforementioned data writing and reading test, and is not described here.

[0081] In the embodiment, multi-channel testing can be designed to realize parallel testing of multiple SPI NAND memories, and dynamically select a test channel according to requirements to reduce testing time. For example, in a preferred embodiment, before all steps are executed, the method can further include:

[0082] Communication with the multi-channel SPI NAND FLASH memory chip is established. In the embodiment, the multi-channel includes a first channel, a second channel, and a third channel, and each channel is provided with a plurality of SPI NAND FLASH memory chips. The aforementioned step S20 can further include: testing the plurality of flash memories in the first channel at a first initial frequency; testing the plurality of flash memories in the second channel at a second initial frequency; and testing the plurality of flash memories in the third channel at a third initial frequency. The present application can automatically test the SPI NAND FLASH memory chip through SPI protocol communication with the multi-channel SPI NAND FLASH memory chip and through the user input automatic test instruction, so as to obtain the test result, so that the user only needs to input the automatic test instruction during the SPI NAND FLASH memory chip testing process, and the testing equipment can automatically complete the test to obtain the test result, reducing manual operation and improving the automation degree of the test. In particular, since communication with the multi-channel SPI NAND FLASH memory chip is established, different customer demand tests can be realized when multiple parallel tests are performed, for example, n flash memories in A channel are tested at A frequency, n flash memories in B channel are tested at B frequency, and n flash memories in C channel are tested at C frequency, and so on, thereby meeting different user requirements.

[0083] Further, an adaptive algorithm can be introduced in the aforementioned method steps to ensure the accuracy of the test. For example, the test frequency can be adjusted in real time according to the performance of the SPI NAND FLASH memory chip to be tested to optimize the test process. For example, in a preferred embodiment, the method can further include:

[0084] adjusting the initial frequency according to a preset linear relationship between temperature and frequency when the ambient temperature changes; and

[0085] adjusting the initial frequency according to a preset linear relationship between voltage and frequency when the communication interface voltage changes.

[0086] As known by those skilled in the art, frequent reading, writing or erasing can change the temperature or interface voltage of the storage chip. In the embodiment, the linear relationship between the temperature of the SPI NAND FLASH storage chip and the frequency can be preset in the software, and then the initial frequency is adjusted according to the measured ambient temperature. For example, when the chip temperature rises and the ambient temperature is also at a high value, a frequency change compensation value can be set to reduce the original frequency interval (for example, from 1 MHz to 0.8 or 0.5 MHz), so as to optimize the test process. The linear relationship between the interface voltage of the SPI NAND FLASH storage chip and the frequency can also be preset in the software, and then the initial frequency is adjusted according to the measured interface voltage, so as to optimize the test process.

[0087] In the embodiment, the independent MCU is provided, and the test results can be further processed. As shown in FIG. 6, in a preferred embodiment, the method for processing the test results can include the following steps: Figure 5

[0088] Step S30, analyzing the write test results, the read test results and / or the erase test results to obtain performance evaluation results;

[0089] Step S40, generating a test report according to the performance evaluation results;

[0090] Step S50, uploading the test report to a cloud server. In the embodiment, the test device can use the independent MCU to connect to the SPI, the MCU can transmit data to the host computer and the computer through the USB high-speed transmission to process the test results at the current frequency and quickly switch the frequency. After obtaining the test results, the test device can also analyze the test results through the MCU to obtain the performance test report of the chip at different frequencies, and the MCU uploads the test report to the cloud server, so as to facilitate data storage, sharing and analysis.

[0091] In the embodiment, the initial frequency can be preset by the user. The user preset can refer to the factory-set frequency of the SPI NAND FLASH storage chip, or the factory-set frequency of the SPI NAND FLASH storage chip can be automatically obtained by the device. For example, in a preferred embodiment, the factory-set frequency of the SPI NAND FLASH storage chip can be obtained by the following steps:

[0092] ​According to the model information of the SPI NAND FLASH memory chip, the read, write and erase frequency thresholds of the SPI NAND FLASH memory chip are obtained;

[0093] The initial frequency is set according to the threshold value.

[0094] The embodiment of the application further provides a test device of the SPI NAND FLASH memory chip, which is used for realizing the above-mentioned method process, and the test device is described with reference to Figure 6 In a preferred embodiment, the test device of the SPI NAND FLASH memory chip can include:

[0095] The MCU control unit 10 is responsible for the control and data processing of the whole test process. Specifically, an MCU with the model of STM32H750VBT6 can be used. The application adjusts the frequency operation through the MCU control of the SPI NAND FLASH read and write process, has the characteristics of easy implementation, high integration and small space occupation, and is convenient for small batch verification.

[0096] The SPI test interface 20 can set the SPI and QSPI interfaces, and is used for establishing the communication between the SPI NAND FLASH memory chip. The embodiment of the application can be compatible with the bandwidth of two transmission interfaces, and supports the frequency test of more than 100MHz of x1, x2 and x4 bit widths.

[0097] The data acquisition and analysis module 30 acquires real-time test data, and sends the results to the MCU control unit for the frequency adjustment of the MCU. In the embodiment of the application, a high-speed data acquisition and analysis module can be used to capture data in real time during the test, and the high-performance processor is used for real-time analysis to reduce the data processing delay.

[0098] The frequency adjustment module 40 realizes the frequency conversion function, which is realized through the clock frequency adjustment inside the MCU. In the embodiment of the application, the frequency adjustment module can support the test of the SPI NAND FLASH memory chip with different frequencies through the programmable clock generation circuit. Since the programmable clock generation circuit is used, the frequency can be adjusted in real time according to the specific requirements to adapt to the requirements of different specifications of NAND.

[0099] In the embodiment of the application, the frequency adjustment module is controlled by the MCU control unit 10. For example, after the MCU control unit 10 receives the test results sent by the data acquisition and analysis module 30, the MCU control unit 10 sends the instructions to the frequency adjustment module 40 according to the test results, the frequency adjustment module 40 adjusts the initial frequency, and the MCU control unit 10 sends the test instructions to inform the relevant test units to execute the test again according to the adjusted frequency.

[0100] In the embodiment of the present application, the MCU control unit 10 can include a user interface 11 and a data processing module 12, the user interface 11 is used for setting input test instructions and displaying test results, and the data processing module 12 is used for processing all data.

[0101] As can be seen from the above, the present application adopts automatic test software combined with hardware circuit to realize comprehensive reading, writing and erasing operations under different frequencies, can be compatible with different specifications of SPI NAND FLASH memory chips, realize frequency change test of the SPI NAND FLASH memory chip, and reduce manual intervention and improve test efficiency.

[0102] The embodiment of the present application also provides a SPI NAND FLASH memory chip test system, which comprises the SPI NAND FLASH memory chip test device. In addition to the test device, the test system can also comprise a network interface, a user interface, a memory and a communication bus. The communication bus is used to realize the connection and communication between the components. The user interface can include a display screen (Display) and an input unit such as a keyboard (Keyboard). The optional user interface can also include a standard wired interface and a wireless interface. The network interface can optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory can be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory.

[0103] The above only describes some or preferred embodiments of the present application, neither the text nor the drawings can limit the scope of protection of the present application, any equivalent structural transformation using the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the scope of protection of the present application.

Claims

1. A test method for an SPI NAND FLASH memory chip, characterized in that, The method comprises the following steps: According to the read data, write data and erase data test instructions input by the user, the SPI NAND FLASH memory chip is tested according to the initial frequency; According to the test results, the initial frequency is adjusted and the test is re-executed; The test according to the initial frequency includes: According to the write data automatic test instruction input by the user, the preset data is written into the SPI NAND FLASH memory chip according to the initial frequency; The SPI NAND FLASH memory chip is read to obtain the first read data; The first read data is compared with the preset data to obtain the write test result; According to the test result that the first read data is inconsistent with the preset data, the initial frequency is adjusted and the write test is re-executed; The initial frequency is adjusted according to the preset frequency interval. The test according to the initial frequency also includes:

2. The method of claim 1, wherein the SPI NAND FLASH memory chip is a K9F1G08U0M. According to the read data automatic test instruction input by the user, the data is read from the SPI NAND FLASH memory chip according to the initial frequency to obtain the second read data; The second read data is compared with the original data to obtain the read test result; According to the test result that the second read data is inconsistent with the original data, the initial frequency is adjusted and the read test is re-executed. The test according to the initial frequency also includes:

3. The method of claim 2, wherein the SPI NAND FLASH memory chip is tested by: According to the erase data automatic test instruction input by the user, the SPI NAND FLASH memory chip is erased according to the initial frequency; It is detected whether there is residual data in the SPI NAND FLASH memory chip to obtain the erase test result; According to the test result that there is residual data in the SPI NAND FLASH memory chip, the initial frequency is adjusted and the erase test is re-executed. Before all the steps are executed, it also includes:

4. The method of claim 1 to 3, wherein, Establish communication with the multi-channel SPI NAND FLASH memory chip. The multi-channel includes a first channel, a second channel and a third channel, each channel is provided with a plurality of SPI NAND FLASH memory chips, and the test according to the initial frequency includes:

5. The method of claim 4, wherein the SPI NAND FLASH memory chip is tested by: The first initial frequency is executed for the plurality of flash memories in the first channel; the second initial frequency is executed for the plurality of flash memories in the second channel; and the third initial frequency is executed for the plurality of flash memories in the third channel. It also includes:

6. The method of claim 5, wherein the SPI NAND FLASH memory chip is tested by: When the ambient temperature changes, the initial frequency is adjusted according to the preset linear relationship between temperature and frequency; And When the communication interface voltage changes, the initial frequency is adjusted according to the preset linear relationship between voltage and frequency. It also includes:

7. The method of claim 6, wherein the SPI NAND FLASH memory chip is tested by: ​ analyzing the write test result, the read test result and / or the erase test result to obtain a performance evaluation result; generating a test report according to the performance evaluation result; uploading the test report to a cloud server.

8. The method of claim 4, wherein the method further comprises: the performing of the corresponding read, write and erase tests on the SPI NAND FLASH memory chip according to the initial frequency comprises: obtaining read, write and erase frequency thresholds of the SPI NAND FLASH memory chip according to model information of the SPI NAND FLASH memory chip; setting the initial frequency according to the thresholds.

9. A test device for SPI NAND FLASH memory chips, characterized in that, comprise: one or more MCU control units and a memory; the memory is coupled with the one or more MCU control units, and the memory is configured to store computer program codes, the computer program codes comprise computer instructions, and the one or more MCU control units invoke the computer instructions to enable the test device to perform the method according to any one of claims 1 to 8.

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