A storage test device and its test method

Abstract

The present invention provides a storage test device and a test method thereof. The device includes: a control module; a verification operation chip electrically connected to the control module and the device under test. The verification operation chip obtains test data of the device under test according to the configuration information provided by the control module; a hardware monitoring module that synchronously collects and verifies the working signals of the device under test during the test process of the device under test; an analysis unit integrated in the hardware monitoring module or the control module, which captures abnormal signals in the working signals. When an abnormal signal appears, the control module freezes the chip state and locks the on-site data of the device under test. After the control module analyzes the on-site data and the test data, an abnormal analysis link is generated; a fault location unit integrated in the control module, which obtains the abnormal location of the device under test according to the abnormal analysis link; updates the configuration information of the hardware monitoring module, and performs cyclic tests until the full-scenario and full-function coverage test of the device under test is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of storage testing, and particularly to a storage testing device and a testing method thereof. Background Art

[0002] eMMC (Embedded Multi Media Card) is a standard specification for embedded memory established by the MMC Association, mainly targeting products such as mobile phones or tablet computers. With the wide application of eMMC storage chips in terminal products such as televisions, set-top boxes, tablet computers or mobile phones, the performance and reliability requirements for eMMC storage chips are getting higher and higher. The most important thing is to ensure the stability and reliability of the data stored in the eMMC.

[0003] In the design process of the chip, detecting potential problems in the chip is the core step to ensure the chip quality. The current verification work faces two major challenges, namely how to comprehensively investigate potential hazards and how to improve the detection efficiency. Chip verification relies on Field Programmable Gate Array (FPGA) chips. The operating speed of FPGA chips is slow and the storage space is insufficient, making it difficult to completely record all signal waveforms during chip operation. Once a problem is found, it is difficult to quickly locate the root cause of the problem, and it takes too long to reproduce the problem. Moreover, the debugging means for chip verification are single, and the debugging method lacks flexible triggering conditions, making it difficult to analyze problems from multiple dimensions. In the verification tests of complex systems such as embedded memory card type system-on-chip, the co-verification efficiency of multiple modules is low. These problems all lead to the verification not meeting the timeliness requirements of eMMC storage chip design. Summary of the Invention

[0004] The purpose of the present invention is to provide a storage testing device and a testing method thereof, which support quickly and comprehensively helping to complete chip design verification and improving the verification analysis efficiency and coverage.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0006] The present invention provides a storage testing device, including:

[0007] A control module;

[0008] A verification running chip, electrically connected to the control module and the device under test. The verification running chip obtains test data of the device under test according to the configuration information provided by the control module.

[0009] A hardware monitoring module, electrically connected to the verification running chip and the device under test, and synchronously collecting and verifying the working signals of the device under test during the test process of the device under test.

[0010] An analysis unit, integrated in the hardware monitoring module or the control module, captures abnormal signals in the working signals. When the abnormal signals occur, the control module freezes the chip state and locks the on-site data of the device under test. After the control module analyzes the on-site data and the test data, an abnormal analysis link is generated; and

[0011] A fault location unit, integrated in the control module, obtains the abnormal location of the device under test according to the abnormal analysis link;

[0012] Wherein, the configuration information of the hardware monitoring module is updated and cyclic testing is performed until the full-scenario and full-function coverage testing of the device under test is completed.

[0013] In an embodiment of the present invention, the storage test device includes a configuration module, which is electrically connected to the control module and receives configuration parameters sent by the control module. During the test process of the device under test, the configuration device adjusts the combination of test interfaces enabled by the device under test according to the configuration parameters. The device under test is electrically connected to the hardware monitoring module through the combination of test interfaces and sends the working signals to the hardware monitoring module.

[0014] In an embodiment of the present invention, the hardware monitoring module includes:

[0015] A signal screening unit, electrically connected to the test interface, and selects the working signals corresponding to the verification focus; and

[0016] A sampling setting unit, sets the sampling frequency of the working signals according to the working frequency of the verification focus.

[0017] In an embodiment of the present invention, the hardware monitoring module includes:

[0018] A logic processing unit, electrically connected to the sampling setting unit, and obtains the waveform logic relationship of multiple working signals;

[0019] A segment intercepting unit, electrically connected to the sampling setting unit, and obtains the time of the wave band to be verified; and

[0020] A data verification unit, electrically connected to the logic processing unit, the segment intercepting unit and the sampling setting unit, obtains the signal information to be analyzed according to the wave band time and the waveform logic relationship, and adds a verification bit to the signal information to be analyzed.

[0021] In an embodiment of the present invention, the hardware monitoring module includes:

[0022] A data compression unit, electrically connected to the data verification unit. When the working signal is a normal signal, the data compression unit compresses the signal information to be analyzed and outputs a data compression package;

[0023] An abnormal warning unit, electrically connected to the data verification unit and the control module. When the working signal is a normal signal, the abnormal warning unit outputs an abnormal warning message to the control module.

[0024] In an embodiment of the present invention, the control module includes:

[0025] A tracking unit. When the analysis unit captures an abnormal signal, the tracking unit generates an abnormal analysis link for the abnormal signal according to the context information of the problem occurrence;

[0026] A fault location unit, traversing and querying all nodes of the abnormal analysis link to locate the fault object of the device under test as the abnormal location of the device under test; and

[0027] A report generation unit, generating a test record report according to the analysis information of the abnormal signal, where the information of the test record report includes test results, problem logs, signal waveforms, and time points.

[0028] In an embodiment of the present invention, the storage test device includes a test daughter board and a host, where the host and the test daughter board are electrically connected. During the test process of the device under test, the verification running chip, the device under test, and the hardware monitoring module are integrated on the same test daughter board.

[0029] In an embodiment of the present invention, the storage test device includes:

[0030] A flash memory, electrically connected to the verification running chip, and the configuration file and the test firmware are stored in the flash memory;

[0031] A first memory, electrically connected to the verification running chip and storing test variables and test data generated during the test process; and

[0032] A second memory, electrically connected to the hardware monitoring module and receiving the data compression package from the hardware monitoring module, where the stored information in the data compression package includes waveform information and timing information of the working signal.

[0033] The present invention provides a storage test method, based on a storage test device as described above, including the following steps:

[0034] Initialize the verification running chip;

[0035] Configure a hardware monitoring module, select the verification focus of the device under test, and obtain the test data of the verification focus;

[0036] During the test process of the device under test, the hardware monitoring module synchronously collects and verifies the working signals of the device under test;

[0037] When detecting that the working signal is abnormal, freeze the chip state and lock the on-site data of the device under test;

[0038] After parsing the on-site data and the test data, generate an abnormal analysis link, and obtain the abnormal location of the device under test; and

[0039] According to the real-time coverage of the verification test and the test results of the device under test, adjust the hardware monitoring resources, and loop through the test combinations until the full-scenario and full-function coverage test of the device under test is completed.

[0040] In an embodiment of the present invention, in the step of configuring the hardware monitoring module, set a cross-module trigger logic link, a multi-condition combination trigger rule, and a dynamically adapted operating frequency.

[0041] As described above, the present invention provides a storage test device and its test method, which can improve the coverage of verification, accelerate the problem analysis process, enhance the integrity of verification, and can generate various types of trigger conditions, and can capture the operating states of various modules when problems occur, improving the ability to cooperate and debug in detail between modules. Specifically, the storage test device and its test method provided by the present invention can optimize the resource allocation of the FPGA, realize the full-process monitoring of the signals during chip operation and the capture of the state at any time, support the setting of a multi-condition trigger mechanism, and can also restore the problem scene, significantly improving the debugging efficiency.

[0042] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0044] Figure 1 It is a schematic structural diagram of a storage test device in an embodiment of the present invention.

[0045] Figure 2 It is a schematic diagram of the configuration object of a configuration module in an embodiment of the present invention.

[0046] Figure 3 This is a schematic structural diagram of a hardware monitoring module in an embodiment of the present invention.

[0047] Figure 4 This is a schematic structural diagram of a control module in an embodiment of the present invention.

[0048] Figure 5 This is a schematic flowchart of a storage test method in an embodiment of the present invention.

[0049] In the figure: A, host; B, test daughter board; 100, verification operation chip; 200, device under test; 310, flash memory; 320, first memory; 330, second memory; 410, transmission interface; 420, general interface; 510, power supply module; 520, log output module; 600, trigger module; 700, configuration module; 800, hardware monitoring module; 810, signal screening unit; 820, sampling setting unit; 830, file format database; 840, logic processing unit; 850, data verification unit; 860, segment intercepting unit; 870, data compression unit; 880, data output unit; 890, exception warning unit; 900, control module; 901, file configuration unit; 902, download unit; 903, parameter configuration unit; 904, trigger rule setting unit; 905, visualization unit; 906, timing setting unit; 907, tracking unit; 908, analysis unit; 909, upload unit; 910, fault location unit; 911, report generation unit; 912, historical database; 913, monitoring interface. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] In the storage test device provided by the present invention, the test object is an embedded storage chip, specifically an eMMC storage chip or a Universal Flash Storage (UFS). The eMMC storage chip includes a main controller and a flash memory, and the main controller and the flash memory are integrated and packaged as a whole. The main controller can be an ARM processor, and the flash memory can be a NAND flash memory. The main controller runs firmware, which can implement key operations such as bad block management, garbage collection, early warning, performance improvement, and lifespan extension of the flash memory, so as to ensure the reliable use of the flash memory. The firmware is extremely complex, and whether the firmware running inside the eMMC storage chip can function accurately and efficiently is crucial for the normal operation and performance of the eMMC storage chip. The storage test device and its test method provided by the present invention can accurately, efficiently, and comprehensively test whether the firmware runs smoothly and can locate the error position in a timely and accurate manner.

[0052] The storage test device provided by the present invention includes a host and a test daughter board. The host and the test daughter board are electrically connected. The test daughter board includes a verification running chip, a device under test, a configuration module, a trigger module, a hardware monitoring module, a plurality of memories, and a plurality of interfaces. The verification running module is a Field Programmable Gate Array (FPGA) chip. The device under test, the verification running chip, and the host are electrically connected. During the operation of the device under test, the verification running chip can obtain the verification test data of the device under test and control the verification test process of the device under test. Among them, preset configuration parameters are stored in the host or configuration parameters can be input to the host to enable the corresponding test function of the storage test device.

[0053] Please refer to Figure 1As shown, in an embodiment of the present invention, multiple memories include a flash memory, a first memory, and a second memory. The flash memory may be a NAND flash memory, the first memory may be a Random Access Memory (RAM), and the second memory may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM). The flash memory is electrically connected to the verification running chip, and the flash memory is used to store test firmware. When the verification running chip runs the test firmware, the storage test method provided by the present invention can be implemented. The first memory is electrically connected to the verification running chip to store the data generated by the verification running chip during operation and can be used to store variables in the test process. The second memory is a large-capacity memory, and the second memory is electrically connected to the hardware monitoring module to quickly store the data output by the hardware monitoring module.

[0054] Please refer to Figure 1 As shown, in an embodiment of the present invention, among the multiple interfaces of the storage test device, there are a transmission interface and a general interface. The transmission interface is electrically connected between the host and the verification running chip and is used to transmit instruction signals and test data, as well as download configuration files and test programs, etc. In this embodiment, the transmission interface may be a USB interface. The general interface is electrically connected between the verification running chip and the second memory. In this embodiment, the general interface may be a Peripheral Component Interconnect Express (PCIE). The general interface can quickly upload the waveform data obtained by the hardware monitoring module with multiple bandwidths and transmit the waveform data to the host through the verification running chip and the transmission interface.

[0055] Please refer to Figure 1 As shown, in an embodiment of the present invention, the storage test device further includes a power supply module, a display module, and a log output module. The power supply module is electrically connected to the verification running chip. At the beginning of the test, the verification running chip is first powered by the power supply module. After power-on, the verification running chip is in a standby state. The power supply module can supply power to each component of the storage test device. In this embodiment, the display module is a display device, and the display module is electrically connected to the verification running chip and is used to display the running state of the storage test device. The log output module is electrically connected to the verification running chip and is used to output the log file of the verification running chip.

[0056] Please refer to Figure 1As shown, in an embodiment of the present invention, the trigger module is electrically connected to the verification operation chip and the device under test, and can receive the configuration parameters sent by the verification operation chip. According to different configuration parameters, the trigger module switches to the corresponding single verification trigger mode or combined verification trigger mode. The single verification trigger mode is to trigger according to a single condition or a single signal. For example, triggering based on the high level or low level or rising edge or falling edge of a single signal. Another example is triggering when the signal voltage exceeds a threshold. The combined verification trigger mode triggers according to the logical combination of multiple conditions or multiple signals. For example, triggering when signal one is at a high level and signal two is at a rising edge. Another example is triggering when signal three is at a low level and signal four is at a falling edge.

[0057] Please refer to Figure 1 As shown, in an embodiment of the present invention, the configuration module is electrically connected to the verification operation chip, the hardware monitoring module and the device under test. The configuration module can receive the configuration file sent by the host through the verification operation chip, and select various test combinations of the device to be tested according to the configuration file. Specifically, multiple test interfaces are provided inside the device under test, and the configuration module can select various combinations of test interfaces inside the device under test, so as to enable various functional combinations of the device under test, so that the device under test participates in the verification test in various forms. Among them, the device under test and the hardware monitoring module are electrically connected. Through the enabled test interfaces inside the device under test, the hardware monitoring module can monitor the waveform data of the device under test through the test interfaces. In this embodiment, the configuration module has multiple working modes. Before the test starts, the working mode of the configuration module is adjusted. Specifically, by adjusting the configuration parameters sent to the configuration module, the working mode of the configuration module is correspondingly adjusted. In different working modes, after the test starts, according to the selected functional combination, the configuration module can select and enable the functional units corresponding to the logical combination in the device under test.

[0058] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, the configuration module can select and enable multiple functional units of the device under test. The functional units that the configuration module can enable include the processor unit eMMC_CPU, the command decoding unit eMMC_CMDDecode, the low-density parity-check unit eMMC_LDPC, the device identification register eMMC_CID, the card-specific data register eMMC_CSD, the extended card-specific data register eMMC_ECSD, the hardware register eMMC_HwReg, the NAND flash controller eMMC_NFC, the data buffer eMMC_DataBuf, the replay protection memory block eMMC_RPMB, the command queue eMMC_CMDQ, and the read-only memory eMMC_ROM. Among them, each functional unit of the device under test has a corresponding function. And according to different firmware designs, there are corresponding requirements and markings for the operations that can be performed or the functions that can be possessed by multiple functional units of the device under test. Examples are as follows. The processor unit is used to execute firmware instructions, manage data transmission, process error correction, and other tasks. The command decoding unit is used to parse commands sent by units such as the power management unit or the processor unit and convert the commands into internal operations of the device under test. The low-density parity-check unit can implement data error correction through low-density parity-check (LDPC) codes to improve the reliability of stored data. The device identification register is used to store the unique identification information of the device under test, such as the manufacturer ID, product serial number, etc. The card-specific data register is used to store the configuration information and characteristic information of the device under test, such as storage capacity, read / write speed, voltage range, etc. The extended card-specific data register is used to store the extended configuration information of the device under test and support more advanced functions and features. The hardware register is used to configure and control the hardware behavior of the device under test, such as clock frequency, power management, etc. The NAND flash controller is used to manage the read / write operations of the NAND flash in the device under test, including bad block management and wear leveling of the NAND flash. The data buffer is used to temporarily store read / write data to improve data transmission efficiency. The replay protection memory block is used to provide a secure storage area and is used to store sensitive data such as keys, authentication information, etc., thereby preventing replay attacks. The command queue is used to support the queuing and execution of multiple commands to improve the concurrent processing ability of the device under test. The read-only memory is used to store the startup code, firmware, or configuration data of the device under test.

[0059] Please refer to Figure 1 and Figure 3As shown, in an embodiment of the present invention, the hardware monitoring module includes a signal screening unit, a sampling setting unit, a file format database, a logic processing unit, a data verification unit, a segment intercepting unit, a data compression unit, a data output unit, and an anomaly warning unit. Among them, the signal screening unit is electrically connected to the device under test and receives multiple signals. The signal screening unit screens out the signals to be sampled from the multiple signals, and the sampling signals can be selected and set by itself. The sampling setting unit is electrically connected to the output end of the signal screening unit and is used to set different sampling frequencies according to the signal frequencies of different sampling signals. The file format database is electrically connected to the input end of the sampling setting unit, and the content stored in the file format database is BIN files or document contents in recognizable formats. The logic processing unit is electrically connected to the output end of the sampling setting unit and is used to identify the front-back relationship of the hardware circuit timing. The data verification unit is electrically connected to the output ends of the logic processing unit and the sampling setting unit, and is used to add a verification bit to the received data to facilitate the verification and comparison of the data received by the backend, so as to confirm the integrity of the data. The segment intercepting unit is electrically connected to the output end of the sampling setting unit and the input end of the data verification unit, and is used to obtain the logic signals of the device under test within a specified test time interval. The data compression unit is electrically connected to the output end of the data verification unit and is used to compress the data that has no problems in data verification, so as to save storage space and improve the transmission speed. The anomaly warning unit is electrically connected to the output end of the data verification unit and is used to check whether the indicators of the input signal meet the expectations. If they do not meet the expectations, the anomaly warning unit will issue a warning to remind the engineering staff to analyze. Among them, issuing a warning can be generating a warning signal. The data output unit is electrically connected to the output ends of the data compression unit and the anomaly warning unit, and is used to output the data, signals, etc. collected, verified, classified, and compressed by the hardware monitoring module. Among them, the data output unit is electrically connected to the second memory and outputs the output data signals, etc. to the second memory for storage. Then, it is transmitted to the host through a general interface, a verification running chip, and a transmission interface.

[0060] Please refer to Figure 1 and Figure 3 As shown, in an embodiment of the present invention, the signals that can be sampled include clock signal clock, reset signal reset, enable signal enable, low-address signal address_l, high-address signal address_h, high-performance bus transmission signals AHB (Advanced High-performance Bus) and AXI (Advancedextensible Interface) signals, etc. In this embodiment, the hardware monitoring module can be a waveform real-time monitor.

[0061] Please refer to Figure 1 andFigure 4 As shown, in an embodiment of the present invention, the host includes a control module, and the control module is electrically connected to the test daughter board. The control module includes a file configuration unit and a download unit. The file configuration unit is used to generate a configuration file or select a configuration file from a storage end, and send the configuration file to the verification running chip. The configuration file stores configuration data and is used to define the logic function of the verification running chip. In this embodiment, the configuration file can be a Bit file. The configuration file is downloaded to the flash memory through a transmission interface and the verification running chip. Before the test, the verification running chip reads and loads the configuration file from the flash memory to complete the initialization before the test. The download unit can transfer the test firmware from the storage end to the test daughter board, and specifically can be downloaded to the flash memory. It should be noted that the storage test method provided by the present invention exists in the form of test firmware. The test firmware is downloaded from the host to the flash memory through a transmission interface, and the verification running chip loads and runs the test firmware, so that the storage test method provided by the present invention can be implemented to test and verify the target device under test.

[0062] Please refer to Figure 1 and Figure 4 As shown, in an embodiment of the present invention, the control module further includes a parameter configuration unit and a trigger rule setting unit. The parameter configuration unit is used to generate configuration parameters or select and read corresponding configuration parameters from a database. The configuration parameters are sent to the configuration module to adjust the working mode of the configuration module, enable the corresponding test interface combination of the device under test, and at the same time adjust the test interface combination monitored by the hardware monitoring module and the monitoring focus of the hardware monitoring module. The configurable configuration parameters include, for example, sampling rate, trigger condition, monitoring range, signal type, and so on. The trigger rule setting unit is used to generate trigger rules. According to different application scenarios, the trigger rule setting unit generates corresponding trigger rules and sends them to the trigger module to form different trigger conditions.

[0063] Please refer to Figure 1 、 Figure 3 and Figure 4As shown, in an embodiment of the present invention, the control module further includes an imaging unit, a timing setting unit, a tracking unit, an analysis unit, an upload unit, a fault location unit, a report generation unit, a historical database, and a monitoring interface. Among them, the imaging unit generates a visual waveform image according to the collected waveform data. The timing setting unit is used to set the timing relationship between signals. The tracking unit is used to track the logical relationship between waveforms. For example, the appearance of waveform three is because waveform one and waveform two are triggered. The analysis unit is used to automatically check the waveform data returned by the test daughter board according to the expected waveform designed, so as to analyze whether the waveform of the signal meets the expectation. The upload unit is used to receive the compressed package transmitted by the data compression unit. The fault location unit can locate the position where the abnormality occurs according to the information returned by the tracking unit, the analysis unit, and the upload unit. Among them, the position where the abnormality occurs can be any functional module, any functional type, and any signal. The report generation unit is used to generate a problem report for the abnormal problems occurring in each test. The historical database stores the historical data of the test for querying, checking, and comparing the test data, etc.

[0064] Please refer to Figures 1 to 4 As shown, in an embodiment of the present invention, in the storage test device, the trigger condition of the trigger module is configured through the control interface, for example, setting the logical combination of trigger signals, such as signal one and signal two are set to trigger simultaneously at a high level. The configuration parameters are transmitted to the verification running chip through the interface. The trigger module implements the corresponding trigger logic according to the configuration parameters. When the hardware monitoring module monitors the signal waveform, it can capture the timing events that meet the trigger conditions. Among them, the captured waveform data can be returned to the host through the interface for further analysis.

[0065] Please refer to Figures 1 to 5 As shown, the storage test method provided by the present invention includes steps S10 to S80.

[0066] Step S10: Load the device under test onto the test daughter board, and load the test firmware and configuration file into the verification running chip.

[0067] Step S20: Configure the hardware monitoring module, select the verification focus of the device under test, and obtain the test data of the verification focus.

[0068] Step S30: During the test process of the device under test, the hardware monitoring module synchronously collects and verifies the working signals of the device under test.

[0069] Step S40: When an abnormal working signal is detected, freeze the chip state and lock the on-site data of the device under test.

[0070] Step S50: After parsing the on-site data and implementing the test data, generate an abnormal analysis link and obtain the abnormal position of the device under test.

[0071] Step S60: Adjust the hardware monitoring resources according to the real-time coverage of the verification test and the test results of the device under test, and loop to execute the test combination until the full-scenario and full-function coverage test of the device under test is completed.

[0072] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S10, the device under test is installed on the test daughter board, and the installation method can be through sockets and interfaces. The verification operation chip, the device under test, and the hardware monitoring module are powered by the power supply module. After power-on, the verification operation chip is in the standby state. Through the download unit and the file configuration unit, a configuration file is sent to the verification operation chip, and the test firmware is downloaded to the flash memory. The verification operation chip loads the configuration file to complete the configuration. At the start of the test, the verification operation chip runs the test firmware to implement the storage test method provided by the present invention.

[0073] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S20, parameter configuration is completed through the parameter configuration unit, and the configured parameters are sent to the configuration module. The configuration module adjusts the test interface combination in the device under test according to the received configuration parameters. Configuration parameters are generated through the parameter configuration unit, and the trigger condition of the trigger unit is set through the trigger rule setting unit, and the trigger condition is sent to the trigger unit in the form of parameters. According to the trigger condition of the trigger unit, the hardware monitoring module can monitor the waveform of the test signal according to the trigger condition. Among them, in step S20, the verification focus in the device under test can be a single or multiple functional units, can be a test environment, or can be a combination of the test environment and the selected functional units. In an entire test process, multiple verification foci of the device under test can be tested in sequence until the comprehensive verification of the device under test is completed. Whenever a verification focus test is completed, step S20 can be returned to, and a new verification focus can be selected. According to the selected verification focus, the hardware monitoring module is reconfigured until the verification foci of the device under test are traversed. In step S20, in the step of configuring the hardware monitoring module, the parameters to be configured include the cross-module trigger logic link, the multi-condition combination trigger rule, and the dynamic adaptation working frequency. Among them, the cross-module trigger logic link is specifically reflected in the timing logic of the functional units in the device under test. The multi-condition combination trigger rule is the trigger rule of the trigger module, specifically reflected in under what rules the signal is sent and under what conditions the operation occurs. The dynamic adaptation working frequency includes the sampling frequency set by the sampling setting unit and the clock logic of each module, etc.

[0074] Please refer to Figures 1 to 5As shown, in an embodiment of the present invention, in step S30, after the test starts, the running chip verifies and runs the test firmware. While the storage firmware in the device under test is running to implement various storage functions, according to the trigger rule, the hardware monitoring module starts to monitor the test process of the device under test. It should be noted that the present invention does not limit the storage firmware in the device under test, and different devices under test may have different storage firmware. In this embodiment, according to the test interface selected by the configuration module, the hardware monitoring module can determine the functional units of the device under test that need to be monitored. Among them, the functional units of one or more devices under test can be monitored. According to the functional units to be monitored, the hardware monitoring module sets signal sampling points and collects relevant data at the signal sampling points. The signal sampling point refers to the sampling time point of the signal. For example, if the garbage collection functional unit of the device under test is being tested at this time, the signal sampling point can be set to the time point when garbage collection starts to transfer data, the time point when garbage collection erases the source block, and so on. In this embodiment, the hardware monitoring module sets or adjusts the sampling time point according to the running frequency of each functional unit in the device under test to ensure that the signal changes of each module can be accurately captured.

[0075] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S30, during the test process, the hardware monitoring module saves the collected data in the corresponding file format according to the format supported by the host, so that the software can correctly read and parse it. The hardware monitoring module can obtain the corresponding file format from the file format database. The file format can be CSV, JSON, binary file, etc. In this embodiment, during the test process, the hardware monitoring module judges whether the monitored signal conforms to the trigger rule according to the preset trigger rule. Among them, the logic processing unit can distinguish the front and rear timing relationships of the hardware circuit, and the logic processing unit sorts the sent signals. And the signals are sent to the data verification unit in the sorted order. The data verification unit sequentially adds a verification bit to the verification data and sends the verification data to the analysis unit. The analysis unit parses the verification data, judges whether the waveform of the signal conforms to the expected shape or analyzes whether the value of the signal conforms to the expectation, and judges whether the occurrence of the signal conforms to the trigger rule. When all the waveforms conform to the expectation, the signal is a normal signal. For the normal signal, the data compression unit compresses the verification signal and the verification data, and sends the compressed test data to the upload unit via the data output unit. The upload unit sends the received data to the historical database for storage. When any of the waveforms does not conform to the expectation, the signal is an abnormal signal. For the abnormal signal, step S40 is executed. The front and rear timing relationships of the hardware circuit can be identified and recorded through the logic processing unit, and the tracking unit can further obtain the logical relationship between the waveforms based on the data transmitted by the logic processing unit. At the first moment when an abnormality occurs, the fault location unit can quickly locate the position where the fault occurs according to the collected data.

[0076] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S30, according to the functional unit to be tested, the segment intercepting unit intercepts waveform data corresponding to a time period from a segment of waveform and sends the waveform data to the data verification unit. According to the timing relationship provided by the logic processing unit and the segment to be verified provided by the segment intercepting unit, after adding a check bit to the waveform data, the data verification unit sends it to the analysis unit. The analysis unit classifies the sampling signals. Specifically, the sampling signals are identified as normal signals or abnormal signals. In an embodiment of the present invention, the analysis unit is arranged in the host, such as Figure 4 As shown. The data verification unit can be electrically connected to the host through a verification running chip and an interface. The analysis result of the analysis unit is returned to the data verification unit. When the sampling signal is a normal signal, the data verification unit sends the sampling signal to the data compression unit. When the sampling signal is an abnormal signal, the data verification unit sends the sampling signal to the abnormal warning unit. In another embodiment of the present invention, the analysis unit is integrated in the hardware monitoring module, such as Figure 3 As shown, the output end of the data verification unit is electrically connected to the input end of the analysis unit, and the output end of the analysis unit is electrically connected to the data compression unit and the abnormal warning unit. Among them, when the sampling signal is a normal signal, the analysis unit sends the sampling signal to the data compression unit. When the sampling signal is an abnormal signal, the analysis unit sends the sampling signal to the abnormal warning unit.

[0077] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S40, during the process of the analysis unit analyzing data, when the signal timing and signal waveform do not meet the expectations, and when functional tests have errors, warnings will be triggered. In the present invention, when the verification of the analysis unit fails, the signal is identified as an abnormal signal. It should be noted that the abnormal signal here can be a single signal or multiple signals. In step S40, first determine whether the abnormal signal is an abnormal signal that needs to be analyzed. If the abnormal signal does not need to be analyzed, ignore the abnormal signal and continue to verify the test and monitor the working signal. If the abnormal signal is an abnormal signal that needs to be analyzed, first stop the verification running chip from running the test firmware and stop the device under test from running the storage firmware to prevent the problem from further expanding or affecting subsequent tests, freeze the state of the device under test, and then execute step S50. Freezing the chip state means that while stopping the firmware operation, save the system state and data when the problem occurs, including register values, signal waveforms, operation logs, etc., to ensure that the problem site is not damaged. The present invention quickly locates problems and retains on-site information, which can provide a basis for subsequent analysis and solution.

[0078] Please refer to Figures 1 to 5As shown, in an embodiment of the present invention, in step S50, the host issues a tracking instruction to enable the tracking unit. In this embodiment, the tracking unit records the context information of the problem occurrence and generates an abnormal analysis link for the abnormal signal. The context information includes time, test conditions, signal status, etc., for subsequent analysis. When analyzing the fault, the report generation module generates a detailed test record report and saves the report to the historical database. The report content includes key information such as test results, problem logs, signal waveforms, time points, etc. In this embodiment, the report can be stored in the historical database in the form of structured data for subsequent query, analysis, and statistics. In this embodiment, the analysis unit and the fault location unit deeply analyze the signal waveform and signal timing to find out the specific reasons for the test failure. The analysis of the signal waveform can be reflected in analyzing the signal waveform and checking for abnormal signals such as noise, jitter, distortion, etc. Checking the signal timing can be reflected in checking whether the signal timing conforms to the design specifications and whether there are timing violations. The conditions for timing violations are preset by the tester, such as the setup time and hold time not meeting the requirements. Combining the waveform and timing analysis results, the specific problem points causing the test failure are located. In the hardware monitoring module, when an abnormal signal appears, the abnormal warning unit generates a warning signal and outputs it externally through the data output unit. The abnormal warning unit can also generate a warning message and output it externally through the data output unit.

[0079] Please refer to Figures 1 to 4 As shown, in an embodiment of the present invention, according to the preset upload period, the data in the second memory is regularly uploaded to the upload unit through the general interface. When the working signals of the device under test are all normal signals, the compressed packet data compressed by the data compression unit is regularly uploaded to the host.

[0080] Please refer to Figures 1 to 5As shown, in an embodiment of the present invention, in step S60, after the abnormal signal processing is completed or the current verification focus has been tested, the real-time coverage of the current verification test is judged. The real-time coverage refers to the proportion of the tested instances to all test cases. In the step of evaluating the test results, when the real-time coverage reaches 100%, the testing of all functional units of the device under test is completed. When all the tests of the device under test pass, the test is completed and the test ends. If the real-time coverage does not reach 100%, the hardware monitoring resources are adjusted and the test is retested. Specifically, switch to a new verification focus, reconfigure the hardware monitoring module according to the new verification focus and start to loop the storage test method of the present invention. If the test of the device under test does not pass completely, for example, after the abnormal signal is located, the tester repairs and updates the storage firmware of the device under test, then the same verification focus needs to be retested and the hardware monitoring module is reconfigured to complete the retest of the corresponding verification focus. In step S60, the test is stopped until the full-scenario and full-function coverage test of the device under test is completed.

[0081] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A storage test device, characterized in that, Including: Control module; Verification running chip, electrically connected to the control module and the device under test, the verification running chip obtains test data of the device under test according to configuration information provided by the control module; Hardware monitoring module, electrically connected to the verification running chip and the device under test, and synchronously collects and verifies working signals of the device under test during the test process of the device under test; Analysis unit, integrated in the hardware monitoring module or the control module, and captures abnormal signals in the working signals. When the abnormal signals appear, the control module freezes the chip state and locks the on-site data of the device under test, and after the control module analyzes the on-site data and the test data, an abnormal analysis link is generated; And Fault location unit, integrated in the control module, and obtains the abnormal location of the device under test according to the abnormal analysis link; Wherein, the configuration information of the hardware monitoring module is updated and the loop test is performed until the full-scenario full-function coverage test of the device under test is completed.

2. The storage test device according to claim 1, wherein, The storage test device includes a configuration module, the configuration module is electrically connected to the verification running chip and receives a configuration file sent by the verification running chip. During the test process of the device under test, the configuration module adjusts the combination of test interfaces enabled by the device under test according to the configuration file, wherein the device under test is electrically connected to the hardware monitoring module through the combination of test interfaces and sends the working signal to the hardware monitoring module.

3. The storage test device according to claim 2, wherein The hardware monitoring module includes: Signal screening unit, electrically connected to the test interface, and selects the working signals of the functional units to be tested in the device under test; and Sampling setting unit, sets the sampling frequency of the working signal according to the working frequency of the functional unit to be tested.

4. The storage test device according to claim 3, characterized in that, The hardware monitoring module includes: Logic processing unit, electrically connected to the sampling setting unit, and obtains the waveform logic relationship of multiple working signals; Segment intercepting unit, electrically connected to the sampling setting unit, and obtains the waveband time to be verified; and Data verification unit, electrically connected to the logic processing unit, the segment intercepting unit and the sampling setting unit, obtains signal information to be analyzed according to the waveband time and the waveform logic relationship, and adds a verification bit to the signal information to be analyzed.

5. A storage test device according to claim 4, characterized in that, The hardware monitoring module includes: Data compression unit, electrically connected to the data verification unit, when the working signal is a normal signal, the data compression unit compresses the signal information to be analyzed and outputs a data compression packet; Abnormal warning unit, electrically connected to the data verification unit and the control module, when the working signal is a normal signal, the abnormal warning unit outputs an abnormal warning message to the control module.

6. The storage test device according to claim 1, wherein The control module includes: Tracking unit, when the analysis unit captures an abnormal signal, the tracking unit generates an abnormal analysis link for the abnormal signal according to the context information of the problem occurrence; A fault location unit traverses and queries all nodes of the abnormal analysis link to locate the fault object of the device under test as the abnormal location of the device under test; and A report generation unit generates a test record report based on the analysis information of the abnormal signal, where the information in the test record report includes test results, problem logs, signal waveforms, and time points.

7. A storage test device according to claim 1, characterized in that, The storage test device includes a test daughter board and a host, where the host and the test daughter board are electrically connected. During the test process of the device under test, the verification running chip, the device under test, and the hardware monitoring module are integrated on the same test daughter board.

8. A storage test device according to claim 1, characterized in that, The storage test device includes: A flash memory electrically connected to the verification running chip, where the flash memory stores test firmware and configuration files of the hardware monitoring module; A first memory electrically connected to the verification running chip and stores test variables and test data generated during the test process; and A second memory electrically connected to the hardware monitoring module and receives a data compression package of the hardware monitoring module, where the stored information in the data compression package includes waveform information and timing information of the working signal.

9. A storage test method, based on a storage test device as described in claim 1, characterized in that, It includes the following steps: Initialize the verification running chip; Configure the hardware monitoring module, select the verification focus of the device under test, and obtain the test data of the verification focus; During the test process of the device under test, the hardware monitoring module synchronously collects and verifies the working signal of the device under test; When the working signal is detected to be abnormal, freeze the chip state and lock the on-site data of the device under test; After parsing the on-site data and the test data, generate an abnormal analysis link and obtain the abnormal location of the device under test; And According to the real-time coverage of the verification test and the test results of the device under test, adjust the hardware monitoring resources and loop to execute the test combination until the full-scenario and full-function coverage test of the device under test is completed.

10. A storage test method according to claim 9, characterized in that, In the step of configuring the hardware monitoring module, set the cross-module trigger logic link, multi-condition combination trigger rule, and dynamic adaptation working frequency.

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