Chip packaging structure and manufacturing method of air chamber for protecting chip functional area

Abstract

The invention discloses a chip packaging structure which comprises a substrate, a chip fixed on the substrate, a packaging body and a plurality of electric connecting pieces. The chip is provided with at least one chip functional area and a plurality of electrical contacts positioned on the periphery of the chip functional area; the packaging body is fixed on the substrate and surrounds and wraps the chip, and the packaging body is provided with at least one air chamber for accommodating the functional areas of the chips and a plurality of through holes corresponding to the electrical contacts respectively; the electric connecting pieces are respectively arranged in the through holes of the packaging body, and each electric connecting piece is provided with an inner end which is electrically connected with each electric contact and an outer end which is exposed outside the packaging body. Therefore, the processing cost of the chip packaging structure is low. In addition, the invention also provides a manufacturing method of the air chamber for protecting the chip functional area, which can reduce additional processing procedures and is beneficial to mass manufacturing.

Description

Technical Field

[0001] The present invention relates to packaging of RF filters such as surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, SAW resonators, and micro-electromechanical sensors, and in particular to a chip packaging structure and a method for manufacturing an air chamber for protecting a chip functional area. Background Art

[0002] Taiwan Patent No. I720239 discloses an embedded RF filter packaging structure and its manufacturing method. Please refer to the aforementioned patent Figure 4 (The following reference numerals are cited from the aforementioned patent case), the filter packaging structure 10 includes a first dielectric layer 18, a SAW filter 14 disposed on the first dielectric layer 18, an adhesive 24 bonded between the SAW filter 14 and the first dielectric layer 18, a dielectric packaging material 20 covering the SAW filter 14, a plurality of through holes 26 respectively penetrating the first dielectric layer 18 and the adhesive 24, and a plurality of metal interconnects 28 respectively disposed in each through hole 26. The SAW filter 14 has an active region 34, and the SAW filter 14 is bonded to the adhesive 24 with the active region 34 facing downward, so that the active region 34 is accommodated in an air cavity 32 of the adhesive 24, so that the active region 34 of the SAW filter 14 and the piezoelectric substrate (please refer to the aforementioned patent case) are connected. Figure 1 ) produces appropriate vibrations and associated sound waves.

[0003] However, when manufacturing the filter packaging structure 10, the adhesive 24 needs to be laser ablated or selectively applied to the dielectric layer 18 (e.g., inkjet) to form the air cavity 32, and the first dielectric layer 18 and the adhesive layer 24 need to be processed by laser ablation, laser drilling, plasma etching, photolithography or mechanical drilling to form the through holes 26, which makes the manufacturing method more complicated and increases the processing cost. Therefore, the filter packaging structure 10 and the manufacturing method thereof in the aforementioned patent case still have room for improvement. Summary of the invention

[0004] In view of the above shortcomings, the main purpose of the present invention is to provide a chip packaging structure with lower processing cost.

[0005] To achieve the above main purpose, the chip packaging structure of the present invention includes a substrate, a chip, a package body, and a plurality of electrical connectors. The substrate has a top surface; the chip is fixed to the top surface of the substrate, the chip has a top surface, at least one chip functional area located on the top surface, and a plurality of electrical contacts located on the top surface, and these electrical contacts are located at the periphery of at least one chip functional area; the package body is fixed to the top surface of the substrate and surrounds and covers the chip, the package body has at least one air chamber and a plurality of through holes, at least one of the air chambers accommodates at least one chip functional area of ​​the chip, and these through holes correspond to each of the electrical contacts respectively; a plurality of electrical connectors are respectively arranged in each of the through holes of the package body, and each of the electrical connectors has an inner end electrically connected to each of the electrical contacts, and an outer end exposed outside the package body.

[0006] Through the above-mentioned technical features, since the package body provided by the chip packaging structure of the present invention does not need to be processed through additional processing procedures (such as laser ablation, laser drilling, plasma etching, photolithography or mechanical drilling) to form at least one of the air chambers and these through holes one by one, the processing cost of the chip packaging structure of the present invention is relatively low.

[0007] Preferably, the package has a first molded layer and a second molded layer, the first molded layer covers the top surface of the substrate and surrounds the periphery of the chip, and the first molded layer has a plurality of through holes, the second molded layer covers a top surface of the first molded layer and each of the electrical connectors, and forms at least one air chamber between the second molded layer and the first molded layer. In this way, the package is formed by the first and second molded layers, so that the package does not need to be formed by additional processing to form the air chambers and the through holes.

[0008] Preferably, the first molded layer has a first sublayer and a second sublayer covering the first sublayer, the first sublayer covers the top surface of the substrate and surrounds the periphery of the chip, the second sublayer has a step portion, a bottom surface of the step portion is fixed to the top surface of the chip, and the step portion is penetrated by the through hole; the second molded layer covers a top surface of the second sublayer and forms at least one air chamber between the second sublayer. In this way, the first molded layer is tightly attached to the substrate and the chip through the first and second sublayers, respectively.

[0009] Preferably, the stepped portion of the second sub-layer has an inner wall surface adjacent to the bottom surface, and the inner wall surface and a bottom surface of the second molded layer surround and form at least one air chamber.

[0010] Preferably, the outer end of each of the electrical connectors is provided with a soldering pad, respectively, and the soldering pads are used to be electrically connected to an external device (such as a printed circuit board).

[0011] Another object of the present invention is to provide a method for manufacturing an air chamber for protecting a chip functional area, which can reduce additional processing steps and is conducive to mass production.

[0012] The manufacturing method of the air chamber for protecting the functional area of ​​a chip of the present invention comprises the following steps: a) fixing a plurality of chips at intervals on a substrate, each of the chips having at least one chip functional area located on the top surface thereof, and a plurality of electrical contacts located on the top surface and at the periphery of each chip functional area; b) forming a first molded layer, the first molded layer covering a top surface of the substrate and surrounding the periphery of each chip, the first molded layer having a plurality of cavities and a plurality of through holes formed by a photolithography process, the cavities corresponding to each chip functional area respectively, and the through holes corresponding to each electrical contact respectively; c) fixing a plurality of electrical contacts on the top surface of the substrate and surrounding the periphery of each chip functional area; The connectors are respectively inserted into each of the through holes; d) forming a second molded layer, the second molded layer covers a top surface of the first molded layer and each of the electrical connectors, the first and second molded layers together form a package body, the package body has a plurality of air chambers corresponding to the functional areas of each chip; e) flattening a top surface of the package body so that each of the electrical connectors has an outer end exposed outside the package body; f) forming a plurality of welding pads on the top surface of the package body, the welding pads are respectively electrically connected to the outer ends of each of the electrical connectors; and g) cutting the substrate and the package body to form a plurality of chip packaging structures.

[0013] Through the above-mentioned technical features, the manufacturing method of the present invention forms the package body through the first and second molded layers together, so that the package body does not need to be processed additionally to form these air chambers and these through holes. Moreover, the manufacturing method of the present invention can also mass-produce the chip packaging structure of the present invention, thereby reducing the manufacturing cost of the chip packaging structure of the present invention.

[0014] Preferably, between step f) and step g), there is also a step of planarizing a bottom surface of the substrate to reduce the thickness of the substrate.

[0015] Preferably, in step b), the first molded layer has a first sublayer and a second sublayer covering the first sublayer; the first sublayer covers the top surface of the substrate and surrounds the periphery of each chip, the second sublayer has a plurality of steps, a bottom surface of each step is fixed to the top surface of each chip, and each step is penetrated by the through hole; the second molded layer covers a top surface of the second sublayer. In this way, the first molded layer is tightly attached to the substrate and the chip through the first and second sublayers, respectively.

[0016] Preferably, in step b), each step of the second sub-layer has an inner wall surface adjacent to the bottom surface, and each inner wall surface surrounds and forms each cavity. Thus, by adjusting the thickness of the second sub-layer, the size of the cavities can be changed.

[0017] Preferably, in the step d), the second molded layer covers a top surface of the second sub-layer and forms each of the air chambers together with each of the inner wall surfaces of the second sub-layer.

[0018] The detailed structure, steps and features of the manufacturing method of the chip packaging structure and the gas chamber for protecting the chip functional area provided by the present invention will be described in detail in the subsequent embodiments. However, those skilled in the art should understand that these detailed descriptions and the specific embodiments listed for implementing the present invention are only used to illustrate the present invention and are not used to limit the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The chip packaging structure and the method for manufacturing the gas chamber for protecting the chip functional area provided by the present invention are further described below with reference to the embodiments and the accompanying drawings, wherein:

[0020] Figure 1 is a cross-sectional view of the chip packaging structure of the present invention;

[0021] Figure 2 It is a flow chart of the method for manufacturing the gas chamber for protecting the functional area of ​​the chip of the present invention;

[0022] Figure 3 is a cross-sectional view showing a plurality of chips fixed to a substrate at intervals;

[0023] Figure 4 Continue Figure 3 , showing the formation of a first molded layer covering the substrate;

[0024] Figure 5 Continue Figure 4 , showing that a plurality of electrical connectors are respectively inserted into each through hole;

[0025] Figure 6 Continue Figure 5 , showing the formation of a second molded layer covering the first molded layer and each electrical connector;

[0026] Figure 7 Continue Figure 6 , showing a top surface of the flattened package body so that each electrical connector has an outer end exposed outside the package body;

[0027] Figure 8 Continue Figure 7 , showing that a plurality of pads are formed on the top surface of the package;

[0028] Fig. 9 Continue Figure 8 , showing planarizing the bottom surface of a substrate to reduce the thickness of the substrate; and

[0029] Fig.10 Continue Fig. 9, showing cutting the substrate and the package body to form multiple chip package structures.

[0030] In the above drawings, the meanings of the reference numerals are as follows:

[0031] 1: Chip packaging structure;

[0032] 10: substrate;

[0033] 11: top surface;

[0034] 12: Bottom;

[0035] 20: Chip;

[0036] 21: top surface;

[0037] 22: Chip functional area;

[0038] 23: electrical contact;

[0039] 30: package body;

[0040] 34: Steps;

[0041] 35: Bottom;

[0042] 36: Inner wall;

[0043] 37: first molded layer;

[0044] 371: first sublayer;

[0045] 372: second sublayer;

[0046] 373: top surface;

[0047] 38: second molded layer;

[0048] 381: top surface;

[0049] 382: Bottom;

[0050] 40: electrical connector;

[0051] 41: inner end;

[0052] 42: outer end;

[0053] 50: welding pad;

[0054] C: air chamber;

[0055] H: through hole;

[0056] S1-S8: steps;

[0057] O: Cavity. DETAILED DESCRIPTION

[0058] First of all, it should be noted that the technical features provided by the present invention are not limited to the specific structures, uses and applications described in the embodiments. The terms used in the description are all illustrative descriptive terms that can be understood by ordinary technicians in the relevant technical field. The directional descriptive terms such as "front, top, bottom, back, left, right, top, bottom, inside, and outside" mentioned in this specification are only illustrative descriptive terms based on the normal use direction, and are not intended to limit the scope of the claims.

[0059] Please read first Figure 1 The chip package structure 1 of the present invention includes a substrate 10 , a chip 20 , a package body 30 , a plurality of electrical connectors 40 , and a plurality of pads 50 .

[0060] The substrate 10 is an integrally formed plate-like structure having a top surface 11 and a bottom surface 12 opposite to the top surface 11. In the present embodiment, the material of the substrate 10 may be one of the following materials, such as a polyimide film (eg ), polyetherimide (e.g. ), polytetrafluoroethylene (PTFE), polysulfone materials (such as ), or another polymer film, such as liquid crystal polymer (LCP).

[0061] The chip 20 may be (but not limited to) a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, or an RF filter of a SAW resonator, or a sensor of a micro-electromechanical system, etc. In this embodiment, the chip 20 takes a SAW filter as an example. The chip 20 has a top surface 21, a chip functional area 22 ( Figure 1 The chip functional area 22 is one, but not limited to one in practice), and a plurality of electrical contacts 23 located on the top surface 21. These electrical contacts 23 are located at the periphery of the chip functional area 22, and these electrical contacts 23 are all pads. The chip functional area 22 is an interdigital transducer (IDT), which is used to convert input electrical signals and sound waves. Since the IDT is a conventional SAW filter component, it is not described here.

[0062] The material of the package body 30 may be (but not limited to) a polymer material or epoxy resin. The package body 30 has a first molded layer 37, the first molded layer 37 has a first sublayer 371 and a second sublayer 372 covering the first sublayer 371, the first sublayer 371 covers the top surface 11 of the substrate 10 and surrounds the periphery of the chip 20 to protect the structure of the chip 20 from damage, the second sublayer 372 has a step portion 34, the step portion 34 has a bottom surface 35 and an inner wall surface 36 adjacent to the bottom surface 35, the second sublayer 372 is fixed to the top surface 21 of the chip 20 with the bottom surface 35 of the step portion 34, and the second sublayer 372 also has a plurality of through holes H penetrating the step portion 34, and these through holes H correspond to the electrical contacts 23 of the chip 20 respectively. The package body 30 further has a second molded layer 38, which covers the top surface 373 of the second sub-layer 372 and forms an air chamber C between the second molded layer 38 and the inner wall surface 36 of the second sub-layer 372. Since the air chamber C accommodates the chip functional area 22 of the chip 20, the number of the air chambers C depends on the number of the chip functional areas 22 ( Figure 1 There is one air chamber C in the invention, but it is not limited to one in practice).

[0063] In this embodiment, the electrical connectors 40 are metal parts (such as copper pillars) and are respectively disposed in the through holes H of the package body 30. Each electrical connector 40 has an inner end 41 electrically connected to the electrical contacts 23 of the chip 20 and an outer end 42 exposed outside the package body 30.

[0064] Each soldering pad 50 is disposed at the outer end 42 of each electrical connector 40 for electrically connecting to an external device (eg, a printed circuit board).

[0065] The above are the structural features of the chip packaging structure 1 of the present invention. The following will further describe the method for manufacturing the gas chamber for protecting the chip functional area. Figure 2 As shown, the manufacturing method of the present invention comprises the following steps:

[0066] like Figure 2 and Figure 3 In step S1, a plurality of chips 20 are fixed to the substrate 10 at intervals, each chip 20 having at least one chip functional region 22 located on its top surface 21, and a plurality of electrical contacts 23 located on the top surface 21 and at the periphery of each chip functional region 22. In this step, a layer of adhesive (not shown) is coated on the top surface 11 of the substrate 10, and then a plurality of chips 20 (four in this embodiment, which can be changed according to the actual manufacturing quantity) are adhered to the top surface 11 of the substrate 10 at intervals for fixing.

[0067] like Figure 2 and Figure 4In step S2 shown, a first molded layer 37 is formed. The first molded layer 37 covers the top surface 11 of the substrate 10 and surrounds the periphery of each chip 20. The first molded layer 37 has a plurality of cavities O and a plurality of through holes H formed by a photolithography process. These cavities O correspond to each chip functional area 22, and these through holes H correspond to each electrical contact 23.

[0068] In this step, a mold (not shown) is used to heat a packaging material (such as a polymer material or epoxy resin) to a molten state, and then the molten material is molded to form a gel-like first molded layer 37. The first molded layer 37 has a first sublayer 371 and a second sublayer 372 covering the first sublayer 371. The first sublayer 371 covers the top surface 11 of the substrate 10 and surrounds the periphery of the chip 20. The second sublayer 372 has a step portion 34. The step portion 34 has a bottom surface 35 and an inner wall surface 36 adjacent to the bottom surface 35. The bottom surface 35 of the step portion 34 is fixed to the top surface 21 of the chip 20. The inner wall surface 36 of the step portion 34 surrounds and forms an open cavity O. Each cavity O corresponds to the chip functional area 22 of each chip 20. The size of each cavity O can be adjusted by adjusting the thickness of the second sublayer 372. In addition, the second sub-layer 372 also has a plurality of through holes H penetrating the step portion 34, and these through holes H correspond to the electrical contacts 23 of the chip 20. It should be noted that the second sub-layer 372 can form these cavities O and these through holes H at one time through a photolithography process, so the processing time can be greatly reduced. The photolithography process is a common procedure in semiconductor processes, so it will not be described in detail here.

[0069] like Figure 2 and Figure 5 In step S3 , a plurality of electrical connectors 40 are respectively inserted into each through hole H, so that the inner end 41 of each electrical connector 40 is respectively electrically connected to each electrical contact 23 .

[0070] like Figure 2 and Figure 6 In step S4 shown, a second molded layer 38 is formed, and the second molded layer 38 covers a top surface 373 of the first molded layer 37 and each electrical connector 40. The first and second molded layers 37 and 38 together form a package body 30, and the package body 30 has a plurality of air chambers C corresponding to each chip functional area 22.

[0071] In this step, another mold (not shown) is used to heat a packaging material (such as a polymer material or epoxy resin) that is the same as the first molded layer 37 to a molten state, and then the molten material is molded to form a second molded layer 38 in a gel state. The second molded layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. The second molded layer 38 covers the top surface 373 of the second sub-layer 372 (that is, the top surface 373 of the first molded layer 37) and each electrical connection member 40 with the bottom surface 382, ​​so that a closed air chamber C (such as Figure 6 shown).

[0072] like Figure 2 and Figure 7 In step S5, the top surface 381 of the package body 30 is flattened so that each electrical connector 40 has an outer end 42 exposed outside the package body 30. In this step, a grinder (not shown) is used to grind and remove excess material from the top surface 381 of the package body 30 (i.e., the top surface 381 of the second molded layer 38), so that the top surface 381 of the package body 30 remains flat until the outer end 42 of each electrical connector 40 is exposed outside the package body 30.

[0073] like Figure 2 and Figure 8 In step S6, a plurality of solder pads 50 are formed on the top surface 381 of the package body 30. The solder pads 50 are respectively electrically connected to the outer ends 42 of the electrical connectors 40. In this step, the solder pads 50 may be (but not limited to) solder bumps.

[0074] like Figure 2 and Fig. 9 In step S7, the bottom surface 12 of the substrate 10 is flattened to reduce the thickness of the substrate 10. In this step, a grinder is also used to grind and remove excess material from the bottom surface 12 of the substrate 10, so that the bottom surface 12 of the substrate 10 remains flat.

[0075] like Figure 2 and Fig.10 In step S8 , the substrate 10 and the package body 30 are cut to form a plurality of chip package structures 1 , thus completing the entire processing steps.

[0076] In summary, the manufacturing method of the present invention forms the package body 30 through the first and second molded layers 37 and 38, so that the package body 30 does not need to undergo additional processing procedures (such as laser ablation, laser drilling, plasma etching, photolithography or mechanical drilling, etc.), that is, the air chambers C and the through holes H can be formed, so that the overall processing steps are relatively simple and easy to achieve, and the chip package structure 1 of the present invention has a lower processing cost. In addition, since the manufacturing method of the present invention can mass-produce the chip package structure 1 of the present invention, the manufacturing cost of the chip package structure 1 of the present invention is also reduced.

[0077] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, comprising: a substrate having a top surface; A chip fixed to the top surface of the substrate, the chip having a top surface, at least one chip functional area located on the top surface, and a plurality of electrical contacts located on the top surface, and the electrical contacts are located at the periphery of at least one chip functional area; a package body fixed to the top surface of the substrate and surrounding and encapsulating the chip, the package body having at least one air chamber and a plurality of through holes, at least one of the air chambers accommodating at least one chip functional area of ​​the chip, and the through holes corresponding to the electrical contacts respectively; and A plurality of electrical connectors are respectively arranged in each of the through holes of the package body, and each of the electrical connectors has an inner end electrically connected to each of the electrical contacts and an outer end exposed outside the package body.

2. The chip packaging structure according to claim 1, characterized in that: The package body has a first molded layer and a second molded layer, the first molded layer covers the top surface of the substrate and surrounds the periphery of the chip, and the first molded layer has a plurality of through holes, the second molded layer covers a top surface of the first molded layer and each of the electrical connectors, and forms at least one air chamber between the second molded layer and the first molded layer.

3. The chip packaging structure according to claim 2, characterized in that: The first molded layer has a first sublayer and a second sublayer covering the first sublayer, the first sublayer covers the top surface of the substrate and surrounds the periphery of the chip, the second sublayer has a step portion and a plurality of through holes, a bottom surface of the step portion is fixed to the top surface of the chip and penetrated by the plurality of through holes; the second molded layer covers a top surface of the second sublayer and forms at least one air chamber with the second sublayer.

4. The chip packaging structure according to claim 3, characterized in that: The stepped portion of the second sub-layer has an inner wall surface adjacent to the bottom surface, and the inner wall surface and a bottom surface of the second molded layer surround and form at least one air chamber.

5. The chip packaging structure according to claim 1, characterized in that: The outer end of each electrical connector is respectively provided with a welding pad.

6. A method for manufacturing an air chamber for protecting a chip functional area, comprising the following steps: a) fixing a plurality of chips at intervals on a substrate, each of the chips having at least one chip functional region located on its top surface, and a plurality of electrical contacts located on the top surface and at the periphery of each chip functional region; b) forming a first molded layer, the first molded layer covering a top surface of the substrate and surrounding the periphery of each chip, the first molded layer having a plurality of cavities and a plurality of through holes formed by a photolithography process, the cavities corresponding to each chip functional area, and the through holes corresponding to each electrical contact; c) inserting a plurality of electrical connectors into each of the through holes; d) forming a second molded layer, the second molded layer covering a top surface of the first molded layer and each of the electrical connectors, the first and second molded layers together forming a package body, the package body having a plurality of air chambers corresponding to each of the chip functional areas; e) planarizing the top surface of the package so that each of the electrical connectors has an outer end exposed outside the package; f) forming a plurality of solder pads on the top surface of the package body, wherein the solder pads are respectively electrically connected to the outer ends of the electrical connectors; and g) cutting the substrate and the package body to form a plurality of chip package structures. 7 . The manufacturing method according to claim 6 , further comprising a step of planarizing a bottom surface of the substrate to reduce a thickness of the substrate between step f) and step g).

8. The manufacturing method according to claim 6, characterized in that: In step b), the first molded layer has a first sublayer and a second sublayer covering the first sublayer; the first sublayer covers the top surface of the substrate and surrounds the periphery of each of the chips, the second sublayer has a plurality of steps and a plurality of through holes, a bottom surface of each of the steps is fixed to the top surface of each of the chips and penetrated by the plurality of through holes; the second molded layer covers a top surface of the second sublayer.

9. The manufacturing method according to claim 8, characterized in that: In the step b), each of the stepped portions of the second sub-layer has an inner wall surface adjacent to the bottom surface, and each of the inner walls surrounds and forms each of the cavities.

10. The manufacturing method according to claim 9, characterized in that: In the step b), each of the inner wall surfaces of the second sub-layer and a bottom surface of the second molded layer surround to form each of the air chambers.

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