Two-dimensional addressable VCSEL array and preparation method thereof, VCSEL chip and laser radar

Abstract

The invention relates to a two-dimensional addressable VCSEL array and a preparation method thereof, a VCSEL chip and a laser radar. The two-dimensional addressable VCSEL array comprises a plurality of VCSEL luminous points, a plurality of metal interconnection layers and a plurality of electrical access parts; part of the metal interconnection layers are arranged at intervals in the first direction and extend in the second direction, the other metal interconnection layers are arranged at intervals in the second direction and extend in the first direction, and the first direction is perpendicular to the second direction; one end of each metal interconnection layer is connected with one electrical access part, and the other end of each metal interconnection layer is correspondingly connected with positive electrodes or negative electrodes of one row or one column of VCSEL luminous points; wherein an electrical isolation area is at least formed on a leakage path between the adjacent electrical access parts.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a two-dimensional addressable VCSEL array and a preparation method thereof, a VCSEL chip and a laser radar. Background Art

[0002] A two-dimensional addressable VCSEL array is a laser emitting device that can independently control each VCSEL light-emitting point. Through an external control signal, any one or more VCSEL units in the two-dimensional addressable VCSEL array can be accurately turned on or off, thereby achieving complex beam control and pattern generation. However, the two-dimensional addressable VCSEL array in the prior art is prone to the situation where the VCSEL light-emitting points are mistakenly lit due to leakage, which greatly affects the light-emitting reliability of the two-dimensional addressable VCSEL array. Summary of the invention

[0003] Based on this, it is necessary to provide a two-dimensional addressable VCSEL array and a preparation method thereof, a VCSEL chip and a laser radar to address the problems in the prior art.

[0004] In a first aspect, the present invention provides a two-dimensional addressable VCSEL array, wherein the two-dimensional addressable VCSEL array comprises a plurality of VCSEL light-emitting points, a plurality of metal interconnection layers and a plurality of electrical access parts;

[0005] Some of the metal interconnection layers are arranged at intervals along the first direction and extend along the second direction, and the remaining metal interconnection layers are arranged at intervals along the second direction and extend along the first direction, and the first direction is perpendicular to the second direction;

[0006] One end of each of the metal interconnection layers is connected to one of the electrical access parts, and the other end is correspondingly connected to the positive electrode or the negative electrode of a row or a column of VCSEL light-emitting points;

[0007] Wherein, an electrical isolation region is formed at least on the leakage path between adjacent electrical access parts.

[0008] In one of the embodiments, the electrical isolation region is arranged along at least a portion of an outer contour of the electrical access portion.

[0009] In one embodiment, the electrical isolation region is a strip-shaped isolation region extending along the first direction or the second direction, and one end of the strip-shaped isolation region extends in a direction away from the electrical access portion.

[0010] In one embodiment, the electrical isolation region is further extended between adjacent metal interconnection layers; and / or

[0011] The electrical isolation region is arranged around the electrical access portion and the outer contour of the metal interconnection layer.

[0012] In one embodiment, there are a plurality of leakage paths of different lengths between adjacent electrical access portions, the widths of the electrical isolation regions are not completely the same at different locations, and the width is negatively correlated with the lengths of the leakage paths.

[0013] In one of the embodiments, when the two-dimensional addressable VCSEL array is powered on, the current density of the electrical access portion is greater than the current density of the metal interconnect layer.

[0014] In one of the embodiments, the VCSEL light emitting point includes a substrate and a first reflector layer, an active layer, a photoelectric limiting layer and a second reflector layer stacked on a surface of the substrate;

[0015] The first reflector layer and the second reflector layer are used to define a resonant cavity for generating standing waves, and the optoelectronic limiting layer is used to define a light-emitting area of ​​the VCSEL light-emitting point.

[0016] In one of the embodiments, the electrical isolation region includes an isolation trench and / or an implanted isolation region;

[0017] The bottom of the isolation trench exposes the surface of the first reflector layer or the substrate; the injection isolation region is located below the isolation trench, and at this time, the isolation trench exposes the surface of the first reflector layer.

[0018] In one embodiment, a first width of the isolation trench between adjacent electrical access portions is greater than a second width of the isolation trench between adjacent metal interconnect layers; and / or

[0019] A first depth of the isolation trench between adjacent electrical entry portions is greater than a second depth of the isolation trench between adjacent metal interconnection layers.

[0020] In one embodiment, a first implantation depth of the implantation isolation region between adjacent electrical access portions is greater than a second implantation depth of the implantation isolation region between adjacent metal interconnection layers; and / or

[0021] A first implantation dose of the implantation isolation region between adjacent electrical access portions is greater than a second implantation dose of the implantation isolation region between adjacent metal interconnection layers.

[0022] In a second aspect, the present invention provides a method for preparing a two-dimensional addressable VCSEL array, comprising:

[0023] Providing a substrate having a plurality of VCSEL light-emitting points formed thereon;

[0024] A plurality of metal interconnection layers and a plurality of electrical access parts are formed; some of the metal interconnection layers are arranged at intervals along the first direction and extend along the second direction, and the remaining metal interconnection layers are arranged at intervals along the second direction and extend along the first direction, and the first direction and the second direction are perpendicular; one end of each of the metal interconnection layers is respectively connected to one of the electrical access parts, and the other end is correspondingly connected to the positive electrode or the negative electrode of a row or a column of the VCSEL light-emitting points; wherein an electrical isolation region is at least formed on the leakage path between adjacent electrical access parts.

[0025] In one embodiment, providing a substrate having a plurality of VCSEL light-emitting points formed thereon comprises:

[0026] providing a substrate;

[0027] forming a first reflector layer, an active layer, a photoelectric limiting layer and a second reflector layer in sequence on the surface of the substrate;

[0028] The first reflector layer, the active layer and the second reflector layer are etched to form a mesa groove exposing a portion of the surface of the first reflector layer, wherein the mesa groove is used to divide a plurality of VCSEL light-emitting points.

[0029] In a third aspect, the present invention provides a VCSEL chip, comprising the two-dimensional addressable VCSEL array as described above.

[0030] In a fourth aspect, the present invention provides a laser radar, comprising the VCSEL chip as described above and a driving circuit for driving the VCSEL chip to operate.

[0031] The above-mentioned two-dimensional addressable VCSEL array and its preparation method, VCSEL chip and laser radar can effectively improve the isolation effect between adjacent electrical access parts by setting an electrical isolation area, thereby reducing the leakage path between adjacent electrical access parts, reducing the leakage risk between adjacent electrical access parts, and further reducing the situation where the VCSEL light-emitting points connected to the adjacent electrical access parts through the metal interconnection layer are mistakenly lit when a control signal is provided to one electrical access part, thereby improving the light-emitting reliability of the VCSEL array. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1is one of the top-down global schematic diagrams of a two-dimensional addressable VCSEL array according to an embodiment;

[0034] Figure 2 FIG2 is a second global top view schematic diagram of a two-dimensional addressable VCSEL array according to an embodiment;

[0035] Figure 3 for Figure 2 A partial schematic top view of a two-dimensional addressable VCSEL array of an embodiment;

[0036] Figure 4 The third global schematic diagram of a two-dimensional addressable VCSEL array from top view according to an embodiment;

[0037] Figure 5 is a schematic diagram of a leakage path according to an embodiment;

[0038] Figure 6 for Figure 3 A cross-sectional view of a two-dimensional addressable VCSEL array along the AA direction of an embodiment;

[0039] Figure 7 for Figure 3 A cross-sectional view of the two-dimensional addressable VCSEL array of the embodiment along the BB direction;

[0040] Figure 8 One of the flow charts of a method for preparing a two-dimensional addressable VCSEL array according to an embodiment;

[0041] Fig. 9 The second flowchart of the method for preparing a two-dimensional addressable VCSEL array according to an embodiment.

[0042] Component number description:

[0043] VCSEL light-emitting point: 100; metal interconnection layer: 200; first metal interconnection layer: 210; second metal interconnection layer: 220; electrical access part: 300; first electrical access part: 310; second electrical access part: 320; electrical isolation area: 400; isolation groove: 410; injection isolation area: 420; substrate: 10; first reflector layer: 20; active layer: 30; photoelectric confinement layer: 40; second reflector layer: 50; first passivation layer: 61; second passivation layer: 62; mesa groove: 70. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0047] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0048] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0050] The present application embodiment provides a two-dimensional addressable VCSEL array, Figure 1 FIG. 1 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the present invention. Figure 1 The two-dimensional addressable VCSEL array includes a plurality of VCSEL light-emitting points 100 , a plurality of metal interconnection layers 200 and a plurality of electrical access parts 300 .

[0051] Some metal interconnection layers 200 are arranged at intervals along the first direction and extend along the second direction, and the remaining metal interconnection layers 200 are arranged at intervals along the second direction and extend along the first direction. The first direction and the second direction may be arranged crosswise, for example, the first direction and the second direction are perpendicular. Figure 1 For example, the first direction may be the X direction, and the second direction may be the Y direction. For ease of explanation, in each embodiment of the present application, the metal interconnection layer 200 arranged at intervals along the X direction and extending along the Y direction is referred to as the first metal interconnection layer 210, and the metal interconnection layer 200 arranged at intervals along the Y direction and extending along the X direction is referred to as the second metal interconnection layer 220. Furthermore, a plurality of first metal interconnection layers 210 may be arranged at equal or unequal intervals along the X direction, and a plurality of second metal interconnection layers 220 may be arranged at equal or unequal intervals along the Y direction, which may be specifically set according to the application scenario of the two-dimensional addressable VCSEL array, and is not limited here.

[0052] One end of each metal interconnect layer 200 is connected to an electrical access portion 300, and the other end is connected to the positive electrode or negative electrode of a row or column of VCSEL light-emitting points 100. The electrical access portion 300 connected to the first metal interconnect layer 210 can be called a first electrical access portion 310, and the electrical access portion 300 connected to the second metal interconnect layer 220 can be called a second electrical access portion 320. That is, the negative electrode of a VCSEL light-emitting point 100 can be connected to the first electrical access portion 310 via the first metal interconnect layer 210, and the positive electrode of the VCSEL light-emitting point 100 can be connected to the second electrical access portion 320 via the second metal interconnect layer 220. Therefore, the negative electrodes of multiple VCSEL light-emitting points 100 in the same column can be connected to the same first metal interconnect layer 210, and the positive electrodes of multiple VCSEL light-emitting points 100 in the same row can be connected to the same second metal interconnect layer 220. The electrical access portion 300 is used to connect to an external control circuit, so as to facilitate the access of control signals of each VCSEL light-emitting point 100. The metal interconnection layer 200 is used to provide the control signal connected to the electrical connection part 300 to the connected VCSEL light-emitting point 100. The control signal is used to select the VCSEL light-emitting point 100 to emit light and control the light intensity of the VCSEL light-emitting point 100 to emit light.

[0053] The VCSEL light emitting point 100 may include multiple optical apertures, such as Figure 1 As shown, a VCSEL light emitting point 100 includes six optical apertures. The cross section of the VCSEL light emitting point 100 may be, but is not limited to, circular, elliptical, polygonal, etc. It should be noted that: Figure 1 The number and arrangement of the optical apertures in the VCSEL light-emitting point 100 are only for exemplary description and are not used to limit the protection scope of this embodiment. Moreover, the position of the VCSEL light-emitting point 100 can be set according to the arrangement position of the metal interconnection layer 200 and the electrical access part 300, which is not limited in this embodiment.

[0054] An electrical isolation region 400 is formed at least on the leakage path between adjacent electrical access portions 300. Figure 1 In the illustrated embodiment, it is taken as an example that the electrical isolation region 400 is provided between adjacent first electrical access portions 310. It is understandable that the electrical isolation region 400 may be provided only between adjacent first electrical access portions 310, or only between adjacent second electrical access portions 320, or both between adjacent first electrical access portions 310 and adjacent second electrical access portions 320, which is not limited in this embodiment.

[0055] In the related art, if the electrical isolation area 400 of the present embodiment is not provided on the leakage path between adjacent electrical input parts 300, it is difficult to achieve effective electrical isolation between adjacent electrical input parts 300. In the case where the isolation between adjacent electrical input parts 300 is insufficient, when a control signal is provided to one electrical input part 300, leakage may occur to the adjacent electrical input part 300, causing the connected VCSEL light-emitting point 100 to be mistakenly lit. Figure 1 For example, when the isolation between adjacent electrical input parts 300 is insufficient, when a control signal is provided to the electrical input part C2, electricity may leak to at least one of the adjacent electrical input parts C1 and C3, thereby causing the VCSEL light-emitting point 100 connected to the electrical input parts C1 and C3 to be mistakenly lit.

[0056] In the embodiment of the application, by providing the electrical isolation region 400, the isolation effect between adjacent electrical access parts 300 can be effectively improved, thereby reducing the leakage path between adjacent electrical access parts 300, reducing the leakage risk between adjacent electrical access parts 300, and further reducing the situation where the VCSEL light-emitting point 100 connected to the adjacent electrical access part 300 through the metal interconnection layer 200 is mistakenly lit when providing a control signal to one electrical access part 300, thereby improving the light-emitting reliability of the VCSEL array.

[0057] Continue to refer Figure 1 In one embodiment, the electrical isolation region 400 is arranged along at least a portion of the outer contour of the electrical access portion 300. The electrical isolation region 400 may surround the outer contour of the electrical access portion 300 except the side facing the metal interconnection layer 200, so as to better isolate the leakage path at the end of the adjacent electrical access portion 300.

[0058] Further, Figure 2 FIG2 is a second schematic diagram of a two-dimensional addressable VCSEL array viewed from above according to an embodiment of the present invention. Figure 3 for Figure 2 A partial schematic top view of a two-dimensional addressable VCSEL array of an embodiment, Figure 3 Shows Figure 2 The part in the dotted box, combined with reference Figure 2 and Figure 3In one embodiment, the electrical isolation region 400 is arranged around the outer contours of the electrical access portion 300 and the metal interconnection layer 200. Specifically, there is a leakage path not only between adjacent electrical access portions 300, but also between adjacent metal interconnection layers 200. Therefore, even if the leakage path between adjacent electrical access portions 300 is isolated by the electrical isolation region 400, when a metal interconnection layer 200 transmits a control signal, the leakage path between adjacent metal interconnection layers 200 may also cause the VCSEL light-emitting point 100 connected to the adjacent metal interconnection layer 200 to be mistakenly lit.

[0059] Figure 4 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the present invention. Figure 4 In one embodiment, the electrical isolation region 400 is a strip-shaped isolation region extending along the first direction or the second direction, and one end of the strip-shaped isolation region extends in a direction away from the electrical access portion 300 . Figure 4 The electrical isolation region 400 shown is a strip-shaped isolation region extending along the Y direction. Specifically, the top view shape of the strip-shaped isolation region can be an "I" shape (such as Figure 4 ), or may be in a "Y" shape (not shown), which is not limited in the present application. Furthermore, when space in the two-dimensional addressable VCSEL array allows, the end of the strip-shaped isolation region away from the metal interconnection layer 200 may protrude beyond the end of the electrical access portion 300 away from the metal interconnection layer 200, so as to better isolate the leakage path at the end of the adjacent electrical access portion 300. When the strip-shaped isolation region is in a "Y" shape, the bifurcation point of the strip-shaped isolation region is at least flush with one end of the electrical access portion 300. In one embodiment, the end of the strip-shaped isolation region away from the metal interconnection layer 200 may also be flush with the end of the electrical access portion 300 away from the metal interconnection layer 200, so as to save space in the two-dimensional addressable VCSEL array.

[0060] Further, continue to refer to Figure 4 , the electrical isolation region 400 is also extended and arranged between adjacent metal interconnection layers 200. Specifically, there is a leakage path not only between adjacent electrical access parts 300, but also between adjacent metal interconnection layers 200. Therefore, even if the leakage path between adjacent electrical access parts 300 is isolated by the electrical isolation region 400, when a metal interconnection layer 200 transmits a control signal, the leakage path between adjacent metal interconnection layers 200 may also cause the VCSEL light-emitting point 100 connected to the adjacent metal interconnection layer 200 to be mistakenly lit.

[0061] Figure 5 is a schematic diagram of a leakage path of an embodiment, Figure 5Take two adjacent electrical access parts C1 and C2 as an example, refer to Figure 5 In one embodiment, there are multiple leakage paths of different lengths between adjacent electrical input parts 300 . Figure 5 Two leakage paths a and b are shown, where leakage path a is shorter than leakage path b. The length of the leakage path can characterize the difficulty of leakage or the magnitude of leakage risk to a certain extent. The longer the leakage path, the lower the risk of leakage, and the shorter the leakage path, the greater the risk of leakage.

[0062] The cross-sectional dimensions of the electrical isolation region 400 are not exactly the same at each location, and the cross-sectional dimensions are negatively correlated with the length of the leakage path. The cross-sectional dimensions refer to the dimensions of the cross section of the electrical isolation region 400 in a plane perpendicular to the extension direction, and the cross-sectional dimensions include the transverse dimensions and longitudinal dimensions of the cross section. Optionally, the transverse dimensions of the cross sections of the electrical isolation region 400 may be different, or the longitudinal dimensions of the cross sections of the electrical isolation region 400 may be different, which is not limited here. Among them, the transverse dimension may be referred to as the width of the electrical isolation region 400, and the longitudinal dimension may be referred to as the thickness or depth of the electrical isolation region 400. The larger the cross-sectional dimensions of the electrical isolation region 400, the better the isolation effect, which can reduce the risk of leakage to a greater extent. Therefore, for leakage paths of different lengths, electrical isolation regions 400 with different cross-sectional dimensions are set on the leakage path, so that different leakage paths can be isolated more accurately.

[0063] Furthermore, a simulation method can be used to analyze the two-dimensional addressable VCSEL array without the electrical isolation region 400 to determine the leakage paths in the two-dimensional addressable VCSEL array and the leakage current distribution on each leakage path. Based on this, the cross-sectional size of the electrical isolation region 400 can be quantitatively set according to the current value of the leakage current of each leakage path.

[0064] In one embodiment, the width of the electrical isolation region 400 is not exactly the same at all locations, and the width is negatively correlated with the length of the leakage path. For example, if the leakage path a is shorter than the leakage path b, the third width of the intersection of the electrical isolation region 400 and the leakage path a can be set to be greater than the fourth width of the intersection of the electrical isolation region 400 and the leakage path a. The junction of the electrical isolation regions 400 of different widths can be set in a stepped manner or in a Figure 5 The gradient setting shown is not limited here. For leakage paths of different lengths, electrical isolation regions 400 of different widths are set on the leakage paths, which can more accurately isolate different leakage paths, reduce the situation where the VCSEL light-emitting point 100 is mistakenly lit, and reduce the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0065] In one of the embodiments, the thickness of the electrical isolation region 400 is not exactly the same at all places, and the thickness is negatively correlated with the length of the leakage path. For example, if the leakage path a is shorter than the leakage path b, the third thickness of the intersection of the electrical isolation region 400 and the leakage path a can be set to be greater than the fourth thickness of the intersection of the electrical isolation region 400 and the leakage path a. Among them, the junction of the electrical isolation regions 400 of different thicknesses can be set in a stepped manner or in a gradual manner, which is not limited here. For leakage paths of different lengths, electrical isolation regions 400 of different thicknesses are set on the leakage paths, which can isolate different leakage paths more accurately, reduce the situation where the VCSEL light-emitting point 100 is mistakenly lit, and reduce the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0066] Figure 6 for Figure 3 A cross-sectional view of a two-dimensional addressable VCSEL array along the AA direction of an embodiment, Figure 7 for Figure 3 A cross-sectional view of a two-dimensional addressable VCSEL array along the BB direction of the embodiment, combined with reference Figure 6 and Figure 7 In one embodiment, adjacent VCSEL light-emitting points 100 are separated by mesa grooves 70. The VCSEL light-emitting point 100 includes a substrate 10 and a first reflector layer 20, an active layer 30, a photoelectric limiting layer 40 and a second reflector layer 50 stacked on the surface of the substrate 10. The first reflector layer 20 and the second reflector layer 50 are used to define a resonant cavity for generating standing waves, and the photoelectric limiting layer 40 is used to define a light-emitting area of ​​the VCSEL light-emitting point 100.

[0067] The active layer 30 includes a quantum well. The material of the active layer 30 includes one or more of AlInGaAs (e.g., AlInGaAs, GaAs, AlGaAs, and InGaAs), InGaAsP (e.g., InGaAsP, GaAs, InGaAs, GaAsP, and GaP), GaAsSb (e.g., GaAsSb, GaAs, and GaSb), InGaAsN (e.g., InGaAsN, GaAs, InGaAs, GaAsN, and GaN), or AlInGaAsP (e.g., AlInGaAsP, AlInGaAs, AlGaAs, InGaAs, InGaAsP, GaAs, InGaAs, GaAsP, and GaP).

[0068] The photoelectric confinement layer 40 may include any one of an air column type photoelectric confinement layer, an oxidation confinement type photoelectric confinement layer, an ion implantation type photoelectric confinement layer, and a tunnel junction type photoelectric confinement layer. Among them, the oxidation confinement type photoelectric confinement layer includes an unoxidized region of AlGaAs material with a high aluminum component and an oxidized region of aluminum oxide material, the oxidized region is located outside the unoxidized region, and the unoxidized region forms a light-emitting region for effective current injection. When the current enters, the current can only flow to the active layer 30 through the opening in the photoelectric confinement layer 40, thereby achieving the limitation of the current injection path and the optical mode field. Furthermore, the AlGaAs layer with a high aluminum component can be converted into aluminum oxide through a selective oxidation process to form an unoxidized region on the periphery.

[0069] The first reflector layer 20 and the second reflector layer 50 have opposite conductivity types, that is, one is N-type doped and the other is P-type doped. For example, the first reflector layer 20 is an N-type layer and the second reflector layer 50 is a P-type layer.

[0070] The first reflector layer 20 includes a first Bragg reflector and a first conductive layer. The first Bragg reflector is located on the substrate 10. The first conductive layer has the same conductivity type as the first Bragg reflector and is located on the top surface of the first Bragg reflector away from the substrate 10. Exemplarily, the first Bragg reflector includes a first AlGaAs layer and a second AlGaAs layer that are alternately stacked and have the same doping type. The first AlGaAs layer and the second AlGaAs layer both contain aluminum elements, and the content of the aluminum element in the first AlGaAs layer is greater than the content of the aluminum element in the second AlGaAs layer, so that the first AlGaAs layer and the second AlGaAs layer have different refractive indices. The mesa groove 70 exposes a portion of the surface of the first conductive layer, the active layer 30 is located on the first conductive layer, and the bottom surface of the first metal interconnect layer 210 contacts the exposed portion of the surface of the first conductive layer. The material of the first conductive layer includes a doped semiconductor to achieve ohmic contact between the first Bragg reflector and the first metal interconnect layer 210.

[0071] The second reflector layer 50 includes a second Bragg reflector and a second conductive layer. The second Bragg reflector is located on the top surface of the active layer 30 away from the substrate 10. The second conductive layer has the same conductivity type as the second Bragg reflector and is located on the top surface of the second Bragg reflector away from the substrate 10. Exemplarily, the second Bragg reflector includes a third AlGaAs layer and a fourth AlGaAs layer that are alternately stacked and have the same doping type. The third AlGaAs layer and the fourth AlGaAs layer both contain aluminum elements, and the content of the aluminum element in the third AlGaAs layer is greater than the content of the aluminum element in the fourth AlGaAs layer, so that the third AlGaAs layer and the fourth AlGaAs layer have different refractive indices. The bottom of the second metal interconnect layer 220 contacts the top surface of the second conductive layer. The material of the second conductive layer includes a doped semiconductor to achieve ohmic contact between the second Bragg reflector and the second metal interconnect layer 220.

[0072] Continue to refer Figure 6 and Figure 7 In one embodiment, the electrical isolation region 400 includes an isolation groove 410. The bottom of the isolation groove 410 exposes the surface of the first reflector layer 20 or the substrate 10. Specifically, the isolation groove 410 is located below the mesa groove 70 and communicates with the mesa groove 70, that is, the isolation groove 410 is located between the first reflector layers 20 of adjacent VCSEL units. The isolation groove 410 is used to achieve electrical isolation between the first reflector layers 20 of two adjacent VCSEL units. Exemplarily, the bottom of the isolation groove 410 is between the bottom of the mesa groove 70 and the top surface of the substrate 10, that is, the bottom of the isolation groove 410 is between the bottom of the mesa groove 70 and the top surface of the substrate 10 forming the first reflector layer 20. Among them, the distance between the bottom of the isolation groove 410 and the top surface of the first reflector layer 20 is greater than or equal to 2 / 3 of the thickness of the first reflector layer 20. In another exemplary embodiment, the bottom of the isolation trench 410 is between the bottom of the mesa trench 70 and the bottom surface of the substrate 10 , that is, the isolation trench 410 is opened into the substrate 10 , and the bottom surface of the substrate 10 is arranged opposite to the top surface of the substrate 10 .

[0073] In one embodiment, when the two-dimensional addressable VCSEL array is powered on, the current density of the electrical access portion 300 is greater than the current density of the metal interconnect layer 200. Specifically, the electrical connection portion is used as a connection structure between the two-dimensional addressable VCSEL array and the external control circuit. Therefore, improving the current carrying capacity of the electrical access portion 300 can enable it to carry a larger current density, so as to ensure that the electrical access portion 300 has good electrical connection performance, thereby improving the reliability of the two-dimensional addressable VCSEL array.

[0074] In one embodiment, if Figure 2As shown, in the case where the electrical isolation region 400 is also extended and arranged between adjacent metal interconnection layers 200, the first width of the isolation trench 410 located between adjacent electrical access portions 300 is greater than the second width of the isolation trench 410 located between adjacent metal interconnection layers 200. It can be understood that since the current density of the electrical access portion 300 is greater than the current density of the metal interconnection layer 200, the density of carriers (electrons and holes) in the film layer near the electrical access portion 300 will also be higher, which means that more carriers move, making it easier for these carriers to generate leakage current during drift and diffusion. Therefore, for the isolation trenches 410 between different structures, setting isolation trenches 410 of different widths can more accurately isolate different leakage paths, reduce the situation where the VCSEL light-emitting point 100 is mistakenly lit, and reduce the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0075] In one embodiment, if Figure 2 As shown, in the case where the electrical isolation region 400 is also extended and arranged between adjacent metal interconnection layers 200, the first depth of the isolation trench 410 located between adjacent electrical access portions 300 is greater than the second depth of the isolation trench 410 located between adjacent metal interconnection layers 200. It can be understood that since the current density of the electrical access portion 300 is greater than the current density of the metal interconnection layer 200, the density of carriers (electrons and holes) in the film layer near the electrical access portion 300 will also be higher, which means that more carriers move, making it easier for these carriers to generate leakage current during drift and diffusion. Therefore, for the isolation trenches 410 between different structures, setting isolation trenches 410 of different depths can more accurately isolate different leakage paths, reduce the situation where the VCSEL light-emitting point 100 is mistakenly lit, and reduce the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0076] Continue to refer Figure 6 and Figure 7In one embodiment, the electrical isolation region 400 includes an isolation trench 410 and an implantation isolation region 420. The bottom of the isolation trench 410 exposes the surface of the first reflector layer 20 or the substrate 10. The bottom of the isolation trench 410 exposes the surface of the first reflector layer 20 or the substrate 10. The implantation isolation region 420 is located below the isolation trench 410, and the isolation trench 410 at this time exposes the surface of the first reflector layer 20. Specifically, the isolation trench 410 and the implantation isolation region 420 are both located between the first reflector layers 20 of adjacent VCSEL units. The isolation trench 410 is located below the mesa trench 70 and is connected to the mesa trench 70, and the implantation isolation region 420 is located below the isolation trench, and the implantation isolation region 420 is formed by ion implantation of the first reflector layer 20 at the bottom of the isolation trench 410. The isolation trench 410 and the implantation isolation region 420 are used to jointly realize the electrical isolation between the first reflector layers 20 of two adjacent VCSEL units.

[0077] In one embodiment, if Figure 2 As shown, in the case where the electrical isolation region 400 is also extended and arranged between adjacent metal interconnection layers 200, the first injection depth of the injection isolation region 420 located between adjacent electrical access parts 300 is greater than the second injection depth of the injection isolation region 420 located between adjacent metal interconnection layers 200. It can be understood that since the current density of the electrical access part 300 is greater than the current density of the metal interconnection layer 200, the density of carriers (electrons and holes) in the film layer near the electrical access part 300 will also be higher, which means that more carriers move, making it easier for these carriers to generate leakage current during drift and diffusion. Therefore, for the isolation trenches 410 between different structures, injection isolation regions 420 with different injection depths are set, which can more accurately isolate different leakage paths, reduce the situation where the VCSEL light-emitting point 100 is mistakenly lit, and reduce the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0078] In one embodiment, if Figure 2As shown, in the case where the electrical isolation region 400 is also extended and arranged between adjacent metal interconnection layers 200, the first implantation dose of the implantation isolation region 420 located between adjacent electrical access portions 300 is greater than the second implantation dose of the implantation isolation region 420 located between adjacent metal interconnection layers 200. It can be understood that since the current density of the electrical access portion 300 is greater than the current density of the metal interconnection layer 200, the density of carriers (electrons and holes) in the film layer near the electrical access portion 300 will also be higher, which means that more carriers move, making it easier for these carriers to generate leakage current during drift and diffusion. Therefore, for the isolation trenches 410 between different structures, implantation isolation regions 420 with different implantation doses are set, so that different leakage paths can be isolated more accurately, the situation where the VCSEL light-emitting point 100 is mistakenly lit can be reduced, and the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array can be reduced.

[0079] The present application also provides a method for preparing a two-dimensional addressable VCSEL array. Figure 8 FIG. 1 is a flow chart of a method for preparing a two-dimensional addressable VCSEL array according to an embodiment of the present invention. Figure 8 The method for preparing a two-dimensional addressable VCSEL array includes step 802 and step 804.

[0080] Step 802 , providing a substrate 10 having a plurality of VCSEL light emitting points 100 formed thereon.

[0081] The material of the substrate 10 is a low-doped III-V compound, where the III-V compound refers to a compound including a III-group element and a V-group element, such as GaAs.

[0082] Step 804 , forming a plurality of metal interconnection layers 200 and a plurality of electrical access portions 300 .

[0083] Part of the metal interconnection layers 200 are arranged at intervals along the first direction and extend along the second direction, and the remaining metal interconnection layers 200 are arranged at intervals along the second direction and extend along the first direction. The first direction is perpendicular to the second direction. One end of each metal interconnection layer 200 is respectively connected to an electrical access portion 300, and the other end is correspondingly connected to the positive electrode or negative electrode of a row or column of VCSEL light-emitting points 100. An electrical isolation region 400 is at least formed on the leakage path between adjacent electrical access portions 300. Exemplarily, the metal interconnection layer 200 is formed by electroplating.

[0084] In the embodiment of the application, by providing the electrical isolation region 400, the isolation effect between adjacent electrical access parts 300 can be effectively improved, thereby reducing the leakage path between adjacent electrical access parts 300, reducing the leakage risk between adjacent electrical access parts 300, and further reducing the situation where the VCSEL light-emitting point 100 connected to the adjacent electrical access part 300 through the metal interconnection layer 200 is mistakenly lit when providing a control signal to one electrical access part 300, thereby improving the light-emitting reliability of the prepared VCSEL array.

[0085] In one embodiment, the step of providing a substrate 10 formed with a plurality of VCSEL light-emitting points 100 includes the following steps: providing a substrate 10, and sequentially forming a first reflector layer 20, an active layer 30, a photoelectric limiting layer 40, and a second reflector layer 50 on the surface of the substrate 10. Etching the first reflector layer 20, the active layer 30, and the second reflector layer 50 to form a mesa groove 70 exposing a portion of the surface of the first reflector layer 20. The first reflector layer 20, the active layer 30, the photoelectric limiting layer 40, and the second reflector layer 50 can be collectively referred to as an epitaxial layer, and a mesa groove is formed by photolithography and etching the front side of the epitaxial layer, and the mesa groove 70 exposes a portion of the surface of the first reflector layer 20 and separates adjacent mesas. That is, the mesa groove 70 is used to divide a plurality of VCSEL light-emitting points 100.

[0086] In one embodiment, taking the case where the electrical isolation region 400 is disposed between adjacent first electrical access portions 310 as an example, after forming the mesa groove 70, the first metal interconnection layer 210 can be formed on the exposed surface of the first reflector layer 20, the sidewall of the mesa groove 70, and the surface of the second reflector layer 50, and the first electrical access portion 310 can be formed on the surface of the first metal interconnection layer 210. The first metal interconnection layer 210 is electrically connected to the first reflector layer 20, respectively.

[0087] In one embodiment, before forming the first metal interconnection layer 210, ion implantation is further performed on the first reflector layer 20 exposed by the isolation trench 410 to form an implantation isolation region 420 in the first reflector layer 20. The orthographic projection of the implantation isolation region 420 on the substrate 10 falls within the orthographic projection of the isolation trench 410 on the substrate 10. The implantation isolation region 420 formed by ion implantation is a high resistance / insulation region, thereby strengthening the electrical isolation between adjacent electrical access portions 300.

[0088] Fig. 9 FIG. 2 is a flow chart of a method for preparing a two-dimensional addressable VCSEL array according to an embodiment of the present invention. Fig. 9 In one embodiment, the method for preparing a two-dimensional addressable VCSEL array includes steps 902 to 922.

[0089] Step 902 , providing a substrate 10 .

[0090] Step 904 , forming a first reflector layer 20 , an active layer 30 , a photoelectric confinement layer 40 and a second reflector layer 50 in sequence on the surface of the substrate 10 .

[0091] Step 906 , etching the first reflector layer 20 , the active layer 30 , and the photoelectric confinement layer 40 to form a mesa groove 70 exposing a portion of the surface of the first reflector layer 20 .

[0092] Step 908 , etching the first reflector layer 20 exposed by the mesa trench 70 to form an isolation trench 410 .

[0093] In step 910 , ion implantation is performed on the first reflector layer 20 exposed by the isolation trench 410 to form an implantation isolation region 420 in the first reflector layer 20 .

[0094] Step 912 , forming a first passivation layer 61 on the surface of the first reflector layer 20 away from the substrate 10 , the sidewall of the isolation trench 410 , and the surface of the second reflector layer 50 away from the substrate 10 .

[0095] Step 914 , forming a first metal interconnection layer 210 on the exposed surface of the first reflector layer 20 and the exposed surface of the first passivation layer 61 .

[0096] Step 916 , forming a first electrical access portion 310 on a portion of the surface of the first metal interconnection layer 210 .

[0097] Step 918 , forming a second passivation layer 62 on the exposed surface of the first metal interconnection layer 210 and the exposed surface of the first passivation layer 61 .

[0098] The second passivation layer 62 can protect the first metal interconnection layer 210 to prevent it from being oxidized or having electrochemical effects.

[0099] Step 920 , forming openings in the first passivation layer 61 and the second passivation layer 62 , and forming a second metal interconnection layer 220 in the openings.

[0100] The second metal interconnection layer 220 is electrically connected to the second reflector layer 50 , the opening is used to expose a portion of the surface of the second reflector layer 50 , and the polarity of the second metal interconnection layer 220 is opposite to that of the first electrode.

[0101] Step 922 , forming a second electrical access portion 320 on a portion of the surface of the second metal interconnection layer 220 .

[0102] In one embodiment, the method for preparing a two-dimensional addressable VCSEL array further includes the following steps: thinning the back side of the substrate 10, and depositing a back metal on the thinned substrate 10. The back side of the substrate 10 (the back side of the wafer) is the side of the substrate 10 that is away from the first reflector layer 20.

[0103] It should be understood that, although the steps in each flowchart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in each flowchart may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0104] The embodiment of the present application further provides a VCSEL chip, comprising the two-dimensional addressable VCSEL array as described above. In one embodiment of the present application, the chip is a two-dimensional addressable vertical cavity surface emitting laser chip.

[0105] An embodiment of the present application also provides a laser radar, including a transmitting end and a receiving end, the transmitting end includes the aforementioned two-dimensional addressable vertical cavity surface emitting laser chip as a light source, a driving circuit for driving the chip to work, and a deflection module for adjusting the field of view (FOV) of the laser radar, etc., and the receiving end includes a photosensitive chip, etc.

[0106] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0107] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A two-dimensional addressable VCSEL array, characterized in that: The two-dimensional addressable VCSEL array includes a plurality of VCSEL light-emitting points, a plurality of metal interconnection layers and a plurality of electrical access parts; Some of the metal interconnection layers are arranged at intervals along the first direction and extend along the second direction, and the remaining metal interconnection layers are arranged at intervals along the second direction and extend along the first direction, and the first direction is perpendicular to the second direction; One end of each of the metal interconnection layers is connected to one of the electrical access parts, and the other end is correspondingly connected to the positive electrode or the negative electrode of a row or a column of VCSEL light-emitting points; Wherein, an electrical isolation region is formed at least on the leakage path between adjacent electrical access parts.

2. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: The electrical isolation region is arranged along at least a portion of the outer contour of the electrical access portion.

3. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: The electrical isolation region is a strip-shaped isolation region extending along the first direction or the second direction, and one end of the strip-shaped isolation region extends in a direction away from the electrical access portion.

4. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: The electrical isolation region is also extended between adjacent metal interconnection layers; and / or The electrical isolation region is arranged around the electrical access portion and the outer contour of the metal interconnection layer.

5. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: There are a plurality of leakage paths of different lengths between adjacent electrical access portions, the widths of the electrical isolation regions are not completely the same at different locations, and the width is negatively correlated with the lengths of the leakage paths.

6. The two-dimensional addressable VCSEL array according to claim 1, characterized in that: When the two-dimensional addressable VCSEL array is powered on, the current density of the electrical access portion is greater than the current density of the metal interconnection layer.

7. The two-dimensional addressable VCSEL array according to any one of claims 1 to 6, characterized in that: The VCSEL light-emitting point comprises a substrate and a first reflector layer, an active layer, a photoelectric limiting layer and a second reflector layer stacked on the surface of the substrate; The first reflector layer and the second reflector layer are used to define a resonant cavity for generating standing waves, and the optoelectronic limiting layer is used to define a light-emitting area of ​​the VCSEL light-emitting point.

8. The two-dimensional addressable VCSEL array according to claim 7, characterized in that: The electrical isolation region includes an isolation trench and / or an implanted isolation region; The bottom of the isolation trench exposes the surface of the first reflector layer or the substrate; The implantation isolation region is located below the isolation trench, and the isolation trench at this time exposes the surface of the first reflector layer.

9. The two-dimensional addressable VCSEL array according to claim 8, characterized in that: A first width of the isolation trench between adjacent electrical access portions is greater than a second width of the isolation trench between adjacent metal interconnection layers; and / or A first depth of the isolation trench between adjacent electrical entry portions is greater than a second depth of the isolation trench between adjacent metal interconnection layers.

10. The two-dimensional addressable VCSEL array according to claim 8, characterized in that: A first implantation depth of the implantation isolation region between adjacent electrical access portions is greater than a second implantation depth of the implantation isolation region between adjacent metal interconnection layers; and / or A first implantation dose of the implantation isolation region between adjacent electrical access portions is greater than a second implantation dose of the implantation isolation region between adjacent metal interconnection layers.

11. A method for preparing a two-dimensional addressable VCSEL array, characterized in that: include: Providing a substrate having a plurality of VCSEL light-emitting points formed thereon; forming a plurality of metal interconnection layers and a plurality of electrical access portions; Some metal interconnection layers are arranged at intervals along the first direction and extend along the second direction, and the remaining metal interconnection layers are arranged at intervals along the second direction and extend along the first direction, and the first direction and the second direction are perpendicular; one end of each of the metal interconnection layers is respectively connected to one of the electrical access parts, and the other end is correspondingly connected to the positive electrode or the negative electrode of a row or a column of the VCSEL light-emitting points; wherein an electrical isolation region is at least formed on the leakage path between adjacent electrical access parts.

12. The method for preparing a two-dimensional addressable VCSEL array according to claim 11, characterized in that: The method of providing a substrate having a plurality of VCSEL light-emitting points formed thereon comprises: providing a substrate; forming a first reflector layer, an active layer, a photoelectric limiting layer and a second reflector layer in sequence on the surface of the substrate; The first reflector layer, the active layer and the second reflector layer are etched to form a mesa groove exposing a portion of the surface of the first reflector layer, wherein the mesa groove is used to divide a plurality of VCSEL light-emitting points.

13. A VCSEL chip, characterized in that: The method comprises a two-dimensional addressable VCSEL array as claimed in any one of claims 1 to 10.

14. A laser radar, characterized in that: It comprises the VCSEL chip as claimed in claim 13 and a driving circuit for driving the VCSEL chip to operate.

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