Synchronized grid connection method for network-forming type energy storage system

Abstract

The invention relates to a synchronous grid connection method for a network-forming type energy storage system, and the method comprises the steps: collecting the three-phase voltages of an upper port and a lower port of a grid connection switch through an off-grid and grid connection controller, calculating the electrical angles of the three-phase voltages of the upper port and the lower port and the difference value, and processing and adjusting the difference value into a stable value; an intelligent real-time approximation algorithm is adopted to process the electrical angle difference value and then change the electrical angle difference value into an angular frequency adjustment value, and the angular frequency adjustment value is sent to an optical fiber receiving port of the energy storage converter through an optical fiber output port; the energy storage converter is supplied to virtual synchronous machine control, and the output voltage frequency and phase of the energy storage converter are adjusted; and finally, when the phase angle difference between the voltage of the upper port and the voltage of the lower port of the grid-connected switch is smaller than 2 degrees, the off-grid and grid-connected controller sends a synchronization completion signal, and the upper computer closes the grid-connected switch through control. According to the method, the frequency difference can be rapidly converged within 1s actively, the output frequency and phase of the energy storage system can be adjusted actively, and large power grid parameters can be locked rapidly.

Description

Technical Field

[0001] The invention belongs to the technical field of power grid operation control, and in particular to a synchronous grid-connected method for a grid-type energy storage system. Background Art

[0002] With the maturity of grid-type energy storage inverter technology, grid-type energy storage inverters are used to establish off-grid isolated grids or to provide support capabilities in parallel with large power grids. In addition, when a large power grid fails, the grid-type energy storage system can operate independently. When the power grid is restored, it needs to be reconnected to the large power grid. In this process, the grid-type energy storage system needs to synchronize the voltage frequency, phase, and amplitude with the large power grid. When the grid connection conditions are met, it can be connected to the large power grid stably and reliably. At present, the method for achieving synchronization is basically to use the frequency difference between the energy storage side grid and the large power grid, passively wait until the phase difference between the two reaches the requirement, and then perform the closing operation in a certain synchronization window. This method is prone to the disadvantages of inaccurate synchronization, small synchronization window, and long synchronization waiting time. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a synchronous grid-connected method for a grid-type energy storage system, which can maintain the stable operation of the power grid, can actively achieve rapid convergence of the frequency difference within 1 second, actively adjust the frequency and phase of the output of the energy storage system, and quickly lock the parameters of the large power grid. It has a long synchronization window, and the grid-connected switch can be closed at any time, and the current and voltage impact at the moment of closing the switch is very small.

[0004] The present invention solves the technical problem by adopting the following technical solutions:

[0005] A synchronous grid-connected method for a grid-connected energy storage system comprises the following steps:

[0006] Step 1: The off-grid controller collects the three-phase voltages of the upper and lower ports of the grid-connected switch, and calculates the electrical angles of the three-phase voltages of the upper and lower ports through two phase-locked loops of the DSP;

[0007] Step 2: In the FPGA of the parallel controller, the electrical angles of the upper and lower port voltages calculated by the phase-locked loop are calculated, and the difference is processed and adjusted to a stable value;

[0008] Step 3: Using an intelligent real-time approximation algorithm, the electrical angle difference is processed and converted into an angular frequency adjustment value. When the off-grid controller receives a synchronization start command from the host computer, the angular frequency adjustment value is sent to the optical fiber receiving port of the energy storage converter through the optical fiber output port;

[0009] Step 4: The energy storage converter receives the angular frequency adjustment value through the optical fiber receiving port and sends it to the virtual synchronous machine control to adjust the output voltage frequency and phase of the energy storage converter;

[0010] Step 5: When the phase angle difference between the upper and lower port voltages of the grid-connected switch is less than 2°, the off-grid controller sends a synchronization completion signal, and the host computer controls the grid-connected switch to close.

[0011] Moreover, the specific implementation method of step 1 is: the upper voltage electrical angle FIPU and the lower voltage electrical angle FIPD are input to the subtractor A1 for subtraction to obtain the electrical angle difference, the electrical angle difference and 16383 are input to the adder A2 to add the electrical angle difference by 16383, the result of the adder A2 is input to the delay operator A3 for a delay of 25ns for an FPGA clock cycle, the electrical angle difference and 0 are input to the adder A4, the electrical angle difference obtained by the subtractor A1 is added by 0, the clock is kept aligned, and the result of the adder A4 is input to the delay operator A5 for a delay of 25ns for an FPGA clock cycle;

[0012] The upper voltage electrical angle FIPU and 0 are input to an adder A6 with an enable function, and 0 is added to the upper voltage electrical angle. The result of the adder A6 and 0 are input to an adder A7 with an enable function, and 0 is added to the result of the adder A6. The result of the adder A7 and K1 are input to a comparison operator A8, and the result of the adder A7 is compared with K1. When the output of the adder A7 is greater than K1, A8 outputs 1. The result of the adder A7 and K2 are input to a comparison operator A9, and the result of the adder A7 is compared with K2. When the output of the adder A7 is less than K2, the comparison operator A9 outputs 1. The results of the comparison operators A8 and A9 are input to an AND logic operator A10, and the results of the comparison operators A8 and A9 are ANDed. When the results of the comparison operators A8 and A9 are both 1, the AND logic operator A10 outputs 1, and the output is 0 in other cases.

[0013] The lower port voltage electrical angle FIPD and 0 are input to the adder A11 with an enable function, and the lower port voltage electrical angle is added with 0. The result of the adder A11 and 0 are input to the adder A12 with an enable function, and the result of the adder A11 is added with 0. The result of the adder A12 and K1 are input to the comparison operator A13, and the result of the adder A12 is compared with K1. When the output of the adder A12 is greater than K1, the output of A13 is 1, and the adder A1 The result of 2 and K2 are input to the comparison operator A13, and the result of the adder A12 is compared with K2. When the output of the adder A12 is less than K2, the comparison operator A13 outputs 1. The results of the comparison operators A13 and A14 are input to the AND logic operator A15, and the results of the comparison operators A13 and A14 are ANDed. When the results of the comparison operators A13 and A14 are both 1, the AND logic operator A15 outputs 1, and the output is 0 in other cases.

[0014] The results of AND logic operator A10 and AND logic operator A15 are input to RS flip-flop A16. When S=1, the output is 1, and when R=1, the output is 0. In other states, the flip-flop maintains the current state. When the result of AND logic operator A15 is 1, the output of RS flip-flop A16 is 1; when the result of AND logic operator A10 is 1, the output of RS flip-flop A16 is 0.

[0015] The results of delay operator A3, delay operator A5 and RS trigger A16 are input to selection switch A17. When the output of RS trigger A16 is 1, selection switch A17 selects the output result of delay operator A5. When the output result of RS trigger A16 is 0, selection switch A17 selects the output result of delay operator A3. The result of selection switch A17 and 16383 are input to AND operation A18, and the output result of selection switch A17 and 16383 are bitwise ANDed.

[0016] Moreover, the specific implementation method of step 3 is as follows: the difference UDF between the processed FIPU and FIPD and 100% are input to the subtractor A19, the difference UDF between the processed FIPU and FIPD is subtracted from 100%, the difference UDF between the processed FIPU and FIPD and 50% are input to the comparator A20, the value of UDF is compared with 50%, when UDF is greater than or equal to 50%, the comparator A20 outputs 1, otherwise the output is 0; the difference UDF between the processed FIPU and FIPD, the subtractor A19 and the result of the comparator A20 are input to the selector A21, when the comparator A20 outputs 1, the selector A21 selects the result of the subtractor A19 operation, when the comparator A20 outputs 0, the UDF value is selected for output; the result of the selector A21 and K3 are input to the multiplier A2 2. The result of selector A21 is multiplied by K3 and then output; the result of multiplier A22 and K4 are input to adder A23, the result of multiplier A22 is added to K4 and then output; the result of adder A23, -K5 and K5 are input to limiter A24, the result output by adder A23 is limited, when the result of adder A23 is greater than K5, limiter A24 outputs K5, when the result of adder A23 is less than -K5, limiter A24 outputs the value of -K5, when the result of adder A23 is between -K5 and K5, limiter A24 outputs the value of A23; the result of limiter A24 and 0 are input to selector A25, when EN=1, selector A25 outputs the result of limiter A24 to DK, when EN=0, the value output by selector A25 is 0.

[0017] Moreover, the specific implementation method of step 4 is as follows: the active power given value PR and the actual operating active power PE are input into the subtractor A26, the active power given value PR and the actual operating active power PE are subtracted to calculate the power difference, the result of the subtractor A26 and the multiplier A29 are input into the subtractor A27, the result of the subtractor A26 and the result of the multiplier A29 are subtracted, the result of the subtractor A27 and J are input into the multiplier A28, the result of the subtractor A27 and J are multiplied, the adder A30 and D are input into the multiplier A29, the output result of the adder A30 and D are multiplied, the result of the multiplier A28 and the delay operator A31 are input into the adder A30, the result of the multiplier A30 and the output result of the delay operator A31 are added, the result of the adder A30 is input into the delay operator A31, The result of adder A31 is delayed by one DSP operation cycle, the result of adder A30 and KA are input to adder A32, and the result of adder A30 is added to KA; the result of adder A32 and 100% are input to adder A33, the result of adder A32 is added with 100%, the result of adder A33 and 50 times TA are input to multiplier A34, the result of adder A34 is multiplied by 50 times TA, the result of multiplier A34 and the result of bitwise AND operator A36 are input to adder A35, and the result of multiplier A34 and the result of bitwise AND operator A36 are added; the result of adder A35 and 16383 are input to bitwise AND operator A36, the result of adder A35 and 16383 are ANDed according to each bit, and the electrical angle is limited to 0~16383. The advantages and positive effects of the present invention are:

[0018] The present invention collects the three-phase voltages of the upper and lower ports of the grid-connected switch through the off-grid controller, and respectively calculates the electrical angles of the three-phase voltages of the upper and lower ports through two phase-locked loops of the DSP; the electrical angles of the upper and lower port voltages calculated by the phase-locked loop are differenced in the FPGA of the off-grid controller, and the difference is processed and adjusted to a stable value; the electrical angle difference is processed by an intelligent real-time approximation algorithm to become an angular frequency adjustment value, and when the off-grid controller receives the synchronization start command of the host computer, the angular frequency adjustment value is sent to the optical fiber receiving port of the energy storage converter through the optical fiber output port; the energy storage converter receives the angular frequency adjustment value through the optical fiber receiving port and gives it to the virtual synchronous machine control to adjust the output voltage frequency and phase of the energy storage converter; finally, when the phase angle difference of the upper and lower port voltages of the grid-connected switch is less than 2°, the off-grid controller sends a synchronization completion signal, and the host computer controls the closing of the grid-connected switch. The present invention can actively realize the rapid convergence of the frequency difference within 1s, actively adjust the output frequency and phase of the energy storage system, and quickly lock the parameters of the large power grid. With a long synchronization window, the grid-connected switch can be closed at any time, and the current and voltage impact at the moment of closing is very small. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of grid-type energy storage system;

[0020] Figure 2 This is a flow chart of the steps of rapid synchronous grid connection of the energy storage system of the present invention;

[0021] Figure 3 This is a logic block diagram of processing the electrical angle difference of the voltage at the upper and lower ports of the grid-connected switch of the present invention;

[0022] Figure 4 This is a schematic diagram of calculating the electrical angle difference of the present invention;

[0023] Figure 5 It is a logic block diagram of the intelligent real-time approximation algorithm of the present invention;

[0024] Figure 6 Generate an electrical angle logic block diagram for the grid-connected energy storage converter of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to the accompanying drawings.

[0026] The grid-connected energy storage system is a new type of intelligent and highly integrated power system that can operate in grid-connected and off-grid modes and can switch freely. Figure 1 This is a schematic diagram of a grid-type energy storage system. The system mainly consists of the following parts:

[0027] Power grid: refers to the national power grid, regional power grid, microgrid or local power grid composed of diesel generators.

[0028] Grid-connected switch: The physical interface connecting the energy storage system and the power grid. The opening and closing operations of the grid-connected switch realize the electrical connection and isolation between the energy storage system and the power grid.

[0029] Grid-connected power storage converter (PCS): Grid-connected power storage converter is used to build an independent power grid or support the operation of the power grid. Multiple PCSs can be operated in parallel to increase the capacity and reliability of the system.

[0030] Energy storage battery: Energy storage batteries are used to store energy and release energy. Common batteries include lithium-ion batteries, lead-acid batteries, sodium-sulfur batteries, etc.

[0031] Load: The electrical equipment in the system that consumes the electrical energy provided by the system.

[0032] Host computer: responsible for monitoring, scheduling and optimizing the operation of the entire energy storage system.

[0033] Off-grid controller: Off-grid controller is a key component to realize smooth switching between off-grid and on-grid modes of energy storage system. It is used to realize the synchronous grid connection function of energy storage system and power grid and seamless switching from grid connection to off-grid.

[0034] A synchronous grid-connected method for a grid-connected energy storage system, such as Figure 2 As shown, the following steps are included:

[0035] Step 1: The off-grid controller collects the three-phase voltages of the upper and lower ports of the grid-connected switch, and calculates the electrical angles of the three-phase voltages of the upper and lower ports through two phase-locked loops of the DSP.

[0036] After the upper and lower port voltages of the grid-connected switch are sampled and calculated in the phase-locked loop in the DSP, the two electrical angles are sent to the FPGA of the grid-connected controller for processing. The FPGA uses a clock with an operating frequency of 40MHz and a period of 25ns. Figure 3 The following is a logic diagram for processing the difference between the upper and lower voltage electrical angles of the grid-connected switch. FIPU is the electrical angle of the upper voltage, FIPD is the electrical angle of the lower voltage, both FIPU and FIPD have amplitudes of 0 to 16383 (in this digital system, 16383 is calibrated as 100%), and the period is a sawtooth wave of the grid period; TA is the DSP operation period, K1 is the maximum electrical angle threshold, K2 corresponds to the minimum electrical angle threshold, and UDF is the difference between FIPU and FIPD after processing.

[0037] A1 is a subtractor, which subtracts FIPU from FIPD to obtain the electrical angle difference; A2 is an adder, which adds 16383 to the difference calculated by A1; A3 is a delay operator, which delays the result of A2 by one FPGA clock cycle of 25ns; A4 is an adder, which adds 0 to the difference of A1, in order to keep the clock aligned with the result of A2; A5 is a delay operator, which delays the result of A4 by one FPGA clock cycle of 25ns. A6, A7, A11, and A12 are adders with enable function, which only operate once when the enable signal EN=1 rises. A6 and A11 add 0 to the electrical angle of the upper and lower port voltages, in order to align the DSP operation clocks of FIPU and FIPD and ensure that the operation is performed at the same time. A7 adds 0 to the result of A6, and A12 adds 0 to the result of A11, in order to delay the signals of FIPU and FIPD by one DSP operation cycle at the same clock. A8, A9, A13, and A14 are comparison operators. A8 compares the result of A7 with K1. When the output of A7 is greater than K1, A8 outputs 1. A9 compares the result of A6 with K2. When the output of A7 is less than K2, A9 outputs 1. A13 compares the result of A12 with K1. When the output of A12 is greater than K1, A13 outputs 1. A14 compares the result of A6 with K2. When the output of A7 is less than K2, A9 outputs 1. A10 is an AND logic operator. It performs an AND operation on the results of A8 and A9. When both A8 and A9 are 1, A10 outputs 1, and in other cases, it outputs 0. A15 is an AND logic operator. It performs an AND operation on the outputs of A13 and A14. When both A13 and A14 are 1, A15 outputs 1, and in other cases, it outputs 0. A16 is an RS flip-flop. When S=1, the output is 1, and when R=1, the output is 0. In other states, the flip-flop maintains the current state. When the result of A15 is 1, the output of A16 is 1; when the result of A10 is 1, the output of A16 is 0. A17 is a selection switch. When the output of A16 is 1, A17 selects the output result of A5. When the output result of A16 is 0, A17 selects the output result of A3. A18 performs a bitwise AND operation. The output result of A17 is calculated bitwise AND with 16383, that is, each bit is ANDed and the result is output. The purpose is to limit the result to the range of 0 to 16383.

[0038] Step 2: In the FPGA of the parallel controller, the electrical angles of the upper and lower port voltages calculated by the phase-locked loop are calculated, and the difference is processed and adjusted to a stable value.

[0039] like Figure 4As shown, assuming that the electrical angle of each power grid cycle is sampled and calculated 8 times, the actual number of sampling times is related to the DSP operation cycle, FIPU corresponds to curve 1, FIPD is curve 2, the difference between FIPU and FIPD is curve 3, and the difference after processing is curve 4. It can be seen from curve 3 that the difference between FIPU and FIPD has positive and negative fluctuations, mainly because there is a sudden change in value when the sawtooth wave changes from the maximum value to 0, and special processing is required at this time. The position of the sudden change is confirmed by judging the maximum and minimum values ​​of FIPU and FIPD. When the difference becomes negative, the difference is added by 100% (i.e. 16383), and the difference output at this position can become positive.

[0040] When it reaches the moment t1, the previous cycle value A12 of FIPD is greater than the maximum value threshold K1 and the current cycle value A11 is less than the minimum value threshold K2. At this time, the FIPD electrical angle changes suddenly, A13 and A14 output 1 at the same time, and the output of the operator A15 is 1, the corresponding RS trigger A16 outputs 1, and A17 selects the output result of A5. The result represents the difference between FIPU and FIPD, which is 2 / 8 at this time.

[0041] From t1 to t2, the RS flip-flop A16 keeps outputting 1, and A17 keeps outputting the result of A5, that is, it keeps the value of 2 / 8.

[0042] When it reaches the moment t2, the last cycle value A8 of FIPU is greater than the maximum value threshold K1 and the current cycle value A6 is less than the minimum value threshold K2. At this time, the FIPU electrical angle suddenly changes position, A8 and A9 output 1 at the same time, and the output of the operator A10 is 1, and the corresponding RS trigger A16 outputs 0, and A17 selects the output result of A5, which means that the difference between FIPU and FIPD is added by 100%. Then the output result of selector A17 is: 100%+(-6 / 8)=2 / 8.

[0043] From t2 to t3, the RS flip-flop A16 keeps outputting 0, and A17 keeps outputting the result of A3, that is, it keeps the value of 2 / 8.

[0044] After time t3, the next cycle is entered, and each time it runs according to the above logic. Finally, the difference between FIPU and FIPD can be guaranteed to be a stable value without data mutation, providing reliable data for subsequent processing.

[0045] Step 3: Use an intelligent real-time approximation algorithm to process the electrical angle difference and convert it into an angular frequency adjustment value. When the off-grid controller receives the synchronization start command from the host computer, the angular frequency adjustment value is sent to the optical fiber receiving port of the energy storage inverter through the optical fiber output port.

[0046] like Figure 5 As shown, K3 is the frequency difference adjustment rate, K4 is the frequency difference compensation value, K5 is the frequency difference limit value, EN is the synchronous function enable signal, UDF is the difference between FIPU and FIPD after processing, and DK is the angular frequency adjustment value output to the energy storage converter. In the figure, A19 is a subtractor, which subtracts 100% from the value of UDF; A20 is a comparator, which compares the value of UDF with 50%. When UDF is greater than or equal to 50%, A20 outputs 1, otherwise it outputs 0; A21 is a selector, when A20 outputs 1, A21 selects the result of A19 operation, when A20 outputs 0, it selects UDF value output; A22 is a multiplier, which multiplies the result of A21 by K3 and outputs it; A23 is an adder, which adds the result of A21 to K3. The result of A22 operation is added to K4 and then output; A24 is a limiter, which limits the result of A23 output. When the result of A23 is greater than K5, A24 outputs K5. When the result of A23 is less than -K5, A24 outputs the value of -K5. When the result of A23 is between -K5 and K5, A24 outputs the value of A23; A25 is a selection switch. When EN=1, A25 outputs the value of A24 to DK. When EN=0, the value output by A25 is 0.

[0047] This part of the function is mainly based on the principle of real-time approximation. According to the difference in the voltage electrical angles of the upper and lower ports of the grid-connected switch, after adjusting the direction, adjusting the speed, and adjusting the amplitude limit, the electrical angle adjustment value that the energy storage system needs to adjust each time is finally calculated and output. The size of K3 affects the synchronization speed. The larger the K3 value, the faster the synchronization time. By setting the value of K3 reasonably, it can be ensured that the synchronization is completed within 1s. Among them, A19~A21 is used to determine the electrical angle adjustment direction of the energy storage system. When UDF is greater than or equal to 50%, it means that the forward adjustment time is long and the reverse adjustment is required. Reverse adjustment is required, that is, after the A19 subtractor processes UDF-100%, the output result is a negative value, and the adjustment direction is the energy storage system minus the corresponding adjustment value; when the UDF difference is less than 50%, it means that the forward adjustment time is short, and UDF is used without processing. The output result is a positive value, and the adjustment direction is the energy storage system plus the corresponding adjustment value. A22 is multiplied by K3 to control the speed of each adjustment. The smaller the value of K3, the slower the adjustment, and vice versa. A24 uses K5 to limit the amplitude to prevent excessive adjustment from causing drastic adjustment of the energy storage system and causing system instability; A25 is used to control the disabling and enabling of this function. When EN=1, the function is enabled and the energy storage system performs synchronous adjustment; when EN=0, the function is disabled and the energy storage system does not respond to adjustment.

[0048] Step 4: The energy storage converter receives the angular frequency adjustment value through the optical fiber receiving port and sends it to the virtual synchronous machine control to adjust the output voltage frequency and phase of the energy storage converter.

[0049] The grid-connected energy storage inverter receives the phase angle adjustment value sent by the off-grid controller through the optical fiber and sends it to the virtual synchronous machine module as an angular frequency adjustment value to generate the electrical angle of the energy storage inverter to adjust the output voltage frequency and phase angle of the energy storage inverter. Figure 6 Generate an electrical angle logic block diagram for the energy storage converter, where P R is the given value of active power, P E is the actual operating active power, J is the virtual synchronous machine inertia coefficient, D is the virtual synchronous machine damping coefficient, KA is the received angular frequency adjustment value, 50TA is 50 times the DSP operation cycle, and FIP_VSG represents the electrical angle output by the energy storage converter. A26 is a subtractor, which subtracts PR and PE to calculate the power difference; A27 is a subtractor, which subtracts the result of A26 from the result of A29; A28 is a multiplier, which multiplies the result of A27 by J; A29 is a multiplier, which multiplies the output result of A30 by D; A30 is an adder, which adds the result of A28 to the output result of A31; A31 means delaying the result of A5 by one DSP operation cycle, which is the previous one of A30 DSP cycle data; A32 is an adder, which adds the result of A30 to KA; A33 is an adder, which adds 100% to the result of A32; A34 is a multiplier, which multiplies the result of A33 by 50 times TA; A35 is an adder, which adds the result of A34 and the result of A36; A36 is a bitwise AND operator, which performs an AND operation on the result of A35 and 16383 according to each bit, and limits the electrical angle to 0~16383.

[0050] Figure 6 Among them, A26~A31 are motion equations of virtual synchronous machine, which are mainly used for the relationship between active power and frequency. The specific formula is as follows:

[0051]

[0052] Where ω is the angular frequency of the output voltage, and Δω is the angular frequency difference of the output voltage.

[0053] A26, A27, and A29 represent P R -P E -D·Δω, A28, A30 and A31 represent The result of A30 output is Δω. A32 indicates that the received angular frequency adjustment value is added to the virtual synchronous machine to adjust the frequency of the grid-type energy storage converter. A33 indicates that the rated angular frequency of the voltage (normalized to 100%, that is, 50x2π corresponds to 100%) is added to the angular frequency difference to calculate the current real-time angular frequency. A34~A36 indicate that the angular frequency is integrated to calculate the electrical angle required for the operation of the grid-type energy storage converter. Among them, A36 is used to return the electrical angle to zero by bitwise AND operation when the electrical angle is integrated to 16383. The final FIP_VSG is a sawtooth wave with an amplitude of 0~16383 and a period of the output voltage period.

[0054] Step 5: When the phase angle difference between the upper and lower port voltages of the grid-connected switch is less than 2°, the off-grid controller sends a synchronization completion signal, and the host computer controls the grid-connected switch to close.

[0055] The grid-connected converter uses the generated electrical angle to generate a three-phase AC voltage modulation signal after voltage loop and current loop calculation, generates a PWM waveform through the IGBT module, and finally outputs a three-phase AC voltage through the LCL filter. The phase angle and frequency of the voltage change with the electrical angle, and the corresponding electrical angle FIPD of the grid-connected switch lower port voltage will change accordingly. The difference between FIPU and FIPD in the off-grid control will be adjusted. When the voltage cycle corresponding to FIPD becomes larger or smaller, the difference between FIPU and FIPD will become smaller. Figure 5 The absolute value of DK calculated in will become smaller. After multiple cycles of operation, until the absolute value of DK is close to 0, FIPU and FIPD will be basically the same, so that the phase angle of the upper and lower port voltages of the grid-connected switch is less than 2°, meeting the grid-connected conditions and completing the synchronization. When the frequency of the upper port voltage of the grid-connected switch fluctuates, the above adjustment can also be used to quickly track the changes and achieve real-time tracking. When the phase angle of the upper and lower port voltages of the grid-connected switch is always less than 2°, the off-grid controller will send a synchronization completion signal to the host computer, and the host computer can control the closing of the grid-connected switch after receiving the signal.

[0056] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. A synchronous grid-connected method for a grid-connected energy storage system, characterized in that: The following steps are involved: Step 1: The off-grid controller collects the three-phase voltages of the upper and lower ports of the grid-connected switch, and calculates the electrical angles of the three-phase voltages of the upper and lower ports through two phase-locked loops of the DSP; Step 2: In the FPGA of the parallel controller, the electrical angles of the upper and lower port voltages calculated by the phase-locked loop are calculated, and the difference is processed and adjusted to a stable value; Step 3: Using an intelligent real-time approximation algorithm, the electrical angle difference is processed and converted into an angular frequency adjustment value. When the off-grid controller receives a synchronization start command from the host computer, the angular frequency adjustment value is sent to the optical fiber receiving port of the energy storage converter through the optical fiber output port; Step 4: The energy storage converter receives the angular frequency adjustment value through the optical fiber receiving port and sends it to the virtual synchronous machine control to adjust the output voltage frequency and phase of the energy storage converter; Step 5: When the phase angle difference between the upper and lower port voltages of the grid-connected switch is less than 2°, the off-grid controller sends a synchronization completion signal, and the host computer controls the grid-connected switch to close.

2. A synchronous grid-connected method for a grid-connected energy storage system according to claim 1, characterized in that: The specific implementation method of step 1 is: the upper voltage electrical angle FIPU and the lower voltage electrical angle FIPD are input to the subtractor A1 for subtraction to obtain the electrical angle difference, the electrical angle difference and 16383 are input to the adder A2 to perform an addition operation of 16383 on the electrical angle difference, the result of the adder A2 is input to the delay operator A3 for a delay of 25ns for an FPGA clock cycle, the electrical angle difference and 0 are input to the adder A4, the electrical angle difference obtained by the subtractor A1 is added with 0, the clock is kept aligned, and the result of the adder A4 is input to the delay operator A5 for a delay of 25ns for an FPGA clock cycle; The upper voltage electrical angle FIPU and 0 are input to an adder A6 with an enable function, and 0 is added to the upper voltage electrical angle. The result of the adder A6 and 0 are input to an adder A7 with an enable function, and 0 is added to the result of the adder A6. The result of the adder A7 and K1 are input to a comparison operator A8, and the result of the adder A7 is compared with K1. When the output of the adder A7 is greater than K1, A8 outputs 1. The result of the adder A7 and K2 are input to a comparison operator A9, and the result of the adder A7 is compared with K2. When the output of the adder A7 is less than K2, the comparison operator A9 outputs 1. The results of the comparison operators A8 and A9 are input to an AND logic operator A10, and the results of the comparison operators A8 and A9 are ANDed. When the results of the comparison operators A8 and A9 are both 1, the AND logic operator A10 outputs 1, and the output is 0 in other cases. The lower port voltage electrical angle FIPD and 0 are input to the adder A11 with an enable function, and the lower port voltage electrical angle is added with 0. The result of the adder A11 and 0 are input to the adder A12 with an enable function, and the result of the adder A11 is added with 0. The result of the adder A12 and K1 are input to the comparison operator A13, and the result of the adder A12 is compared with K1. When the output of the adder A12 is greater than K1, the output of A13 is 1, and the adder A1 The result of 2 and K2 are input to the comparison operator A13, and the result of the adder A12 is compared with K2. When the output of the adder A12 is less than K2, the comparison operator A13 outputs 1. The results of the comparison operators A13 and A14 are input to the AND logic operator A15, and the results of the comparison operators A13 and A14 are ANDed. When the results of the comparison operators A13 and A14 are both 1, the AND logic operator A15 outputs 1, and the output is 0 in other cases. The results of AND logic operator A10 and AND logic operator A15 are input to RS flip-flop A16. When S=1, the output is 1, and when R=1, the output is 0. In other states, the flip-flop maintains the current state. When the result of AND logic operator A15 is 1, the output of RS flip-flop A16 is 1; when the result of AND logic operator A10 is 1, the output of RS flip-flop A16 is 0. The results of delay operator A3, delay operator A5 and RS trigger A16 are input to selection switch A17. When the output of RS trigger A16 is 1, selection switch A17 selects the output result of delay operator A5. When the output result of RS trigger A16 is 0, selection switch A17 selects the output result of delay operator A3. The result of selection switch A17 and 16383 are input to AND operation A18, and the output result of selection switch A17 and 16383 are bitwise ANDed.

3. A synchronous grid-connected method for a grid-connected energy storage system according to claim 1, characterized in that: The specific implementation method of step 3 is as follows: the difference UDF of the processed FIPU and FIPD and 100% are input to the subtractor A19, the difference UDF of the processed FIPU and FIPD is subtracted from 100%, the difference UDF of the processed FIPU and FIPD and 50% are input to the comparator A20, the value of UDF is compared with 50%, when UDF is greater than or equal to 50%, the comparator A20 outputs 1, otherwise the output is 0; the difference UDF of the processed FIPU and FIPD, the result of the subtractor A19 and the comparator A20 are input to the selector A21, when the comparator A20 outputs 1, the selector A21 selects the result of the subtractor A19 operation, when the comparator A20 outputs 0, the UDF value is selected for output; the result of the selector A21 and K3 are input to the multiplier A22 , the result of selector A21 is multiplied by K3 and then output; the result of multiplier A22 and K4 are input to adder A23, the result of multiplier A22 is added to K4 and then output, the result of adder A23, -K5 and K5 are input to limiter A24, the result output by adder A23 is limited, when the result of adder A23 is greater than K5, limiter A24 outputs K5, when the result of adder A23 is less than -K5, limiter A24 outputs the value of -K5, when the result of adder A23 is between -K5 and K5, limiter A24 outputs the value of A23; the result of limiter A24 and 0 are input to selection switch A25, when EN=1, selection switch A25 outputs the result of limiter A24 to DK, when EN=0, the value output by selection switch A25 is 0.

4. A synchronous grid-connected method for a grid-connected energy storage system according to claim 1, characterized in that: The specific implementation method of step 4 is as follows: the active power given value PR and the actual operating active power PE are input to the subtractor A26, the active power given value PR and the actual operating active power PE are subtracted to calculate the power difference, the result of the subtractor A26 and the multiplier A29 are input to the subtractor A27, the result of the subtractor A26 and the result of the multiplier A29 are subtracted, the result of the subtractor A27 and J are input to the multiplier A28, the result of the subtractor A27 and J are multiplied, the adder A30 and D are input to the multiplier A29, the output result of the adder A30 is multiplied by D, the result of the multiplier A28 and the delay operator A31 are input to the adder A30, the result of the multiplier A30 and the output result of the delay operator A31 are added, the result of the adder A30 is input to the delay operator A31, The result of adder A31 is delayed by one DSP operation cycle, the result of adder A30 and KA are input to adder A32, and the result of adder A30 is added to KA; the result of adder A32 and 100% are input to adder A33, and the result of adder A32 is added to 100%, the result of adder A33 and 50 times TA are input to multiplier A34, and the result of adder A34 is multiplied by 50 times TA, the result of multiplier A34 and the result of bitwise AND operator A36 are input to adder A35, and the result of multiplier A34 and the result of bitwise AND operator A36 are added; the result of adder A35 and 16383 are input to bitwise AND operator A36, and the result of adder A35 is ANDed with 16383 according to each bit, and the electrical angle is limited to 0~16383.

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