Synchronous rectification control circuit, synchronous rectification control method and synchronous rectification circuit

Abstract

The invention relates to a synchronous rectification control circuit, a synchronous rectification control method and a synchronous rectification circuit. The control circuit comprises a detection circuit which compares the drain-source voltage with the output voltage and generates a detection pulse signal, the detection pulse signal comprises any one of a first level signal and a second level signal, and the levels of the first level signal and the second level signal are opposite; the counting circuit is used for generating a counting pulse signal according to the drain-source voltage, the driving signal provided by the synchronous rectification control circuit for the synchronous rectification switch and the detection pulse signal; and the turn-on control circuit is used for determining a target turn-on condition corresponding to the synchronous rectification switch according to the counting pulse signal and providing a driving signal for the synchronous rectification switch according to the target turn-on condition and the drain-source voltage. The problem of mistaken switching-on caused by oscillation is avoided while normal switching-on of the synchronous rectification switch in a full-load range of the synchronous rectification circuit is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a synchronous rectification control circuit, a synchronous rectification control method and a synchronous rectification circuit. Background Art

[0002] In a flyback circuit using a primary side regulator (PSR), when paired with a synchronous rectifier (SR), the SR is required to be turned on normally within the full load range, otherwise the sampling of the PSR control circuit will be wrong, resulting in abnormal output voltage. However, within the full load range, the operating waveform of the SR varies greatly. After the SR's turn-on condition is fixed, the synchronous rectifier switch in the SR may turn on normally when the load is heavy, but not when the load is unloaded, resulting in low output voltage; or the synchronous rectifier switch in the SR turns on normally when the load is heavy and unloaded, but turns on by mistake when the resonance is strengthened. Summary of the invention

[0003] Based on this, it is necessary to provide a synchronous rectification control circuit, a synchronous rectification control method and a synchronous rectification circuit, so that the synchronous rectification switch can be normally turned on within the full load range and avoid oscillation causing the synchronous rectification switch to be turned on incorrectly.

[0004] A synchronous rectification control circuit is connected to a synchronous rectification switch in a synchronous rectification circuit, comprising:

[0005] a detection circuit, configured to compare the drain-source voltage of the synchronous rectification switch with the output voltage of the synchronous rectification circuit, and generate a detection pulse signal, wherein the detection pulse signal includes any one of a first level signal and a second level signal, wherein the first level signal and the second level signal have opposite levels;

[0006] a counting circuit connected to the detection circuit, and configured to generate a counting pulse signal according to the drain-source voltage, the driving signal provided by the synchronous rectification control circuit to the synchronous rectification switch, and the detection pulse signal;

[0007] The on-control circuit is connected to the counting circuit and is used to determine the target on-condition corresponding to the synchronous rectification switch according to the counting pulse signal, and provide a driving signal to the synchronous rectification switch according to the target on-condition and the drain-source voltage.

[0008] In one embodiment, the first level signal is used to characterize that the drain-source voltage is greater than the output voltage, and the second level signal is used to characterize that the drain-source voltage is less than or equal to the output voltage; the detection circuit is also used to determine that the detection pulse signal jumps from the second level signal to the first level signal after the drain-source voltage is greater than the output voltage for a preset time.

[0009] In one embodiment, the detection circuit comprises:

[0010] A comparison module, used for comparing the drain-source voltage with the output voltage;

[0011] The delay module is connected to the comparison module and the counting circuit respectively, and is used to output the first level signal after the drain-source voltage is greater than the output voltage for a preset time; and is also used to output the second level signal when the drain-source voltage is less than or equal to the output voltage.

[0012] In one embodiment, the first input terminal of the comparison module is connected to the first input terminal of the delay module for receiving the output voltage; the second input terminal of the comparison module is used to receive the drain-source voltage; the output terminal of the comparison module is connected to the second input terminal of the delay module; and the output terminal of the delay module is connected to the input terminal of the counting circuit.

[0013] In one embodiment, the counting pulse signal includes a first counting pulse signal and a second counting pulse signal of opposite levels; the opening control circuit is pre-configured with a first opening condition and a second opening condition, and the opening control circuit is used to use the first opening condition as the target opening condition when the first counting pulse signal is received; and use the second opening condition as the target opening condition when the second counting pulse signal is received;

[0014] Among them, the first counting pulse signal represents that the synchronous rectification switch receives a driving signal for controlling the shutdown of the synchronous rectification switch, and when the drain-source voltage satisfies the shutdown condition of the synchronous rectification switch, the number of jumps of the detection pulse signal from the first target level signal to the second target level signal meets the target value, and the second counting pulse signal represents that the number of jumps does not meet the target value; one of the first target level signal and the second target level signal is a first level signal, and the other is a second level signal; the first turn-on condition and the second turn-on condition have different restrictions on the change slope of the drain-source voltage.

[0015] In one embodiment, the counting circuit comprises:

[0016] a counting module, the counting module being connected to the detection circuit, and being used for counting the number of transitions of the detection pulse signal from the first target level signal to the second target level signal, and comparing the number of transitions of the detection pulse signal with a target value, and generating a comparison signal according to the comparison result; one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal;

[0017] A signal generating module is connected to the counting module and the opening control circuit respectively, and is used to generate the counting pulse signal according to the comparison signal.

[0018] In one embodiment, the counting circuit further includes:

[0019] A reset module, wherein a first input terminal of the reset module is used to receive the driving signal, a second input terminal of the reset module is used to receive the drain-source voltage, and an output terminal of the reset module is respectively connected to the counting module and the signal generating module;

[0020] Among them, the reset module is used to generate a reset signal when receiving a drive signal that controls the conduction of the synchronous rectification switch and / or the drain-source voltage meets the turn-on condition of the synchronous rectification switch, and the reset signal is used to reset the number of jumps of the counting module; the signal generating module is also used to generate the counting pulse signal according to the comparison signal and the reset signal.

[0021] In one embodiment, the counting module comprises:

[0022] A plurality of D flip-flops connected in sequence corresponding to the target value, the reverse output end of each D flip-flop is connected to the input end of the D flip-flop, and the same-direction output end of the previous D flip-flop is connected to the clock signal end of the next D flip-flop; the clock signal end of the first D flip-flop is connected to the output end of the detection circuit; the reset ends of the plurality of D flip-flops are respectively connected to the output end of the reset module; the reverse output end and the same-direction output end of the D flip-flop have opposite output levels; when the detection pulse signal jumps from the first target level signal to the second target level signal, the same-direction output end of the first D flip-flop outputs a signal with the same level as the input end;

[0023] An AND gate, wherein the multiple input terminals of the AND gate are connected to the same-direction output terminals of the multiple D flip-flops, and the output terminal of the AND gate is connected to the signal generating module; used to generate a first comparison signal indicating that the number of transitions meets the target value when the same-direction output terminals of the D flip-flops output signals of the same level, and also used to generate a second comparison signal indicating that the number of transitions does not meet the target value when the same-direction output terminals of the D flip-flops output signals of different levels;

[0024] The comparison signal includes the first comparison signal and the second comparison signal of opposite levels, and the signal generating module is further used to generate the counting pulse signal according to the comparison signal and the reset signal.

[0025] In one embodiment, the signal generation module includes:

[0026] RS trigger, the reset input terminal of the RS trigger is connected to the output terminal of the counting module, the set input terminal of the RS trigger is connected to the output terminal of the reset module; the reverse output terminal of the RS trigger is used to output the counting pulse signal.

[0027] In one embodiment, the reset module includes:

[0028] A NOR gate, wherein the first input end of the NOR gate is used as the first input end of the reset module; and the output end of the NOR gate is connected to the counting module;

[0029] A comparison unit, wherein the first input end of the comparison unit serves as the second input end of the reset module, and the second input end of the comparison unit is used to receive the turn-on threshold of the synchronous rectification switch; the output end of the comparison unit is connected to the second input end of the NOR gate, and is used to compare the drain-source voltage with the turn-on threshold;

[0030] A NOT gate, wherein the input end of the NOT gate is connected to the output end of the NOR gate, and the output end of the NOT gate is connected to the set end of the RS trigger.

[0031] In one embodiment, the opening control circuit includes:

[0032] a selection module, wherein an input end of the selection module is connected to an output end of the counting circuit, the selection module is pre-configured with a first opening condition and a second opening condition, and is used to determine a target opening condition of the first opening condition and the second opening condition according to the counting pulse signal;

[0033] A drive generation module is connected to the selection module and the synchronous rectification switch respectively, and is used to generate a drive signal according to the target selection condition, the drain-source voltage and the turn-on threshold of the synchronous rectification switch.

[0034] A synchronous rectification control method is used to control a synchronous rectification switch in a synchronous rectification circuit, the method comprising:

[0035] Comparing the drain-source voltage of the synchronous rectification switch with the output voltage of the synchronous rectification circuit, and generating a detection pulse signal; the detection pulse signal includes any one of a first level signal and a second level signal, and the first level signal and the second level signal have opposite levels;

[0036] Generate a counting pulse signal according to the detection pulse signal, the drain-source voltage and the driving signal received by the synchronous rectification switch;

[0037] Determining a target turn-on condition corresponding to the synchronous rectification switch according to the count pulse signal;

[0038] A driving signal is provided to the synchronous rectification switch according to the target turn-on condition and the drain-source voltage.

[0039] In one embodiment, the synchronous rectification control method further includes:

[0040] After the drain-source voltage is greater than the output voltage for a preset time, determining that the detection pulse signal jumps from the second level signal to the first level signal;

[0041] The first level signal is used to represent that the drain-source voltage is greater than the output voltage, and the second level signal is used to represent that the drain-source voltage is less than or equal to the output voltage.

[0042] In one embodiment, the counting pulse signal includes a first counting pulse signal and a second counting pulse signal of opposite levels; the generating of the counting pulse signal according to the detection pulse signal, the drain-source voltage and the driving signal received by the synchronous rectification switch includes:

[0043] When the synchronous rectification switch receives a driving signal for controlling the synchronous rectification switch to be turned off, and the drain-source voltage satisfies the turn-off condition of the synchronous rectification switch, if the number of transitions of the detection pulse signal from the first target level signal to the second target level signal meets the target value, a first counting pulse signal is generated; if the number of transitions of the detection pulse signal from the first target level signal to the second target level signal does not meet the target value, a second counting pulse signal is generated;

[0044] The step of determining a target turn-on condition corresponding to the synchronous rectification switch according to the count pulse signal comprises:

[0045] According to the first counting pulse signal, taking the first opening condition as the target opening condition;

[0046] According to the second counting pulse signal, taking the second opening condition as the target opening condition;

[0047] Among them, one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal; the first turn-on condition and the second turn-on condition have different restrictions on the change slope of the drain-source voltage.

[0048] In one embodiment, the synchronous rectification control method further includes:

[0049] When a driving signal for controlling the synchronous rectification switch to be turned on is received, a reset signal is generated; when the drain-source voltage satisfies a turn-on condition of the synchronous rectification switch, the reset signal is generated;

[0050] The reset signal is used to reset the number of jumps.

[0051] A synchronous rectification circuit comprises a primary circuit and a secondary circuit, wherein the secondary circuit comprises a synchronous rectification switch and the above-mentioned synchronous rectification control circuit.

[0052] A synchronous rectification control circuit is used to provide a driving signal to control a synchronous rectification switch in a flyback power supply circuit. The synchronous rectification control circuit includes:

[0053] A detection circuit, used for detecting the drain-source voltage of the synchronous rectification switch and comparing it with a reference signal to generate a detection pulse signal;

[0054] a counting circuit connected to the detection circuit, and configured to generate a counting pulse signal according to the detection pulse signal and the drive signal, wherein when the drive signal indicates that the synchronous rectification switch is turned on, the counting pulse signal is reset to zero and counted again; and

[0055] The turn-on control circuit is connected to the counting circuit, and is used to determine the target turn-on condition corresponding to the synchronous rectification switch according to the counting pulse signal, and provide a driving signal to the synchronous rectification switch according to the target turn-on condition and the drain-source voltage. When the counting pulse signal is higher than a preset value, the target turn-on condition of the synchronous rectification switch is lowered.

[0056] In the above-mentioned synchronous rectification control circuit, the detection circuit compares the drain-source voltage of the synchronous rectification switch and the output voltage of the synchronous rectification circuit, and generates a detection pulse signal. The counting circuit generates a counting pulse signal according to the drain-source voltage, the detection pulse signal and the drive signal provided by the synchronous rectification control circuit to the synchronous rectification switch. The opening control circuit confirms the target opening condition corresponding to the synchronous rectification switch according to the counting pulse signal, and provides a drive signal to the synchronous rectification switch according to the target opening condition and the drain-source voltage to control the opening and closing of the synchronous rectification switch. In the present disclosure, the target opening condition is determined by the counting pulse signal, and the counting pulse signal is determined by the drain-source voltage, the output voltage of the synchronous rectification circuit and the drive signal provided by the synchronous rectification control circuit to the synchronous rectification switch. Thereby, the target opening condition is determined according to the fluctuation of the drain-source voltage of the synchronous rectification circuit under different states, ensuring that the synchronous rectification switch is normally opened when the synchronous rectification circuit is in the full load range, while avoiding the problem of oscillation causing the synchronous rectification switch to be opened incorrectly.

[0057] In the above synchronous rectification control method, the drain-source voltage of the synchronous rectification switch and the output voltage of the synchronous rectification circuit are compared, and a detection pulse signal is generated. According to the detection pulse signal, the drain-source voltage and the drive signal received by the synchronous rectification switch, a counting pulse signal is generated. According to the counting pulse signal, the target turn-on condition corresponding to the synchronous rectification switch is determined, and according to the target turn-on condition and the drain-source voltage, a drive signal is provided to the synchronous rectification switch to control the turn-on and turn-off of the synchronous rectification switch. The target turn-on condition is determined by the counting pulse signal, and the counting pulse signal is determined by the drain-source voltage, the output voltage of the synchronous rectification circuit and the drive signal provided by the synchronous rectification control circuit to the synchronous rectification switch. Thus, the target turn-on condition is determined according to the fluctuation of the drain-source voltage of the synchronous rectification circuit under different states, so as to ensure that the synchronous rectification switch is normally turned on when the synchronous rectification circuit is in the full load range, and avoid the problem of oscillation causing the synchronous rectification switch to be turned on by mistake. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 It is a schematic diagram of the structure of a typical synchronous rectification circuit;

[0060] Figure 2 In some embodiments Figure 1 A corresponding schematic diagram between the drain-source voltage of the corresponding synchronous rectification switch and the timing diagram of the driving signal;

[0061] Figure 3 A schematic diagram of the structure of a synchronous rectification circuit in some embodiments;

[0062] Figure 4 It is a structural schematic diagram of a synchronous rectification control circuit in some embodiments;

[0063] Figure 5 is a schematic diagram of the structure of a detection circuit in some embodiments;

[0064] Figure 6 is a circuit diagram of a detection circuit in some embodiments;

[0065] Figure 7 is a schematic diagram of the structure of a counting circuit in some embodiments;

[0066] Figure 8 is a circuit diagram of a counting circuit in some embodiments;

[0067] Fig. 9 It is a schematic diagram of the structure of the opening control circuit in some embodiments;

[0068] Fig.10 is a circuit diagram of an opening control circuit in some embodiments;

[0069] Fig.11 is a schematic diagram of a timing diagram of a drain-source voltage of a synchronous rectification switch and a corresponding signal of a synchronous rectification control circuit in some embodiments;

[0070] Fig.12 Schematic diagram of a flow chart of a synchronous rectification control method in some embodiments.

[0071] Description of reference numerals:

[0072] Synchronous rectification control circuit 100; synchronous rectification switch 102; detection circuit 104; counting circuit 106; opening control circuit 108; comparison module 202; delay module 204; counting module 206; signal generating module 208; reset module 210; selection module 212; drive generating module 214. DETAILED DESCRIPTION

[0073] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first opening condition may be referred to as a second opening condition, and similarly, a second opening condition may be referred to as a first opening condition. Both the first opening condition and the second opening condition are opening conditions, but they are not the same opening condition.

[0076] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0077] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0078] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0079] Figure 1 It is a schematic diagram of the structure of a typical synchronous rectification circuit. Figure 2 In some embodiments Figure 1 The corresponding schematic diagram between the drain-source voltage of the corresponding synchronous rectification switch and the timing diagram of the drive signal, see Figure 1 , Figure 2The synchronous rectifier (SR) 10 includes a synchronous rectifier switch 12 and a synchronous rectifier control circuit 14. The synchronous rectifier control circuit 14 is connected to the control end of the synchronous rectifier switch 12 and is used to send a drive signal SR_PWM to the control end of the synchronous rectifier switch 12 for controlling the synchronous rectifier switch 12 to turn on or off. As an example, the synchronous rectifier control circuit 14 is an SR controller; in the t1-t2 stage, the synchronous rectifier circuit is in a heavy load state, in the t3-t5 stage, the synchronous rectifier circuit is in a no-load state, and in the t6-t8 stage, the synchronous rectifier circuit is in a free resonance state.

[0080] Assume that the turn-on condition of the synchronous rectification switch 12 is that the time for the drain-source voltage Vds to drop from the output voltage VDD to the turn-on threshold Vth_on is less than 50ns; wherein Vds is the drain-source voltage between the drain terminal and the source terminal of the synchronous rectification switch 12 in the SR, VDD is the output voltage of the synchronous rectification circuit, VDD=Vds+Vs, Vs is the voltage of the secondary side of the transformer in the synchronous rectification circuit, and Vth_on is the turn-on threshold of the synchronous rectification switch 12. The time for Vds to drop from VDD to Vth_on is determined by the rise time of the drain voltage at the drain terminal of the primary MOS tube when the primary side is turned off, and the rise time of the drain voltage is determined by the peak value of the primary current at the turn-off moment. The larger the secondary side load of the synchronous rectification circuit, the larger the peak value of the primary current, and the shorter the time for Vds of the synchronous rectification switch 12 to drop from VDD to Vth_on.

[0081] In the t1-t2 stage, the time for Vds to drop from VDD to Vth_on is 20ns, which is less than 50ns, and the turn-on condition of the synchronous rectification switch 12 is met. When Vds is less than Vth_on, the synchronous rectification switch 12 is normally turned on. In the t3-t5 stage, the time for Vds to drop from VDD to Vth_on is 200ns, which is greater than 50ns, and the turn-on condition of the synchronous rectification switch 12 is not met. The synchronous rectification switch 12 cannot be turned on normally. In order to ensure that the synchronous rectification switch 12 is turned on normally in the t3-t5 stage, the turn-on condition of the synchronous rectification switch 12 can be relaxed to the time for Vds to drop from VDD to Vth_on is less than 500ns. The relaxation of the turn-on condition does not affect the normal turn-on of the synchronous rectification switch 12 in the t1-t2 stage. In the t6-t8 stage, the synchronous rectification circuit is in a free resonance state. When the resonance is enhanced, the time for the Vds of the synchronous rectification switch 12 to drop from VDD to Vth_on becomes shorter to meet the relaxed turn-on condition (less than 500ns), resulting in the problem of the synchronous rectification switch 12 being turned on by mistake. How to make the synchronous rectification switch 12 turn on normally when the load is in a heavy load state and a no-load state, and not turn on by mistake when the resonance is enhanced has become an urgent problem to be solved.

[0082] As an example, the rated output current of the synchronous rectification circuit is 2 amperes. When the actual output current is greater than or equal to 1.5 amperes, it is considered that the load of the synchronous rectification circuit is in a heavy load state.

[0083] Figure 3 is a schematic diagram of the structure of a synchronous rectification circuit in some embodiments, Figure 4 is a schematic diagram of the structure of the synchronous rectification control circuit in some embodiments, see Figure 3 , Figure 4 In order to enable the synchronous rectification switch 102 to be normally turned on when the load of the synchronous rectification circuit is in a no-load state and not to be mistakenly turned on when the resonance is strengthened, the present disclosure provides a synchronous rectification control circuit 100, and the synchronous rectification control circuit 100 is connected to the synchronous rectification switch 102 in the synchronous rectification circuit. The synchronous rectification control circuit 100 includes: a detection circuit 104, a counting circuit 106 and an opening control circuit 108.

[0084] The detection circuit 104 is connected to the synchronous rectification switch 102 and the output end of the synchronous rectification circuit respectively, and is used to obtain the drain-source voltage Vds of the synchronous rectification switch 102 and the output voltage VDD of the synchronous rectification circuit, and compare the drain-source voltage Vds of the synchronous rectification switch 102 and the output voltage VDD of the synchronous rectification circuit, and generate a detection pulse signal Detect_Vds; wherein the detection pulse signal Detect_Vds represents the comparison result between the source-drain voltage Vds and the output voltage VDD, and the detection pulse signal Detect_Vds includes any one of the first level signal and the second level signal, that is, a detection pulse signal Detect_Vds of a level is generated at the same time, such as the first level signal or the second level signal; the levels of the first level signal and the second level signal are opposite, that is, one of the first level signal and the second level signal is a high level 1, and the other is a low level 0.

[0085] The counting circuit 106 is connected to the detection circuit 104 and is used to generate a counting pulse signal Condition_Switch according to the drain-source voltage Vds, the driving signal SR_PWM provided by the synchronous rectification control circuit 100 to the synchronous rectification switch 102 and the detection pulse signal Detect_Vds.

[0086] As an example, the counting pulse signal Condition_Switch represents whether the number of jumps of the detection pulse signal Detect_Vds from the first target level signal to the second target level signal meets the preset condition when the synchronous rectification switch 102 is turned off under the control of the driving signal SR_PWM that controls the synchronous rectification switch 102 to turn off, and the drain-source voltage Vds corresponding to the synchronous rectification switch 102 cannot turn on the synchronous rectification switch 102, and one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal. It can be understood that the conduction and opening states of the synchronous rectification switch 102 are the same.

[0087] Furthermore, the synchronous rectification switch 102 is turned off under the control of the drive signal SR_PWM that controls the synchronous rectification switch 102 to be turned off, which means that the drive signal SR_PWM received by the synchronous rectification switch 102 is a low level 0, and the drain-source voltage Vds corresponding to the synchronous rectification switch 102 cannot turn on the synchronous rectification switch 102, which means that the drain-source voltage Vds is greater than the turn-on threshold Vth_on of the synchronous rectification switch 102, that is, Vds>Vth_on.

[0088] It can be understood that the levels of the counting pulse signal Condition_Switch indicating that the number of transitions meets the preset condition and the counting pulse signal Condition_Switch indicating that the number of transitions does not meet the preset condition are opposite.

[0089] The on control circuit 108 is connected to the counting circuit 106 and is used to determine the target on condition corresponding to the synchronous rectifier switch 102 according to the counting pulse signal Condition_Switch, and provide a driving signal SR_PWM to the synchronous rectifier switch 102 according to the target on condition and the drain-source voltage Vds.

[0090] It can be understood that the target turn-on conditions corresponding to the count pulse signals Condition_Switch of different levels are different, and the drive signal SR_PWM is determined by the target turn-on condition and the drain-source voltage Vds; wherein the target turn-on condition defines the maximum time for the drain-source voltage Vds of the synchronous rectifier switch 102 to change from VDD to Vth_on when the count pulse signal Condition_Switch corresponding to the control synchronous rectifier switch 102 is turned on. The turn-on control circuit 108 confirms that the synchronous rectifier switch 102 meets the turn-on condition when the time for the drain-source voltage Vds of the synchronous rectifier switch 102 to change from VDD to Vth_on is less than the maximum time defined by the target turn-on condition; when the synchronous rectifier switch 102 meets the turn-on condition and the drain-source voltage Vds of the synchronous rectifier switch 102 is a voltage that satisfies the control of the synchronous rectifier switch 102 to be turned on, the drive signal SR_PWM for controlling the synchronous rectifier switch 102 to be turned on is provided to the synchronous rectifier switch 102. Furthermore, the target turn-on condition defines the maximum time for the drain-source voltage Vds of the synchronous rectifier switch 102 to drop from VDD to Vth_on when the counting pulse signal Condition_Switch corresponding to the control synchronous rectifier switch 102 is turned on. When the drain-source voltage Vds of the synchronous rectifier switch 102 is less than or equal to the turn-on threshold Vth_on of the synchronous rectifier switch 102, it is determined that the drain-source voltage Vds satisfies the voltage for turning on the synchronous rectifier switch 102.

[0091] In the above-mentioned synchronous rectification control circuit, the detection circuit 104 compares the drain-source voltage of the synchronous rectification switch and the output voltage of the synchronous rectification circuit, and generates a detection pulse signal. The counting circuit 106 generates a counting pulse signal according to the drain-source voltage, the detection pulse signal and the driving signal provided by the synchronous rectification control circuit to the synchronous rectification switch. The opening control circuit confirms the target opening condition corresponding to the synchronous rectification switch 102 according to the counting pulse signal, and provides a driving signal to the synchronous rectification switch according to the target opening condition and the drain-source voltage to control the opening and closing of the synchronous rectification switch. In the present disclosure, the target opening condition is determined by the counting pulse signal, and the counting pulse signal is determined by the drain-source voltage, the output voltage of the synchronous rectification circuit and the driving signal provided by the synchronous rectification control circuit to the synchronous rectification switch. Thus, the target opening condition is determined according to the fluctuation of the drain-source voltage of the synchronous rectification circuit under different states, ensuring that the synchronous rectification switch 102 is normally opened when the synchronous rectification circuit is in the full load range, while avoiding the problem of oscillation causing the synchronous rectification switch 102 to be opened incorrectly.

[0092] In one embodiment, the first level signal is used to characterize that the drain-source voltage Vds is greater than the output voltage VDD, and the second level signal is used to characterize that the drain-source voltage Vds is less than or equal to the output voltage VDD; the detection circuit 104 is also used to determine that the detection pulse signal Detect_Vds jumps from the second level signal to the first level signal after the drain-source voltage Vds is greater than the output voltage VDD for a preset time. It can be understood that the preset time is greater than the duration of the drain-source voltage Vds greater than the output voltage VDD caused by the jitter burr of the drain-source voltage Vds. By setting the preset time, the false detection caused by the jitter burr of the drain-source voltage Vds can be eliminated, avoiding the problem that the synchronous rectification control circuit 100 sends an erroneous drive signal to the synchronous rectification switch 102, resulting in the malfunction of the synchronous rectification circuit.

[0093] Figure 5 is a schematic diagram of the structure of the detection circuit in some embodiments, see Figure 5 In one embodiment, the detection circuit 104 includes: a comparison module 202 and a delay module 204; the comparison module 202 is used to compare the drain-source voltage Vds and the output voltage VDD and generate a comparison level signal; the delay module 204 is connected to the comparison module 202 and the counting circuit 106 respectively, and is used to output the first level signal when the duration of the comparison level signal representing that the drain-source voltage Vds is greater than the output voltage VDD is greater than or equal to a preset time; the delay module 204 is also used to output the second level signal when the comparison level signal representing that the drain-source voltage Vds is less than or equal to the output voltage VDD is received; wherein the comparison level signal includes any one of the first comparison level signal and the second comparison level signal, that is, a comparison level signal of one level, such as the first comparison level signal or the second comparison level signal, is generated at the same time; the first comparison level signal and the second comparison level signal have opposite levels, that is, one of the first comparison level signal and the second comparison level signal is a high level 1, and the other is a low level 0.

[0094] It can be understood that the delay module 204 is further configured to maintain the level of the detection pulse signal Detect_Vds unchanged when the duration of receiving the comparison level signal indicating that the drain-source voltage Vds is greater than the output voltage VDD is less than a preset time.

[0095] Figure 6 is a circuit diagram of a detection circuit in some embodiments, see Figure 6In one embodiment, the first input terminal of the comparison module 202 is connected to the first input terminal of the delay module 204 for receiving the output voltage VDD; the second input terminal of the comparison module 202 is used to receive the drain-source voltage Vds; the output terminal of the comparison module 202 is connected to the second input terminal of the delay module 204; the output terminal of the delay module 204 is connected to the input terminal of the counting circuit 106.

[0096] See also Figure 6 The comparison module 202 includes a current source I0, a MOS transistor P0, a MOS transistor P1, a MOS transistor P2, a MOS transistor P3, a MOS transistor P4, a MOS transistor N1, a MOS transistor N2, a MOS transistor N3 and a MOS transistor N4, and the delay module 204 includes a MOS transistor P5, a MOS transistor N5 and a capacitor C1; the current source I0 is respectively connected to the control end of the MOS transistor P0, the control end of the MOS transistor P1, the control end of the MOS transistor P2 and the control end of the MOS transistor P4; the first end of the MOS transistor P0 is connected to the first end of the MOS transistor P1, and the second end of the MOS transistor P0 is connected to the current source I0; the first end of the MOS transistor P1 is used as the first input end of the comparison module 202 for receiving the output voltage VDD, and the second end of the MOS transistor P1 is respectively connected to the first end of the MOS transistor N1 and the control end of the MOS transistor N1; the first end of the MOS transistor P2 is used as the second input end of the comparison module 202 for receiving the drain-source voltage Vds, and the second end of the MOS transistor P2 is respectively connected to the control end of the MOS transistor P3 and the control end of the MOS transistor P4. The first end of the MOS transistor N2 is connected to provide a control voltage V1 to the control end of the MOS transistor P3; the first end of the MOS transistor P3 is connected to the first end of the MOS transistor P1, the second end of the MOS transistor P3 is respectively connected to the first end of the MOS transistor N3 and the control end of the MOS transistor N4, and the control voltage V2 is provided to the control end of the MOS transistor N4; the first end of the MOS transistor P4 is connected to the first end of the MOS transistor P1, and the second end of the MOS transistor P4 is connected to the first end of the MOS transistor N4, serving as the output end of the comparison module 202; the second end of the MOS transistor N1 is grounded, the control end of the MOS transistor N2 is connected to the control end of the MOS transistor N1, and the second end of the MOS transistor N2 is grounded; the control end of the MOS transistor N3 is connected to the control end of the MOS transistor N1, and the second end of the MOS transistor N3 is grounded; the second end of the MOS transistor N4 is grounded. The control end of the MOS transistor P5 is connected to the second end of the MOS transistor P4 and one end of the capacitor C1 respectively, and serves as the input end of the delay module 204, and is used to receive the control voltage V3 representing the comparison level signal. The first end of the MOS transistor P5 is connected to the first end of the MOS transistor P1, and the second end of the MOS transistor P5 is connected to the first end of the MOS transistor N5, and serves as the output end of the delay module 204; the control end of the MOS transistor N5 is connected to the control end of the MOS transistor N1, the second end of the MOS transistor N5 is grounded, and the other end of the capacitor C1 is grounded.

[0097] by Figure 6 For example, the working principle of the detection circuit 104 is as follows: the current source I0, the drain-source voltage Vds and the output voltage VDD turn on the MOS transistors P1, P2, P3 and P4. When the drain-source voltage Vds is greater than the output voltage VDD, the control voltage V1 increases. When the control voltage increases to a first voltage, the MOS transistor P3 is turned off; wherein the first voltage is equal to the difference between the absolute value of the output voltage VDD and the turn-on threshold Vth_P3, i.e., VDD-|Vth_P3|, and Vth_P3 is the turn-on threshold of the MOS transistor P3. After the MOS transistor P3 is turned off, the turned-on MOS transistor N3 pulls the control voltage V2 down to 0, and the MOS transistor N4 is turned off. MOS tube P4 starts to charge capacitor C1. After a preset time TH_last delay, capacitor C1 is charged to a second voltage, wherein the second voltage is equal to the difference between the output voltage VDD and the absolute value of the turn-on threshold Vth_P5, i.e., VDD-|Vth_P5|, Vth_P5 is the turn-on threshold of MOS tube P5. MOS tube P5 is turned off, and a detection pulse signal Detect_Vds of a low level 0 is output. When the drain-source voltage Vds is less than the output voltage VDD, the control voltage V1 is pulled down to GND, the control voltage V2 is pulled up to the output voltage VDD, the MOS tube N4 is turned on, the control voltage V3 is pulled down to GND, and a detection pulse signal Detect_Vds of a high level 1 is output. It can be understood that the preset time corresponding to the delay module 204 can be adjusted by selecting different MOS tubes P5.

[0098] See also Figure 6 The detection circuit 104 further includes an inverter INV1 , an input end of the inverter INV1 is connected to an output end of the delay module 204 , and an output end of the inverter INV1 is connected to an input end of the counting circuit 106 .

[0099] Specifically, the input end of the invertor INV1 is connected to the second end of the MOS tube P5, and the output end of the invertor INV1 is connected to the input end of the counting circuit 106. When the drain-source voltage Vds is greater than the output voltage VDD and continues for a preset time, the input end of the invertor INV1 is grounded, and the invertor INV1 outputs a detection pulse signal Detect_Vds of a high level 1; when the drain-source voltage Vds is less than the output voltage VDD, the input end of the invertor INV1 maintains a high level, and the invertor INV1 outputs a detection pulse signal Detect_Vds of a low level 0.

[0100] In one embodiment, the counting pulse signal Condition_Switch includes a first counting pulse signal and a second counting pulse signal with opposite levels; the opening control circuit 108 is pre-configured with a first opening condition Condition1 and a second opening condition Condition2, and the opening control circuit 108 is used to use the first opening condition Condition1 as the target opening condition when the first counting pulse signal is received; and use the second opening condition Condition2 as the target opening condition when the second counting pulse signal is received.

[0101] Among them, the first counting pulse signal represents that the synchronous rectifier switch 102 receives the driving signal for controlling the shutdown of the synchronous rectifier switch 102, and the drain-source voltage Vds meets the shutdown condition of the synchronous rectifier switch 102, the number of jumps of the detection pulse signal Detect_Vds from the first target level signal to the second target level signal meets the target value, and the second counting pulse signal represents that the number of jumps does not meet the target value; one of the first target level signal and the second target level signal is a first level signal, and the other is a second level signal; the first opening condition Condition1 and the second opening condition Condition2 have different restrictions on the change slope of the drain-source voltage Vds; the target value is greater than the number of jumps of the detection pulse signal Detect_Vds from the first target level signal to the second target level signal caused by the burr of the drain-source voltage Vds. By setting the target value, it is possible to further avoid the misdetection caused by the burr of the drain-source voltage Vds, and avoid the problem that the synchronous rectifier control circuit 100 sends an erroneous driving signal to the synchronous rectifier switch 102, resulting in the malfunction of the synchronous rectifier circuit.

[0102] As an example, the target value includes one of 1, 2, 3 and 4. Further, the target value is 3, which avoids malfunction of the synchronous rectification circuit and reduces the cost of the synchronous rectification control circuit 100.

[0103] It can be understood that the slope of the drain-source voltage Vds refers to the rate of change of the drain-source voltage Vds from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectifier switch 102; the first change rate corresponding to the first turn-on condition Condition1 is greater than the first change rate corresponding to the second turn-on condition, that is, Vds needs to reach a larger slope under the first turn-on condition to allow it to be turned on. The setting of the first turn-on condition Condition1 enables the synchronous rectifier switch 102 to be turned on normally when the synchronous rectifier circuit is in a heavy load state, and shields the problem of the synchronous rectifier switch 102 being turned on incorrectly due to resonance. The setting of the second turn-on condition Condition2 enables the synchronous rectifier switch 102 to be turned on normally when the synchronous rectifier circuit is in a no-load state. By configuring the first turn-on condition Condition1 and the second turn-on condition Condition2 in the turn-on control circuit 108, the synchronous rectifier switch 102 is turned on normally when the synchronous rectifier circuit is in a full load range, and avoids the oscillation caused by resonance causing the synchronous rectifier switch 102 to be turned on incorrectly.

[0104] As an example, the time for the drain-source voltage Vds defined by the first turn-on condition Condition1 to drop from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectification switch 102 is less than the first time period, and the time for the drain-source voltage Vds defined by the second turn-on condition Condition2 to drop from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectification switch 102 is less than the second time period; the first time period is less than the second time period, for example, the first time period is 50ns and the second time period is 1us.

[0105] When the target turn-on condition is the first turn-on condition Condition1, when the time for the drain-source voltage Vds of the synchronous rectification switch 102 to drop from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectification switch 102 is less than the first time period, the driving signal SR_PWM provided to the synchronous rectification switch 102 is confirmed according to the relationship between the drain-source voltage Vds and the turn-on threshold Vth_on. When the time for the drain-source voltage Vds of the synchronous rectification switch 102 to drop from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectification switch 102 is greater than the first time period, the driving signal SR_PWM for controlling the synchronous rectification switch 102 to be turned off is provided to the synchronous rectification switch 102.

[0106] When the target turn-on condition is the second turn-on condition Condition2, when the time for the drain-source voltage Vds of the synchronous rectifier switch 102 to drop from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectifier switch 102 is less than the second time period, the drive signal SR_PWM provided to the synchronous rectifier switch 102 is confirmed according to the relationship between the drain-source voltage Vds and the turn-on threshold Vth_on. When the time for the drain-source voltage Vds of the synchronous rectifier switch 102 to drop from the output voltage VDD to the turn-on threshold Vth_on of the synchronous rectifier switch 102 is greater than the second time period, the drive signal SR_PWM for controlling the synchronous rectifier switch 102 to be turned off is provided to the synchronous rectifier switch 102.

[0107] Figure 7 is a schematic diagram of the structure of the counting circuit in some embodiments, see Figure 7 In one embodiment, the counting circuit 106 includes a counting module 206 and a signal generating module 208 .

[0108] The counting module 206 is connected to the detection circuit 104, and is used to count the number of jumps of the detection pulse signal Detect_Vds from the first target level signal to the second target level signal, and compare the number of jumps of the detection pulse signal Detect_Vds with the target value, and generate a comparison signal according to the comparison result; one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal.

[0109] It can be understood that the levels of the comparison signal indicating that the number of transitions is equal to the target value and the comparison signal indicating that the number of transitions is less than the target value are opposite.

[0110] The signal generating module 208 is connected to the counting module 206 and the switching control circuit 108 respectively, and is used for receiving a comparison signal, generating a counting pulse signal Condition_Switch according to the comparison signal, and sending the counting pulse signal Condition_Switch to the switching control circuit 108 .

[0111] See also Figure 7In one embodiment, the counting circuit 106 further includes a reset module 210; a first input end of the reset module 210 is used to receive a drive signal SR_PWM, a second input end of the reset module 210 is used to receive a drain-source voltage Vds of the synchronous rectifier switch 102, and an output end of the reset module 210 is respectively connected to the counting module 206 and the signal generating module 208; wherein the reset module 210 is used to generate a reset signal when receiving a drive signal SR_PWM for controlling the conduction of the synchronous rectifier switch 102 and / or the drain-source voltage Vds satisfies the turn-on condition of the synchronous rectifier switch 102, and the reset signal is used to reset the number of jumps of the counting module 206; the signal generating module 208 is also used to generate the counting pulse signal Condition_Switch according to the comparison signal and the reset signal.

[0112] The drain-source voltage Vds satisfies the on-condition of the synchronous rectifier switch 102, which means that the drain-source voltage Vds is less than the on-threshold value Vth_on of the synchronous rectifier switch 102. The reset signal resets the number of transitions, which means that the number of transitions is reset to zero.

[0113] Figure 8 is a circuit diagram of a counting circuit in some embodiments, see Figure 8 In one embodiment, the counting module 206 includes: a plurality of D flip-flops and an AND gate F1 connected in sequence corresponding to the target value.

[0114] The reverse output terminal QN of each D flip-flop is connected to the input terminal D of the D flip-flop, and the same-direction output terminal Q of the previous D flip-flop is connected to the clock signal terminal C of the next D flip-flop; the clock signal terminal C of the first D flip-flop is connected to the output terminal of the detection circuit 104; the reset terminals of the multiple D flip-flops are respectively connected to the output terminals of the reset module 210, and the same-direction output terminals Q of the multiple D flip-flops are respectively connected to the multiple input terminals of the AND gate F1; the levels of the reverse output terminal QN and the same-direction output terminal Q of the D flip-flop are opposite; when the detection pulse signal Detect_Vds jumps from the first target level signal to the second target level signal, the same-direction output terminal Q of the first D flip-flop outputs a signal with the same level as the input terminal of the first D flip-flop.

[0115] The input terminal D and the reverse output terminal QN of the same D flip-flop are connected, and the first D flip-flop is a D flip-flop in which there is no clock signal terminal C connected to the same-direction output terminal Q of another D flip-flop among multiple sequentially connected D flip-flops.

[0116] The AND gate F1 is used to generate a first comparison signal indicating that the number of transitions meets the target value when the same-direction output terminals Q of the D flip-flops output signals of the same level, and the AND gate F1 is also used to generate a second comparison signal indicating that the number of transitions does not meet the target value when the same-direction output terminals Q of the D flip-flops output signals of different levels. The output terminal of the AND gate F1 is connected to the signal generation module 208 to output the first comparison signal or the second comparison signal to the signal generation module 208.

[0117] The comparison signal includes a first comparison signal and a second comparison signal with opposite levels; the signal generation module 208 is further used to generate a counting pulse signal according to the comparison signal and a reset signal.

[0118] See also Figure 8 In one embodiment, the counting module 206 further includes an inverter INV2, an input end of the inverter INV2 is connected to an output end of the detection circuit 104, and an output end of the inverter INV2 is connected to a clock signal end C of the first D flip-flop in the counting module 206.

[0119] See also Figure 8 In one embodiment, the signal generating module 208 includes: an RS trigger RS1; a reset input terminal R of the RS trigger RS1 is connected to the output terminal of the counting module 206 to receive the comparison signal output by the counting module 206, that is, to receive the first comparison signal or the second comparison signal; a set input terminal S of the RS trigger RS1 is connected to the output terminal of the reset module 210 to receive the reset signal RESET output by the reset module 210 or to receive a level signal opposite to the reset signal RESET; and a reverse output terminal QN of the RS trigger is used to output the counting pulse signal Condition_Switch.

[0120] See also Figure 8In one embodiment, the reset module 210 includes: a NOR gate F2, a comparison unit and an NOR gate INV3; the first input end of the NOR gate F2 serves as the first input end of the reset module 210 to receive the drive signal SR_PWM; the output end of the NOR gate F2 is connected to the counting module 206. The first input end of the comparison unit serves as the second input end of the reset module 210 to receive the drain-source voltage Vds of the synchronous rectifier switch 102, and the second input end of the comparison unit is used to receive the turn-on threshold Vth_on of the synchronous rectifier switch 102; the output end of the comparison unit is connected to the second input end of the NOR gate F2, and the comparison unit is used to compare the drain-source voltage Vds and the turn-on threshold Vth_on, and output the comparison result to the second input end of the NOR gate F2. The input end of the NOT gate INV3 is connected to the output end of the NOR gate F2, and the output end of the NOT gate INV3 is connected to the set end S of the RS trigger; wherein, the output end of the NOR gate F2 serves as the output end connecting the reset module 210 and the counting module 206, and the output end of the NOT gate INV3 serves as the output end connecting the reset module 210 and the signal generating module 208, and the reset module 210 provides reset signals with opposite levels to the counting module 206 and the signal generating module 208 respectively, that is, the reset signal provided by the output end of the NOR gate F2 to the counting module 206 and the reset signal provided by the output end of the NOR gate INV3 to the signal generating module 208 are of opposite levels.

[0121] by Figure 8Taking the counting circuit of the counting circuit 106 as an example, the working principle of the counting circuit 106 is exemplarily described. It is assumed that the driving signal SR_PWM for controlling the conduction of the synchronous rectifier switch 102 is 0, and when the drain-source voltage Vds is less than Vth_on, the drain-source voltage Vds satisfies the turn-on condition of the synchronous rectifier switch 102, and the target value is 3. The counting module 206 includes a D flip-flop D1 and a D flip-flop D2. The D flip-flops D1 and D2 work at the falling edge of the signal received at the clock terminal C, and the first target level signal is a low level 0, and the second target level signal is a high level 1. When the driving signal SR_PWM is 0 and the drain-source voltage Vds is greater than Vth_on, the output end of the NOR gate F2 in the reset module 210 provides a reset signal of a high level 1 to the reset end of the D flip-flop in the counting module 206, and the output end of the invertor INV3 in the reset module 210 provides a reset signal of a high level 1 to the set input end S of the RS flip-flop RS1 in the signal generating module 208. Provide a reset signal of low level 0; when the detection pulse signal Detect_Vds received by the invertor INV2 in the counting module 206 jumps from 0 to 1 (the rising edge of the detection pulse signal Detect_Vds is detected), the counting circuit 106 starts to count the number of jumps, and as the number of times the detection pulse signal Detect_Vds jumps from 0 to 1 increases, the D flip-flops D1 and D flip-flops D2 work in sequence, and when the detection pulse signal Detect_Vds is detected to jump from 0 to 1 for the third time, the AND gate F1 in the counting module 206 provides a first comparison signal of high level 1 to the reset input terminal R of the RS flip-flop RS1 in the signal generating module 208, and the RS flip-flop RS1 in the signal generating module 208 outputs a counting pulse signal Condition_Switch of high level 1 according to the reset signal of low level 0 of the set input terminal S and the first comparison signal of high level 1 of the reset input terminal R. During the process of counting the number of transitions by the counting circuit 106, once the driving signal SR_PWM=1 and / or the drain-source voltage Vds is less than Vth_on, the output end of the NOR gate F2 in the reset module 210 provides a reset signal of low level 0 to the reset end of the D flip-flop (D1 and D2) in the counting module 206, and the output end of the NOR gate INV3 in the reset module 210 provides a reset signal of high level 1 to the set input end S of the RS flip-flop RS1 in the signal generating module 208, and the counting circuit 106 resets the number of transitions to 0, and the counting circuit 106 outputs a counting pulse signal Condition_Switch of low level 0. The opening control circuit 108 determines the target opening condition corresponding to the synchronous rectification switch 102 according to the level of the received counting pulse signal, and provides the driving signal SR_PWM to the synchronous rectification switch 102 according to the target opening condition and the drain-source voltage Vds.

[0122] Fig. 9is a schematic diagram of the structure of the opening control circuit in some embodiments, see Fig. 9 In one embodiment, the opening control circuit 108 includes: a selection module 212 and a drive generation module 214.

[0123] The input end of the selection module 212 is connected to the output end of the counting circuit 106, and the selection module 212 is pre-configured with a first turn-on condition Condition1 and a second turn-on condition Condition2, and is used for the selection module 212 to determine the target turn-on condition in the first turn-on condition Condition1 and the second turn-on condition Condition2 according to the counting pulse signal Condition_Switch. Through the selection module 212, the target turn-on condition corresponding to the first turn-on condition Condition1 and the second turn-on condition Condition2 and the counting pulse signal Condition_Switch can be selected, so as to avoid the problem that a single turn-on condition causes the synchronous rectification switch 102 to be turned on normally when the synchronous rectification circuit is in a no-load state, or the synchronous rectification switch 102 in the synchronous rectification circuit is turned off, and the oscillation caused by the resonance causes the synchronous rectification switch 102 to be turned on by mistake.

[0124] The drive generation module 214 is connected to the selection module 212 and the synchronous rectification switch 102, respectively, and is used to generate a drive signal SR_PWM according to the target gating condition, the drain-source voltage Vds, and the turn-on threshold Vth_on of the synchronous rectification switch 102. The drive generation module 214 generates a drive signal SR_PWM for controlling the synchronous rectification switch 102 to turn on when the time when the drain-source voltage Vds drops from the output voltage VDD to the turn-on threshold Vth_on satisfies the target gating condition and the drain-source voltage Vds is less than the turn-on threshold Vth_on.

[0125] Fig.10 FIG. 1 is a circuit diagram of an opening control circuit in some embodiments, see Fig.10In one embodiment, the selection module 212 includes an invertor INV4, an AND gate F3 and an AND gate F4; the input end of the invertor INV4 and the first input end of the AND gate F4 are connected to the output end of the counting circuit 106 to receive the counting pulse signal Condition_Switch, and the input end of the invertor INV4 is connected to the first input end of the AND gate F3; the second input end of the AND gate F3 is pre-configured with one of the first opening condition Condition1 and the second opening condition Condition2, and the output end of the AND gate F3 is connected to the driving generation module 214; the second input end of the AND gate F4 is pre-configured with the other opening condition Condition1 and the second opening condition Condition2 condition, and the output end of the AND gate F4 is connected to the drive generating module 214; wherein, when the counting pulse signal Condition_Switch is at a low level 0, the AND gate F3 provides the driving generating module 214 with the turn-on condition pre-configured at the second input end of the AND gate F3 as the target turn-on condition, that is, a pulse signal corresponding to the turn-on condition pre-configured at the second input end of the AND gate F3 is provided to the driving generating module 214; when the counting pulse signal Condition_Switch is at a high level 1, the AND gate F4 provides the driving generating module 214 with the turn-on condition pre-configured at the second input end of the AND gate F4 as the target turn-on condition, that is, a pulse signal corresponding to the turn-on condition pre-configured at the second input end of the AND gate F4 is provided to the driving generating module 214.

[0126] As an example, the second input terminal of the AND gate F3 is pre-configured with the first opening condition Condition1, and the second input terminal of the AND gate F4 is pre-configured with the second opening condition Condition2. At this time, when the counting pulse signal Condition_Switch is at a low level of 0, the AND gate F3 provides the first turn-on condition Condition1 as the target turn-on condition to the drive generation module 214, that is, provides the drive generation module 214 with a pulse signal corresponding to the first turn-on condition Condition1, and satisfies the first turn-on condition Condition1 when the drain-source voltage Vds drops from VDD to Vth_on, and provides a pulse signal of a high level 1, otherwise, provides a pulse signal of a low level 0; when the counting pulse signal Condition_Switch is at a high level of 1, the AND gate F4 provides the second turn-on condition Condition2 as the target turn-on condition to the drive generation module 214, that is, provides the drive generation module 214 with a pulse signal corresponding to the second turn-on condition Condition2, and satisfies the second turn-on condition Condition2 when the drain-source voltage Vds drops from VDD to Vth_on, and provides a pulse signal of a high level 1, otherwise, provides a pulse signal of a low level 0.

[0127] Continue to see Fig.10 In one embodiment, the drive generation module 214 includes an AND gate F5, an AND gate F6, an OR gate F7, an RS flip-flop RS2, a first comparison unit, and a second comparison unit; wherein the first input terminal of the AND gate F5 is connected to the output terminal of the AND gate F3, the second input terminal of the AND gate F5 is connected to the output terminal of the first comparison unit, and the output terminal of the AND gate F5 is connected to the first input terminal of the OR gate F7; the first input terminal of the AND gate F6 is connected to the second input terminal of the AND gate F5, the second input terminal of the AND gate F6 is connected to the output terminal of the AND gate F4, and the output terminal of the AND gate F6 is connected to the second input terminal of the OR gate F7; the output terminal of the OR gate F7 is connected to the set input terminal S of the RS flip-flop RS2; the reset input terminal R of the RS flip-flop RS2 is connected to the output terminal of the second comparison unit, and the same-direction output terminal Q of the RS flip-flop RS2 is connected to the reset input terminal R of the RS flip-flop RS2. and connected to the synchronous rectification switch 102 to provide a driving signal SR_PWM to the synchronous rectification switch 102; a first input end of the first comparison unit is used to receive a drain-source voltage Vds of the synchronous rectification switch 102, a second input end of the first comparison unit is used to receive a turn-on threshold Vth_on of the synchronous rectification switch 102, and the first comparison unit is used to compare the drain-source voltage Vds with the turn-on threshold Vth_on; a first input end of the second comparison unit is used to receive the drain-source voltage Vds of the synchronous rectification switch 102, a second input end of the second comparison unit is used to receive a turn-off threshold Vth_off of the synchronous rectification switch 102, and the turn-off threshold Vth_off is greater than the turn-on threshold Vth_on; the second comparison unit is used to compare the drain-source voltage Vds with the turn-off threshold Vth_off.

[0128] When the drain-source voltage Vds is less than the turn-on threshold Vth_on, the first comparison unit provides a high level 1 to AND gates F5 and F6, and AND gates F5 and F6 provide a level signal obtained according to the target turn-on condition to the set input terminal S of the trigger RS2; when the drain-source voltage Vds is greater than the turn-off threshold Vth_off, the second comparison unit provides a high level 1 to the reset input terminal R of the trigger RS2.

[0129] Fig.11 Schematic diagram of a timing diagram of a drain-source voltage of a synchronous rectification switch and a corresponding signal of a synchronous rectification control circuit in some embodiments, Figure 6 , Figure 8 and Fig.10 As an example, see the circuit diagram of Fig.11In the stage t1-t4, the load of the synchronous rectification circuit is heavy load, and the target turn-on condition corresponding to the synchronous rectification switch is the first turn-on condition Condition1. The synchronous rectification switch is normally turned on or off under the condition that the first turn-on condition Condition1 is satisfied. In the stage t4-t5, the resonance of the synchronous rectification circuit is strengthened. After the moment t5, the drain-source voltage Vds < the turn-on threshold Vth_on. Since the target turn-on condition at this time is the more stringent first turn-on condition Condition1, the synchronous rectification switch 102 will not be turned on by mistake at the moment t5. In the stage t5-t6, after the moment t4, the synchronous rectification circuit enters the light load state. After the drive signal SR_PWM is the low level 0 that controls the turn-off of the synchronous rectification switch 102, the drain-source voltage Vds undergoes multiple cycles of resonant oscillation. After time t5, when the drain-source voltage Vds> the turn-on threshold Vth_on, when the drain-source voltage Vds increases from less than the output voltage VDD to greater than the output voltage VDD for the third time, the counting circuit 106 outputs the count pulse signal Condition_Switch of high level 1, and the turn-on control circuit 108 confirms that the target turn-on condition is switched from the first turn-on condition Condition1 to the loose second turn-on condition Condition2 according to the count pulse signal Condition_Switch of high level 1, the second turn-on condition Condition2, in order to cope with the situation where the load is light, so that the synchronous rectification switch 102 is normally turned on when the load is light. In the t6-t7 stage, the target turn-on condition maintains the second turn-on condition Condition2, and the synchronous rectification switch 102 is normally turned on at time t7. After the driving signal SR_PWM becomes high level 1 at time t7, the counting pulse signal Condition_Switch of the counting circuit 106 is reset to 0 to prevent the synchronous rectification switch 102 from being turned on by mistake due to the resonant oscillation after the subsequent driving signal SR_PWM becomes low level 0.

[0130] Based on the same inventive concept, the embodiment of the present application also provides a vehicle synchronous rectification control method for implementing the above-mentioned synchronous rectification control circuit. The implementation scheme for solving the problem provided by the method is similar to the implementation scheme recorded in the above-mentioned control circuit, so the specific limitations in one or more synchronous rectification control method embodiments provided below can refer to the limitations on the synchronous rectification control circuit above, and will not be repeated here.

[0131] Fig.12 is a flow chart of a synchronous rectification control method in some embodiments, see Figure 3 , Figure 4 , Fig.12 In one embodiment, a synchronous rectification control method is provided for controlling a synchronous rectification switch 102 in a synchronous rectification circuit, the method comprising:

[0132] S102, comparing the drain-source voltage of the synchronous rectification switch with the output voltage of the synchronous rectification circuit, and generating a detection pulse signal.

[0133] Specifically, the detection circuit 104 obtains the drain-source voltage Vds of the synchronous rectification switch 102 and the output voltage VDD of the synchronous rectification circuit, and compares the drain-source voltage Vds of the synchronous rectification switch 102 and the output voltage VDD of the synchronous rectification circuit, and generates a detection pulse signal Detect_Vds; wherein the detection pulse signal Detect_Vds represents the comparison result between the source-drain voltage Vds and the output voltage VDD, including any one of the first level signal and the second level signal, that is, a detection pulse signal Detect_Vds of a level is generated at the same time, and the levels of the first level signal and the second level signal are opposite.

[0134] S104, generating a counting pulse signal according to the detection pulse signal, the drain-source voltage and the driving signal received by the synchronous rectification switch.

[0135] The counting circuit 106 generates a counting pulse signal Condition_Switch according to the detection pulse signal Detect_Vds, the drain-source voltage Vds and the driving signal SR_PWM received by the synchronous rectification switch 102 . The counting pulse signal Condition_Switch is used to determine a target turn-on condition corresponding to the synchronous rectification switch 102 .

[0136] S106, determining a target turn-on condition corresponding to the synchronous rectification switch according to the counting pulse signal.

[0137] Specifically, the turn-on control circuit 108 receives the counting pulse signal Condition_Switch, and determines the target turn-on condition corresponding to the synchronous rectifier switch 102 according to the counting pulse signal Condition_Switch; wherein the target turn-on condition defines the maximum time for the drain-source voltage Vds of the synchronous rectifier switch 102 to change from VDD to Vth_on when the synchronous rectifier switch 102 corresponding to the counting pulse signal Condition_Switch is turned on.

[0138] S108, providing a driving signal to the synchronous rectification switch according to the target turn-on condition and the drain-source voltage.

[0139] Specifically, the on-control circuit 108 generates a drive signal SR_PWM according to the target on-condition and the drain-source voltage Vds, and provides the drive signal SR_PWM to the synchronous rectifier switch 102. It can be understood that when the time for the drain-source voltage Vds of the synchronous rectifier switch 102 to change from VDD to Vth_on is less than the maximum time defined by the target on-condition, it is confirmed that the synchronous rectifier switch 102 meets the on-condition; when the synchronous rectifier switch 102 meets the on-condition and the drain-source voltage Vds of the synchronous rectifier switch 102 is a voltage that satisfies the control of the on-condition of the synchronous rectifier switch 102, the drive signal SR_PWM for controlling the on-condition of the synchronous rectifier switch 102 is provided to the synchronous rectifier switch 102.

[0140] In the above synchronous rectification control method, the drain-source voltage Vds of the synchronous rectification switch 102 is compared with the output voltage VDD of the synchronous rectification circuit, and a detection pulse signal is generated. According to the detection pulse signal, the drain-source voltage and the drive signal received by the synchronous rectification switch, a counting pulse signal is generated, and the target opening condition corresponding to the synchronous rectification switch is determined according to the counting pulse signal, and according to the target opening condition and the drain-source voltage, a drive signal is provided to the synchronous rectification switch to control the opening and closing of the synchronous rectification switch. The target opening condition is determined by the counting pulse signal, and the counting pulse signal is determined by the drain-source voltage, the output voltage of the synchronous rectification circuit and the drive signal provided by the synchronous rectification control circuit to the synchronous rectification switch. Thus, the target opening condition is determined according to the fluctuation of the drain-source voltage of the synchronous rectification circuit under different states, and the synchronous rectification switch 102 is ensured to be normally opened when the synchronous rectification circuit is in the full load range, while avoiding the problem of oscillation causing the synchronous rectification switch 102 to be opened incorrectly.

[0141] In one embodiment, the synchronous rectification control method further includes: after the drain-source voltage Vds is greater than the output voltage VDD for a preset time, determining that the detection pulse signal Detect_Vds jumps from the second level signal to the first level signal; wherein the first level signal is used to characterize that the drain-source voltage Vds is greater than the output voltage VDD, and the second level signal is used to characterize that the drain-source voltage Vds is less than or equal to the output voltage VDD. The preset time is greater than the duration of the drain-source voltage Vds greater than the output voltage VDD caused by the jitter glitch of the drain-source voltage Vds. By setting the preset time, the false detection caused by the jitter glitch of the drain-source voltage Vds can be eliminated, avoiding the problem that the synchronous rectification control circuit 100 sends an erroneous drive signal to the synchronous rectification switch 102, resulting in the malfunction of the synchronous rectification circuit.

[0142] In one embodiment, the counting pulse signal Condition_Switch includes a first counting pulse signal and a second counting pulse signal of opposite levels; the counting pulse signal Condition_Switch is generated according to the detection pulse signal, the drain-source voltage and the drive signal SR_PWM received by the synchronous rectification switch, including: when the synchronous rectification switch 102 receives the drive signal SR_PWM for controlling the shutdown of the synchronous rectification switch 102, and the drain-source voltage Vds satisfies the shutdown condition of the synchronous rectification switch 102, if the number of jumps of the detection pulse signal from the first target level signal to the second target level signal meets the target value, then a first counting pulse signal is generated; if the number of jumps of the detection pulse signal from the first target level signal to the second target level signal does not meet the target value, then a second counting pulse signal is generated;

[0143] The step of determining a target turn-on condition corresponding to the synchronous rectification switch according to the count pulse signal comprises:

[0144] According to the first counting pulse signal, taking the first opening condition as the target opening condition;

[0145] According to the second counting pulse signal, taking the second opening condition as the target opening condition;

[0146] Among them, one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal; the first turn-on condition and the second turn-on condition have different restrictions on the change slope of the drain-source voltage.

[0147] In one of the embodiments, the synchronous rectification control method further includes: generating a reset signal when a drive signal for controlling the conduction of the synchronous rectification switch is received; generating the reset signal when the drain-source voltage satisfies the turn-on condition of the synchronous rectification switch; wherein the reset signal is used to reset the number of jumps.

[0148] The present disclosure also provides a synchronous rectification circuit, including a primary circuit and a secondary circuit, wherein the secondary circuit includes a synchronous rectification switch and the above-mentioned synchronous rectification control circuit.

[0149] Based on the same inventive concept, the present disclosure also provides a synchronous rectification control circuit for providing a drive signal to control a synchronous rectification switch in a flyback power supply circuit, the synchronous rectification control circuit comprising: a detection circuit, a counting circuit and an opening control circuit as in any of the above embodiments; the detection circuit is used to detect the drain-source voltage of the synchronous rectification switch, and compare it with a reference signal to generate a detection pulse signal, wherein the reference signal can be the output voltage of the flyback power supply circuit, or a detection signal or other reference signal proportional to the output voltage; the counting circuit is connected to the detection circuit, and is used to generate a counting pulse signal according to the detection pulse signal and the driving signal, and when the driving signal indicates that the synchronous rectification switch is turned on, the counting pulse signal is cleared and re-counted; the opening control circuit is connected to the counting circuit, and is used to determine the target opening condition corresponding to the synchronous rectification switch according to the counting pulse signal, and provide a driving signal to the synchronous rectification switch according to the target opening condition and the drain-source voltage, and when the counting pulse signal is higher than a preset value, the target opening condition of the synchronous rectification switch is reduced. In one embodiment, reducing the target opening condition of the synchronous rectification switch includes reducing the falling slope of the drain-source voltage of the synchronous rectification switch.

[0150] It can be understood that the reference signal can be the output voltage of the synchronous rectification switch, or it can be a proportional value of the output voltage or other reference value; the target value is greater than the number of jumps of the detection pulse signal from a low level to a high level caused by the glitch of the drain-source voltage Vds, or the number of jumps of the detection pulse signal from a high level to a low level.

[0151] The present disclosure provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above-mentioned synchronous rectification control method when executed by a processor.

[0152] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps of the above-mentioned synchronous rectification control method when executing the computer program.

[0153] A person of ordinary skill in the art can understand that all or part of the processes in the synchronous rectification control method of the above-mentioned embodiment can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0154] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0155] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A synchronous rectification control circuit, connected to a synchronous rectification switch in a synchronous rectification circuit, characterized in that: include: a detection circuit, configured to compare the drain-source voltage of the synchronous rectification switch with the output voltage of the synchronous rectification circuit, and generate a detection pulse signal, wherein the detection pulse signal includes any one of a first level signal and a second level signal, wherein the first level signal and the second level signal have opposite levels; a counting circuit connected to the detection circuit, and configured to generate a counting pulse signal according to the drain-source voltage, the driving signal provided by the synchronous rectification control circuit to the synchronous rectification switch, and the detection pulse signal; The on-control circuit is connected to the counting circuit and is used to determine the target on-condition corresponding to the synchronous rectification switch according to the counting pulse signal, and provide a driving signal to the synchronous rectification switch according to the target on-condition and the drain-source voltage.

2. The synchronous rectification control circuit according to claim 1, characterized in that: The first level signal is used to characterize that the drain-source voltage is greater than the output voltage, and the second level signal is used to characterize that the drain-source voltage is less than or equal to the output voltage; the detection circuit is also used to determine that the detection pulse signal jumps from the second level signal to the first level signal after the drain-source voltage is greater than the output voltage for a preset time.

3. The synchronous rectification control circuit according to claim 2, characterized in that: The detection circuit comprises: A comparison module, used for comparing the drain-source voltage with the output voltage; The delay module is connected to the comparison module and the counting circuit respectively, and is used to output the first level signal after the drain-source voltage is greater than the output voltage for a preset time; and is also used to output the second level signal when the drain-source voltage is less than or equal to the output voltage.

4. The synchronous rectification control circuit according to claim 3, characterized in that: The first input terminal of the comparison module is connected to the first input terminal of the delay module for receiving the output voltage; the second input terminal of the comparison module is used to receive the drain-source voltage; the output terminal of the comparison module is connected to the second input terminal of the delay module; the output terminal of the delay module is connected to the input terminal of the counting circuit.

5. The synchronous rectification control circuit according to claim 1, characterized in that: The counting pulse signal includes a first counting pulse signal and a second counting pulse signal with opposite levels; The opening control circuit is pre-configured with a first opening condition and a second opening condition, and the opening control circuit is used to use the first opening condition as the target opening condition when receiving the first counting pulse signal; When the second counting pulse signal is received, taking the second opening condition as the target opening condition; Wherein, the first counting pulse signal indicates that the synchronous rectifier switch receives a driving signal for controlling the synchronous rectifier switch to turn off, and when the drain-source voltage satisfies the turn-off condition of the synchronous rectifier switch, the number of transitions of the detection pulse signal from the first target level signal to the second target level signal meets the target value, and the second counting pulse signal indicates that the number of transitions does not meet the target value; one of the first target level signal and the second target level signal is a first level signal, and the other is a second level signal; The first turn-on condition and the second turn-on condition have different restrictions on the change slope of the drain-source voltage.

6. The synchronous rectification control circuit according to claim 1, characterized in that: The counting circuit comprises: a counting module, the counting module being connected to the detection circuit, and being used for counting the number of transitions of the detection pulse signal from the first target level signal to the second target level signal, and comparing the number of transitions of the detection pulse signal with a target value, and generating a comparison signal according to the comparison result; one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal; A signal generating module is connected to the counting module and the opening control circuit respectively, and is used to generate the counting pulse signal according to the comparison signal.

7. The synchronous rectification control circuit according to claim 6, characterized in that: The counting circuit also includes: A reset module, wherein a first input terminal of the reset module is used to receive the driving signal, a second input terminal of the reset module is used to receive the drain-source voltage, and an output terminal of the reset module is respectively connected to the counting module and the signal generating module; Among them, the reset module is used to generate a reset signal when receiving a drive signal that controls the conduction of the synchronous rectification switch and / or the drain-source voltage meets the turn-on condition of the synchronous rectification switch, and the reset signal is used to reset the number of jumps of the counting module; the signal generating module is also used to generate the counting pulse signal according to the comparison signal and the reset signal.

8. The synchronous rectification control circuit according to claim 7, characterized in that: The counting module comprises: A plurality of D flip-flops connected in sequence corresponding to the target value, the reverse output end of each D flip-flop is connected to the input end of the D flip-flop, and the same-direction output end of the previous D flip-flop is connected to the clock signal end of the next D flip-flop; the clock signal end of the first D flip-flop is connected to the output end of the detection circuit; the reset ends of the plurality of D flip-flops are respectively connected to the output end of the reset module; the reverse output end and the same-direction output end of the D flip-flop have opposite output levels; when the detection pulse signal jumps from the first target level signal to the second target level signal, the same-direction output end of the first D flip-flop outputs a signal with the same level as the input end; An AND gate, wherein the multiple input terminals of the AND gate are connected to the same-direction output terminals of the multiple D flip-flops, and the output terminal of the AND gate is connected to the signal generating module; used to generate a first comparison signal indicating that the number of transitions meets the target value when the same-direction output terminals of the D flip-flops output signals of the same level, and also used to generate a second comparison signal indicating that the number of transitions does not meet the target value when the same-direction output terminals of the D flip-flops output signals of different levels; The comparison signal includes the first comparison signal and the second comparison signal of opposite levels, and the signal generating module is further used to generate the counting pulse signal according to the comparison signal and the reset signal.

9. The synchronous rectification control circuit according to claim 7, characterized in that: The signal generating module comprises: RS trigger, the reset input terminal of the RS trigger is connected to the output terminal of the counting module, the set input terminal of the RS trigger is connected to the output terminal of the reset module; the reverse output terminal of the RS trigger is used to output the counting pulse signal.

10. The synchronous rectification control circuit according to claim 9, characterized in that: The reset module comprises: A NOR gate, wherein the first input end of the NOR gate is used as the first input end of the reset module; and the output end of the NOR gate is connected to the counting module; A comparison unit, wherein the first input end of the comparison unit serves as the second input end of the reset module, and the second input end of the comparison unit is used to receive the turn-on threshold of the synchronous rectification switch; the output end of the comparison unit is connected to the second input end of the NOR gate, and is used to compare the drain-source voltage with the turn-on threshold; A NOT gate, wherein the input end of the NOT gate is connected to the output end of the NOR gate, and the output end of the NOT gate is connected to the set end of the RS trigger.

11. The synchronous rectification control circuit according to claim 1, characterized in that: The opening control circuit comprises: a selection module, wherein an input end of the selection module is connected to an output end of the counting circuit, the selection module is pre-configured with a first opening condition and a second opening condition, and is used to determine a target opening condition of the first opening condition and the second opening condition according to the counting pulse signal; A drive generation module is connected to the selection module and the synchronous rectification switch respectively, and is used to generate a drive signal according to the target selection condition, the drain-source voltage and the turn-on threshold of the synchronous rectification switch.

12. A synchronous rectification control method for controlling a synchronous rectification switch in a synchronous rectification circuit, characterized in that: The method comprises: Comparing the drain-source voltage of the synchronous rectification switch with the output voltage of the synchronous rectification circuit, and generating a detection pulse signal; the detection pulse signal includes any one of a first level signal and a second level signal, and the first level signal and the second level signal have opposite levels; Generate a counting pulse signal according to the detection pulse signal, the drain-source voltage and the driving signal received by the synchronous rectification switch; Determining a target turn-on condition corresponding to the synchronous rectification switch according to the count pulse signal; A driving signal is provided to the synchronous rectification switch according to the target turn-on condition and the drain-source voltage.

13. The synchronous rectification control method according to claim 12, characterized in that: Also includes: After the drain-source voltage is greater than the output voltage for a preset time, determining that the detection pulse signal jumps from the second level signal to the first level signal; The first level signal is used to represent that the drain-source voltage is greater than the output voltage, and the second level signal is used to represent that the drain-source voltage is less than or equal to the output voltage.

14. The synchronous rectification control method according to claim 12, characterized in that: The counting pulse signal includes a first counting pulse signal and a second counting pulse signal with opposite levels; The step of generating a counting pulse signal according to the detection pulse signal, the drain-source voltage and the driving signal received by the synchronous rectification switch comprises: When the synchronous rectification switch receives a driving signal for controlling the synchronous rectification switch to be turned off, and the drain-source voltage satisfies the turn-off condition of the synchronous rectification switch, if the number of transitions of the detection pulse signal from the first target level signal to the second target level signal meets the target value, a first counting pulse signal is generated; if the number of transitions of the detection pulse signal from the first target level signal to the second target level signal does not meet the target value, a second counting pulse signal is generated; The step of determining a target turn-on condition corresponding to the synchronous rectification switch according to the count pulse signal comprises: According to the first counting pulse signal, taking the first opening condition as the target opening condition; According to the second counting pulse signal, taking the second opening condition as the target opening condition; Among them, one of the first target level signal and the second target level signal is the first level signal, and the other is the second level signal; the first turn-on condition and the second turn-on condition have different restrictions on the change slope of the drain-source voltage.

15. The synchronous rectification control method according to claim 14, characterized in that: Also includes: generating a reset signal when receiving a driving signal for controlling the synchronous rectification switch to be turned on; When the drain-source voltage satisfies a turn-on condition of the synchronous rectification switch, generating the reset signal; The reset signal is used to reset the number of jumps.

16. A synchronous rectification circuit, comprising a primary circuit and a secondary circuit, characterized in that: The secondary circuit includes a synchronous rectification switch and a synchronous rectification control circuit as described in any one of claims 1-11.

17. A synchronous rectification control circuit, used for providing a driving signal to control a synchronous rectification switch in a flyback power supply circuit, characterized in that: The synchronous rectification control circuit includes: A detection circuit, used for detecting the drain-source voltage of the synchronous rectification switch and comparing it with a reference signal to generate a detection pulse signal; a counting circuit connected to the detection circuit, and configured to generate a counting pulse signal according to the detection pulse signal and the drive signal, wherein when the drive signal indicates that the synchronous rectification switch is turned on, the counting pulse signal is reset to zero and counted again; and The turn-on control circuit is connected to the counting circuit, and is used to determine the target turn-on condition corresponding to the synchronous rectification switch according to the counting pulse signal, and provide a driving signal to the synchronous rectification switch according to the target turn-on condition and the drain-source voltage. When the counting pulse signal is higher than a preset value, the target turn-on condition of the synchronous rectification switch is lowered.

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