Power supply circuit and electronic equipment
By designing a power supply circuit in electronic products, using the first detection circuit to detect the voltage drop of the path and controlling the clock frequency of the power management chip by the controller, the problem of poor effect of electronic products when starting at low voltage extreme speed is solved, and a more stable low voltage extreme speed start effect is achieved.
Patent Information
- Application Number
- CN202510053685.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-04-25
AI Technical Summary
Existing electronic products have poor results when starting at low voltage extreme speed, which can easily lead to repeated triggering of undervoltage protection, resulting in abnormal chip status or stuck and unable to start the computer.
A power supply circuit is designed, including a charging connector, a first switch, a charging chip, a battery, a power management chip, a controller, and a first detection circuit. The first detection circuit detects the passage voltage drop between the charger and the input end of the first switch member, and the controller controls the clock frequency of the power management chip according to the detection results, reduces the clock frequency to reduce the working current, and avoids the charged power being unable to meet the power consumption required during the power boot process.
It effectively avoids the problem of repeatedly triggering UVLO when the electronic device starts at low voltage and speed, improves the low voltage and speed start effect of electronic devices, and ensures the stable operation and user experience of the equipment.
Smart Images
Figure CN119891733A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic products, and in particular to a power supply circuit and an electronic device. Background Art
[0002] In related technologies, with the rapid development of mobile Internet, electronic products such as mobile phones have become an indispensable tool in people's lives. In this context, the battery life of electronic products has become increasingly important. In order to meet users' demand for long-term use, related manufacturers have begun to seek various technological innovations to extend battery life.
[0003] Silicon batteries, as a new type of battery technology, are gradually becoming popular. Compared with traditional lithium-ion batteries, silicon batteries have higher energy density, which can extend battery life. However, a characteristic of silicon batteries is that the capacity under low voltage accounts for a high proportion. Therefore, it is necessary to gradually reduce the shutdown voltage point to fully tap the capacity of silicon batteries. Therefore, relevant manufacturers are also committed to the research and development of low-voltage shutdown technology. At the same time as the low-voltage shutdown, in order to ensure the user experience, the startup voltage point is also reduced synchronously. When the charger is plugged in, it is required to start up immediately. By optimizing the system startup process and improving hardware performance, electronic products can be started up in an instant, allowing users to use the functions of electronic products more quickly, improving the user experience.
[0004] However, when the charger plugged into the electronic device is a weak load charger or the charging cable is poor quality and aged, resulting in high impedance, and the startup current is relatively large, at this time, since the charging current is small and the current consumed by the startup is relatively large, it is easy for the charged power to fail to meet the power consumption required during the startup process. Therefore, during the low-voltage ultra-fast startup process, it is likely to cause repeated triggering of the under-voltage protection (Under Voltage Lock Out, UVLO), causing the electronic product to restart repeatedly, which is easy to cause the electronic product chip to be abnormal, or even stuck and unable to start. It can be seen that the existing electronic products have the problem of poor low-voltage ultra-fast startup effect. Summary of the invention
[0005] The present application provides a power supply circuit and an electronic device, which can solve the problem that existing electronic products have poor low-voltage extremely fast starting effect.
[0006] In a first aspect, the present application provides a power supply circuit, the power supply circuit comprising: a charging connector, a first switch, a charging chip, a battery, a power management chip, a controller and a first detection circuit, the charging connector is electrically connected to a first input terminal of the charging chip through the first switch, the first output terminal of the charging chip is electrically connected to the battery, and the second output terminal of the charging chip is electrically connected to the power management chip;
[0007] The first detection end of the first detection circuit is electrically connected to the input end of the first switch element, the second detection end of the first detection circuit is electrically connected to the output end of the first switch element, the output end of the first detection circuit is electrically connected to the controller, and the controller is electrically connected to the power management chip;
[0008] Among them, the first detection circuit is used to detect the path voltage drop between the charger and the input end of the first switch component during the charging process of the power supply circuit based on the charging connector, and the controller is used to control the clock frequency of the power management chip according to the detection result of the first detection circuit.
[0009] In a second aspect, the present application provides an electronic device, comprising the power supply circuit described in the first aspect.
[0010] In the embodiment of the present application, since the first detection circuit can detect the voltage drop in the path between the charger and the charging connector, and the controller can control the clock frequency of the power management chip according to the detection result of the first detection circuit, when the voltage drop in the path is large, it will cause the charging current to be small. Therefore, at this time, the controller can control the clock frequency of the power management chip to decrease, and the working current of the power management chip is positively correlated with the clock frequency. Therefore, reducing the clock frequency of the power management chip can make the working current of the power management chip also decrease synchronously, thereby avoiding the problem that the charged power cannot meet the power consumption required in the startup process, and further avoiding the electronic device to which the power circuit belongs triggering UVLO, so as to improve the low-voltage and extremely fast startup effect of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 is a schematic diagram of the structure of a power supply circuit in an embodiment of the present application;
[0012] Figure 2 is a partial schematic diagram of the connection between the charging connector, the first detection circuit and the power management circuit in an embodiment of the present application;
[0013] Figure 3 It is a partial schematic diagram of the connection between the charging chip, the second detection circuit, the control circuit and the power management circuit in an embodiment of the present application;
[0014] Figure 4 is a waveform diagram of the output voltage of the power button and the voltage change of the enable terminal of the second comparator during the boot process in an embodiment of the present application;
[0015] Figure 5 It is a flow chart of a working principle of a power supply circuit in an embodiment of the present application. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0017] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0018] In the following, in conjunction with the accompanying drawings, a power supply circuit and an electronic device provided in an embodiment of the present application are described in detail through specific embodiments and their application scenarios.
[0019] See also Figure 1 and Figure 2 , the embodiment of the present application provides a power supply circuit, the power supply circuit comprising: a charging connector 110, a first switch 121, a charging chip 130, a battery 140, a power management chip 150, a controller 160 and a first detection circuit 170, the charging connector 110 is electrically connected to the first input terminal 131 of the charging chip 130 through the first switch 121, the first output terminal 132 of the charging chip 130 is electrically connected to the battery 140, and the second output terminal 133 of the charging chip 130 is electrically connected to the power management chip 150;
[0020] The first detection end of the first detection circuit 170 is electrically connected to the input end of the first switch 121, the second detection end of the first detection circuit 170 is electrically connected to the output end of the first switch 121, the output end of the first detection circuit 170 is electrically connected to the controller 160, and the controller 160 is electrically connected to the power management chip 150;
[0021] Among them, the first detection circuit 170 is used to detect the path voltage drop between the charger and the input end of the first switch element 121 during the charging process of the power circuit based on the charging connector 110, and the controller 160 is used to control the clock frequency of the power management chip 150 according to the detection result of the first detection circuit 170.
[0022] The power circuit can be applied to various electronic devices, for example, mobile phones, tablet computers, various smart wearable devices, etc. The power circuit can charge the battery 140 through the charging connector 110, and the power circuit can also power various electrical components in the electronic device.
[0023] The charging connector 110 may be any common charging connector 110, for example, the charging connector 110 may be a Universal Serial Bus Type-C (USB Type-C) connector, a Lightning connector, a Micro USB connector, etc. It is understood that the charging connector 110 may be plugged into an external charging cable, and when the charging connector 110 is plugged into the charging cable, the charging connector 110 may conduct the charging cable and the connected first switch 121.
[0024] The battery 140 may be any type of battery 140, for example, a battery 140 with a high capacity ratio at low voltage, such as a silicon battery 140. In addition, the battery 140 may also be other common batteries 140, such as a lithium battery 140. The charging chip 130 may be any common charging integrated circuit (IC) in various electronic devices. The power management chip 150 may be any common power management chip 150 in electronic devices, wherein the power management chip 150 may be used to control the power-on and power-off states of various devices in the electronic device. The controller 160 may be any control chip in an electronic device, for example, the electronic device may be a central processing unit (CPU).
[0025] The path voltage drop between the above-mentioned charger and the input end of the first switch element 121 may refer to: the difference between the output voltage of the charger and the voltage of the input end of the first switch element 121, that is, the voltage drop of the output voltage of the charger in the charging line, and the charging line is the line connecting the charger and the charging connector 110.
[0026] The first detection circuit 170 may be any detection circuit capable of detecting the voltage drop in the path between the charger and the charging connector 110. When the charger plugged into the electronic device is a weak load charger or the charging cable is poor quality and aged, resulting in a large impedance, the voltage drop in the path between the charger and the input end of the first switch 121 is large. At this time, the charging current is small. If the electronic device is still turned on normally, the charged power may not meet the power consumption required during the startup process, which may cause repeated triggering of UVLO. Based on this, in an embodiment of the present application, the controller 160 is enabled to control the clock frequency of the power management chip 150 according to the detection result of the first detection circuit 170. In this way, when the voltage drop in the path between the charger and the input end of the first switch element 121 is large, the controller 160 can control the clock frequency of the power management chip 150 to decrease, and the working current of the power management chip 150 is positively correlated with the clock frequency. Therefore, reducing the clock frequency of the power management chip 150 can also reduce the working current of the power management chip 150 synchronously, thereby avoiding the problem that the charged power cannot meet the power consumption required in the startup process, and further avoiding the problem of the electronic device to which the power circuit belongs repeatedly triggering UVLO.
[0027] The clock frequency of the power management chip 150 may refer to the number of times the internal clock signal of the power management chip 150 oscillates per second, usually expressed in Hertz (Hz). For example, 1 GHz means 1 billion oscillations per second, 1 MHz means 1 million oscillations per second, and 1 kHz means 1000 oscillations per second. The clock frequency is one of the important indicators for measuring the processing speed of the chip. The higher the frequency, the faster the processing speed is usually. Therefore, when the clock frequency of the power management chip 150 is reduced, the processing speed of the power management chip 150 will also decrease accordingly, and accordingly, the operating current of the power management chip 150 will also decrease accordingly.
[0028] The first switch 121 can be various types of metal-oxide-semiconductor field-effect transistors (MOSFET, MOS for short), or other semiconductor devices with the same function as MOS. In some embodiments of the present application, the first switch 121 is an N-type MOS tube, and the source of the first switch 121 is the input terminal, the drain of the first switch 121 is the input terminal, and the gate of the first switch 121 is the control terminal. The third output terminal 134 of the charging chip 130 is electrically connected to the control terminal of the first switch 121.
[0029] The first switch 121 can reuse the overvoltage protection (OVP) MOS in the power circuit, wherein the power circuit can also detect the voltage at the input end of the first switch 121, and the charging chip 130 is configured to: when the voltage at the input end of the first switch 121 is greater than the preset safety voltage threshold, control the first switch 121 to disconnect, so as to protect the circuit at the rear end of the first switch 121. It can be understood that during the charging process of the power circuit based on the charging connector 110, the first switch 121 is in the on state.
[0030] Specifically, since the full-on impedance of the first switch element 121 is known and fixed, by electrically connecting the first detection end of the first detection circuit 170 to the input end of the first switch element 121, and electrically connecting the second detection end of the first detection circuit 170 to the output end of the first switch element 121, the first detection circuit 170 can detect the input end voltage and the output end voltage of the first switch element 121 based on the first detection end and the second detection end, and can calculate the charging current according to the input end voltage and the output end voltage of the first switch element 121 and the full-on impedance of the first switch element 121. At the same time, since the output of the charger The output voltage can also be known based on the charging request voltage. Therefore, the actual path voltage drop between the charger and the input terminal of the first switch element 121 can be determined based on the difference between the output voltage of the charger and the input terminal voltage of the first switch element 121. In this way, it is possible to subsequently determine whether the charging current is too small and whether the path voltage drop between the charger and the input terminal of the first switch element 121 is too large based on the calculated charging current and the actual path voltage drop. Based on this, the clock frequency of the power management chip 150 is controlled to avoid the problem of repeated triggering of UVLO by the electronic device to which the power circuit belongs.
[0031] In this implementation, since the first detection circuit 170 can detect the path voltage drop between the charger and the charging connector 110, and the controller 160 can control the clock frequency of the power management chip 150 according to the detection result of the first detection circuit 170, when the path voltage drop is large, it will cause the charging current to be small. Therefore, at this time, the controller 160 can control the clock frequency of the power management chip 150 to decrease, and the working current of the power management chip 150 is positively correlated with the clock frequency. Therefore, reducing the clock frequency of the power management chip 150 can also reduce the working current of the power management chip 150 synchronously, thereby avoiding the problem that the charged power cannot meet the power consumption required during the startup process, and further avoiding the electronic device to which the power circuit belongs triggering UVLO, so as to improve the low-voltage and extremely fast startup effect of the electronic device.
[0032] Optionally, the third output terminal 134 of the charging chip 130 is electrically connected to the control terminal of the first switch element 121;
[0033] The first detection circuit 170 includes a first operational amplifier 171, a first resistor 172, a second resistor 173, a third resistor 174, a fourth resistor 175 and a first comparator 1713. The positive electrode of the first operational amplifier 171 is electrically connected to the input end of the first switch 121 through the first resistor 172. One end of the first resistor 172 electrically connected to the input end of the first switch 121 is the first detection end of the first detection circuit 170. The negative electrode of the first operational amplifier 171 is electrically connected to the output end of the first switch 121 through the second resistor 173. The second resistor 173 is electrically connected to the first One end of the output end of the switch element 121 is electrically connected to the second detection end of the first detection circuit 170, the positive electrode of the first operational amplifier 171 is also grounded through the third resistor 174, the fourth resistor 175 is connected in parallel between the negative electrode of the first operational amplifier 171 and the output end of the first operational amplifier 171, the voltage value of the input voltage of the positive electrode of the first comparator 1713 is the actual path voltage drop value, the positive electrode of the first comparator 1713 is electrically connected to the controller 160, wherein the actual path voltage drop value is the voltage difference between the output voltage of the charger and the voltage of the input end of the first switch element 121.
[0034] See also Figure 2 , the input end of the first switch 121 is represented by point a, the output end of the first switch 121 is represented by point b, the output end of the first operational amplifier 171 is represented by point d, and the output end of the first comparator 1713 is represented by point f, wherein the first operational amplifier 171 can be a differential proportional operational amplifier. At this time, the voltage at point a is Ua, the voltage at point b is Ub, and according to the principle of the operational amplifier circuit, the voltage at point d is:
[0035]
[0036] The resistance value of the first resistor 172 is equal to the resistance value of the second resistor 173, the resistance value of the third resistor 174 is equal to the resistance value of the fourth resistor 175, R1 is the resistance value of the first resistor 172, R f1 is the resistance value of the third resistor 174 .
[0037] The full on-resistance of the first switch element 121 is known to be fixed, which is r Q1 , that U a -U b The size of the charging current i busThe size of U a -U b =r Q1 *i bus ; For conventional charging cables, the charging cable path impedance can be assumed to be R bus , the R bus It can also refer to the impedance of the path from the charger output to point a. Then the voltage drop of the path from the charger output to point a is Assume a situation: set the resistors R1 and R f1 , so that We can get U0=U d , that is, the output voltage of the first operational amplifier 171 is the voltage drop of the path from the charger output to point a. The voltage drop of the path is based on the preset R1 and R f1 Therefore, the channel voltage drop can be used as the ideal channel voltage drop from the charger output to point a, that is, the voltage value of the output voltage of the first operational amplifier 171 is the ideal channel voltage drop from the charger to point a.
[0038] At the same time, the first comparator 1713 can compare the ideal channel voltage drop U d The relative size between the actual path pressure drop value, when U d When U is less than the actual channel voltage drop value, the first comparator 1713 can output a high level control signal. d When the voltage drop value is greater than or equal to the actual path voltage drop value, the first comparator 1713 can output a low-level control signal. Based on this, it can be determined whether the path impedance in the charging line is too large through the output result of the first comparator 1713. Specifically, when the first comparator 1713 outputs a high-level control signal, the output voltage of the first operational amplifier 171 is the actual path voltage drop from the charger output to point a is greater than the ideal path voltage drop U d When , it can be determined that the path impedance in the charging line is too large. At this time, the controller 160 can control the clock frequency of the power management chip 150 to decrease.
[0039] In this implementation, the structure of the first detection circuit 170 is designed so that the output voltage of the first operational amplifier 171 is the ideal path voltage drop from the charger to point a, and the relative size between the ideal path voltage drop and the actual path voltage drop is compared by the first comparator 1713. In this way, it is only necessary to determine whether the path impedance in the charging line is too large based on the output signal of the first comparator 1713, so that the controller 160 can control the clock frequency of the power management chip 150 based on the output signal of the first comparator 1713, thereby reducing the risk of repeatedly triggering UVLO during the charging process.
[0040] Optionally, the power supply circuit also includes a voltage output module 176, and the first detection circuit 170 also includes a second operational amplifier 177, a fifth resistor 178, a sixth resistor 179, a seventh resistor 1711 and an eighth resistor 1712, the positive electrode of the second operational amplifier 177 is electrically connected to the output end of the voltage output module 176 through the fifth resistor 178, the output voltage of the output end of the voltage output module 176 is equal to the output voltage of the charger, the negative electrode of the second operational amplifier 177 is electrically connected to the input end of the first switch element 121 through the sixth resistor 179, the negative electrode of the second operational amplifier 177 is also grounded through the seventh resistor 1711, the eighth resistor 1712 is connected in parallel between the positive electrode of the second operational amplifier 177 and the output end of the second operational amplifier 177, and the output end of the second operational amplifier 177 is electrically connected to the positive electrode of the first comparator 1713.
[0041] The voltage output module 176 may be a module in the power management chip 150 or the charging chip 130, wherein the output voltage of the voltage output module 176 may be a charging request voltage, that is, a charger output voltage, and the output voltage of the voltage output module 176 may be determined according to a protocol agreement within the electronic device.
[0042] See also Figure 2 In some embodiments of the present application, the output end of the second operational amplifier 177 is represented by point e. The second operational amplifier 177 can be a differential proportional operational amplifier. According to the principle of the operational amplifier circuit, the voltage at point e is:
[0043]
[0044] The resistance value of the fifth resistor 178 is equal to the resistance value of the sixth resistor 179, the resistance value of the seventh resistor 1711 is equal to the resistance value of the eighth resistor 1712, and R f2 is the resistance value of the seventh resistor 1711, U ref is the output voltage of the output terminal of the voltage output module 176 .
[0045] In some embodiments of the present application, the resistors R2 and Rf2 can be set to be equal to each other, R2 = R f2 , then U e =U ref -U a is the actual path impedance voltage drop from the charger output voltage to point a, so U e As the above actual path pressure drop value. Specifically, if U d <U e, it is considered that the charger's load capacity is insufficient or the data impedance is too large. At this time, after comparison by the first comparator 1713, a high-level control signal is output to the controller 160. The controller 160 notifies the power management chip 150 to reduce the frequency to reduce the startup current and ensure that the startup process does not trigger UVLO, resulting in repeated restarts or more serious problems. In addition, other resistance values can also be set to form different proportional control, which can be adjusted according to actual needs.
[0046] In this embodiment, by designing the structure of the first detection circuit 170, the output voltage of the second operational amplifier 177 is the actual path voltage drop value, and the actual path voltage drop value is obtained by the second operational amplifier 177 through operational amplification calculation based on the output voltage of the voltage output module 176 and the actual voltage at the input end of the first switch element 121. This is beneficial to improve the accuracy of the calculated actual path voltage drop value, and further to improve the accuracy of the result output by the first comparator 1713, so as to avoid the problem of repeated triggering of UVLO during the charging process due to inaccurate actual path voltage drop value.
[0047] Optionally, the resistance value of the first resistor 172 is equal to the resistance value of the second resistor 173, the resistance value of the third resistor 174 is equal to the resistance value of the fourth resistor 175, the resistance value of the fifth resistor 178 is equal to the resistance value of the sixth resistor 179, the resistance value of the seventh resistor 1711 is equal to the resistance value of the eighth resistor 1712, and the resistance value of the fifth resistor 178 is equal to the resistance value of the seventh resistor 1711;
[0048] in, The R f1 is the resistance value of the third resistor 174, R1 is the resistance value of the first resistor 172, and R bus is the resistance value of the charging line connecting the charger and the charging connector 110, the r Q1 is the on-resistance value of the first switch element 121;
[0049] When the output voltage of the first operational amplifier 171 is less than the output voltage of the second operational amplifier 177 , the first comparator 1713 outputs a first level, and the controller 160 controls the clock frequency of the power management chip 150 to decrease.
[0050] Among them, the resistance value of the charging line connecting the charger and the charging connector 110 can be equal to the charging line path impedance Rbus, and the on-resistance value of the first switch element 121 can refer to: when the first switch element 121 is fully turned on, the resistance value between the input end and the output end of the first switch element 121.
[0051] In this implementation mode, it can be seen from the discussion in the above embodiments that when When the output voltage of the first operational amplifier 171 is equal to the voltage drop of the path from the charger output to point a, and since the resistance value of the fifth resistor 178 is equal to the resistance value of the seventh resistor 1711, U e =U ref -U a is the actual path impedance voltage drop from the charger output voltage to point a. Therefore, by using And make the resistance value of the fifth resistor 178 equal to the resistance value of the seventh resistor 1711. In this way, the first comparator 1713 compares the relative size of the output voltage of the first operational amplifier 171 and the output voltage of the second operational amplifier 177 to determine whether the path impedance in the charging line is too large, which helps to simplify the determination process of whether the path impedance in the charging line is too large.
[0052] Optionally, the power supply circuit further includes a second connection circuit 180 and a second detection circuit 190, the second output terminal 133 is electrically connected to the power management chip 150 through the second connection circuit 180, the input terminal of the second detection circuit 190 is electrically connected to the second connection circuit 180, and the output terminal of the second detection circuit 190 is electrically connected to the controller 160;
[0053] The second detection circuit 190 is used to detect the current in the power management chip 150 , and the controller 160 is also used to control the clock frequency of the power management chip 150 according to the detection result of the second detection circuit 190 .
[0054] The current in the power management chip 150 is the system current in the power management chip 150 during the startup process. The second detection circuit 190 can be any detection circuit capable of detecting the current size in the power management chip 150 .
[0055] In this implementation, since the controller 160 can control the clock frequency of the power management chip 150 according to the detection result of the second detection circuit 190, the current in the power management chip 150 can be detected based on the second detection circuit 190. When the current in the power management chip 150 is too large, the clock frequency of the power management chip 150 can be controlled to decrease by the controller 160, thereby avoiding the problem of the electronic device repeatedly triggering the UVLO due to the excessive current in the power management chip 150 when the charging current is small.
[0056] Optionally, the second connection circuit 180 includes a second switch element 181, the second output terminal 133 of the charging chip 130 is electrically connected to the input terminal of the second switch element 181, and the output terminal of the second switch element 181 is electrically connected to the power management circuit;
[0057] The second detection circuit 190 includes a third operational amplifier 191, a ninth resistor 192, a tenth resistor 193, an eleventh resistor 194 and a twelfth resistor 195. The positive electrode of the third operational amplifier 191 is electrically connected to the input end of the second switch element 181 through the ninth resistor 192, the negative electrode of the third operational amplifier 191 is electrically connected to the output end of the second switch element 181 through the tenth resistor 193, the negative electrode of the third operational amplifier 191 is also grounded through the eleventh resistor 194, the twelfth resistor 195 is connected in parallel between the positive electrode of the third operational amplifier 191 and the output end of the third operational amplifier 191, and the output end of the third operational amplifier 191 is electrically connected to the controller 160.
[0058] The second switch 181 may be any type of MOS tube, or other semiconductor devices having the same function as the MOS tube. In some embodiments of the present application, the second switch 181 is an N-type MOS tube, and the source of the second switch 181 is the input terminal, the drain of the second switch 181 is the input terminal, and the gate of the second switch 181 is the control terminal. The third operational amplifier 191 may be a differential ratio operational amplifier.
[0059] See also Figure 3 , add a MOS tube as the second switch 181 on the system power supply VPH path, and similarly collect the voltage across the MOS tube through the third operational amplifier 191 to output a parameter that can characterize the system current. The output end of the third operational amplifier 191 is represented by point D. According to the principle of operational amplifier circuit, the voltage at point D is: Assume that the full on resistance of the second switch element 181 is r Q2 , the system current of the power management circuit is I vph , then the voltage difference between the input and output ends of the second switch element 181 is: U B -U C =r Q2 *I vph , so the system current is: Therefore, as long as the resistor Then the voltage U at the output terminal of the third operational amplifier 191 is D =I vph , when the system current exceeds a certain threshold value I during the startup process pre, the controller 160 notifies the power management chip 150 to reduce the frequency to avoid abnormal startup with large load, causing the system voltage to drop and trigger UVLO, repeated restart and other serious problems. The controller 160 monitors the system current in real time, and when the system power exceeds the set threshold, it reduces the startup current in real time to achieve stable startup, does not trigger UVLO restart, and increases the startup speed as much as possible under the premise of ensuring stability. Moreover, the ratio is adjustable, and whether to trigger the frequency control of the power management chip 150 in advance or later can be adjusted according to actual needs.
[0060] In this embodiment, by designing the structure of the second connection circuit 180 and the second detection circuit 190, the magnitude of the current in the power management chip 150 can be determined according to the output voltage of the third operational amplifier 191, thereby realizing a control process of controlling the clock frequency of the power management chip 150 according to the determined magnitude of the current in the power management chip 150.
[0061] Optionally, the resistance value of the ninth resistor 192 is equal to the resistance value of the tenth resistor 193 , and the resistance value of the eleventh resistor 194 is equal to the resistance value of the twelfth resistor 195 ;
[0062] in, R3 is the resistance value of the ninth resistor 192. f3 is the resistance value of the eleventh resistor 194, and the r Q2 is the on-resistance value of the second switch element 181;
[0063] The detection result of the second detection circuit 190 includes the voltage at the output end of the third operational amplifier 191, and the controller 160 is configured to control the clock frequency of the power management chip 150 to decrease when the voltage at the output end of the third operational amplifier 191 is greater than a first threshold.
[0064] In this implementation mode, it can be seen from the discussion in the above embodiments that when When the voltage U at the output terminal of the third operational amplifier 191 is D =I vph, that is, the voltage value of the output terminal of the third operational amplifier 191 is equal to the current value in the power management chip 150. Therefore, by comparing the voltage value of the output terminal of the third operational amplifier 191 with the first threshold value, it can be determined whether the current in the power management chip 150 is too large. When the voltage of the output terminal of the third operational amplifier 191 is greater than the first threshold value, it can be determined that the current in the power management chip 150 is too large. At this time, the controller 160 can control the clock frequency of the power management chip 150 to decrease to avoid the problem of repeated triggering of UVLO by the electronic device due to excessive current in the power management chip 150 when the charging current is small.
[0065] During the startup process of an electronic device, some power modules may fail to power on due to some reasons, causing the electronic device to get stuck at a certain power-on node. At this time, it is usually necessary for relevant maintenance personnel to disassemble and repair the device before it can be restored. Based on this, the following further improves the structure of the power circuit with some embodiments to avoid such problems.
[0066] Optionally, the power supply circuit also includes a control circuit 200, which is electrically connected to the control end of the second switch element 181, wherein the control circuit 200 is used to detect the power-on status of N power modules of the power management chip 150 during the startup of the electronic device to which the power supply circuit belongs, and the control circuit 200 is also used to control the second switch element 181 to be turned on or off according to the power-on status of the N power modules, where N is an integer greater than 1.
[0067] The N power modules can correspond to the N power units in the electronic device one by one, and when the power module is powered on, it can supply power to the corresponding power unit to start the corresponding power unit. The power unit can be a power device, or a unit composed of two or more power devices.
[0068] It can be understood that the above-mentioned N power modules can be the N power modules that must be powered on during the startup process of the electronic device, that is, only when the N power modules are successfully powered on can the electronic device be successfully started. Conversely, if at least one of the N power modules fails to power on, the electronic device cannot be successfully started.
[0069] In this implementation, since the control circuit 200 can detect the power-on status of the N power modules of the power management chip 150 during the startup process of the electronic device to which the power circuit belongs, when the control circuit 200 detects that there is a power module with an abnormal power-on status during the startup process, the second switch element 181 can be controlled to disconnect and the system power VPH can be powered off and reset, thereby preventing the electronic device from being stuck at a certain power-on node. In this way, even if some power modules fail to power on during the startup process, the system power VPH can also be automatically powered off and reset, that is, it can be automatically restored without the need for relevant maintenance personnel to disassemble the machine, which is beneficial to improving user experience.
[0070] Optionally, the control circuit 200 includes a power button 201, a delay circuit 202, a proportional circuit 203, a NOT gate circuit 204, a second comparator 205, a thirteenth resistor 206 and a fourteenth resistor 207;
[0071] The first output terminal 132 is also grounded through the thirteenth resistor 206 and the fourteenth resistor 207 in sequence, the line connecting the thirteenth resistor 206 and the fourteenth resistor 207 includes a first connection point 208, and the control end of the second switch element 181 is electrically connected to the first connection point 208; the power management chip 150 is configured to: during the process of starting up the electronic device, power on the N power modules in sequence according to the sequence number from small to large;
[0072] Of the two input terminals of the second comparator 205, one is electrically connected to the output terminal of the first power module 209, and the other is electrically connected to the output terminal of the Nth power module 2011; the power button 201 is electrically connected to the enable terminal of the second comparator 205 through the delay circuit 202, the proportional circuit 203 and the NOT gate circuit 204 in sequence, and the output terminal of the second comparator 205 is electrically connected to the first connection point 208.
[0073] The first power module 209 may be the first module to be powered on among the N power modules during the process of starting up the electronic device, and the Nth power module 2011 may be the last module to be powered on among the N power modules during the process of starting up the electronic device. It can be understood that when the power module is powered on successfully, the output end of the corresponding power module can output a high level, and accordingly, when the power module fails to be powered on or has not been powered on, the output end of the corresponding power module can output a low level. In the process of the N power modules being powered on in sequence, if a certain power module fails to be powered on, the other power modules arranged after the power module that failed to be powered on cannot be powered on either, until the power module that failed to be powered on is successfully powered on, that is, among the N power modules, the power-on identification of the other power modules other than the Nth power module 2011 can all cause the Nth power module 2011 to fail to be powered on, so that only when the N power modules are all successfully powered on, the output end of the Nth power module 2011 will output a high level.
[0074] See also Figure 3 In some embodiments of the present application, the control circuit 200 can reuse the second switch element 181 with the second detection circuit 190. During normal startup and standby, the gate drive voltage of the second switch element 181 is Wherein, VBAT is the voltage of the battery 140, the U A By default, the second switch 181 can be driven to be fully turned on, that is, the input and output of the second switch 181 are fully turned on; the second comparator 205 is newly added in this embodiment, and the second comparator 205 can be a comparator with "logic AND". Specifically, when both inputs of the second comparator 205 are input with a high level, the second comparator 205 outputs a high level, and when at least one of the two inputs of the second comparator 205 outputs a low level, the second comparator 205 outputs a low level. The second comparator 205 is enabled by the power key 201 signal pwrkey through the delay circuit 202, the proportional amplifier circuit and the NOT gate. The voltage V1 at the output end of the first power module 209 and the voltage VN at the output end of the Nth power module 2011 are used as the two input voltages of the second comparator 205. When V1 and VN are both high levels, the second comparator 205 outputs a high level, but when one of them is low or both are low levels, the second comparator 205 outputs a low level. At this time, U AThe second switch 181 is pulled low, which disconnects the input and output terminals of the second switch 181, and the system power supply VPH is reset. The power button 201 signal is at a low level when it is pressed to start the machine, that is, the low level is effective. The delay circuit 202 delays the output of the key signal and waits for the power-on to be completed. The proportional circuit 203 amplifies / reduces the key signal level and duration, and then reversely drives the second comparator 205 to start through the NOT gate circuit 204. Figure 4 As shown, when the power button is pressed, the voltage change waveform of the output end of the power button 201 and the enable end of the second comparator 205, wherein Pwrkey is the voltage of the output end of the power button 201, and Pwrkey1 is the voltage of the enable end of the second comparator 205:
[0075] The key pwrkey is pressed for t1 time -> after the delay circuit 202 delays for t2 -> pwrkey1 outputs a high level and lasts for t3 time, wherein the delay time of the delay circuit 202 is longer than the normal startup time of the electronic device;
[0076] In the above process, after t2 time, the second comparator 205 is turned on. If both V1 and VN are powered on, the second comparator 205 outputs a high level, and the second switch element 181 remains turned on. If at least one of V1 and VN is not powered on, the second comparator 205 outputs a low level, the second switch element 181 is disconnected, and the system is powered off. After t3 time, the second comparator 205 is turned off, the second switch element 181 is turned on again, and the system is powered on again.
[0077] In this embodiment, by designing the structure of the control circuit 200, the control circuit 200 can automatically detect whether N power modules are successfully powered on within the normal startup time, that is, detect whether the electronic device is normally powered on, and when at least one power module among the N power modules fails to power on within the set time, the system power VPH can be controlled to power off and reset, thereby preventing the electronic device from getting stuck at a certain power-on node. In this way, even if some power modules fail to power on during the startup process, the system power VPH can also automatically power off and reset, that is, it can automatically recover without the need for relevant maintenance personnel to disassemble the machine, which is conducive to improving user experience.
[0078] It should be noted that the models and operating parameters of each device in the power supply circuit in the embodiment of the present application can be adaptively adjusted as needed to suit different scenarios. For example, the resistors in the power supply circuit can be replaced with variable resistors. In addition, software can also be adjusted to suit different scenarios, making the power supply circuit more flexible.
[0079] See also Figure 5 , Figure 5A schematic diagram of a working principle corresponding to the above power supply circuit is provided for some embodiments of the present application. The working principle of the power supply circuit includes the following steps:
[0080] Insert the charger, that is, connect the charging connector 110 to the charging cable and charge the power circuit;
[0081] Detecting the actual path voltage drop value and the ideal path voltage drop value corresponding to the charging line by the first detection circuit 170, wherein the ideal path voltage drop value and the actual path voltage drop value are the ideal path voltage drop value and the actual path voltage drop value described in the above embodiment;
[0082] When the ideal channel voltage drop is less than the actual channel voltage drop value, the controller 160 notifies the power management chip 150 to reduce the clock frequency to reduce the system current;
[0083] When the ideal path voltage drop is greater than or equal to the actual path voltage drop value, normal charging and the startup process of the electronic device are triggered;
[0084] Determine whether the current in the power management chip 150 is greater than a first threshold based on the second detection circuit 190;
[0085] If the second detection circuit 190 determines that the current in the power management chip 150 is greater than or equal to the first threshold, the controller 160 notifies the power management chip 150 to reduce the clock frequency to reduce the system current;
[0086] If the second detection circuit 190 determines that the current in the power management chip 150 is less than the first threshold, the power on continues;
[0087] Based on the control circuit 200, it is determined whether the N power modules are successfully powered on. If yes, the process ends; if not, the second switch 181 is disconnected by the control circuit 200 to achieve system reset.
[0088] An embodiment of the present application further provides an electronic device, which includes the power supply circuit described in the above embodiment.
[0089] In this implementation, since the electronic device includes the power supply circuit described in the above embodiment, the electronic device can implement each process of the above power supply circuit and has the same beneficial effects, which will not be described again to avoid repetition.
[0090] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.
Claims
1. A power supply circuit, characterized in that: The power circuit comprises: a charging connector, a first switch, a charging chip, a battery, a power management chip, a controller and a first detection circuit, wherein the charging connector is electrically connected to a first input terminal of the charging chip through the first switch, a first output terminal of the charging chip is electrically connected to the battery, and a second output terminal of the charging chip is electrically connected to the power management chip; The first detection end of the first detection circuit is electrically connected to the input end of the first switch element, the second detection end of the first detection circuit is electrically connected to the output end of the first switch element, the output end of the first detection circuit is electrically connected to the controller, and the controller is electrically connected to the power management chip; Among them, the first detection circuit is used to detect the path voltage drop between the charger and the input end of the first switch component during the charging process of the power supply circuit based on the charging connector, and the controller is used to control the clock frequency of the power management chip according to the detection result of the first detection circuit.
2. The power supply circuit according to claim 1, characterized in that: The third output terminal of the charging chip is electrically connected to the control terminal of the first switch element; The first detection circuit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator, wherein the positive electrode of the first operational amplifier is electrically connected to the input end of the first switch component through the first resistor, and one end of the first resistor electrically connected to the input end of the first switch component is the first detection end of the first detection circuit, the negative electrode of the first operational amplifier is electrically connected to the output end of the first switch component through the second resistor, and one end of the second resistor electrically connected to the output end of the first switch component is the second detection end of the first detection circuit, the positive electrode of the first operational amplifier is also grounded through the third resistor, the fourth resistor is connected in parallel between the negative electrode of the first operational amplifier and the output end of the first operational amplifier, the output end of the first operational amplifier is electrically connected to the negative electrode of the first comparator, the voltage value of the input voltage of the positive electrode of the first comparator is an actual path voltage drop value, and the positive electrode of the first comparator is electrically connected to the controller, wherein the actual path voltage drop value is the voltage difference between the output voltage of the charger and the voltage of the input end of the first switch component.
3. The power supply circuit according to claim 2, characterized in that: The power supply circuit also includes a voltage output module, and the first detection circuit also includes a second operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor. The positive electrode of the second operational amplifier is electrically connected to the output end of the voltage output module through the fifth resistor, and the output voltage of the output end of the voltage output module is equal to the output voltage of the charger. The negative electrode of the second operational amplifier is electrically connected to the input end of the first switch element through the sixth resistor, and the negative electrode of the second operational amplifier is also grounded through the seventh resistor. The eighth resistor is connected in parallel between the positive electrode of the second operational amplifier and the output end of the second operational amplifier, and the output end of the second operational amplifier is electrically connected to the positive electrode of the first comparator.
4. The power supply circuit according to claim 3, characterized in that: The resistance value of the first resistor is equal to the resistance value of the second resistor, the resistance value of the third resistor is equal to the resistance value of the fourth resistor, the resistance value of the fifth resistor is equal to the resistance value of the sixth resistor, the resistance value of the seventh resistor is equal to the resistance value of the eighth resistor, and the resistance value of the fifth resistor is equal to the resistance value of the seventh resistor; in, The R f1 is the resistance value of the third resistor, R1 is the resistance value of the first resistor, and R bus is the resistance value of the charging line connecting the charger and the charging connector, the r Q1 is the on-resistance value of the first switch element; When the output terminal voltage of the first operational amplifier is less than the output terminal voltage of the second operational amplifier, the first comparator outputs a first level, and the controller controls the clock frequency of the power management chip to decrease.
5. The power supply circuit according to any one of claims 1 to 4, characterized in that: The power supply circuit further includes a second connection circuit and a second detection circuit, the second output end is electrically connected to the power management chip through the second connection circuit, the input end of the second detection circuit is electrically connected to the second connection circuit, and the output end of the second detection circuit is electrically connected to the controller; The second detection circuit is used to detect the current size in the power management chip, and the controller is also used to control the clock frequency of the power management chip according to the detection result of the second detection circuit.
6. The power supply circuit according to claim 5, characterized in that: The second connection circuit includes a second switch element, the second output end of the charging chip is electrically connected to the input end of the second switch element, and the output end of the second switch element is electrically connected to the power management circuit; The second detection circuit includes a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor, the positive electrode of the third operational amplifier is electrically connected to the input end of the second switch component through the ninth resistor, the negative electrode of the third operational amplifier is electrically connected to the output end of the second switch component through the tenth resistor, the negative electrode of the third operational amplifier is also grounded through the eleventh resistor, the twelfth resistor is connected in parallel between the positive electrode of the third operational amplifier and the output end of the third operational amplifier, and the output end of the third operational amplifier is electrically connected to the controller.
7. The power supply circuit according to claim 6, characterized in that: The resistance value of the ninth resistor is equal to the resistance value of the tenth resistor, and the resistance value of the eleventh resistor is equal to the resistance value of the twelfth resistor; in, R3 is the resistance value of the ninth resistor, f3 is the resistance value of the eleventh resistor, and the r Q2 is the on-resistance value of the second switch element; The detection result of the second detection circuit includes the voltage at the output end of the third operational amplifier, and the controller is configured to control the clock frequency of the power management chip to decrease when the voltage at the output end of the third operational amplifier is greater than a first threshold.
8. The power supply circuit according to claim 6, characterized in that: The power supply circuit also includes a control circuit, which is electrically connected to the control end of the second switch element, wherein the control circuit is used to detect the power-on status of N power modules of the power management chip during the startup process of the electronic device to which the power supply circuit belongs, and the control circuit is also used to control the second switch element to be turned on or off according to the power-on status of the N power modules, and N is an integer greater than 1.
9. The power supply circuit according to claim 8, characterized in that: The control circuit includes a power button, a delay circuit, a proportional circuit, a NOT gate circuit, a second comparator, a thirteenth resistor and a fourteenth resistor; The first output terminal is also grounded through the thirteenth resistor and the fourteenth resistor in sequence, the line connecting the thirteenth resistor and the fourteenth resistor includes a first connection point, and the control end of the second switch is electrically connected to the first connection point; the power management chip is configured to: during the process of starting up the electronic device, power on the N power modules in sequence according to the sequence numbers from small to large; Of the two input terminals of the second comparator, one is electrically connected to the output terminal of the first power module, and the other is electrically connected to the output terminal of the Nth power module; the power button is electrically connected to the enable terminal of the second comparator through the delay circuit, the proportional circuit and the NOT gate circuit in sequence, and the output terminal of the second comparator is electrically connected to the first connection point.
10. An electronic device, characterized in that: A power supply circuit comprising any one of claims 1 to 9.