Dead time regulation and control circuit

Abstract

The invention discloses a dead time regulation and control circuit and a circuit board, which are used for regulating and controlling dead time introduced by a dead time generation circuit to a driving signal, and comprise a signal switching unit, a linear correction unit and a comparison control unit, the comparison control unit feeds back control signals to the linear correction unit and the signal switching unit through an external resistor, and the comparison control unit controls the linear correction unit to output a voltage VC1 and a voltage VC2 which are used for the dead time generation circuit and can be linearly controlled. The comparison control unit controls the signal switching unit to output a level signal S used for controlling the dead zone time generation circuit to switch the working state, and the resistance value of an external resistor of the comparison control unit and the dead zone time introduced by the dead zone time generation circuit are in a linear relation. The comparison control unit is externally connected with a resistor and is matched with the linear correction unit, so that the linear regulation and control of the dead time of the dead time generation circuit in the prior art are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of signal regulation, and in particular to a dead time regulation circuit. Background Art

[0002] In the prior art, such as Figure 1 The dead time generating circuit in Figure 2-3 The dead time sequence diagram shows that the dead time generating circuit introduces dead time to the rising edge of the input signal Vin1 or the falling edge of the input signal Vin2 by switching the working state by inputting a high level or a low level to the input terminal S. The input signals of the input terminals Vin1 and Vin2 are the same, and the control voltages Vc1 and Vc2 are used to control the corresponding delay times Td1 and Td2. However, the control voltages Vc1 and Vc2 are in a negative power exponential relationship with the delay times Td1 and Td2, not a linear relationship. Therefore, it will have a negative impact on the dead time control. For example, within a certain control voltage value range, the dead time fluctuates violently with the control voltage, and the output signal that meets the requirements cannot be obtained. The dead time is of great significance to the normal operation of the active clamp resonant circuit. Especially in the active clamp forward converter, due to the fluctuation of the external component parameters, the resonance time of the clamp circuit is also different. If the dead time cannot be flexibly adjusted according to the actual situation, the main switch in the power stage circuit cannot achieve zero voltage switching. Therefore, it is urgently needed to be able to calibrate the relationship between the control voltages Vc1, Vc2 and the delay times Td1, Td2 into a linear relationship to realize a dead time control circuit of linear control. Summary of the invention

[0003] In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a dead time control circuit, which realizes linear control of the dead time of the dead time generating circuit in the prior art by connecting an external resistor to the comparison control unit and cooperating with the linear correction unit.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] A dead time control circuit is used to control the dead time introduced by a dead time generating circuit to a driving signal, comprising a signal switching unit, a linear correction unit, and a comparison control unit. The comparison control unit feeds back control signals to the linear correction unit and the signal switching unit respectively through external resistors. The comparison control unit controls the linear correction unit to output a voltage VC1 or a voltage VC2 that is used for the dead time generating circuit and can be linearly controlled. The comparison control unit controls the signal switching unit to output a level signal S that is used to control the dead time generating circuit to switch a working state. There is a linear relationship between the resistance value of the external resistor of the comparison control unit and the dead time introduced by the dead time generating circuit.

[0006] In the dead time control circuit, the comparison control unit includes a control terminal RSET, a comparator, and an inverter. The control terminal RSET outputs a voltage to the input terminal of the comparator through an external resistor, and the other input terminal of the comparator inputs a reference voltage Vref. The output terminal of the comparator is connected to the inverter, and the inverter feeds back a control signal to the linear correction unit based on the level signal output by the comparator.

[0007] In the dead time control circuit, the inverter includes a MOS tube MP4, a MOS tube MN4, a current source I3, and a current source I4; the output end of the comparator is respectively connected to the gate of the MOS tube MP4 and the gate of the MOS tube MN4; the source of the MOS tube MP4 is connected to the power supply VCC through the current source I3; the source of the MOS tube MN4 is grounded through the current source I4; the drain of the MOS tube MP4 and the drain of the MOS tube MN4 are respectively connected to the linear correction unit.

[0008] In the dead time control circuit, the linear correction unit includes a MOS transistor MP2, a MOS transistor MN2, a MOS transistor MP3, a MOS transistor MN3, a capacitor C1, and a capacitor C2. The gate of the MOS transistor MN2 is connected to the drain of the MOS transistor MP4, and its source is respectively connected to the drain and gate of the MOS transistor MP2, and its drain is grounded. The drain of the MOS transistor MP2 is the output end of the voltage VC2, and its source is connected to the power supply VCC. The capacitor C1 is connected in parallel between the source and the drain of the MOS transistor MP2. The gate of the MOS transistor MP3 is connected to the drain of the MOS transistor MN4, and its source is respectively connected to the drain and gate of the MOS transistor MN3, and its drain is connected to the power supply VCC. The drain of the MOS transistor MN3 is the output end of the voltage VC1, and its source is grounded. The capacitor C2 is connected in parallel between the source and the drain of the MOS transistor MN3. The signal switching unit is respectively connected to the gate of the MOS transistor MP2 and the gate of the MOS transistor MN3.

[0009] In the dead time control circuit, the signal switching unit includes a NAND gate, a MOS transistor MP1, a MOS transistor MN1, a current source I1, and a current source I2. The gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MP2, the source thereof is respectively connected to the power supply VCC and one end of the current source I1, the drain thereof is respectively connected to one end of the current source I2 and an input end of the NAND gate, the other end of the current source I1 is respectively connected to the drain of the MOS transistor MN1 and the other input end of the NAND gate, the source of the MOS transistor MN1 is grounded, the gate thereof is connected to the gate of the MOS transistor MN3, the other end of the current source I2 is grounded, and the output end of the NAND gate outputs a level signal S for controlling the dead time generating circuit to switch the working state.

[0010] In the dead time control circuit, the inverter further includes a MOS transistor MP5, a MOS transistor MN5, a MOS transistor MP6, and a MOS transistor MN6. The drain of the MOS transistor MN4 is respectively connected to the gate of the MOS transistor MP3, the gate of the MOS transistor MP5, and the gate of the MOS transistor MN5. The source of the MOS transistor MP5 and the source of the MOS transistor MP6 are both connected to the power supply VCC, and the drain thereof is respectively connected to the drain of the MOS transistor MN5, the gate of the MOS transistor MP6, and the gate of the MOS transistor MN6. The source of the MOS transistor MN5 and the source of the MOS transistor MN6 are both grounded, and the drain of the MOS transistor MN6 is respectively connected to the drain of the MOS transistor MP6 and the gate of the MOS transistor MN2.

[0011] In the dead time control circuit, the capacitor C1 and the capacitor C2 are non-polar capacitors.

[0012] In the dead time control circuit, the control terminal RSET is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the reference voltage Vref.

[0013] In the dead time control circuit, the MOS tube MP1, MOS tube MN1, MOS tube MP2, MOS tube MN2, MOS tube MP3, MOS tube MN3, MOS tube MP4, MOS tube MN4, MOS tube MP5, MOS tube MN5, MOS tube MP6, and MOS tube MN6 are all enhancement field effect tubes.

[0014] Beneficial effects:

[0015] The present invention provides a dead time control circuit, which uses the comparison control unit to connect an external resistor and cooperate with the linear correction unit, so that technicians can adjust the resistance value of the external resistor to achieve linear control of the dead time of the dead time generating circuit in the prior art. At the same time, the signal switching unit switches and controls the working state of the dead time generating circuit, thereby achieving linear control of the dead time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of a prior art dead time generating circuit provided by the present invention;

[0017] Figure 2 A rising edge timing diagram of a prior art dead time generating circuit provided by the present invention;

[0018] Figure 3 A falling edge timing diagram of a prior art dead time generating circuit provided by the present invention;

[0019] Figure 4 A circuit diagram of an example 1 of a dead time control circuit provided by the present invention;

[0020] Figure 5 This is a circuit diagram of Example 2 of the dead time control circuit provided by the present invention.

[0021] Explanation of main component symbols: 1-signal switching unit, 2-linear correction unit, 3-comparison control unit, 3.1-inverter. DETAILED DESCRIPTION

[0022] The present invention provides a dead time control circuit and a circuit board. In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] In the description of the present invention, it should be understood that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0024] See also Figure 1-3In the dead zone generating circuit of the prior art, when the input terminal S inputs a high level, the field effect tube M3 is turned on and the field effect tube M4 is turned off. When the square wave signal input by the input terminal Vin1 is in a rising edge transition, the drain of the field effect tube M5 is discharged, and the dead zone generating circuit inverts the square wave signal and introduces a dead zone time Td1; when the input terminal S inputs a low level, the field effect tube M3 is turned off and the field effect tube M4 is turned on. When the square wave signal input by the input terminal Vin2 is in a falling edge transition, the field effect tube M2 is charged. A reverse current is generated during the charging process of the field effect tube M2. The dead zone generating circuit inverts the square wave signal and introduces a dead zone time Td2.

[0025] Therefore, combined with the dead zone generation circuit, the rising edge dead zone time Td1 can be obtained as:

[0026]

[0027] According to the above formulas (1) and (2), VCC is the supply voltage, Vref is the reference voltage, μ n is the mobility of the field effect transistor M5, Cox1 is the gate oxide capacitance of the field effect transistor M5, W1 is the gate width of the field effect transistor M5, L1 is the gate length of the field effect transistor M5, VT1 is the threshold of the field effect transistor M5, and CT1 is the parasitic capacitance of the field effect transistor M5. From the above formulas (1) and (2), it can be seen that K is a constant, and the rising edge dead time Td1 is not linearly related to the control voltage VC1.

[0028] Similarly, the falling edge dead time Td2 is:

[0029]

[0030] According to the above formula (3), VDD is the supply voltage, Vref is the reference voltage, μ p is the mobility of the field effect transistor M2, Cox2 is the gate oxide capacitance of the field effect transistor M2, W2 is the gate width of the field effect transistor M2, L2 is the gate length of the field effect transistor M2, VT2 is the threshold of the field effect transistor M2, and CT2 is the parasitic capacitance of the field effect transistor M2. From the above formulas (1) and (2), it can be seen that K is a constant, and the rising edge dead time Td2 is not linearly related to the control voltage VC2. It can be seen that the dead time generation circuit in the prior art needs to be improved.

[0031] See also Figure 4-5The present invention provides a dead time control circuit for controlling the dead time introduced by the dead time generating circuit to the driving signal, comprising a signal switching unit 1, a linear correction unit 2, and a comparison control unit 3. The comparison control unit 3 feeds back a control signal to the linear correction unit 2 and the signal switching unit 1 respectively through an external resistor, so as to control the linear correction unit 2 to output a voltage VC1 or a voltage VC2 which is used for the dead time generating circuit and can be linearly controlled, and Figure 1 The input terminals VC1 and VC2 of the dead time generating circuit in the embodiment correspond to each other, so as to control the dead time Td1 and Td2 respectively; the signal switching unit 1 is used to control the output of the level signal S for controlling the dead time generating circuit to switch the working state, and the level signal S is input Figure 1 The input terminal S of the dead time generating circuit in the comparison control unit 3 controls the dead time generating circuit to introduce dead time to the rising edge or falling edge of the driving signal through the high and low potential changes of the level signal S. There is a linear relationship between the resistance value of the external resistor of the comparison control unit 3 and the dead time introduced by the dead time generating circuit. The technician can achieve linear control of the dead time Td1 or Td2 by adjusting the resistance value of the external resistor. Preferably, the external resistor mode of the comparison control unit 3 can be pull-up, pull-down or other connection modes with adjustable level to achieve signal control. In addition, the resistor type can be an adjustable resistor, a fixed resistor or other types of resistors according to actual conditions.

[0032] Furthermore, in the dead time control circuit, the comparison control unit 3 includes a control terminal RSET, a comparator, and an inverter 3.1. The control terminal RSET outputs a voltage to the input terminal of the comparator through an external resistor, and the other input terminal of the comparator inputs a reference voltage Vref. The output terminal of the comparator is connected to the inverter 3.1, and the inverter 3.1 feeds back a control signal to the linear correction unit 2 based on the level signal output by the comparator.

[0033] For details, please refer to Example 1. Figure 4 In the dead time control circuit, the inverter 3.1 includes a MOS tube MP4, a MOS tube MN4, a current source I3, and a current source I4. The output end of the comparator is connected to the gate of the MOS tube MP4 and the gate of the MOS tube MN4 respectively. The source of the MOS tube MP4 is connected to the power supply VCC through the current source I3. The source of the MOS tube MN4 is grounded through the current source I4. The drain of the MOS tube MP4 and the drain of the MOS tube MN4 are connected to the linear correction unit 2 respectively, so that the MOS tube MP4 and the MOS tube MN4 constitute an inverter.

[0034] Preferably, the control terminal RSET is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the reference voltage Vref. Taking the input mode of the above comparator as an example, when the input of the control terminal RSET is at a high level, that is, RESET > Vref, the comparator outputs a high level. After the high-level signal passes through the inverter formed by the MOS transistor MP4 and the MOS transistor MN4, the high-level signal is converted into a low-level control signal and fed back to the linear correction unit 2 to achieve circuit control. On the contrary, when the input of the control terminal RSET is at a low level, that is, RESET < Vref, the comparator outputs a low level, and a high-level control signal is fed back to the linear correction unit 2.

[0035] Further, please refer to Figure 4 , the linear correction unit 2 includes an MOS transistor MP2, an MOS transistor MN2, an MOS transistor MP3, an MOS transistor MN3, a capacitor C1, and a capacitor C2. The gate of the MOS transistor MN2 is connected to the drain of the MOS transistor MP4, and its source is respectively connected to the drain and gate of the MOS transistor MP2, and its drain is grounded. The drain of the MOS transistor MP2 is the output terminal of the voltage VC2, and its source is connected to the power supply VCC. The capacitor C1 is connected in parallel between the source and drain of the MOS transistor MP2. The gate of the MOS transistor MP3 is connected to the drain of the MOS transistor MN4, and its source is respectively connected to the drain and gate of the MOS transistor MN3, and its drain is connected to the power supply VCC. The drain of the MOS transistor MN3 is the output terminal of the voltage VC1, and its source is grounded. The capacitor C2 is connected in parallel between the source and drain of the MOS transistor MN3. The signal switching unit 1 is respectively connected to the gate of the MOS transistor MP2 and the gate of the MOS transistor MN3.

[0036] Among them, the MOS transistor MP2, the MOS transistor MN2, and the capacitor C1 constitute the upper half control unit of the linear correction unit for controlling the output of the voltage VC2, and the MOS transistor MP3, the MOS transistor MN3, and the capacitor C2 constitute the lower half control unit of the linear correction unit 2 for controlling the output of the voltage VC2. When the control signal fed back by the comparison control unit 3 is at a high level, the MOS transistor MN2 is turned on, and the MOS transistor MP3 is turned off. The upper half control unit works, and the lower half control unit does not work. The capacitor C1 is charged and outputs the control voltage VC2 to the dead time generation circuit.

[0037] Similarly, when the control signal fed back by the comparison control unit 3 is at a low level, the MOS transistor MP3 is turned on, and the MOS transistor MN2 is turned off. The lower half control unit works, and the upper half control unit does not work. The capacitor C2 is charged and outputs the control voltage VC1 to the dead time generation circuit.

[0038] For further information, see Figure 4 The signal switching unit 1 includes a NAND gate, a MOS transistor MP1, a MOS transistor MN1, a current source I1, and a current source I2. The gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MP2, and its source is respectively connected to the power supply VCC and one end of the current source I1, and its drain is respectively connected to one end of the current source I2 and an input end of the NAND gate. The other end of the current source I1 is respectively connected to the drain of the MOS transistor MN1 and the other input end of the NAND gate. The source of the MOS transistor MN1 is grounded, and its gate is connected to the gate of the MOS transistor MN3. The other end of the current source I2 is grounded. The output end of the NAND gate outputs a level signal S for controlling the dead time generation circuit to switch the working state. The dead time generation circuit introduces a dead time to the rising edge or falling edge of the driving signal according to the high or low state of the level signal S.

[0039] The specific principle is: when the control signal fed back by the comparison control unit 3 is at a high level, the MOS tube MN2 is turned on, the MOS tube MP3 is turned off, and the upper half control unit of the linear correction unit 2 works normally. Correspondingly, the MOS tube MP2 is turned on, and the MOS tube MN3 is turned off. Then the MOS tube MP1 in the signal switching unit is turned on, and the MOS tube MN1 is turned off. The source of the MOS tube MP1 is connected to the power supply VCC, and its drain is the power supply voltage. The current source I1 flows to the MOS tube MN1, and the drain potential of the MOS tube MN1 rises. Therefore, the output of the NOR gate is a low-level signal S.

[0040] Similarly, when the control signal fed back by the comparison control unit 3 is at a low level, the lower half control unit of the linear correction unit 2 works normally, then the MOS tube MP1 in the signal switching unit is turned off, the MOS tube MN1 is turned on, no current flows through the MOS tube MP1, and the drain potential is zero, so the output of the NOR gate is a high level signal S.

[0041] See also Figure 4 , the linearization principle of the dead time control circuit provided by the present invention is as follows:

[0042] When the control terminal RSET input is at a high level, the feedback control signal is at a low level, and the lower half control unit of the linear correction unit 2 works normally, that is, the MOS tube MP3 is in a conducting state, and the MOS tube MN3 is also in a conducting state due to the diode connection mode. The capacitor C2 mainly plays the role of printing voltage fluctuations, so the circuit of the lower half control unit can be simplified to a series circuit consisting of the external resistor R of the control terminal RSET, the MOS tube MP3, and the MOS tube MN3 in a diode connection mode. The resistance of the MOS tube MN3 in the diode connection mode is 1 / gm3, gm3 is the saturation region transconductance of the MOS tube MN3, and the resistance of the MOS tube MP3 is R on3 , then the current flowing through MOS tube MN3 is

[0043]

[0044] Since the MOS tube MN3 is connected in diode mode, the current can also be expressed as:

[0045]

[0046] From the above equations (4) and (5), the voltage VC1 can be calculated as:

[0047]

[0048] Among them, VCC is the power supply voltage, VTN is the threshold voltage of MOS tube MN3, μ n is the electron mobility of the MOS tube MN3, Cox1 is the gate oxide layer capacitance of the MOS tube MN3, W1 and L1 are the gate width and gate length of the MOS tube MN3 respectively.

[0049] Similarly, when the control terminal RSET input is at a low level, the feedback control signal is at a high level, and the upper half of the linear correction unit 2 operates normally, that is, the MOS tube MN2 is in a conducting state, and the MOS tube MP2 is also in a conducting state due to the diode connection mode. Then, the relationship between the voltage Vc2 and the external resistor R is:

[0050]

[0051] The resistance of MOS tube MP2 is 1 / gm2, the resistance of MOS tube MN2 is Ron2, VTP is the threshold voltage of MOS tube MP2, μ p is the electron mobility of the MOS tube MP2, Cox2 is the gate oxide layer capacitance of the MOS tube MP2, and W2 and L2 are the gate width and gate length of the MOS tube MP23 respectively.

[0052] Based on the relationship between the external resistor and the voltage VC1 and the voltage VC2, the dead time control circuit of the present invention is applied to the prior art such as Figure 1 In the dead time generating circuit of the present invention, the dead time will be changed from being controlled by the voltage VC1 / VC2 to being controlled by the external resistor R. It should be noted that in the derivation process of the following equations, the power supply voltage VCC and the reference voltage Vref in the dead time regulating circuit of the present invention and the dead time generating circuit are equal, that is, the same power supply is used.

[0053] Taking the rising edge dead time Td1 as an example, when the control terminal RSET input is at a high level, the feedback control signal is at a low level, and the level signal S output by the signal switching unit is at a low level, the following is obtained:

[0054]

[0055] Where ΔV is the difference between the voltage of the parasitic capacitor CT1 of the field effect transistor M5 before discharge and the comparison voltage of the comparator of the dead time generating circuit, which is equal to VCC-Vref. Substituting equation (6) into equation (8) yields:

[0056]

[0057] In the circuit, if the size of the MOS tube MP3 is large, its on-resistance is very small, and the transconductance gm3 of the MOS tube MN3 connected in the diode mode is also large, the value of the resistance 1 / gm3 is very small. The on-resistance of these two field effect tubes is small relative to the external resistance R, so R3 = Ron3 + 1 / gm3. Therefore, the relationship between the dead time Td1 and the external resistance R can be simplified to:

[0058]

[0059] From equation (10), it can be seen that the relationship between the dead time Td1 and the external resistor R is a linear relationship, and due to the existence of the on-resistance R3, the relationship curve between the dead time Td1 and the external resistor R does not pass through the zero point. The on-resistance R3 determines the minimum value of the adjustment range of the dead time Td1, which is determined by the device parameters of the MOS tube MP3 and the MOS tube MN3.

[0060] Similarly, referring to equation (8) and combining equation (7), the relationship between the dead time Td2 and the external resistor R can be deduced as:

[0061]

[0062] Wherein, CT2 is the parasitic capacitance of the field effect transistor M2 in the dead time generating circuit, R2 is the sum of the on-resistances of the MOS transistor MN2 and the MOS transistor MP2, and the on-resistance R2 determines the minimum value of the adjustment range of the dead time Td2, which is determined by the device parameters of the MOS transistor MP2 and the MOS transistor MN2.

[0063] Embodiment 2, specifically, refer to Figure 5 The inverter 3.1 further includes a MOS transistor MP5, a MOS transistor MN5, a MOS transistor MP6, and a MOS transistor MN6. The drain of the MOS transistor MN4 is respectively connected to the gate of the MOS transistor MP3, the gate of the MOS transistor MP5, and the gate of the MOS transistor MN5. The source of the MOS transistor MP5 and the source of the MOS transistor MP6 are both connected to the power supply VCC. The drains thereof are respectively connected to the drain of the MOS transistor MN5, the gate of the MOS transistor MP6, and the gate of the MOS transistor MN6. The source of the MOS transistor MN5 and the source of the MOS transistor MN6 are both grounded. The drain of the MOS transistor MN6 is respectively connected to the drain of the MOS transistor MP6 and the gate of the MOS transistor MN2. In the second embodiment, two groups of inverters are added to the comparison control unit 3, namely, the first group of inverters composed of the MOS tubes MP5 and MOS tubes MN5 and the second group of inverters composed of the MOS tubes MP6 and MOS tubes MN6, and the feedback control signal is output separately to the MOS tubes MN2 and MOS tubes MP3 of the linear correction unit 2, thereby improving the accuracy of the control signal.

[0064] Preferably, the capacitor C1 and the capacitor C2 are non-polar capacitors.

[0065] Preferably, the MOS transistor MP1, MOS transistor MN1, MOS transistor MP2, MOS transistor MN2, MOS transistor MP3, MOS transistor MN3, MOS transistor MP4, MOS transistor MN4, MOS transistor MP5, MOS transistor MN5, MOS transistor MP6, and MOS transistor MN6 are all enhancement type field effect transistors.

[0066] In summary, this circuit uses the comparison control unit 1 to connect an external resistor and cooperate with the linear correction unit 2, so that technicians can adjust the resistance value of the external resistor to achieve linear regulation of the dead time of the dead time generating circuit in the prior art, and at the same time, the signal switching unit switches and controls the working state of the dead time generating circuit to achieve linear regulation of the dead time.

[0067] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of the present invention, and all these changes or substitutions should fall within the protection scope of the claims attached to the present invention.

Claims

1. A dead time control circuit, characterized in that: The invention is used for regulating the dead time introduced by the dead time generating circuit to the driving signal, and comprises a signal switching unit, a linear correction unit and a comparison control unit. The comparison control unit respectively feeds back control signals to the linear correction unit and the signal switching unit through external resistors. The comparison control unit controls the linear correction unit to output voltages VC1 and VC2 which are used for the dead time generating circuit and can be linearly controlled. The comparison control unit controls the signal switching unit to output a level signal S which is used for controlling the dead time generating circuit to switch the working state. There is a linear relationship between the resistance value of the external resistor of the comparison control unit and the dead time introduced by the dead time generating circuit.

2. The dead time control circuit according to claim 1, characterized in that: The comparison control unit includes a control terminal RSET, a comparator, and an inverter. The control terminal RSET outputs a voltage to the input terminal of the comparator through an external resistor. The other input terminal of the comparator inputs a reference voltage Vref. The output terminal of the comparator is connected to the inverter. The inverter feeds back a control signal to the linear correction unit based on the level signal output by the comparator.

3. The dead time control circuit according to claim 2, characterized in that: The inverter includes a MOS transistor MP4, a MOS transistor MN4, a current source I3, and a current source I4. The output end of the comparator is connected to the gate of the MOS transistor MP4 and the gate of the MOS transistor MN4 respectively. The source of the MOS transistor MP4 is connected to the power supply VCC through the current source I3. The source of the MOS transistor MN4 is grounded through the current source I4. The drain of the MOS transistor MP4 and the drain of the MOS transistor MN4 are connected to the linear correction unit respectively.

4. The dead time control circuit according to claim 3, characterized in that: The linear correction unit includes a MOS transistor MP2, a MOS transistor MN2, a MOS transistor MP3, a MOS transistor MN3, a capacitor C1, and a capacitor C2. The gate of the MOS transistor MN2 is connected to the drain of the MOS transistor MP4, and the source thereof is respectively connected to the drain and the gate of the MOS transistor MP2, and the drain thereof is grounded. The drain of the MOS transistor MP2 is the output end of the voltage VC2, and the source thereof is connected to the power supply VCC. The capacitor C1 is connected in parallel between the source and the drain of the MOS transistor MP2. The gate of the MOS transistor MP3 is connected to the drain of the MOS transistor MN4, and the source thereof is respectively connected to the drain and the gate of the MOS transistor MN3, and the drain thereof is connected to the power supply VCC. The drain of the MOS transistor MN3 is the output end of the voltage VC1, and the source thereof is grounded. The capacitor C2 is connected in parallel between the source and the drain of the MOS transistor MN3. The signal switching unit is respectively connected to the gate of the MOS transistor MP2 and the gate of the MOS transistor MN3.

5. The dead time control circuit according to claim 4, characterized in that: The signal switching unit includes a NAND gate, a MOS transistor MP1, a MOS transistor MN1, a current source I1, and a current source I2. The gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MP2, the source thereof is respectively connected to the power supply VCC and one end of the current source I1, the drain thereof is respectively connected to one end of the current source I2 and an input end of the NAND gate, the other end of the current source I1 is respectively connected to the drain of the MOS transistor MN1 and the other input end of the NAND gate, the source of the MOS transistor MN1 is grounded, the gate thereof is connected to the gate of the MOS transistor MN3, the other end of the current source I2 is grounded, and the output end of the NAND gate outputs a level signal S for controlling the dead time generating circuit to switch the working state.

6. The dead time control circuit according to claim 5, characterized in that: The inverter further includes a MOS transistor MP5, a MOS transistor MN5, a MOS transistor MP6, and a MOS transistor MN6. The drain of the MOS transistor MN4 is respectively connected to the gate of the MOS transistor MP3, the gate of the MOS transistor MP5, and the gate of the MOS transistor MN5. The source of the MOS transistor MP5 and the source of the MOS transistor MP6 are both connected to the power supply VCC. The drains thereof are respectively connected to the drain of the MOS transistor MN5, the gate of the MOS transistor MP6, and the gate of the MOS transistor MN6. The source of the MOS transistor MN5 and the source of the MOS transistor MN6 are both grounded. The drain of the MOS transistor MN6 is respectively connected to the drain of the MOS transistor MP6 and the gate of the MOS transistor MN2.

7. The dead time control circuit according to claim 5, characterized in that: The capacitor C1 and the capacitor C2 are non-polar capacitors.

8. The dead time control circuit according to claim 5, characterized in that: The control terminal RSET is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to a reference voltage Vref.

9. The dead time control circuit according to claim 6, characterized in that: The MOS transistor MP1, MOS transistor MN1, MOS transistor MP2, MOS transistor MN2, MOS transistor MP3, MOS transistor MN3, MOS transistor MP4, MOS transistor MN4, MOS transistor MP5, MOS transistor MN5, MOS transistor MP6, and MOS transistor MN6 are all enhanced field effect transistors.

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