Parameter selection method of EMI suppression circuit and related device

Abstract

The invention discloses a parameter selection method of an EMI suppression circuit and a related device. The EMI suppression circuit is applied to the motor driving circuit comprising an MOS tube, and the EMI suppression circuit comprises a first capacitor and a resistor which are connected in series. The method comprises the following steps: determining a first ringing frequency of a switch node related to the MOS tube in the motor driving circuit in a first state; determining a second ringing frequency of the switch node in the motor drive circuit in a second state; determining a frequency offset factor based on the first ringing frequency and the second ringing frequency; a first target value of the first capacitance and a second target value of the resistance are determined based on the frequency offset factor, the second capacitance, and the first ringing frequency. Therefore, the parameter determination time of the EMI suppression circuit can be greatly shortened, the rectification time of electromagnetic compatibility authentication of a product is reduced, and the competitiveness of the product is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electromagnetic interference suppression, and in particular to a parameter selection method for an EMI suppression circuit and related devices. Background Art

[0002] At present, the suppression of electromagnetic interference in the drive circuit of the motor is usually achieved by connecting an RC buffer circuit in parallel between the source and drain of the MOS (Metal-Oxide-Semiconductor) tube of the drive circuit (between the drain and source). However, the selection of the resistance value and the capacitance value of R and C in the RC buffer circuit is usually achieved by trial and error. That is, after each parameter is selected, on-site testing is carried out in the electromagnetic compatibility laboratory to determine whether the parameter meets the requirements. Since the determination of the final parameter requires repeated tests many times, this will cause a waste of R&D time and testing costs, which is not conducive to product development and may even delay the time for the product to be launched on the market. Summary of the invention

[0003] The embodiments of the present application provide a parameter selection method for an EMI suppression circuit and a related device.

[0004] In a first aspect, an embodiment of the present application provides a parameter selection method for an EMI suppression circuit, wherein the EMI suppression circuit is applied to a motor drive circuit including a MOS tube, and the EMI suppression circuit includes a first capacitor and a resistor connected in series; the method includes: determining a first ringing frequency of a switch node related to the MOS tube in the motor drive circuit in a first state; the motor drive circuit in the first state is not connected to the EMI suppression circuit; determining a second ringing frequency of the switch node in the motor drive circuit in a second state; the MOS tube of the motor drive circuit in the second state is connected in parallel with a second capacitor; determining a frequency offset factor based on the first ringing frequency and the second ringing frequency; determining a first target value of the first capacitor and a second target value of the resistor based on the frequency offset factor, the second capacitor and the first ringing frequency.

[0005] In the above scheme, the first target value of the first capacitor and the second target value of the resistor included in the EMI suppression circuit are determined based on the frequency offset factor, the second capacitor and the first ringing frequency, including: determining the parasitic capacitance of the motor drive circuit in the first state based on the frequency offset factor and the second capacitor; determining the parasitic inductance of the motor drive circuit in the first state based on the parasitic capacitance and the first ringing frequency; determining the first target value of the first capacitor and the second target value of the resistor based on the parasitic capacitance and the parasitic inductance.

[0006] In the above scheme, determining the parasitic capacitance of the motor drive circuit in the first state based on the frequency offset factor and the second capacitance includes: square the frequency offset factor, subtract one, and divide the square by the capacitance value of the second capacitance to obtain the capacitance value of the parasitic capacitance;

[0007] The method of determining the parasitic inductance of the motor drive circuit in the first state based on the parasitic capacitance and the first ringing frequency includes: squaring the product of 2π and the first ringing frequency to obtain a first intermediate value; multiplying the first intermediate value by the capacitance value of the parasitic capacitance to obtain a second intermediate value; and determining the reciprocal of the second intermediate value as the inductance value of the parasitic inductance.

[0008] In the above scheme, the first target value of the first capacitor and the second target value of the resistor based on the parasitic capacitance and the parasitic inductance are determined, including: multiplying the capacitance value of the parasitic capacitor and a first preset parameter as the first target value of the first capacitor; determining the ratio of the parasitic inductance to the parasitic capacitance, and determining the value range of the resistor based on the ratio; and selecting the second target value of the resistor from the value range according to a preset selection condition.

[0009] In the above scheme, the selection condition includes that the second target value selected from the value range is equal to the square root of the ratio.

[0010] In the above scheme, the method also includes: the power of the selected resistor is greater than a target threshold; the target threshold is determined based on a first target value of the first capacitor, a switching frequency of the MOS tube, and a bus voltage applied to the motor drive circuit.

[0011] In the above scheme, the process of determining the second capacitor includes: determining the parasitic capacitance of the MOS tube according to the model of the MOS tube; and multiplying the second preset parameter and the capacitance value of the parasitic capacitance of the MOS tube as the capacitance value of the second capacitor.

[0012] In the above scheme, determining the frequency offset factor based on the first ringing frequency and the second ringing frequency includes: dividing the first ringing frequency by the second ringing frequency to obtain the frequency offset factor.

[0013] In the above scheme, the method also includes: determining the ringing amplitude and ringing frequency of the switch node in the motor drive circuit in the third state; judging whether the ringing amplitude and ringing frequency meet the electromagnetic compatibility certification standard, and if not, recalculating the value of the first capacitor and the value of the resistor of the EMI suppression circuit; wherein the MOS tube in the motor drive circuit in the third state is connected in parallel with the EMI suppression circuit, and the value of the first capacitor of the EMI suppression circuit is the first target value, and the value of the resistor is the second target value.

[0014] In the above scheme, if the motor drive circuit includes: an upper bridge arm and a lower bridge arm, wherein the upper bridge arm includes at least a first MOS transistor; the lower bridge arm includes at least a second MOS transistor corresponding to the first MOS transistor, and the first MOS transistor and the second MOS transistor are connected in series between a positive bus and a negative bus; the switch node is located at the connection between the first MOS transistor and the second MOS transistor; the method further includes: determining the value of a first capacitor and a resistor in the EMI suppression circuit connected in parallel with the second MOS transistor; judging whether the ringing of the switch node of the motor drive circuit in the fourth state meets the electromagnetic compatibility certification standard; the second MOS transistor in the motor drive circuit in the fourth state is connected in parallel with the corresponding EMI suppression circuit; if satisfied, completing the parameter selection of the EMI suppression circuit; if not satisfied, determining the value of a first capacitor and a resistor in the EMI suppression circuit connected in parallel with the first MOS transistor, so that the motor drive circuit is in the fifth state; the first MOS transistor in the motor drive circuit in the fifth state is connected in parallel with the corresponding EMI suppression circuit, and the second MOS transistor is connected in parallel with the corresponding EMI suppression circuit.

[0015] In a second aspect, an embodiment of the present application further provides a parameter selection device for an EMI suppression circuit, comprising:

[0016] A first determination module is used to determine a first ringing frequency of a switch node associated with the MOS transistor in a motor drive circuit in a first state; the motor drive circuit in the first state is not connected to the EMI suppression circuit; and determine a second ringing frequency of the switch node in a motor drive circuit in a second state; the MOS transistor of the motor drive circuit in the second state is connected in parallel with a second capacitor;

[0017] The second determination module is used to determine a frequency shift factor based on the first ringing frequency and the second ringing frequency; and determine a first target value of the first capacitor and a second target value of the resistor based on the frequency shift factor, the second capacitor and the first ringing frequency.

[0018] In the above scheme, the second determination module is specifically used to: determine the parasitic capacitance of the motor drive circuit in the first state based on the frequency offset factor and the second capacitance; determine the parasitic inductance of the motor drive circuit in the first state based on the parasitic capacitance and the first ringing frequency; and determine the first target value of the first capacitance and the second target value of the resistance based on the parasitic capacitance and the parasitic inductance.

[0019] In the above scheme, the second determination module is specifically used to: obtain the capacitance value of the parasitic capacitance by squaring the frequency offset factor, subtracting one, and then dividing the result by the capacitance value of the second capacitor; squaring the product of 2π and the first ringing frequency to obtain a first intermediate value; multiplying the first intermediate value by the capacitance value of the parasitic capacitor to obtain a second intermediate value; and determining the reciprocal of the second intermediate value as the inductance value of the parasitic inductance.

[0020] In the above scheme, the second determination module is specifically used to: multiply the capacitance value of the parasitic capacitor by the first preset parameter as the first target value of the first capacitor; and determine the ratio of the parasitic inductance to the parasitic capacitance, and determine the value range of the resistor based on the ratio; and select the second target value of the resistor from the value range according to a preset selection condition.

[0021] In the above scheme, the second determination module is specifically used to: select the power of the resistor greater than the target threshold; the target threshold is determined based on the first target value of the first capacitor, the switching frequency of the MOS tube and the bus voltage applied to the motor drive circuit.

[0022] In the above solution, the first determination module is specifically used to: determine the parasitic capacitance of the MOS tube according to the model of the MOS tube; and multiply the second preset parameter and the capacitance value of the parasitic capacitance of the MOS tube as the capacitance value of the second capacitor.

[0023] In the above solution, the second determination module is specifically used to: divide the first ringing frequency by the second ringing frequency to obtain the frequency offset factor.

[0024] In the above scheme, the second determination module is specifically used to: determine the ringing amplitude and ringing frequency of the switch node in the motor drive circuit in the third state; judge whether the ringing amplitude and ringing frequency meet the electromagnetic compatibility certification standard, and if not, recalculate the value of the first capacitor and the value of the resistor of the EMI suppression circuit; wherein, the MOS tube in the motor drive circuit in the third state is connected in parallel with the EMI suppression circuit, and the value of the first capacitor of the EMI suppression circuit is the first target value, and the value of the resistor is the second target value.

[0025] In the above scheme, if the motor drive circuit includes: an upper bridge arm and a lower bridge arm, wherein the upper bridge arm includes at least a first MOS transistor; the lower bridge arm includes at least a second MOS transistor corresponding to the first MOS transistor, and the first MOS transistor and the second MOS transistor are connected in series between the positive bus and the negative bus; the switch node is located at the connection between the first MOS transistor and the second MOS transistor; the second determination module is specifically used to: determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the second MOS transistor; judge whether the ringing of the switch node of the motor drive circuit in the fourth state meets the electromagnetic compatibility certification standard; the second MOS transistor in the motor drive circuit in the fourth state is connected in parallel with the corresponding EMI suppression circuit; if satisfied, complete the parameter selection of the EMI suppression circuit; if not satisfied, then determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the first MOS transistor, so that the motor drive circuit is in the fifth state; the first MOS transistor in the motor drive circuit in the fifth state is connected in parallel with the corresponding EMI suppression circuit, and the second MOS transistor is connected in parallel with the corresponding EMI suppression circuit.

[0026] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of any of the methods described above when executed by the processor.

[0027] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the methods described above are implemented.

[0028] The embodiment of the present application provides a parameter selection method for an EMI suppression circuit and a related device. The EMI suppression circuit is applied to a motor drive circuit including a MOS tube, and the EMI suppression circuit includes a first capacitor and a resistor connected in series; the method includes: determining a first ringing frequency of a switch node related to the MOS tube in a motor drive circuit in a first state; the motor drive circuit in the first state is not connected to the EMI suppression circuit; determining a second ringing frequency of the switch node in a motor drive circuit in a second state; the MOS tube of the motor drive circuit in the second state is connected in parallel with a second capacitor; determining a frequency shift factor based on the first ringing frequency and the second ringing frequency; determining a first target value of the first capacitor and a second target value of the resistor based on the frequency shift factor, the second capacitor and the first ringing frequency. In this application, in view of the shortcomings of the above method, the present invention proposes a scientific and fast method for determining the parameters of the RC buffer circuit (i.e., the EMI suppression circuit) of the external MOS tube motor drive circuit, which specifically includes: determining the frequency offset factor according to the ringing frequency of the switch node in the drive circuit without the buffer circuit and the ringing frequency of the switch node in the drive circuit with a parallel capacitor; then, according to this frequency offset factor, the aforementioned parallel capacitor and the ringing frequency of the switch node in the drive circuit without the buffer circuit, the capacitance value and the resistance value in the buffer circuit are calculated. Through the above calculation method, the parameter determination time of the motor drive circuit for the RC buffer circuit in parallel with the MOS tube can be greatly shortened, the rectification time of the electromagnetic compatibility certification of the product can be reduced, and the competitiveness of the product can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 FIG. 1 is a flow chart of a parameter selection method for an EMI suppression circuit provided in an embodiment of the present application. Figure 1 ;

[0030] Figure 2 FIG. 1 is a schematic diagram of the structure of a driving circuit of a brushless motor provided in an embodiment of the present application;

[0031] Figure 3 FIG. 1 is a schematic diagram of the structure of a drive circuit of a brushed motor provided in an embodiment of the present application;

[0032] Figure 4 FIG. 1 is a flow chart of a parameter selection method for an EMI suppression circuit provided in an embodiment of the present application. Figure 2 ;

[0033] Figure 5 FIG. 1 is a flow chart of a parameter selection method for an EMI suppression circuit provided in an embodiment of the present application. Figure 3 ;

[0034] Figure 6 Shown is a schematic diagram of a parameter selection device for an EMI suppression circuit provided in an embodiment of the present application;

[0035] Figure 7 Shown is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] With the advancement of automobile intelligence, the integration of intelligent devices in automobiles is a symbol of automobile intelligence. At this stage, various intelligent devices containing motors such as flip instruments, sliding screens, and ceiling screens are integrated in automobiles, further promoting the development of automobile intelligence and electrification.

[0038] However, with the increase in the number of electronic devices in cars, especially those containing motors, various switches in the drive circuit need to operate continuously to drive the motors to work normally, further increasing the EMI (Electromagnetic Interference) risk of components and bringing further difficulties in the Electro Magnetic Compatibility (EMC) certification of cars and auto parts.

[0039] At present, most automotive motor drive circuits are implemented using MOS tubes (other high-voltage fields may use other switching tubes, such as thyristors, IGBTs, etc.). MOS tubes will generate a lot of EMI problems during the switching process. In order to solve or reduce the EMI interference of motor drive circuits, the current mainstream solutions are: (1) adding a shielding cover or metal casing to the MOS tube circuit to shield the interference source; (2) connecting an RC buffer circuit in parallel at both ends of the MOS (drain and source), and absorbing the high-frequency energy of the MOS tube switching process through the RC buffer circuit, thereby achieving the effect of reducing the EMI of the system.

[0040] However, if the first method is chosen, by blocking the propagation of interference signals on the interference path, this method can mainly solve the problem of radiation interference path, and the conduction interference path is difficult to solve in this way. Moreover, by adding shielding covers and metal shells, the cost of the product will increase, resulting in a waste of resources. If the second method is chosen, since the parasitic parameters of each hardware PCB board are different, the RC parameter values ​​selected for each hardware PCB board must be different. This mainstream approach is mainly implemented through trial and error in parameter configuration. According to the cutoff frequency of the electromagnetic compatibility over-standard frequency point tested, the RC circuit parameter value is selected to filter out this frequency point. After each parameter is selected, it is determined whether the parameter meets the requirements through on-site testing in the electromagnetic compatibility laboratory. Since the cost of electromagnetic compatibility testing is very high, this method will obviously cause a waste of testing costs. At the same time, since there are tens of thousands of matching combination values ​​of R and C, continuous attempts will cause further waste of time and testing costs, which is not conducive to product development. In addition, since it is impossible to determine whether this over-standard frequency point is generated from the motor drive circuit, this method is used to reduce electromagnetic compatibility interference, which plays a small role.

[0041] As mentioned above, connecting the RC buffer circuit in parallel at both ends of the motor-driven MOS tube (between the drain and source) provides a prerequisite for reducing the EMI disturbance of the motor-driven circuit, but how to select the corresponding R and C parameter values ​​according to the actual design of the circuit board. If there is no scientific and fast determination method, it will cause a waste of R&D time and testing costs, which is not conducive to product development and may even delay the time to market for the product.

[0042] Based on this, in order to solve the above problems, the embodiment of the present application provides a scientific and fast method for determining the parameters of the RC buffer circuit of the external MOS tube motor drive circuit, by determining the frequency offset factor according to the ringing frequency of the switch node in the drive circuit without the buffer circuit and the ringing frequency of the switch node in the drive circuit with a parallel capacitor; then, according to this frequency offset factor, the aforementioned parallel capacitor and the ringing frequency of the switch node in the drive circuit without the buffer circuit, the capacitance value and the resistance value in the buffer circuit are calculated. Through the above calculation method, the parameter determination time of the motor drive circuit for the RC buffer circuit in parallel with the MOS tube can be greatly shortened, the rectification time of the product's electromagnetic compatibility certification can be reduced, and the competitiveness of the product can be improved.

[0043] The technical solution provided by the present application is described in detail below with reference to the accompanying drawings and embodiments.

[0044] See also Figure 1, which shows a flow chart of a parameter selection method of an EMI suppression circuit provided in an embodiment of the present application. The EMI suppression circuit is applied to a motor drive circuit including a MOS tube, and the EMI suppression circuit includes a first capacitor and a resistor connected in series. Figure 1 As shown, the method may include:

[0045] Step 101: determining a first ringing frequency of a switch node associated with the MOS transistor in a motor drive circuit in a first state; the motor drive circuit in the first state is not connected to the EMI suppression circuit;

[0046] Step 102: determining a second ringing frequency of the switch node in the motor drive circuit in the second state; the MOS transistor of the motor drive circuit in the second state is connected in parallel with a second capacitor;

[0047] Step 103: Determine a frequency shift factor based on the first ringing frequency and the second ringing frequency;

[0048] Step 104: Determine a first target value of the first capacitor and a second target value of the resistor based on the frequency shift factor, the second capacitor, and the first ringing frequency.

[0049] It should be noted that the motor drive circuit can be found in Figure 2 and Figure 3 .in, Figure 2 FIG. 1 is a schematic diagram of a topological structure of a driving circuit of a brushless motor provided in an embodiment of the present application; Figure 3 The figure shows a topological structure diagram of a driving circuit of a brushed motor provided in an embodiment of the present application. Figure 2 SW1, SW2, SW3 and Figure 3 SW1 and SW2 in Figure 1 The switch node mentioned in the process shown, that is, in the motor drive circuit, the switch node is located between two MOS tubes connected in series. The EMI suppression circuit is also the aforementioned RC buffer circuit. This RC buffer circuit includes a first capacitor C1 and a resistor connected in series. In addition, this RC buffer circuit is connected in parallel with the MOS tube in the motor drive circuit to suppress electromagnetic interference. The parameter selection method of the suppression circuit can be a method for selecting the value of the first capacitor and the value of the resistor in the RC buffer circuit.

[0050] based on Figures 1 to 3, the parameter selection method of the suppression circuit provided in the embodiment of the present application is to determine the first ringing frequency f0 of the switch node associated with the MOS tube when the RC buffer circuit is not set, and to determine the second ringing frequency f1 of the switch node associated with the MOS tube when a second capacitor C2 is connected in parallel at both ends of the MOS tube; then, a frequency shift factor is calculated according to the first ringing frequency and the second ringing frequency, wherein the frequency shift factor can be the quotient obtained by dividing the first ringing frequency by the second ringing frequency, that is, the frequency shift factor m=f0 / f1. After obtaining the frequency shift factor, the value of the first capacitor and the value of the resistor are calculated in combination with the second capacitor and the first ringing frequency, that is, the first target value and the second target value are calculated.

[0051] Here, for step 101 and step 102, the ringing frequency of the switch node of the MOS tube can be measured by an oscilloscope.

[0052] Here, the process of determining the second capacitor C2 includes: determining the parasitic capacitor C0 of the MOS tube according to the model of the MOS tube; and multiplying the second preset parameter and the capacitance value of the parasitic capacitor of the MOS tube as the capacitance value of the second capacitor.

[0053] That is, according to the model of the MOS tube, the specification of the MOS tube is queried to determine the capacitance value of the parasitic capacitor C0 corresponding to the MOS tube, and then the capacitance value of the parasitic capacitor corresponding to the MOS tube is multiplied by the second preset parameter as the capacitance value of the second capacitor. The value range of the second preset parameter can be 3 to 7.

[0054] In some embodiments, Figure 4 As shown, step 103 may include:

[0055] Step 401: determining the parasitic capacitance of the motor drive circuit in the first state based on the frequency offset factor and the second capacitance;

[0056] Step 402: determining a parasitic inductance of the motor drive circuit in the first state based on the parasitic capacitance and the first ringing frequency;

[0057] Step 403: Determine a first target value of the first capacitor and a second target value of the resistor based on the parasitic capacitance and the parasitic inductance.

[0058] Here, step 401 may include: square the frequency offset factor, subtract one from the square, and divide the result by the capacitance value of the second capacitor to obtain the capacitance value of the parasitic capacitor.

[0059] That is, the calculation formula of the parasitic capacitance of the motor drive circuit in the first state is as follows:

[0060]

[0061] Among them, C p is the capacitance value of the parasitic capacitance of the motor drive circuit in the first state.

[0062] Here, for step 402, it can include: squaring the product of 2π and the first ringing frequency to obtain a first intermediate value; multiplying the first intermediate value by the capacitance value of the parasitic capacitor to obtain a second intermediate value; and determining the reciprocal of the second intermediate value as the inductance value of the parasitic inductance.

[0063] That is, the calculation formula of the parasitic inductance of the motor drive circuit in the first state is as follows:

[0064]

[0065] Among them, L p is the inductance value of the parasitic inductance of the motor drive circuit in the first state. (2πf0) 2 is the first intermediate value; (2πf0) 2 *C p is the second intermediate value.

[0066] In some embodiments, step 403 may include: multiplying the capacitance value of the parasitic capacitor by a first preset parameter as a first target value of the first capacitor; determining a ratio of the parasitic inductance to the parasitic capacitance, and determining a value range of the resistance based on the ratio; and selecting a second target value of the resistance from within the value range according to a preset selection condition.

[0067] Here, the value range of the first preset parameter K can be 1 to 3. The first target value of the first capacitor C1 is equal to K*C p The product of .

[0068] For the second target value of the resistor, according to the parasitic inductance L p With the parasitic capacitance C p A ratio of the first and second target values ​​of the resistors; a value range determined according to the ratio, the value range being a value in which the second target value is greater than or equal to the square root of the ratio. Then, a second target value of the resistor is selected from the value range according to a preset selection condition. In an optional embodiment, the selection condition may include that the second target value selected from the value range is equal to the square root of the ratio.

[0069] In some embodiments, the method may further include: the power of the selected resistor is greater than a target threshold; the target threshold is determined based on a first target value of the first capacitor, a switching frequency of the MOS tube, and a bus voltage applied to the motor drive circuit.

[0070] It should be noted that in actual application, the power of the selected resistor must be greater than a certain threshold, that is, greater than the target threshold. Here, the target threshold is determined based on the first target value of the first capacitor, the switching frequency of the MOS tube, and the bus voltage applied to the motor drive circuit. For example, the target threshold is the product of the first target value of the first capacitor, the switching frequency of the MOS tube, and the square of the bus voltage applied to the motor drive circuit. That is, the power of the selected resistor Among them, P R is the power of the selected resistor; is the square of bus voltage; F SW is the switching frequency.

[0071] In some embodiments, the method also includes: determining the ringing amplitude and ringing frequency of the switch node in the motor drive circuit in the third state; judging whether the ringing amplitude and ringing frequency meet the electromagnetic compatibility certification standard, and if not, recalculating the value of the first capacitor and the value of the resistor of the EMI suppression circuit; wherein the MOS tube in the motor drive circuit in the third state is connected in parallel with the EMI suppression circuit, and the value of the first capacitor of the EMI suppression circuit is the first target value, and the value of the resistor is the second target value.

[0072] It should be noted that the technical solution described here is: the above-calculated first target capacitor and the resistor with the second target value are connected in series and then connected in parallel to the MOS tube to form a motor drive circuit in the third state. Then, calculate whether the ringing amplitude and ringing frequency at the switch node of the motor drive circuit in the third state meet the electromagnetic compatibility certification standard; if not, recalculate in the above manner to obtain the value of the first capacitor and the value of the resistor in the EMI suppression circuit until the appropriate value of the first capacitor and the value of the resistor are found; or, adjust the value of the first capacitor and the value of the resistor in the EMI suppression circuit in parallel with other MOS tubes related to the switch node. If it is satisfied, the parameter selection is completed.

[0073] In the case where at least two MOS transistors are associated with a switch node, in some embodiments, if the motor drive circuit includes: an upper bridge arm and a lower bridge arm, wherein the upper bridge arm includes at least a first MOS transistor; the lower bridge arm includes at least a second MOS transistor corresponding to the first MOS transistor, and the first MOS transistor and the second MOS transistor are connected in series between a positive bus and a negative bus; the switch node is located at the connection between the first MOS transistor and the second MOS transistor; the method may further include:

[0074] Determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the second MOS transistor; determine whether the ringing of the switch node of the motor drive circuit in the fourth state meets the electromagnetic compatibility certification standard; the second MOS transistor in the motor drive circuit in the fourth state is connected in parallel with the corresponding EMI suppression circuit;

[0075] If satisfied, the parameter selection of the EMI suppression circuit is completed;

[0076] If not satisfied, then determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the first MOS tube, so that the motor drive circuit is in the fifth state; the first MOS tube in the motor drive circuit in the fifth state is connected in parallel with the corresponding EMI suppression circuit, and the second MOS tube is connected in parallel with the corresponding EMI suppression circuit.

[0077] It should be noted that if Figure 2 and Figure 3 In the motor drive circuit shown, the MOS transistor Q1 associated with the switch node SW1 is also the first MOS transistor included in the upper bridge arm mentioned above; the MOS transistor Q2 associated with the switch node SW1 is also the second MOS transistor included in the lower bridge arm mentioned above.

[0078] In actual application, for the ringing on the switch node of the entire motor drive circuit to meet the electromagnetic compatibility certification standard, the EMI suppression circuit can be connected in parallel to the second MOS tube included in the lower bridge arm, and the value of the first capacitor and the value of the resistor included in the corresponding EMI suppression circuit can be calculated. If the ringing on the switch node still does not meet the electromagnetic compatibility certification standard, the EMI suppression circuit is connected in parallel to the first MOS tube included in the upper bridge arm, and the value of the first capacitor and the value of the resistor included in the corresponding EMI suppression circuit are calculated. It should be noted that the value of the first capacitor and the value of the resistor included in the EMI suppression circuit corresponding to the second MOS tube can be obtained by multiple calculations above. Figure 1 Similarly, the value of the first capacitor and the value of the resistor included in the EMI suppression circuit corresponding to the first MOS tube can also be obtained by multiple calculations. Figure 1Calculated by the method flow shown.

[0079] For example, Figure 2 The motor drive circuit shown in the figure has an upper bridge arm including three MOS tubes: Q1, Q3, and Q5; and a lower bridge arm including three MOS tubes: Q2, Q4, and Q6. The switch nodes include: SW1, SW2, and SW3. When the motor drive circuit needs to be connected in parallel with an EMI suppression circuit, the lower bridge arm includes three MOS tubes: Q2, Q4, and Q6, and the EMI suppression circuit is connected in parallel respectively, and the value of the first capacitor and the value of the resistor in each EMI suppression circuit are obtained according to the above calculation method. Then, it is verified whether each switch node in the motor drive circuit meets the electromagnetic compatibility certification standard. If not, the upper bridge arm includes three MOS tubes: Q1, Q3, and Q5, and the EMI suppression circuit is connected in parallel respectively, and the value of the first capacitor and the value of the resistor in each EMI suppression circuit are obtained according to the above calculation method.

[0080] In actual application, the lower bridge arm contains three MOS tubes: Q2, Q4, Q6 are connected in parallel to the EMI suppression circuit in a certain order. Then, the measurement of the first ringing frequency and the second ringing frequency is measured when the motor drive circuit is in different states, and their values ​​are different.

[0081] For example, Figure 2 Taking the motor drive circuit shown in the figure as an example, when the lower bridge arm includes three MOS tubes: Q2, Q4, and Q6 are connected in parallel with the EMI suppression circuit respectively, if the EMI suppression circuit is connected in parallel with Q2 first, and the value of the first capacitor and the value of the resistor of the EMI suppression circuit are calculated, then the first ringing frequency corresponding to SW1 is Figure 2 The motor drive circuit shown in the figure is measured without all RC snubber circuits; the second ringing frequency is Figure 2 The motor drive circuit shown in the figure is measured with all RC snubber circuits removed and the second capacitor connected in parallel to Q2. The EMI suppression circuit is connected in parallel to Q4, and the value of the first capacitor and the value of the resistor of the EMI suppression circuit are calculated. At this time, the first ringing frequency is Figure 2 The motor drive circuit shown in the figure is measured without the RC snubber circuit except the RC snubber circuit in parallel with Q2; the second ringing frequency is Figure 2 In the motor drive circuit shown, except for the RC buffer circuit connected in parallel with Q2, the other RC buffer circuits do not exist, and the second capacitor connected in parallel with Q3 is measured. The values ​​of the first capacitor and the resistor in the RC buffer circuits connected in parallel with the other MOS tubes are calculated, and so on.

[0082] In order to understand the parameter selection method of the EMI suppression circuit provided by the present application, Figure 2The brushless motor driving circuit shown in FIG. 1 is used as an example to illustrate the parameter selection method of the EMI suppression circuit (i.e., RC buffer circuit) of the MOS tube Q2 included in the lower bridge arm. Figure 5 As shown, specifically, it may include:

[0083] Step 1: When there is no SMD RC snubber circuit, use an oscilloscope to measure the ringing frequency f0 of the MOS tube switch node.

[0084] At this time, there is no RC buffer circuit in the motor driving circuit, that is, the motor driving circuit is in the first state.

[0085] Step 2, query the parasitic capacitance value C0 of the MOS tube Q2 connected in parallel with the RC buffer circuit (query the Coss parameter from the specification sheet of the MOS tube).

[0086] Step 3, connect a capacitor C2 in parallel at both ends of the MOS tube, the value of C2 is 3 to 7 times of C0, after C2 is connected in parallel between the drain and source of the MOS tube Q2, use the oscilloscope to measure the ringing frequency f1 of the switch node of the MOS tube Q2 again.

[0087] Step 4: Calculate the frequency shift factor m based on the tested ringing frequencies f0 and f1, where

[0088]

[0089] Step 5: Calculate the parasitic capacitance C of the original switch circuit when the capacitor C2 is not connected in parallel. p ,in

[0090] Here, the original switch circuit may be a motor drive circuit in the first state.

[0091] Step 6: Calculate the parasitic inductance L in the original switch loop p ,in

[0092] Step 7. Calculate the resistance value R in the RC snubber circuit S ,in Actual engineering time S Choose a common resistance value near the equal sign.

[0093] Step 8, calculate the capacitance value C1 in the RC snubber circuit, where C1 = K*C P , where the value range of K is 1 to 3, and the capacitance value of C1 is selected according to the actual project.

[0094] Step 9: Since resistors of the same size in different packages have different powers, check the power P of the buffer resistor. R Whether P needs to be satisfied R >C1*VIN 2 *Fsw requirement, where V IN is the bus voltage of the MOS driving circuit, and Fsw is the switching frequency of the MOS tube.

[0095] Step 10, check whether the ringing amplitude / ringing frequency of the relevant switch node meets the requirements after the RC snubber circuit is attached.

[0096] In actual application, the values ​​of the first capacitor and the resistor in the parallel RC buffer circuit of other MOS tubes can also be calculated in a similar manner as described above. However, the measurement of the first ringing frequency and the second ringing frequency in the calculation process is determined according to the state of the specific motor drive circuit. The specific calculation can refer to the method described above and will not be repeated here.

[0097] In this application, if Figure 2 The reason why the switching waveform at the switch node (SW1, SW2, SW3 in the figure) of the motor drive circuit shown in the figure is prone to ringing is that the entire switch loop may have a part of parasitic inductance and parasitic capacitance in the drive circuit loop due to the different wiring methods and manufacturing materials of the suppression circuit board (PCB). Parasitic inductance, parasitic capacitance, and loop parasitic resistance will form the LRC parasitic circuit. If the damping ratio parameters of the LRC parasitic circuit are unreasonable, when the LRC circuit is subjected to step excitation, under-damped and undamped oscillations will be generated in the LC circuit, and high-frequency resonant frequencies will be superimposed on the waveform at the MOS tube switch node. These high-frequency resonant frequencies will radiate or conduct outward, which may easily cause the motor drive electromagnetic compatibility index to exceed the standard. If the rectification is not timely, the product will be delayed or even unable to be put on the market because it does not comply with relevant laws and regulations, which will have a great impact on the product. If the parameter value of the LRC circuit is adjusted, the LRC circuit loop can produce an under-damped response when it is subjected to step excitation, eliminate the ringing phenomenon, and achieve the purpose of reducing electromagnetic compatibility interference. Since the return path in the switching loop is difficult to determine, and the values ​​of parasitic inductance and parasitic capacitance are very small, the parasitic inductance and parasitic capacitance in the LRC parasitic circuit are difficult to measure directly by measuring equipment. Therefore, if the parasitic inductance and parasitic capacitance of the switching loop can be quickly estimated, then the ringing phenomenon can be easily eliminated or reduced by adjusting the parameters of the LRC circuit (external RC buffer), thereby achieving the purpose of reducing electromagnetic compatibility interference. The core purpose of this method lies in this, providing a simple method to quickly estimate the parasitic inductance and parasitic capacitance in the switching loop, by adjusting the external RC buffer circuit, and modifying the parameter values ​​of the capacitor and resistor in the RC buffer circuit by the estimated parasitic inductance and parasitic capacitance, so as to suppress the ringing phenomenon of the parasitic LRC loop, thereby achieving the purpose of reducing electromagnetic compatibility interference.

[0098] like Figure 6 As shown, the embodiment of the present application further provides a parameter selection device 600 for an EMI suppression circuit, comprising:

[0099] The first determination module 601 is used to determine a first ringing frequency of a switch node related to the MOS transistor in a motor drive circuit in a first state; the motor drive circuit in the first state is not connected to the EMI suppression circuit; and determine a second ringing frequency of the switch node in a motor drive circuit in a second state; the MOS transistor in the motor drive circuit in the second state is connected in parallel with a second capacitor;

[0100] The second determination module 602 is used to determine a frequency shift factor based on the first ringing frequency and the second ringing frequency; and determine a first target value of the first capacitor and a second target value of the resistor based on the frequency shift factor, the second capacitor and the first ringing frequency.

[0101] In some embodiments, the second determination module is specifically used to: determine the parasitic capacitance of the motor drive circuit in the first state based on the frequency offset factor and the second capacitance; determine the parasitic inductance of the motor drive circuit in the first state based on the parasitic capacitance and the first ringing frequency; and determine the first target value of the first capacitance and the second target value of the resistance based on the parasitic capacitance and the parasitic inductance.

[0102] In some embodiments, the second determination module is specifically used to: obtain the capacitance value of the parasitic capacitance by squaring the frequency offset factor, subtracting one, and then dividing the result by the capacitance value of the second capacitor; squaring the product of 2π and the first ringing frequency to obtain a first intermediate value; multiplying the first intermediate value by the capacitance value of the parasitic capacitor to obtain a second intermediate value; and determining the reciprocal of the second intermediate value as the inductance value of the parasitic inductance.

[0103] In some embodiments, the second determination module is specifically used to: multiply the capacitance value of the parasitic capacitor by a first preset parameter as a first target value of the first capacitor; and determine a ratio of the parasitic inductance to the parasitic capacitance, and determine a value range of the resistor based on the ratio; and select a second target value of the resistor from the value range according to a preset selection condition.

[0104] In some embodiments, the second determination module is specifically used to: select the power of the resistor to be greater than a target threshold; the target threshold is determined based on the first target value of the first capacitor, the switching frequency of the MOS tube, and the bus voltage applied to the motor drive circuit.

[0105] In some embodiments, the first determination module is specifically used to: determine the parasitic capacitance of the MOS tube according to the model of the MOS tube; and multiply the second preset parameter and the capacitance value of the parasitic capacitance of the MOS tube as the capacitance value of the second capacitor.

[0106] In some embodiments, the second determination module is specifically configured to: divide the first ringing frequency by the second ringing frequency to obtain the frequency offset factor.

[0107] In some embodiments, the second determination module is specifically used to: determine the ringing amplitude and ringing frequency of the switch node in the motor drive circuit in the third state; determine whether the ringing amplitude and ringing frequency meet the electromagnetic compatibility certification standard, and if not, recalculate the value of the first capacitor and the value of the resistor of the EMI suppression circuit; wherein the MOS tube in the motor drive circuit in the third state is connected in parallel with the EMI suppression circuit, and the value of the first capacitor of the EMI suppression circuit is the first target value, and the value of the resistor is the second target value.

[0108] In some embodiments, if the motor drive circuit includes: an upper bridge arm and a lower bridge arm, wherein the upper bridge arm includes at least a first MOS tube; the lower bridge arm includes at least a second MOS tube corresponding to the first MOS tube, and the first MOS tube and the second MOS tube are connected in series between a positive bus and a negative bus; the switch node is located at the connection between the first MOS tube and the second MOS tube; the second determination module is specifically used to: determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the second MOS tube; determine whether the ringing of the switch node of the motor drive circuit in the fourth state meets the electromagnetic compatibility certification standard; the second MOS tube in the motor drive circuit in the fourth state is connected in parallel with the corresponding EMI suppression circuit; if satisfied, complete the parameter selection of the EMI suppression circuit; if not satisfied, then determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the first MOS tube, so that the motor drive circuit is in the fifth state; the first MOS tube in the motor drive circuit in the fifth state is connected in parallel with the corresponding EMI suppression circuit, and the second MOS tube is connected in parallel with the corresponding EMI suppression circuit.

[0109] It should be noted that the parameter selection device for the EMI suppression circuit provided in the embodiment of the present application has the same technical features as the parameter selection method for the EMI suppression circuit described above. The technical features appearing here have been described in detail above and will not be repeated here.

[0110] An embodiment of the present application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of any of the methods described above when executed by the processor.

[0111] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the methods described above are implemented.

[0112] Figure 7 It is a schematic block diagram of a device 700 according to an embodiment of the present application. Figure 7 The device 700 shown includes a memory 701, a processor 702, a communication interface 703 and a bus 704. The memory 701, the processor 702 and the communication interface 703 are connected to each other through the bus 704.

[0113] The memory 701 may be a graphics processing unit (GPU) storage system, a read-only memory (ROM), a static storage device, a dynamic storage device and / or a random access memory (RAM). The memory 701 may store programs. When the programs stored in the memory 701 are executed by the processor 702, the processor 702 is used to execute the various steps of the method of the embodiment of the present application. For example, the aforementioned Figure 1 The various steps of the embodiments shown in the figure.

[0114] The processor 702 can adopt a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an application specific integrated circuit (ASIC), and / or one or more integrated circuits to execute relevant programs to implement the method of the method embodiment of the present application.

[0115] The processor 702 may also be an integrated circuit chip with signal processing capability. In the implementation process, each step of the method of the embodiment of the present application may be completed by hardware integrated logic circuits in the processor 1202 and / or software instructions.

[0116] The processor 702 may also be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit, a field programmable gate array (FPGA), and / or other programmable logic devices, discrete gates and / or transistor logic devices, and discrete hardware components. The disclosed methods, steps, and logic block diagrams in the embodiments of the present application may be implemented and / or executed. The general purpose processor may be a microprocessor and / or the processor may also be any conventional processor, etc.

[0117] The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, and / or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory and / or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 701, and the processor 702 reads the information in the memory 701, and combines its hardware to complete the functions required to be executed by the units included in the embodiments of the present application, and / or execute the methods of the various method embodiments in the present application, for example, it can execute Figure 1 etc. The various steps / functions of the embodiments shown.

[0118] The communication interface 703 may use, but is not limited to, a transceiver or other transceiver device to implement communication between the device 700 and other devices or a communication network.

[0119] The bus 704 may include a path for transmitting information between various components of the device 700 (eg, the memory 701 , the processor 1202 , and the communication interface 703 ).

[0120] It should be understood that the device 700 shown in the embodiment of the present application may be a processor or a chip for executing the method described in the embodiment of the present application.

[0121] It should be understood that in the embodiment of the present application, the processor may be a graphics processing unit (GPU), and the processor may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) and / or other programmable logic devices, discrete component gate circuits and / or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor and / or the processor may also be any conventional processor, etc.

[0122] It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0123] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0124] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0125] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined and / or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0126] The units described as separate components may and / or may not be physically separated, and the components shown as units may and / or may not be physical units, that is, they may be located in one place and / or may be distributed on multiple network units. Some and / or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0127] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0128] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware and / or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, and / or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, and / or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL, Digital Subscriber Line)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can read and / or a data storage device such as a server, data center, etc. that contains one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disk (DVD)) and / or a semiconductor medium (e.g., a solid state drive (SSD)), etc.

[0129] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A parameter selection method for an EMI suppression circuit, characterized in that: The EMI suppression circuit is applied to a motor drive circuit including a MOS tube, and the EMI suppression circuit includes a first capacitor and a resistor connected in series; the method includes: Determining a first ringing frequency of a switch node associated with the MOS transistor in a motor drive circuit in a first state; the motor drive circuit in the first state is not connected to the EMI suppression circuit; Determining a second ringing frequency of the switch node in the motor drive circuit in the second state; the MOS tube of the motor drive circuit in the second state is connected in parallel with the second capacitor; determining a frequency shift factor based on the first ringing frequency and the second ringing frequency; A first target value of the first capacitance and a second target value of the resistance are determined based on the frequency shift factor, the second capacitance, and the first ringing frequency.

2. The method according to claim 1, characterized in that The determining, based on the frequency shift factor, the second capacitance and the first ringing frequency, a first target value of the first capacitance and a second target value of the resistance included in the EMI suppression circuit comprises: determining a parasitic capacitance of the motor drive circuit in a first state based on the frequency shift factor and the second capacitance; determining a parasitic inductance of the motor drive circuit in a first state based on the parasitic capacitance and the first ringing frequency; A first target value of the first capacitance and a second target value of the resistance are determined based on the parasitic capacitance and the parasitic inductance.

3. The method according to claim 2, characterized in that The determining the parasitic capacitance of the motor drive circuit in the first state based on the frequency offset factor and the second capacitance comprises: The capacitance value of the parasitic capacitor is obtained by square the frequency offset factor, subtracting one from the square, and dividing the result by the capacitance value of the second capacitor; The determining the parasitic inductance of the motor drive circuit in the first state based on the parasitic capacitance and the first ringing frequency comprises: The product of 2π and the first ringing frequency is squared to obtain a first intermediate value; the first intermediate value is multiplied by the capacitance value of the parasitic capacitor to obtain a second intermediate value; and the reciprocal of the second intermediate value is determined as the inductance value of the parasitic inductance.

4. The method according to claim 2, characterized in that: The determining the first target value of the first capacitor and the second target value of the resistor based on the parasitic capacitance and the parasitic inductance comprises: multiplying the capacitance value of the parasitic capacitor and a first preset parameter as the first target value of the first capacitor; The ratio of the parasitic inductance to the parasitic capacitance is determined, and a value range of the resistor is determined based on the ratio; and a second target value of the resistor is selected from the value range according to a preset selection condition.

5. The method according to claim 4, characterized in that The selected condition includes that the second target value selected from the value range is equal to the square root of the ratio.

6. The method according to claim 4, characterized in that The method also includes: the power of the selected resistor is greater than a target threshold; the target threshold is determined based on a first target value of the first capacitor, a switching frequency of the MOS tube, and a bus voltage applied to the motor drive circuit.

7. The method according to claim 1, characterized in that The process of determining the second capacitance includes: Determining the parasitic capacitance of the MOS tube according to the model of the MOS tube; The product of the second preset parameter and the capacitance value of the parasitic capacitance of the MOS tube is the capacitance value of the second capacitor.

8. The method according to claim 1, characterized in that The determining a frequency shift factor based on the first ringing frequency and the second ringing frequency comprises: The frequency shift factor is obtained by dividing the first ringing frequency by the second ringing frequency.

9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: Determining a ringing amplitude and a ringing frequency of the switch node in the motor drive circuit in a third state; Determine whether the ringing amplitude and the ringing frequency meet the electromagnetic compatibility certification standard, and if not, recalculate the value of the first capacitor and the value of the resistor of the EMI suppression circuit; The MOS tube in the motor driving circuit in the third state is connected in parallel with the EMI suppression circuit, and the value of the first capacitor of the EMI suppression circuit is the first target value, and the value of the resistor is the second target value.

10. The method according to claim 9, characterized in that If the motor drive circuit includes: an upper bridge arm and a lower bridge arm, wherein the upper bridge arm at least includes a first MOS tube; the lower bridge arm at least includes a second MOS tube corresponding to the first MOS tube, and the first MOS tube and the second MOS tube are connected in series between a positive bus and a negative bus; the switch node is located at the connection between the first MOS tube and the second MOS tube; the method further includes: Determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the second MOS transistor; determine whether the ringing of the switch node of the motor drive circuit in the fourth state meets the electromagnetic compatibility certification standard; the second MOS transistor in the motor drive circuit in the fourth state is connected in parallel with the corresponding EMI suppression circuit; If satisfied, the parameter selection of the EMI suppression circuit is completed; If not satisfied, then determine the value of the first capacitor and the value of the resistor in the EMI suppression circuit connected in parallel with the first MOS tube, so that the motor drive circuit is in the fifth state; the first MOS tube in the motor drive circuit in the fifth state is connected in parallel with the corresponding EMI suppression circuit, and the second MOS tube is connected in parallel with the corresponding EMI suppression circuit.

11. A parameter selection device for an EMI suppression circuit, characterized in that: include: A first determining module, configured to determine a first ringing frequency of a switch node associated with the MOS transistor in a motor driving circuit in a first state; The motor drive circuit in the first state is not connected to the EMI suppression circuit; and determining a second ringing frequency of the switch node in the motor drive circuit in the second state; the MOS tube of the motor drive circuit in the second state is connected in parallel with the second capacitor; The second determination module is used to determine a frequency shift factor based on the first ringing frequency and the second ringing frequency; and determine a first target value of the first capacitor and a second target value of the resistor based on the frequency shift factor, the second capacitor and the first ringing frequency.

12. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the steps of the method according to any one of claims 1 to 10 when executed by the processor.

13. A computer-readable storage medium, characterized in that: The computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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