Charge pump architecture for driving high-side NMOS (N-channel metal oxide semiconductor) power field effect transistor
By adopting a piezoelectric charge pump design in the charge pump architecture that drives high-side NMOS power field effect tubes, the combination of MOS tubes and capacitors solves the problems of high output impedance, limited efficiency and high EMI in the prior art, achieving a more efficient and reliable charge pump driving effect, suitable for high-power applications.
Patent Information
- Application Number
- CN202510315575.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2025-04-25
AI Technical Summary
When driving high-side NMOS power field effect transistors, the prior art has problems such as high output impedance, limited efficiency, high EMI and complex control, which is difficult to meet the needs of high-power applications.
A charge pump design based on a double-pindle charge pump architecture is adopted, including PMOS tube M1, NMOS tube M2, M3 and M4, charge storage capacitor C1 and fly capacitor C2. The high-side NMOS power field effect tube is driven by a combination of MOS tube and capacitor. The design controls the storage and transfer of charge through the switching state of the MOS tube during the charging and multiplication phase, reducing the output impedance.
The design has a lower output impedance, which can charge MOSFET faster, improve switching speed and reduce losses; at the same time, there is no inductance, reduce EMI interference, improve reliability, and is suitable for voltage-doubling voltage values in two different voltage domains, covering a wider range of application scenarios.
Smart Images
Figure CN119891752A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a charge pump architecture for driving a high-side NMOS power field effect transistor. Background Art
[0002] The mainstream solutions for driving high-side NMOS tubes include voltage doubler charge pump, Dickson charge pump and Boost hybrid charge pump architecture. Among these three architectures, the voltage doubler charge pump has a simple structure and high efficiency, which is suitable for medium-power applications. At the same time, the switching loss is low and the output voltage is easy to control; but the load capacity is limited by the charge pump capacitor and the switching frequency, and the driving of high-power MOSFET needs to be optimized. The Dickson charge pump can be cascaded to increase the voltage; it is suitable for low-power applications; but the output impedance is high, and the efficiency is limited by the diode voltage drop and the capacitor series loss; the driving ability is weak. The Boost hybrid charge pump is suitable for high-power applications and can provide higher voltage; the output power can be adjusted, but it requires an inductor, occupies a large PCB space, and has high EMI; the control is complex and the switching loss is high. Summary of the invention
[0003] In order to solve the defects of the prior art, the present invention provides a charge pump architecture for driving a high-side NMOS power field effect transistor, including: a PMOS tube M1, NMOS tubes M2, M3 and M4, a charge storage capacitor C1, a flying capacitor C2, a high-side driving unit, a low-side driving unit, a VCC generating unit, a feedback unit, a level conversion unit, and voltage terminals VB, VCC, CF1 and CF2; The source of M1 and the upper plate of C1 are electrically connected to VB; the drain of M1, the drain of M2, and the upper plate of C2 are electrically connected to CF2; the source of M2, the drain of M3, and the lower plate of C1 are electrically connected to VCC; the source of M3, the drain of M4, and the lower plate of C2 are electrically connected to CF1; the source of M4 is grounded; The gates of M1 and M2 are both controlled by the high-side drive unit; the gates of M3 and M4 are both controlled by the low-side drive unit; The charge pump function is mainly realized through MOS tubes M1, M2, M3, M4, charge storage capacitor C1, and flying capacitor C2; In the charging stage, M1 and M3 are turned off, M2 and M4 are turned on, and C2 is charged to the voltage VCC; In the multiplication stage, M2 and M4 are turned off, M1 and M3 are turned on, the voltage of the lower plate of C2 is VCC, and the voltage of the upper plate of C2 is doubled to 2×VCC to charge C1.
[0004] For more specific details of the charge pump architecture of the present invention, please refer to the specific implementation method.
[0005] The advantages and beneficial effects of the present invention are: providing a charge pump architecture for driving a high-side NMOS power field effect transistor, which is based on a voltage-doubler charge pump architecture; compared with the Dickson charge pump architecture, the voltage-doubler charge pump has a lower output impedance, can charge the MOSFET faster, improve the switching speed, and reduce losses; compared with the Boost hybrid charge pump architecture, the voltage-doubler charge pump does not require an inductor, reduces EMI interference, and improves reliability; and the scheme of the present invention has voltage-doubler voltage values applicable to two different voltage domains, which can cover a wider range of application scenarios.
[0006] The present invention also has the following characteristics: 1. The present invention realizes a high-side NMOS power field effect tube driving circuit based on a voltage doubling charge pump architecture. The charge pump has low impedance, reduces driving loss, and improves the switching speed of high-power MOSFET.
[0007] 2. The present invention designs a multiplier voltage value that is suitable for two voltage domains, which can cover a wider range of applications.
[0008] 3. The present invention designs a short-circuit detection circuit to avoid MOSFET failure caused by overshoot or undervoltage of the charge pump, thereby improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 is a functional block diagram of the charge pump architecture of the present invention; Figure 2 It is the circuit diagram of the high-side driver unit; Figure 3 It is the circuit diagram of the low-side driver unit; Figure 4 This is the circuit diagram of the VCC generation unit; Figure 5 is the circuit diagram of the feedback unit; Figure 6 is a circuit diagram of a level conversion unit. DETAILED DESCRIPTION
[0010] The specific implementation of the present invention is further described below in conjunction with the accompanying drawings and embodiments. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.
[0011] The technical solutions specifically implemented in the present invention are as follows: like Figure 1 As shown, the present invention provides a charge pump architecture for driving a high-side NMOS power field effect transistor, including: a PMOS tube M1, NMOS tubes M2, M3 and M4, a charge storage capacitor C1, a flying capacitor C2, a high-side driving unit, a low-side driving unit, a VCC generating unit, a feedback unit, a level conversion unit, and voltage terminals VB, VCC, CF1 and CF2; The source of M1 and the upper plate of C1 are electrically connected to VB; the drain of M1, the drain of M2, and the upper plate of C2 are electrically connected to CF2; the source of M2, the drain of M3, and the lower plate of C1 are electrically connected to VCC; the source of M3, the drain of M4, and the lower plate of C2 are electrically connected to CF1; the source of M4 is grounded; The gates of M1 and M2 are both controlled by the high-side drive unit; the gates of M3 and M4 are both controlled by the low-side drive unit; The charge pump function is mainly realized through MOS tubes M1, M2, M3, M4, charge storage capacitor C1, and flying capacitor C2; In the charging stage, M1 and M3 are turned off, M2 and M4 are turned on, and C2 is charged to the voltage VCC; In the multiplication stage, M2 and M4 are turned off, M1 and M3 are turned on, the voltage of the lower plate of C2 is VCC, and the voltage of the upper plate of C2 is doubled to 2×VCC to charge C1.
[0012] like Figure 2 As shown, the high-side drive unit includes: an input terminal IN, output terminals HSD_H and HSD_L, PMOS tubes M5 and M7, NMOS tubes M6 and M8, VDD control logic modules U1 and U2, HSD conduction detection module U3, LSD conduction detection module U4, voltage terminals VB and VCC_GEN; HSD_H is electrically connected to the gate of M1; HSD_L is electrically connected to the gate of M2; The source of M5 and the source of M7 are both electrically connected to VB; the drain of M5 and the drain of M6 are both electrically connected to HSD_H; the gate of M5 and the gate of M6 are both controlled by the VDD control logic module U1; the source of M6 and the source of M8 are both electrically connected to VCC_GEN; the drain of M7 and the drain of M8 are both electrically connected to HSD_L; the gate of M7 and the gate of M8 are both controlled by the VDD control logic module U2; The input terminal IN is electrically connected to the VDD control logic module U1 and the VDD control logic module U2 respectively; HSD_H is also electrically connected to the VDD control logic module U2 through the HSD conduction detection module U3; HSD_L is also electrically connected to the VDD control logic module U1 through the LSD conduction detection module U4.
[0013] In the high-side driver unit, the withstand voltage of all devices is VDD; the voltage swing of HSD_H and HSD_L is between VCC_GEN and VB.
[0014] The working principle of the high-side drive unit includes: after the low-voltage control signal of the input terminal IN passes through the VDD control logic unit U1 and the VDD control logic module U2, a control signal with a high level of VB is generated to control the on and off states of transistors M5, M6, M7, and M8 (the VDD control logic unit U1 controls the on and off states of M5 and M6, and the VDD control logic module U2 controls the on and off states of M7 and M8), wherein M5 and M6 are used to output the signal HSD_H, and M7 and M8 are used to output the signal HSD_L; in order to prevent M5, M6 from being turned on at the same time as M7 and M8 to generate a short-circuit current, the HSD conduction detection unit U3 detects the states of M5 and M6 in real time and outputs a control signal to the VDD control logic unit U2, and the LSD conduction detection unit U4 detects the states of transistors M7 and M8 in real time and outputs a control signal to the VDD control logic unit U1.
[0015] like Figure 3 As shown, the low-side drive unit includes: an input terminal IN, output terminals LSD_H and LSD_L, PMOS tubes M9, M10 and M12, NMOS tubes M11, M13 and M14, diodes D1 and D2, resistors R1 and R2, a current source I1, a switch S1, a VDD control logic module U5, a logic and level conversion module U6, an LSD conduction detection module U7, and voltage terminals VB, VDD, CF1 and VCC_GEN; LSD_H is electrically connected to the gate of M3; LSD_L is electrically connected to the gate of M4; The source of M9 and the source of M10 are electrically connected to VB; the drain of M9, the gate of M9, and the gate of M10 are electrically connected to the drain of M11; the drain of M10 is grounded through D2, and R2 is connected in parallel at both ends of D2; the source of M11 is electrically connected to CF1 through R1; the gate of M11 and the drain of M14 are electrically connected to LSD_H; the gate of M11 is also electrically connected to CF1 through D1; the gate of M11 is also electrically connected to VB through S1 and I1. The source of M12 is electrically connected to VDD; the drain of M12 and the drain of M13 are electrically connected to LSD_L; the source of M13 and the source of M14 are grounded; the gate of M12, the gate of M13 and the gate of M14 are controlled by the VDD control logic module U5; the VDD control logic module U5 is also electrically connected to VDD; the drain of M10 is also electrically connected to the VDD control logic module U5; S1 is controlled by the logic and level conversion module U6; The input terminal IN is electrically connected to the VDD control logic module U5 and the logic and level conversion module U6 respectively; LSD_L is also electrically connected to the logic and level conversion module U6 through the LSD conduction detection module U7; the logic and level conversion module U6 is also electrically connected to VCC_GEN.
[0016] In the low-side drive unit, the voltage swing of LSD_H is between CF1 and CF1+VD1 (VD1 is the voltage between the two ends of diode D1); the voltage swing of LSD_L is between 0 and VDD; M9, M10, M11, R1, R2 and D2 form the HSD conduction detection circuit.
[0017] The working principle of the low-side drive unit includes: the low-voltage control signal of the input terminal IN generates a control signal with a high level of VB after passing through the logic and level conversion module U6. The control signal is used to control the current source I1 to output to LSD_H, and is also used to control the state of M11; M9 and M10 form a current mirror circuit, which is input to the VDD control logic unit U5 to generate a control signal with a high level of VB. The control signal is used to control the conduction and shutdown of M12, M13 and M14, and then output the signal LSD_L; D1 and R1 form a buffer absorption circuit, and D2 and R2 also form a buffer absorption circuit; the LSD conduction detection unit U7 detects the state of M12 and M13 in real time, and outputs the control signal to the logic and level conversion unit U6.
[0018] like Figure 4 As shown, the VCC generating unit includes: an input terminal Vi, an output terminal Vo, NMOS tubes M15 and M16, a PMOS tube M17, a diode D3, resistors R3 and R4, and a voltage terminal VB; Vi is electrically connected to the gate of M15; Vo is electrically connected to the source of M16 and the source of M17 respectively; The source of M15 and the drain of M17 are both grounded; the drain of M15 is electrically connected to the gate of M16 and the gate of M17 through R3; VB is electrically connected to the gate of M16 and the gate of M17 through D3; the drain of M16 is electrically connected to VB through R4.
[0019] In the VCC generation unit, during the power-on process, the voltage of VB is equal to VCC; the voltage value of the buffered voltage Vo is lower than VB by VD3 (VD3 is the voltage between the two ends of the diode D3), and this voltage is used to start the circuit; when VB approaches its set value, the voltage is switched to VCC.
[0020] The working principle of the VCC generation unit includes: the signal of Vi is used to control the on and off of M15, so as to determine whether to switch VB to VCC; D3 is a clamping diode, and D3 and R3 form a buffer absorption circuit; VB is input to M16 and M17 after passing through D3 to form a voltage buffer circuit, and the output is Vo, and R4 is used for current limiting of the voltage buffer circuit.
[0021] like Figure 5As shown, the feedback unit includes: input terminals VREF and SEL, output terminal Vout, NMOS tubes M18, M21 and M22, PMOS tubes M19 and M20, resistors R5, R6, R7, R8 and R9, current source I2, operational amplifier A1, comparator A2, inverter A3, voltage terminals VB and VCC; VREF is electrically connected to the non-inverting input terminal of the operational amplifier A1; the gates of SEL and M22 are electrically connected to the input terminal of the inverter A3; Vout is electrically connected to the output terminal of the comparator A2; The source of M18 is electrically connected to the inverting input terminal of the operational amplifier A1; the source of M18 is also grounded through R7; the drain of M18 is electrically connected to the source of M19; the drain of M18 is also electrically connected to the source of M20 through R6; the gate of M18 is electrically connected to the output terminal of the operational amplifier A1; the drain of M19 and the drain of M20 are both electrically connected to the non-inverting input terminal of the comparator A2; the gate of M19 is electrically connected to VB through R8; the gate of M19 is also electrically connected to the drain of M21; the source of M20 is also electrically connected to VB through R5; the gate of M20 is electrically connected to VB through R9; the gate of M20 is also electrically connected to the drain of M22; the source of M21 and the source of M22 are both grounded through the current source I2; the gate of M21 is electrically connected to the output terminal of the inverter A3; the inverting input terminal of the comparator A2 is electrically connected to VCC.
[0022] In the feedback unit, the part composed of A1, M18, R5, R6 and R7 generates two optional reference voltages V1 and V2; VCC is compared with the voltage value of V1 or V2 through comparator A2 to determine the charging state of the charge pump to form negative feedback.
[0023] The working principle of the feedback unit includes: the circuit composed of A1, M18 and R7 can generate a constant current of VREF / R7, thereby generating voltages V1 and V2 with a fixed voltage difference relative to VB with R5 and R6; the voltage selection signal of the input terminal SEL directly controls the on and off of M22, and controls the on and off of M20 after being stepped down by R9, so that the voltage V1 is input to the non-inverting input terminal of the comparator A2 for comparison with the voltage VCC of the inverting input terminal, and then the comparator A2 outputs the voltage Vout; and the voltage selection signal of the input terminal SEL controls the on and off of M21 after passing through the inverter A3, and controls the on and off of M19 after being stepped down by R8, so that the voltage V1 is input to the non-inverting input terminal of the comparator A2 for comparison with the voltage VCC of the inverting input terminal, and then the comparator A2 outputs the voltage Vout.
[0024] like Figure 6As shown, the level conversion unit includes: an input terminal IN, output terminals OUT and OUTZ, PMOS tubes M23, M24, M25, M26, M31 and M32, NMOS tubes M27, M28, M29, M30, M33 and M34, resistors R10, R11 and R12, inverter A4, voltage terminals VB and VCC_GEN; The input terminal IN is electrically connected to the input terminal of the inverter A4 and the gate of M33 respectively; the output terminal OUT is electrically connected to the drain of M26 and the drain of M30 respectively; the output terminal OUTZ is electrically connected to the drain of M25 and the drain of M29 respectively; The source of M23, the source of M24, the source of M25, and the source of M26 are all electrically connected to VB; the drain of M23 is electrically connected to the gate of M25; the drain of M23 is also electrically connected to the gate of M24, the drain of M27, the gate of M28, the gate of M29, and the source of M32 through R10; the gate of M23 is electrically connected to the drain of M24 and the gate of M26 through R11; the gate of M23 is also electrically connected to the gate of M27, the drain of M28, the gate of M29, and the source of M32. The gate of M30 and the source of M31 are electrically connected respectively; the source of M27, the source of M28, the source of M29 and the source of M30 are all electrically connected to VCC_GEN; the drain of M31 is electrically connected to the drain of M33; the gate of M31 and the gate of M32 are both electrically connected to VCC_GEN through R12; the drain of M32 is electrically connected to the drain of M34; the source of M33 and the source of M34 are both grounded; the gate of M34 is electrically connected to the output end of inverter A4.
[0025] In the level conversion unit, the voltage at the input terminal IN is raised to OUT which is close to VB.
[0026] The working principle of the level conversion unit includes: the high level of the input terminal IN is raised to VB, and the low level is raised to VCC_GEN; M31, M32, M33, M34 and inverter A4 form an "AND" logic, and R10, R11, and R12 are buffer absorption resistors; when the power is just turned on, VCC_GEN is a low level, and M31 and M32 are turned on; when the input terminal IN is a high level, M33, M23, M28, M29, and M26 are turned on, OUT output is VB, and OUTZ output is VCC_GEN; when the input terminal IN is a low level, M34, M24, M28, M25, and M30 are turned on, OUT output is VCC_GEN, and OUTZ output is VB.
[0027] More specifically, the connection relationship between the units is as follows: The input terminal IN of the high-side driving unit is electrically connected to the output terminal OUT of the level conversion unit; The output terminals HSD_H and HSD_L of the high-side driver unit are used to drive M1 and M2; The input terminal IN of the low-side drive unit is used for input: controlled by the control logic module ( Figure 1 The control logic in the Figure 1 level conversion in the signal; The output terminals LSD_H and LSD_L of the low-side driver unit are used to drive M and M4; The input terminal Vi of the VCC generation unit is used to input the voltage signal V1 or V2 in the feedback unit, and one of them can be selected according to different application scenarios; The output terminal Vo of the VCC generation unit is connected to the VCC_GEN of the high-side driver unit through a two-or-one switch; The input terminal VREF of the feedback unit is used to input an external bias signal, or to input the voltage of a bandgap reference module in other circuits; The input terminal SEL of the feedback unit is used to input an external control signal, or to input a control signal in other circuits; The output terminal Vout of the feedback unit is connected to the control logic module ( Figure 1 The control logic in the module) is connected, and there is also a control signal CLK connected to the control logic module ( Figure 1 The control logic module ( Figure 1 The signal output by the control logic in the control logic module is connected to the input terminal IN of the level conversion module; The input terminal IN of the level conversion unit is connected to the control logic module ( Figure 1 The output terminal of the control logic in the circuit is connected; The output terminal OUT of the level conversion unit is connected to the input terminal IN of the high-side driving unit to control the switching state of M1 and M2; The output terminal OUTZ of the level conversion unit is also connected to the input terminal IN of the high-side driving unit for controlling the switching states of M1 and M2.
[0028] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A charge pump architecture for driving a high-side NMOS power field effect transistor, characterized in that: include: PMOS tube M1, NMOS tubes M2, M3 and M4, charge storage capacitor C1, flying capacitor C2, high-side drive unit, low-side drive unit, voltage terminals VB, VCC, CF1 and CF2; The source of M1 and the upper plate of C1 are electrically connected to VB; the drain of M1, the drain of M2, and the upper plate of C2 are electrically connected to CF2; the source of M2, the drain of M3, and the lower plate of C1 are electrically connected to VCC; the source of M3, the drain of M4, and the lower plate of C2 are electrically connected to CF1; the source of M4 is grounded; The gates of M1 and M2 are both controlled by the high-side drive unit; the gates of M3 and M4 are both controlled by the low-side drive unit; In the charging stage, M1 and M3 are turned off, M2 and M4 are turned on, and C2 is charged to the voltage VCC; In the multiplication stage, M2 and M4 are turned off, M1 and M3 are turned on, the voltage of the lower plate of C2 is VCC, and the voltage of the upper plate of C2 is doubled to 2×VCC to charge C1.
2. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 1, characterized in that: The high-side drive unit includes: output terminals HSD_H and HSD_L, PMOS tubes M5 and M7, NMOS tubes M6 and M8, VDD control logic modules U1 and U2, and voltage terminals VB and VCC_GEN; HSD_H is electrically connected to the gate of M1; HSD_L is electrically connected to the gate of M2; The source of M5 and the source of M7 are both electrically connected to VB; the drain of M5 and the drain of M6 are both electrically connected to HSD_H; the gate of M5 and the gate of M6 are both controlled by the VDD control logic module U1; the source of M6 and the source of M8 are both electrically connected to VCC_GEN; the drain of M7 and the drain of M8 are both electrically connected to HSD_L; the gate of M7 and the gate of M8 are both controlled by the VDD control logic module U2.
3. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 2, characterized in that: The high-side drive unit further includes: an input terminal IN, an HSD conduction detection module U3, and an LSD conduction detection module U4; The input terminal IN is electrically connected to the VDD control logic module U1 and the VDD control logic module U2 respectively; HSD_H is also electrically connected to the VDD control logic module U2 through the HSD conduction detection module U3; HSD_L is also electrically connected to the VDD control logic module U1 through the LSD conduction detection module U4.
4. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 1, characterized in that: The low-side drive unit includes: output terminals LSD_H and LSD_L, PMOS tubes M9, M10 and M12, NMOS tubes M11, M13 and M14, diodes D1 and D2, resistors R1 and R2, current source I1, switch S1, VDD control logic module U5, voltage terminals VB, VDD and CF1; LSD_H is electrically connected to the gate of M3; LSD_L is electrically connected to the gate of M4; The source of M9 and the source of M10 are both electrically connected to VB; the drain of M9, the gate of M9 and the gate of M10 are both electrically connected to the drain of M11; the drain of M10 is grounded through D2, and R2 is also connected in parallel at both ends of D2; the source of M11 is electrically connected to CF1 through R1; the gate of M11 and the drain of M14 are both electrically connected to LSD_H; the gate of M11 is also electrically connected to CF1 through D1; the gate of M11 is also electrically connected to VB through S1 and I1; the source of M12 is electrically connected to VDD; the drain of M12 and the drain of M13 are both electrically connected to LSD_L; the source of M13 and the source of M14 are both grounded; the gate of M12, the gate of M13 and the gate of M14 are all controlled by the VDD control logic module U5.
5. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 4, characterized in that: The low-side driving unit further includes: a logic and level conversion module U6; S1 is controlled by the logic and level conversion module U6.
6. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 5, characterized in that: The low side drive unit further comprises: an input terminal IN, an LSD conduction detection module U7; The input terminal IN is electrically connected to the VDD control logic module U5 and the logic and level conversion module U6 respectively; LSD_L is also electrically connected to the logic and level conversion module U6 through the LSD conduction detection module U7.
7. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 1, characterized in that: Also includes a VCC generation unit; The VCC generating unit includes: an input terminal Vi, an output terminal Vo, NMOS tubes M15 and M16, a PMOS tube M17, a diode D3, resistors R3 and R4, and a voltage terminal VB; Vi is electrically connected to the gate of M15; Vo is electrically connected to the source of M16 and the source of M17 respectively; The source of M15 and the drain of M17 are both grounded; the drain of M15 is electrically connected to the gate of M16 and the gate of M17 through R3; VB is electrically connected to the gate of M16 and the gate of M17 through D3; the drain of M16 is electrically connected to VB through R4.
8. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 1, characterized in that: Also includes a feedback unit; The feedback unit includes: input terminals VREF and SEL, output terminal Vout, NMOS tubes M18, M21 and M22, PMOS tubes M19 and M20, resistors R5, R6, R7, R8 and R9, current source I2, operational amplifier A1, comparator A2, inverter A3, voltage terminals VB and VCC; VREF is electrically connected to the non-inverting input terminal of the operational amplifier A1; the gates of SEL and M22 are electrically connected to the input terminal of the inverter A3; Vout is electrically connected to the output terminal of the comparator A2; The source of M18 is electrically connected to the inverting input terminal of the operational amplifier A1; the source of M18 is also grounded through R7; the drain of M18 is electrically connected to the source of M19; the drain of M18 is also electrically connected to the source of M20 through R6; the gate of M18 is electrically connected to the output terminal of the operational amplifier A1; the drain of M19 and the drain of M20 are both electrically connected to the non-inverting input terminal of the comparator A2; the gate of M19 is electrically connected to VB through R8; the gate of M19 is also electrically connected to the drain of M21; the source of M20 is also electrically connected to VB through R5; the gate of M20 is electrically connected to VB through R9; the gate of M20 is also electrically connected to the drain of M22; the source of M21 and the source of M22 are both grounded through the current source I2; the gate of M21 is electrically connected to the output terminal of the inverter A3; the inverting input terminal of the comparator A2 is electrically connected to VCC.
9. The charge pump architecture for driving a high-side NMOS power field effect transistor according to claim 1, characterized in that: Also included is a level conversion unit; The level conversion unit includes: an input terminal IN, output terminals OUT and OUTZ, PMOS tubes M23, M24, M25, M26, M31 and M32, NMOS tubes M27, M28, M29, M30, M33 and M34, resistors R10, R11 and R12, an inverter A4, and voltage terminals VB and VCC_GEN; The input terminal IN is electrically connected to the input terminal of the inverter A4 and the gate of M33 respectively; the output terminal OUT is electrically connected to the drain of M26 and the drain of M30 respectively; the output terminal OUTZ is electrically connected to the drain of M25 and the drain of M29 respectively; The source of M23, the source of M24, the source of M25, and the source of M26 are all electrically connected to VB; the drain of M23 is electrically connected to the gate of M25; the drain of M23 is also electrically connected to the gate of M24, the drain of M27, the gate of M28, the gate of M29, and the source of M32 through R10; the gate of M23 is electrically connected to the drain of M24 and the gate of M26 through R11; the gate of M23 is also electrically connected to the gate of M27, the drain of M28, the gate of M29, and the source of M32. The gate of M30 and the source of M31 are electrically connected respectively; the source of M27, the source of M28, the source of M29 and the source of M30 are all electrically connected to VCC_GEN; the drain of M31 is electrically connected to the drain of M33; the gate of M31 and the gate of M32 are both electrically connected to VCC_GEN through R12; the drain of M32 is electrically connected to the drain of M34; the source of M33 and the source of M34 are both grounded; the gate of M34 is electrically connected to the output end of inverter A4.