A power supply circuit with a small volume and a wide application range

Abstract

The present invention relates to the technical field of power supply circuits, and particularly relates to a power supply circuit with a small volume and a wide application range. The integrated circuit control chip of the power supply circuit includes a working frequency control circuit. After an external adjusting resistor or a square wave signal is connected through a pin, the working frequency control circuit can control the frequency of the output signal by setting adjusting resistors with different resistance values to control the working frequency of the power supply circuit, or can control the working frequency of the power supply circuit by connecting square wave signals with different frequencies, thereby reducing the volume of the power supply circuit and increasing the application range of the power supply circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and particularly relates to a power supply circuit with a small volume and a wide application range. Background Art

[0002] The power supply circuits in the prior art usually include an integrated circuit control chip and an external power circuit, and the operating frequency of the power supply circuit is determined by the integrated circuit control chip. When there is only one integrated circuit control chip working alone in the circuit system, the operating frequency can be controlled by connecting an external adjusting resistor to the chip. When there are multiple integrated circuit control chips working simultaneously in the circuit system, a square wave signal is usually used to control multiple integrated circuit control chips simultaneously, so that the operating frequencies of the power supply circuits controlled by multiple integrated circuit control chips are the same, thereby ensuring the consistency of the operation of each power supply circuit in the circuit system. However, the integrated circuit control chips of the power supply circuits in the prior art usually have two pins, which are respectively used to connect an external adjusting resistor and a square wave signal to control the operating frequency of the power supply circuit, which obviously does not conform to the development trend of the integration and miniaturization of the power supply circuit. Summary of the Invention

[0003] In view of this, the present invention provides a power supply circuit with a small volume and a wide application range to solve the technical problem that the integrated circuit control chip of the power supply circuit in the prior art uses two pins to control the operating frequency of the power supply circuit, resulting in a relatively large volume of the power supply circuit.

[0004] The technical solution provided by the present invention is as follows:

[0005] In a first aspect, the present invention provides a working frequency control circuit, including:

[0006] An input pin, which is used to receive an externally input square wave signal or connect an external adjusting resistor;

[0007] A first control circuit, whose first end is connected to the input pin, whose second end is connected to an external power supply, and whose third end is grounded, and is used to obtain a signal with the same frequency as the square wave signal or a first low-level signal according to whether the signal input by the input pin is a square wave signal, and output a second low-level signal or a high-level signal according to the signal with the same frequency as the square wave signal or the first low-level signal;

[0008] A second control circuit, whose first end is connected to the fourth end of the first control circuit, whose second end is connected to the input pin, whose third end is connected to an external power supply, and whose fourth end is grounded, and is used to output a third low-level signal or a periodic output signal according to the second low-level signal or the high-level signal output by the first control circuit;

[0009] An output circuit, with its first end connected to the fifth end of a second control circuit, its second end connected to the fourth end of a first control circuit, its third end connected to the fifth end of the first control circuit, and its fourth end connected to the sixth end of the first control circuit, for outputting an output signal having the same frequency as a square wave signal or an output signal whose frequency is controlled by the resistance value of an adjustment resistor according to a signal having the same frequency as the square wave signal or a first low-level signal, a second low-level signal or a high-level signal, a second low-level signal or an inverted signal of the high-level signal, and a third low-level signal or a periodic output signal.

[0010] In an alternative embodiment, the first control circuit includes:

[0011] A signal detection circuit, with its first end connected to an input pin, its second end connected to an external power supply, its third end grounded, and its fourth end connected to the fourth end of the output circuit, for detecting the input signal of the input pin, outputting an output signal having the same frequency as the square wave signal when the input signal is a square wave signal, and outputting a first low-level signal when the input signal is not a square wave signal;

[0012] A switch control circuit, with its first end connected to the fourth end of the signal detection circuit, its second end connected to the external power supply, its third end grounded, its fourth end connected to the input pin, its fifth end connected to the first end of the second control circuit and the second end of the output circuit, and its sixth end connected to the third end of the output circuit, for outputting a second low-level signal when the signal detection circuit outputs an output signal having the same frequency as the square wave signal, and outputting a high-level signal when the signal detection circuit outputs a first low-level signal.

[0013] In an alternative embodiment, the second control circuit includes:

[0014] A switch circuit, with its first end connected to the fourth end of the first control circuit, its second end connected to the external power supply, and its third end connected to the input pin;

[0015] A voltage control circuit, with its first end connected to a first fixed voltage and its second and third ends connected to the fourth end of the switch circuit;

[0016] A first charging circuit, with its first end connected to the fourth end of the switch circuit, its second end connected to the external power supply, and its third end grounded;

[0017] A second charging circuit, with its first end connected to the fourth end of the first charging circuit, its second end connected to a second fixed voltage, its third end connected to the external power supply, its fourth end grounded, and its fifth end connected to the fifth end of the first charging circuit and the first end of the output circuit;

[0018] When the first control circuit outputs a second low-level signal, the switching circuit turns off the first charging circuit, and the second charging circuit outputs a third low-level signal. When the first control circuit outputs a high-level signal, the first charging circuit operates under the control of the switching circuit and the voltage control circuit. The first charging circuit outputs a periodic output signal, and the second charging circuit outputs an output signal with the same period as the periodic output signal according to the periodic output signal.

[0019] In an alternative embodiment, the signal detection circuit includes a first inverter, a first AND gate, a first switching transistor, a second switching transistor, a first resistor, and a first capacitor. The switching control circuit includes a third switching transistor, a fourth switching transistor, a second resistor, a second capacitor, a second inverter, a first NAND gate, a second NAND gate, a third NAND gate, a third inverter, and a fourth inverter;

[0020] The input terminal of the first inverter is connected to the input pin. The output terminal of the first inverter is connected to the first terminal of the first switching transistor, the first input terminal of the first AND gate, and the first terminal of the second switching transistor. The second terminal of the first switching transistor is connected to an external power supply. The third terminal of the first switching transistor is connected to the second input terminal of the first AND gate, one end of the first capacitor, and one end of the first resistor. The other end of the first resistor is connected to the second terminal of the second switching transistor. The third terminal of the second switching transistor is connected to the other end of the first capacitor and grounded; The output terminal of the first AND gate is connected to the first terminal of the third switching transistor, the first terminal of the fourth switching transistor, and the fourth terminal of the output circuit;

[0021] The second terminal of the third switching transistor is connected to an external power supply. The third terminal of the third switching transistor is connected to one end of the second resistor. The other end of the second resistor is connected to the second terminal of the fourth switching transistor, one end of the second capacitor, and the input terminal of the second inverter. The third terminal of the fourth switching transistor is connected to the second end of the second capacitor and grounded. The output terminal of the second inverter is connected to the first input terminal of the first NAND gate and the first input terminal of the third NAND gate. The second input terminal of the first NAND gate is connected to the input pin. The output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate. The second input terminal of the second NAND gate is connected to the output terminal of the third NAND gate and the input terminal of the third inverter. The output terminal of the second NAND gate is connected to the second input terminal of the third NAND gate. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the third terminal of the output circuit. The output terminal of the fourth inverter is connected to the first terminal of the second control circuit and the second terminal of the output circuit.

[0022] In an alternative embodiment, the switching circuit includes a fifth switching transistor and an eighth switching transistor. The voltage control circuit includes a first comparator. The first charging circuit includes a sixth switching transistor, a seventh switching transistor, a ninth switching transistor, and a third capacitor. The second charging circuit includes a second comparator, a tenth switching transistor, a fourth capacitor, a fifth inverter, and a first current source;

[0023] The first end of the fifth switching tube is connected to the first end of the eighth switching tube, the fourth end of the first control circuit, and the second end of the output circuit. The second end of the fifth switching tube is connected to an external power supply. The third end of the fifth switching tube is connected to the first and second ends of the sixth switching tube, the first end of the seventh switching tube, the output end of the first comparator, the negative input end of the first comparator, and the second end of the eighth switching tube. The third end of the eighth switching tube is connected to an input pin. The positive input end of the first comparator is connected to a first fixed voltage.

[0024] The third end of the sixth switching tube is connected to the second end of the seventh switching tube and the external power supply. The third end of the seventh switching tube is connected to the positive input end of the second comparator, one end of the third capacitor, and the first end of the ninth switching tube. The negative input end of the second comparator is connected to a second fixed voltage. The output end of the second comparator is connected to the first end of the tenth switching tube. The other end of the third capacitor is connected to the second end of the ninth switching tube and grounded. The second end of the tenth switching tube is connected to the output end of the first current source, the input end of the fifth inverter, and one end of the fourth capacitor. The other end of the fourth capacitor is connected to the third end of the tenth switching tube and grounded. The output end of the fifth inverter is connected to the third end of the ninth switching tube and the first end of the output circuit. The input end of the first current source is connected to the external power supply.

[0025] In an alternative embodiment, the output circuit includes a second AND gate, a third AND gate, and a first OR gate. The first input end of the second AND gate is connected to the fifth end of the second control circuit. The second input end of the second AND gate is connected to the fourth end of the first control circuit. The first input end of the third AND gate is connected to the fifth end of the first control circuit. The second input end of the third AND gate is connected to the sixth end of the first control circuit. The output end of the second AND gate is connected to the first input end of the first OR gate. The output end of the third AND gate is connected to the second input end of the first OR gate. The output end of the first OR gate outputs an output signal having the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjustment resistor.

[0026] In an alternative embodiment, the first fixed voltage is less than the switching threshold voltage of the first inverter; when the external power supply charges the second capacitor through the third switching tube and the second resistor, within one period of the square wave signal, the voltage across the second capacitor is less than the switching threshold voltage of the second inverter.

[0027] In an alternative embodiment, the lowest frequency of the output signal of the output circuit is controlled according to the parameters of the second resistor and the second capacitor.

[0028] In a second aspect, the present invention provides an integrated circuit control chip, and the chip includes the operating frequency control circuit of the first aspect and any one of the first aspect of the present invention.

[0029] In a third aspect, the present invention provides a power supply circuit with a small volume and a wide application range, and the power supply circuit includes the integrated circuit control chip of the second aspect of the present invention.

[0030] The technical solution of the present invention has the following advantages:

[0031] In the present invention, after the operating frequency control circuit realizes external connection of an adjustment resistor or a square wave signal through an input pin, by setting adjustment resistors with different resistance values, the frequency of the output signal of the operating frequency control circuit can be controlled, or by connecting square wave signals with different frequencies, the frequency of the output signal of the operating frequency control circuit can be controlled, thereby reducing the use of pins.

[0032] In the present invention, the minimum frequency of the output signal of the operating frequency control circuit is controlled by controlling the parameters of the second resistor and the second capacitor.

[0033] In the present invention, the integrated circuit control chip of the power supply circuit includes an operating frequency control circuit. After the operating frequency control circuit realizes external connection of an adjustment resistor or a square wave signal through a pin, by setting adjustment resistors with different resistance values, the frequency of the output signal can be controlled to realize the control of the operating frequency of the power supply circuit, or by connecting square wave signals with different frequencies, the control of the operating frequency of the power supply circuit can be realized, thereby reducing the volume of the power supply circuit and increasing the application range of the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 It is the block diagram of the operating frequency control circuit in the embodiment of the present invention;

[0036] Figure 2 It is the block diagram of the operating frequency control circuit in another embodiment of the present invention;

[0037] Figure 3 It is the structural schematic diagram of the operating frequency control circuit in the embodiment of the present invention;

[0038] Figure 4 It is the block diagram of the operating frequency control circuit in another embodiment of the present invention;

[0039] Figure 5 It is the waveform diagram of the output signal when the input pin of the operating frequency control circuit in the embodiment of the present invention is connected to an adjustment resistor;

[0040] Figure 6 It is the waveform diagram of the output signal when a square wave signal is input to the input pin of the working frequency control circuit in the embodiment of the present invention;

[0041] Figure 7 It is the structural block diagram of the power supply circuit with a small volume and a wide application range in the embodiment of the present invention;

[0042] Figure 8 It is the structural block diagram of the power supply circuit with a small volume and a wide application range in another embodiment of the present invention. Specific Embodiments

[0043] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0044] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0045] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] The embodiment of the present invention provides a working frequency control circuit, as Figure 1As shown in the figure, the circuit includes: input pins G1 / G2, which are used to receive externally input square-wave signals or connect to an external adjustable resistor RL; a first control circuit 1, whose first end is connected to the input pins G1 / G2, whose second end is connected to an external power supply, and whose third end is grounded, and is used to obtain a signal with the same frequency as the square-wave signal or a first low-level signal according to whether the input to the input pins G1 / G2 is a square-wave signal, and output a second low-level signal or a high-level signal according to the signal with the same frequency as the square-wave signal or the first low-level signal; a second control circuit 2, whose first end is connected to the fourth end of the first control circuit 1, whose second end is connected to the input pins G1 / G2, whose third end is connected to an external power supply, and whose fourth end is grounded, and is used to output a third low-level signal or a periodic output signal according to the second low-level signal or the high-level signal output by the first control circuit 1; an output circuit 3, whose first end is connected to the fifth end of the second control circuit 2, whose second end is connected to the fourth end of the first control circuit 1, whose third end is connected to the fifth end of the first control circuit 1, and whose fourth end is connected to the sixth end of the first control circuit 1, and is used to output an output signal with the same frequency as the square-wave signal or an output signal whose frequency is controlled by the resistance value of the adjustable resistor according to the signal with the same frequency as the square-wave signal or the first low-level signal, the second low-level signal or the high-level signal, the inverted signal of the second low-level signal or the high-level signal, and the third low-level signal or the periodic output signal.

[0048] It should be noted that the input pins G1 / G2 refer to one pin, which can either connect to the adjustable resistor or receive externally input square-wave signals. Thus, this operating frequency control circuit can receive square-wave signals or connect to the adjustable resistor through one input pin. Among them, when receiving a square-wave signal, the input signal is processed by the first control circuit 1, the second control circuit 2, and the output circuit 3 to output an output signal with the same frequency as the square-wave signal; when connecting to the adjustable resistor, if the resistance value of the adjustable resistor changes, an output signal with a changed frequency is output through the processing of the first control circuit 1, the second control circuit 2, and the output circuit 3. Thus, this operating frequency control circuit can control the frequency of the output signal by inputting square-wave signals with different frequencies or connecting adjustable resistors with different resistance values. When this operating frequency control circuit is applied to the integrated circuit control chip of the power supply circuit, the operating frequency of the power supply circuit is controlled.

[0049] In the present invention, after the operating frequency control circuit realizes external connection of the adjustable resistor or the square-wave signal through one input pin, the frequency of the output signal of the operating frequency control circuit can be controlled by setting adjustable resistors with different resistance values, or the frequency of the output signal of the operating frequency control circuit can be controlled by connecting square-wave signals with different frequencies, thereby reducing the use of pins.

[0050] In an optional implementation manner, asFigure 2 As shown in the figure, the first control circuit 1 includes: a signal detection circuit 11, whose first end is connected to the input pin, whose second end is connected to the external power supply, whose third end is grounded, and whose fourth end is connected to the fourth end of the output circuit. The signal detection circuit 11 is used to detect the input signal of the input pin and output a corresponding output signal. When the input signal is a square wave signal, it outputs an output signal with the same frequency as the square wave signal. When the input signal is not a square wave signal, it outputs a first low-level signal; a switch control circuit 12, whose first end is connected to the fourth end of the signal detection circuit 11, whose second end is connected to the external power supply, whose third end is grounded, whose fourth end is connected to the input pin, whose fifth end is connected to the first end of the second control circuit and the second end of the output circuit, and whose sixth end is connected to the third end of the output circuit. The switch control circuit 12 is used to output a second low-level signal when the signal detection circuit 11 outputs an output signal with the same frequency as the square wave signal, and output a high-level signal when the signal detection circuit 11 outputs a first low-level signal.

[0051] Specifically, as Figure 3 shown in the figure, the signal detection circuit includes a first inverter NOT1, a first AND gate AND1, a first switching transistor M1, a second switching transistor M2, a first resistor R1, and a first capacitor C1. The switch control circuit includes a third switching transistor M3, a fourth switching transistor M4, a second resistor R2, a second capacitor C2, a second inverter NOT2, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a third inverter NOT3, and a fourth inverter NOT4;

[0052] The input end of the first inverter NOT1 is connected to the input pin. The output end of the first inverter NOT1 is connected to the first end of the first switching transistor M1, the first input end of the first AND gate AND1, and the first end of the second switching transistor M2. The second end of the first switching transistor M1 is connected to the external power supply. The third end of the first switching transistor M1 is connected to the second input end of the first AND gate AND1, one end of the first capacitor C1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the second end of the second switching transistor M2. The third end of the second switching transistor M2 is connected to the other end of the first capacitor C1 and grounded. The output end of the first AND gate AND1 is connected to the first end of the third switching transistor M3, the first end of the fourth switching transistor M4, and the fourth end of the output circuit;

[0053] The second terminal of the third switching transistor M3 is connected to an external power supply. The third terminal of the third switching transistor M3 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the second terminal of the fourth switching transistor M4, one end of the second capacitor C2, and the input terminal of the second inverter NOT2. The third terminal of the fourth switching transistor M4 is connected to the second terminal of the second capacitor C2 and grounded. The output terminal of the second inverter NOT2 is connected to the first input terminal of the first NAND gate NAND1 and the first input terminal of the third NAND gate NAND3. The second input terminal of the first NAND gate NAND1 is connected to an input pin. The output terminal of the first NAND gate NAND1 is connected to the first input terminal of the second NAND gate NAND2. The second input terminal of the second NAND gate NAND2 is connected to the output terminal of the third NAND gate NAND3 and the input terminal of the third inverter NOT3. The output terminal of the second NAND gate NAND2 is connected to the second input terminal of the third NAND gate NAND3. The output terminal of the third inverter NOT3 is connected to the input terminal of the fourth inverter NOT4 and the third terminal of the output circuit. The output terminal of the fourth inverter NOT4 is connected to the first terminal of the second control circuit and the second terminal of the output circuit.

[0054] Specifically, by providing a signal detection circuit 11 and a switch control circuit 12 in the first control circuit 1, and by providing the above-mentioned components in the signal detection circuit 11 and the switch control circuit 12. Among them, the charging and discharging process of the first capacitor C1 in the signal detection circuit 11 and the cooperative operation with other components of the signal detection circuit 11 cause the output to be a level signal with the same frequency when the input is a square wave signal; a second capacitor C2 is provided in the switch control circuit 12, and when the external power supply charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2, within one period of the square wave signal, the voltage across the second capacitor C2 is less than the switching threshold voltage of the second inverter NOT2, thereby causing the output of the switch control circuit not to change. The specific working modes of the various components in the signal detection circuit and the switch control circuit will be described below.

[0055] In an alternative embodiment, as Figure 4As shown, the second control circuit 2 includes: a switch circuit 21, whose first end is connected to the fourth end of the first control circuit 1, whose second end is connected to an external power supply, and whose third end is connected to the input pins G1 / G2; a voltage control circuit 22, whose first end is connected to a first fixed voltage V1, and whose second and third ends are connected to the fourth end of the switch circuit 21; a first charging circuit 23, whose first end is connected to the fourth end of the switch circuit 21, whose second end is connected to the external power supply, and whose third end is grounded; a second charging circuit 24, whose first end is connected to the fourth end of the first charging circuit 23, whose second end is connected to a second fixed voltage V2, whose third end is connected to the external power supply, whose fourth end is grounded, and whose fifth end is connected to the fifth end of the first charging circuit 23 and the first end of the output circuit; when the first control circuit 1 outputs a second low-level signal, the switch circuit 21 turns off the first charging circuit 23, and the second charging circuit 24 outputs a third low-level signal; when the first control circuit 1 outputs a high-level signal, the first charging circuit 23 operates under the control of the switch circuit 21 and the voltage control circuit 22, the first charging circuit 23 outputs a periodic output signal, and the second charging circuit 24 outputs an output signal with the same period as the periodic output signal according to the periodic output signal.

[0056] As Figure 3 shown, the switch circuit includes a fifth switching transistor M5 and an eighth switching transistor M8, the voltage control circuit includes a first comparator CMP1, the first charging circuit includes a sixth switching transistor M6, a seventh switching transistor M7, a ninth switching transistor M9, and a third capacitor C3, and the second charging circuit includes a second comparator CMP2, a tenth switching transistor M10, a fourth capacitor C4, a fifth inverter NOT5, and a first current source B1;

[0057] The first end of the fifth switching transistor M5 is connected to the first end of the eighth switching transistor M8, the fourth end of the first control circuit, and the second end of the output circuit. The second end of the fifth switching transistor M5 is connected to the external power supply. The third end of the fifth switching transistor M5 is connected to the first and second ends of the sixth switching transistor M6, the first end of the seventh switching transistor M7, the output end of the first comparator CMP1, the negative input end of the first comparator CMP1, and the second end of the eighth switching transistor M8. The third end of the eighth switching transistor M8 is connected to the input pins. The positive input end of the first comparator CMP1 is connected to the first fixed voltage V1;

[0058] The third terminal of the sixth switching transistor M6 is connected to the second terminal of the seventh switching transistor M7 and an external power supply. The third terminal of the seventh switching transistor M7 is connected to the positive input terminal of the second comparator CMP2, one end of the third capacitor C3, and the first terminal of the ninth switching transistor M9. The negative input terminal of the second comparator CMP2 is connected to a second fixed voltage. The output terminal of the second comparator CMP2 is connected to the first terminal of the tenth switching transistor. The other end of the third capacitor C3 is connected to the second terminal of the ninth switching transistor M9 and grounded. The second terminal of the tenth switching transistor is connected to the output terminal of the first current source B1, the input terminal of the fifth inverter NOT5, and one end of the fourth capacitor C4. The other end of the fourth capacitor C4 is connected to the third terminal of the tenth switching transistor and grounded. The output terminal of the fifth inverter NOT5 is connected to the third terminal of the ninth switching transistor M9 and the first terminal of the output circuit. The input terminal of the first current source B1 is connected to the external power supply.

[0059] Specifically, by providing a first charging circuit including a third capacitor and a second charging circuit including a fourth capacitor in the second control circuit, during the operation of the circuit, the third capacitor and the fourth capacitor are continuously charged and discharged. Thus, in cooperation with other structures in the second control circuit, the second control circuit outputs a constant signal when a square wave signal is connected to the input pin, and outputs a periodically changing signal when a regulating resistor is connected to the input pin. The specific working modes of the various components in the second control circuit will be described below.

[0060] In an alternative embodiment, as Figure 3 shown, the output circuit 3 includes a second AND gate AND2, a third AND gate AND3, and a first OR gate OR1. The first input terminal of the second AND gate AND2 is connected to the fifth terminal of the second control circuit 2. The second input terminal of the second AND gate AND2 is connected to the fourth terminal of the first control circuit 1. The first input terminal of the third AND gate AND3 is connected to the fifth terminal of the first control circuit 1. The second input terminal of the third AND gate AND3 is connected to the sixth terminal of the first control circuit 1. The output terminal of the second AND gate AND2 is connected to the first input terminal of the first OR gate OR1. The output terminal of the third AND gate AND3 is connected to the second input terminal of the first OR gate OR1. The output terminal of the first OR gate OR1 outputs an output signal having the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the regulating resistor.

[0061] Specifically, by providing a second AND gate AND2, a third AND gate AND3, and a first OR gate OR1 in the output circuit, and receiving the output signal of the signal detection circuit 11, two output signals of the switch control circuit 12, and the output signal of the second charging circuit 24, a periodic output signal can thus be output. The specific working modes of the various components in the output circuit will be described below.

[0062] Specifically, as Figure 3As shown below, the working principle of the operating frequency control circuit will be described when the input pin is connected to the adjusting resistor and when the input square wave signal is applied respectively.

[0063] (1) When the input pin is connected to the adjusting resistor, the input pins G1 / G2 are grounded through the adjusting resistor RL, that is, the input pins G1 / G2 are at low level. Therefore, at this time, the input terminal of the first inverter NOT1, the first input terminal of the first NAND gate NAND1, and the source electrode of the eighth switching transistor M8 are all at low level. The first inverter NOT1 outputs a high level, the first switching transistor M1 is turned off, and the second switching transistor M2 is turned on. The first input terminal of the first AND gate AND1 is pulled low through the first resistor R1 and the second switching transistor M2. Therefore, the output signal CL1 of the first AND gate AND1 is always at low level. At this time, the third switching transistor M3 is turned on, and the fourth switching transistor M4 is turned off. Therefore, the input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. After charging for more than one cycle time, the terminal voltage of the second capacitor C2 exceeds the switching threshold voltage VT of the second inverter NOT2, and the second inverter NOT2 outputs a low level. Also, since the first input terminal of the first NAND gate NAND1 is at low level, the first NAND gate NAND1 outputs a high level. Therefore, the third NAND gate NAND3 outputs a high level, and the second NAND gate NAND2 outputs a low level. Thus, it can be obtained that the output signal P1 of the third inverter NOT3 is at low level, and the output signal is at high level.

[0064] The output signal at high level After entering the fifth switching transistor M5 and the eighth switching transistor M8, the fifth switching transistor M5 is turned off, and the eighth switching transistor M8 is turned on. At this time, the control terminal voltages of the sixth switching transistor M6 and the seventh switching transistor M7 are pulled low through the eighth switching transistor M8 and the adjusting resistor RL, and the sixth switching transistor M6 and the seventh switching transistor M7 are turned on. A current flows through the adjusting resistor RL. At this time, under the adjustment of the first comparator CMP1, the voltage at point D is equal to the first fixed voltage V1. Since the drain-source voltage difference of the eighth switching transistor M8 is extremely small, it can be obtained that the voltage of the input pins G1 / G2 = the voltage at point D = the first fixed voltage V1. First, since the first fixed voltage V1 is less than the switching threshold voltage VT of the inverter, this first fixed voltage V1 is still at low level relative to the first inverter NOT1, that is, when the eighth switching transistor M8 is turned on and the voltage of the input pins G1 / G2 is equal to the first fixed voltage V1, it does not affect the output signal of the first control circuit 1; second, when the eighth switching transistor M8 is turned on and the voltage of the input pins G1 / G2 is equal to the first fixed voltage V1, it can be obtained that the current flowing through the adjusting resistor RL = the current flowing through the sixth switching transistor M6 = , and since the sixth switching transistor M6 and the seventh switching transistor M7 form a 1:N current mirror, the current flowing through the seventh switching transistor M7 , during the first cycle when the circuit is powered on, since there is no charge in the third capacitor C3, its terminal voltage VC is less than the second fixed voltage V2. The second comparator CMP2 outputs a low level, and the tenth switching transistor M10 is turned off. The current I1 output by the first current source B1 charges the fourth capacitor C4, and the terminal voltage of the fourth capacitor C4 gradually rises to a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is a low level, and the ninth switching transistor M9 is turned off. The current I2 charges the third capacitor C3, and the terminal voltage VC of the third capacitor C3 gradually increases. After the first time t1, the terminal voltage VC increases to be greater than the second fixed voltage V2, and the second comparator CMP2 outputs a high level. The tenth switching transistor M10 is turned on, and the input terminal of the fifth inverter NOT5 is instantaneously pulled low through the tenth switching transistor M10. The output signal CL2 of the fifth inverter NOT5 switches to a high level, and the ninth switching transistor M9 is turned on. The terminal voltage VC of the third capacitor C3 is instantaneously pulled low through the ninth switching transistor M9, and the output of the second comparator CMP2 switches to a low level. The tenth switching transistor M10 is turned off. The current I1 output by the first current source B1 charges the fourth capacitor C4. After the second time t2, the terminal voltage of the fourth capacitor C4 gradually rises to a high level state. Before the terminal voltage of the fourth capacitor C4 rises to a high level state greater than the switching threshold voltage VT of the fifth inverter NOT5, the fifth inverter NOT5 always outputs a high level, and the ninth switching transistor M9 is always in the on state. The terminal voltage VC of the third capacitor C3 is always in a low level state. After the terminal voltage of the fourth capacitor C4 rises to a high level state, the output signal CL2 of the fifth inverter NOT5 switches to a low level again, and the circuit enters the next cycle.

[0065] After that, from the structure of the output circuit 3, when the signal P1 is at a low level, the signal is at a high level, and the signal CL1 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5. At this time, the waveform diagram when the adjustment resistor RL is connected can be obtained, as Figure 5 shown.

[0066] From the above analysis, the first time , the second time . Therefore, the second time t2 is a fixed value. By setting the adjustment resistor RL with different resistance values, the first time t1 can be controlled, thereby realizing the control of the operating frequency of the power supply circuit.

[0067] (2) When the input pins G1 / G2 are connected to a square wave signal, it is introduced in two cases;

[0068] (1) The square wave signal is connected to the chip no later than the input power supply VIN:

[0069] (i) When the initial state of the square wave signal is low, the input terminal of the first inverter NOT1, the first input terminal of the first NAND gate NAND1, and the source electrode of the eighth switching transistor M8 are all at low level. The first inverter NOT1 outputs a high level, the first switching transistor M1 is turned off, and the second switching transistor M2 is turned on. Since there is no charge in the first capacitor C1 during the first cycle of power-on of the circuit, therefore, the first input terminal of the first AND gate AND1 is instantaneously pulled low through the first resistor R1 and the second switching transistor M2, and the output signal CL1 of the first AND gate AND1 is at low level. At this time, the third switching transistor M3 is turned on, and the fourth switching transistor M4 is turned off. Therefore, the input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. At this time, the second resistor R2 and the second capacitor C2 are designed such that the voltage of the second capacitor C2 cannot be charged to be greater than the switching threshold voltage VT of the second inverter NOT2 within one cycle of the square wave signal. Therefore, it can be obtained that the input terminal of the second inverter NOT2 is at low level, and the output terminal of the second inverter NOT2 outputs a high level. Also, since the first input terminal of the first NAND gate NAND1 is at low level, therefore, the first NAND gate NAND1 outputs a high level. At this time, if the third NAND gate NAND3 is at low level in the initial state, then the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 still outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is at high level, and the output signal of the fourth inverter NOT4 is at low level. Therefore, the fifth switching transistor M5 is turned on, and the eighth switching transistor M8 is turned off. The control terminal voltages of the sixth switching transistor M6 and the seventh switching transistor M7 are pulled high through the fifth switching transistor M5, and the sixth switching transistor M6 and the seventh switching transistor M7 are turned off. Since there is no charge in the third capacitor C3 during the first cycle of power-on of the circuit, therefore, its terminal voltage VC is less than the second fixed voltage V2, and the second comparator CMP2 outputs a low level. The tenth switching transistor M10 is turned off, and the current I1 output by the first current source B1 charges the fourth capacitor C4. The terminal voltage of the fourth capacitor C4 gradually rises to a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is at low level. At this time, from the structure of the output circuit 3, it can be seen that when the signal P1 is at high level, the signal is at low level, the signal CL1 is at low level, and the signal CL2 is at low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is at low level; if the third NAND gate NAND3 is at high level in the initial state, then the second NAND gate NAND2 outputs a low-high level, and the third NAND gate NAND3 still outputs a high level. At this time, the output signal P1 of the third inverter NOT3 is at low level, and the output signal is at a high level. Therefore, the fifth switching transistor M5 is turned off and the eighth switching transistor M8 is turned on. As analyzed in (1), the output signal CL2 of the fifth inverter NOT5 first outputs a low level, then a high level, and then a low level. At this time, according to the structure of the output circuit 3, when the signal P1 is at a low level and the signal is at a high level and the signal CL1 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5, and finally the output signal CL of the first OR gate OR1 is also at a low level.

[0070] After the square wave signal switches from a low level to a high level, the input terminal of the first inverter NOT1, the first input terminal of the first NAND gate NAND1, and the source electrode of the eighth switching transistor M8 all switch to a high level. The first inverter NOT1 outputs a low level, the first switching transistor M1 is turned on, and the second switching transistor M2 is turned off. The input power supply VIN charges the first capacitor C1 through the first switching transistor M1. At this time, since the first inverter NOT1 outputs a low level, the output signal CL1 of the first AND gate AND1 is also at a low level. At this time, the third switching transistor M3 is turned on and the fourth switching transistor M4 is turned off. Therefore, the input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. Since within one cycle of the square wave signal, the voltage of the second capacitor C2 cannot be charged to be greater than the switching threshold voltage VT of the second inverter NOT2, it can be obtained that the input terminal of the second inverter NOT2 is still at a low level, and the output terminal of the second inverter NOT2 outputs a high level. Also, since the first input terminal of the first NAND gate NAND1 is at a high level, the first NAND gate NAND1 outputs a low level. Therefore, it can be obtained that the second NAND gate NAND2 outputs a high level and the third NAND gate NAND3 outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is at a high level, and the output signal of the fourth inverter NOT4 is at a low level. Therefore, the fifth switching transistor M5 is turned on, the sixth switching transistor M6 and the seventh switching transistor M7 are turned off, the second comparator CMP2 outputs a low level, the tenth switching transistor M10 is turned off, and the terminal voltage of the fourth capacitor C4 is in a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is at a low level. At this time, according to the structure of the output circuit 3, when the signal P1 is at a high level, the signal is at a low level, the signal CL1 is at a low level, and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is at a low level.

[0071] After the square wave signal switches from high level to low level, the input terminal of the first inverter NOT1, the first input terminal of the first NAND gate NAND1, and the source electrode of the eighth switching transistor M8 all switch to low level. The first inverter NOT1 outputs a high level, the first switching transistor M1 turns off, the second switching transistor M2 turns on, and the first capacitor C1 slowly discharges through the first resistor R1 and the second switching transistor M2. The terminal voltage of the first capacitor C1 first maintains a high level state for a period of time and then switches to a low level state. Therefore, after the first AND gate AND1 outputs a high level for a period of time, it switches to a low level. When the output signal CL1 of the first AND gate AND1 is at a high level, the third switching transistor M3 turns off, the fourth switching transistor M4 turns on, and the second capacitor C2 is discharged to 0 through the fourth switching transistor M4. Therefore, the input terminal of the second inverter NOT2 remains at a low level, and the output terminal of the second inverter NOT2 outputs a high level. Also, since the first input terminal of the first NAND gate NAND1 is at a low level, the first NAND gate NAND1 outputs a high level. At this time, since the third NAND gate NAND3 output a low level before, the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 still outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is at a high level, and the output signal of the fourth inverter NOT4 is at a low level; afterwards, when the output signal CL1 of the first AND gate AND1 switches to a low level, the third switching transistor M3 turns on, the fourth switching transistor M4 turns off, and the input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. Since within one cycle of the square wave signal, the voltage of the second capacitor C2 cannot be charged to be greater than the switching threshold voltage VT of the second inverter NOT2, it can be obtained that the input terminal of the second inverter NOT2 still remains at a low level. At this time, the output signal P1 of the third inverter NOT3 still remains at a high level, and the output signal of the fourth inverter NOT4 still remains at a low level; therefore, the fifth switching transistor M5 turns on, the sixth switching transistor M6 and the seventh switching transistor M7 turn off, the second comparator CMP2 outputs a low level, the tenth switching transistor M10 turns off, and the terminal voltage of the fourth capacitor C4 is at a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is at a low level; at this time, from the structure of the output circuit 3, it can be seen that when the signal P1 is at a high level, the signal is at a low level, and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5. That is, at this time, the output signal CL of the first OR gate OR1 maintains a high level for a period of time and then switches to a low level.

[0072] After the square wave signal switches from low level to high level, from the above analysis, it can be seen that the signal P1 is at a high level, the signal When the signal is at a low level, the signal CL1 is at a low level, and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is at a low level.

[0073] After that, the circuit enters the next cycle of the stable state. From what is described in (i), the waveform diagram when receiving a square wave signal in the stable state of the circuit can be obtained, as Figure 6 shown.

[0074] (ii) When the initial state of the square wave signal is at a high level, as in (i), the input terminal of the first inverter NOT1, the first input terminal of the first NAND gate NAND1, and the source electrode of the eighth switching transistor M8 are all switched to a high level. The first inverter NOT1 outputs a low level, the first switching transistor M1 conducts, and the second switching transistor M2 turns off. The input power supply VIN charges the first capacitor C1 through the first switching transistor M1. At this time, since the first inverter NOT1 outputs a low level, the output signal CL1 of the first AND gate AND1 is also at a low level. At this time, the third switching transistor M3 conducts, and the fourth switching transistor M4 turns off. Therefore, the input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. Since within the time of one cycle of the square wave signal, the voltage of the second capacitor C2 cannot be charged to be greater than the switching threshold voltage VT of the second inverter NOT2, it can be obtained that the input terminal of the second inverter NOT2 is still at a low level, and the output terminal of the second inverter NOT2 outputs a high level. Also, since the first input terminal of the first NAND gate NAND1 is at a high level, the first NAND gate NAND1 outputs a low level. Therefore, it can be obtained that the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is at a high level, and the output signal of the fourth inverter NOT4 is at a low level; therefore, the fifth switching transistor M5 conducts, and the sixth and seventh switching transistors M6 and M7 turn off. Since there is no charge in the third capacitor C3 during the first cycle when the circuit is powered on, its terminal voltage VC is less than the second fixed voltage V2, and the second comparator CMP2 outputs a low level, and the tenth switching transistor M10 turns off. The current I1 output by the first current source B1 charges the fourth capacitor C4, and the terminal voltage of the fourth capacitor C4 gradually rises to a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is at a low level; at this time, from the structure of the output circuit 3, when the signal P1 is at a high level, the signal is at a low level, the signal CL1 is at a low level, and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is at a low level.

[0075] After the square wave signal switches from high level to low level, the input terminal of the first inverter NOT1, the first input terminal of the first NAND gate NAND1, and the source electrode of the eighth switching transistor M8 all switch to low level. The first inverter NOT1 outputs a high level. The first switching transistor M1 is turned off, and the second switching transistor M2 is turned on. The first capacitor C1 slowly discharges through the first resistor R1 and the second switching transistor M2. The terminal voltage of the first capacitor C1 first maintains a high level state for a period of time and then switches to a low level state. Therefore, after the first AND gate AND1 outputs a high level for a period of time, it then switches to a low level. When the output signal CL1 of the first AND gate AND1 is at a high level, the third switching transistor M3 is turned off, and the fourth switching transistor M4 is turned on. The second capacitor C2 is discharged to 0 through the fourth switching transistor M4. Therefore, the input terminal of the second inverter NOT2 remains at a low level, and the output terminal of the second inverter NOT2 outputs a high level. Also, since the first input terminal of the first NAND gate NAND1 is at a low level, the first NAND gate NAND1 outputs a high level. At this time, since the third NAND gate NAND3 previously output a low level, the second NAND gate NAND2 outputs a high level, and the third NAND gate NAND3 still outputs a low level. At this time, the output signal P1 of the third inverter NOT3 is at a high level, and the output signal of the fourth inverter NOT4 is at a low level; afterwards, when the output signal CL1 of the first AND gate AND1 switches to a low level, the third switching transistor M3 is turned on, and the fourth switching transistor M4 is turned off. The input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. Since within one cycle of the square wave signal, the voltage of the second capacitor C2 cannot be charged to be greater than the switching threshold voltage VT of the second inverter NOT2, it can be obtained that the input terminal of the second inverter NOT2 still remains at a low level. At this time, the output signal P1 of the third inverter NOT3 still remains at a high level, and the output signal of the fourth inverter NOT4 still remains at a low level; therefore, the fifth switching transistor M5 is turned on, the sixth switching transistor M6 and the seventh switching transistor M7 are turned off, the second comparator CMP2 outputs a low level, the tenth switching transistor M10 is turned off, and the terminal voltage of the fourth capacitor C4 is at a high level state. Therefore, at this time, the output signal CL2 of the fifth inverter NOT5 is at a low level; at this time, from the structure of the output circuit 3, it can be seen that when the signal P1 is at a high level, the signal is at a low level, and when the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is the same as the output signal CL2 of the fifth inverter NOT5. That is, at this time, the output signal CL of the first OR gate OR1 maintains a high level for a period of time and then switches to a low level.

[0076] After the square wave signal switches from low level to high level, from the above analysis, it can be seen that the signal P1 is at a high level, the signal When the signal CL0 is at a low level, the signal CL1 is at a low level, and the signal CL2 is at a low level, the output signal CL of the first OR gate OR1 (i.e., the output signal of the operating frequency control circuit) is at a low level.

[0077] After that, the circuit enters the next cycle of the stable state; as described in (ii), when the circuit is in the stable state, the waveform diagram when receiving the square wave signal is still as Figure 6 shown.

[0078] (2) The square wave signal is connected to the chip later than the input power supply VIN:

[0079] At this time, as analyzed in (1) above, when the input power supply VIN is connected to the chip and the square wave signal is not connected to the chip, the input pins G1 / G2 are in an indeterminate state. However, regardless of whether the input pins G1 / G2 are at a high level or a low level, at the initial stage of power-on, the output signal CL1 of the first AND gate AND1 is always at a low level. Therefore, the third switch transistor M3 is turned on, the fourth switch transistor M4 is turned off, and the input power supply VIN charges the terminal voltage of the second capacitor C2 to a high level through the third switch transistor M3 and the second resistor R2. So at this time, the output of the NOT gate A3 is always at a low level, the output of the first NAND gate NAND1 is always at a high level, the output of the third NAND gate NAND3 is always at a high level, and the output signal P1 of the third inverter NOT3 is always at a low level.

[0080] After that, the square wave signal is connected to the input pins G1 / G2. When the first falling edge of the square wave signal arrives, that is, after the square wave signal switches from high level to low level, the first inverter NOT1 outputs a high level, the first switching transistor M1 is turned off, and the second switching transistor M2 is turned on. The first capacitor C1 discharges slowly through the first resistor R1 and the second switching transistor M2. The terminal voltage of the first capacitor C1 first maintains the high level state for a period of time and then switches to the low level state. Therefore, the first AND gate AND1 outputs a high level for a period of time and then switches to the low level. When the output signal CL1 of the first AND gate AND1 is at the high level, the third switching transistor M3 is turned off, and the fourth switching transistor M4 is turned on. The second capacitor C2 is discharged to 0 through the fourth switching transistor M4. Therefore, the input terminal of the second inverter NOT2 switches to the low level, and the output terminal of the second inverter NOT2 outputs a high level. Also, since the first input terminal of the first NAND gate NAND1 is at the low level, the first NAND gate NAND1 outputs a high level. At this time, since the third NAND gate NAND3 output a high level before, the second NAND gate NAND2 outputs a low level, and the third NAND gate NAND3 still outputs a high level. At this time, the output signal P1 of the third inverter NOT3 is still at the low level; when the output signal CL1 of the first AND gate AND1 switches to the low level, the third switching transistor M3 is turned on, and the fourth switching transistor M4 is turned off. The input power supply VIN charges the second capacitor C2 through the third switching transistor M3 and the second resistor R2. Since within the time of one cycle of the square wave signal, the voltage of the second capacitor C2 cannot be charged to be greater than the switching threshold voltage VT of the second inverter NOT2, it can be obtained that the input terminal of the second inverter NOT2 is still at the low level, the output terminal of the second inverter NOT2 still outputs a high level, and the third NAND gate NAND3 still outputs a high level.

[0081] After the square wave signal switches from low level to high level, the circuit working state is as in (ii); from the above analysis, it can be obtained that although in the second case, the circuit working condition is different from that in (1), when the circuit is stable, the waveform diagram when connecting the square wave signal is still as Figure 6 shown; from the analysis in (1) and (2), it can be known that the frequency of the output signal CL of the working frequency control circuit is the same as the frequency of the square wave signal. By connecting square wave signals with different frequencies, the control of the working frequency of the power supply circuit is realized.

[0082] In addition, it should be noted that when the frequency of the square wave signal is relatively low, it will cause the voltage of the second capacitor C2 to be charged to be greater than the switching threshold voltage VT of the second inverter NOT2. At this time, the output signal P1 of the third inverter NOT3 is always at the low level, and the output signal of the fourth inverter NOT4 It is always at a high level, and the fifth switching transistor M5 is always turned off. When the square wave signal is at a low level, the eighth switching transistor M8 is turned on, and the second control circuit 2 operates briefly. The output signal CL of the operating frequency control circuit generates a brief high-level state. When the square wave signal is at a high level, the eighth switching transistor M8 is turned off, and the output signal CL of the operating frequency control circuit is always at a low level. Therefore, the frequency of the output signal CL of the operating frequency control circuit is the same as the frequency of the square wave signal. However, since an additional frequency detection circuit is provided inside the chip to detect the frequency of the output signal CL of the operating frequency control circuit, when its frequency is low, the chip is in an off state. It can be seen that by adjusting the parameters of the second resistor R2 and the second capacitor C2, the lowest frequency of the output signal CL of the operating frequency control circuit can be controlled.

[0083] This embodiment also provides an integrated circuit control chip, which includes the operating frequency control circuit of the above embodiment.

[0084] This embodiment also provides a power supply circuit with a small volume and a wide application range, such as Figure 7 and Figure 8 as shown. The power supply circuit includes the integrated circuit control chip U1 of the above embodiment. Specifically, the power supply circuit further includes an external power circuit.

[0085] Among them, when multiple power supply circuits are set in the circuit system, each power supply circuit includes an integrated circuit control chip, and each integrated circuit control chip includes an operating frequency control circuit. When the same square wave signal is input through the input pin of the operating frequency control circuit, the operating frequency control circuit can output signals with the same operating frequency. Thus, the operating frequencies of the power supply circuits controlled by multiple integrated circuit control chips can be the same, ensuring the consistency of the operation of each power supply circuit in the circuit system. When only one power supply circuit is set in the circuit system, an external adjustable resistor or an input square wave signal can be used to control the operating frequency of the power supply circuit.

[0086] Therefore, for the power supply circuit with a small volume and a wide application range provided by this embodiment, after an external adjustable resistor or a square wave signal is connected through one pin, the operating frequency of the power supply circuit can be controlled, thereby reducing the volume of the power supply circuit and increasing its application range.

[0087] Although the example embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions, and modifications to these embodiments without departing from the spirit of the present invention and the protection scope defined by the appended claims. Such modifications and variations all fall within the scope defined by the appended claims. For other examples, those of ordinary skill in the art should easily understand that while maintaining the protection scope of the present invention, the order of the process steps can be changed.

[0088] In addition, the scope of application of the present invention is not limited to the processes, mechanisms, manufacturing, compositions of matter, means, methods, and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will readily understand that for processes, mechanisms, manufacturing, compositions of matter, means, methods, or steps that already exist or will be developed in the future, as long as they perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described in the present invention, they can be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacturing, compositions of matter, means, methods, or steps within their scope of protection.

Claims

1. A working frequency control circuit, characterized in that, Comprising: An input pin for receiving an externally input square wave signal or connecting an external adjusting resistor; A first control circuit, with its first end connected to the input pin, its second end connected to an external power supply, and its third end grounded, for obtaining a signal with the same frequency as the square wave signal or a first low-level signal according to whether the input at the input pin is a square wave signal, and outputting a second low-level signal or a high-level signal according to the signal with the same frequency as the square wave signal or the first low-level signal. The fourth end of the first control circuit outputs the second low-level signal or the high-level signal, the fifth end of the first control circuit outputs the inverted signal of the second low-level signal or the inverted signal of the high-level signal, and the sixth end of the first control circuit outputs the signal with the same frequency as the square wave signal or the first low-level signal; A second control circuit, with its first end connected to the fourth end of the first control circuit, its second end connected to the input pin, its third end connected to an external power supply, and its fourth end grounded, for outputting a third low-level signal or a periodic output signal at the fifth end of the second control circuit according to the second low-level signal or the high-level signal output by the first control circuit; An output circuit, with its first end connected to the fifth end of the second control circuit, its second end connected to the fourth end of the first control circuit, its third end connected to the fifth end of the first control circuit, and its fourth end connected to the sixth end of the first control circuit, for outputting an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjusting resistor according to the signal with the same frequency as the square wave signal or the first low-level signal, the second low-level signal or the high-level signal, the inverted signal of the second low-level signal or the high-level signal, and the third low-level signal or the periodic output signal.

2. The operating frequency control circuit according to claim 1, wherein The first control circuit includes: A signal detection circuit, with its first end connected to the input pin, its second end connected to an external power supply, its third end grounded, and its fourth end connected to the fourth end of the output circuit, for detecting the input signal at the input pin, and outputting an output signal with the same frequency as the square wave signal when the input signal is a square wave signal, and outputting a first low-level signal when the input signal is not a square wave signal; A switch control circuit, with its first end connected to the fourth end of the signal detection circuit, its second end connected to an external power supply, its third end grounded, its fourth end connected to the input pin, its fifth end connected to the first end of the second control circuit and the second end of the output circuit, and its sixth end connected to the third end of the output circuit, for outputting a second low-level signal when the signal detection circuit outputs an output signal with the same frequency as the square wave signal, and outputting a high-level signal when the signal detection circuit outputs a first low-level signal.

3. The operating frequency control circuit according to claim 2, wherein The second control circuit includes: A switch circuit, with its first end connected to the fourth end of the first control circuit, its second end connected to an external power supply, and its third end connected to the input pin; A voltage control circuit, with its first end connected to a first fixed voltage, and its second and third ends connected to the fourth end of the switch circuit; A first charging circuit, with its first end connected to the fourth end of the switch circuit, its second end connected to an external power supply, and its third end grounded; A second charging circuit, whose first end is connected to the fourth end of the first charging circuit, whose second end is connected to a second fixed voltage, whose third end is connected to an external power supply, whose fourth end is grounded, and whose fifth end is connected to the fifth end of the first charging circuit and the first end of the output circuit; When the first control circuit outputs a second low-level signal, the switching circuit turns off the first charging circuit, and the second charging circuit outputs a third low-level signal. When the first control circuit outputs a high-level signal, the first charging circuit operates under the control of the switching circuit and the voltage control circuit. The first charging circuit outputs a periodic output signal, and the second charging circuit outputs an output signal with the same period as the periodic output signal.

4. The operating frequency control circuit according to claim 3, wherein The signal detection circuit includes a first inverter, a first AND gate, a first switching transistor, a second switching transistor, a first resistor, and a first capacitor. The switching control circuit includes a third switching transistor, a fourth switching transistor, a second resistor, a second capacitor, a second inverter, a first NAND gate, a second NAND gate, a third NAND gate, a third inverter, and a fourth inverter; The input end of the first inverter is connected to an input pin. The output end of the first inverter is connected to the first end of the first switching transistor, the first input end of the first AND gate, and the first end of the second switching transistor. The second end of the first switching transistor is connected to an external power supply. The third end of the first switching transistor is connected to the second input end of the first AND gate, one end of the first capacitor, and one end of the first resistor. The other end of the first resistor is connected to the second end of the second switching transistor. The third end of the second switching transistor is connected to the other end of the first capacitor and grounded; The output end of the first AND gate is connected to the first end of the third switching transistor, the first end of the fourth switching transistor, and the fourth end of the output circuit; The second end of the third switching transistor is connected to an external power supply. The third end of the third switching transistor is connected to one end of the second resistor. The other end of the second resistor is connected to the second end of the fourth switching transistor, one end of the second capacitor, and the input end of the second inverter. The third end of the fourth switching transistor is connected to the second end of the second capacitor and grounded. The output end of the second inverter is connected to the first input end of the first NAND gate and the first input end of the third NAND gate. The second input end of the first NAND gate is connected to the input pin. The output end of the first NAND gate is connected to the first input end of the second NAND gate. The second input end of the second NAND gate is connected to the output end of the third NAND gate and the input end of the third inverter. The output end of the second NAND gate is connected to the second input end of the third NAND gate. The output end of the third inverter is connected to the input end of the fourth inverter and the third end of the output circuit. The output end of the fourth inverter is connected to the first end of the second control circuit and the second end of the output circuit.

5. The operating frequency control circuit according to claim 3, wherein The switching circuit includes a fifth switching transistor and an eighth switching transistor. The voltage control circuit includes a first comparator. The first charging circuit includes a sixth switching transistor, a seventh switching transistor, a ninth switching transistor, and a third capacitor. The second charging circuit includes a second comparator, a tenth switching transistor, a fourth capacitor, a fifth inverter, and a first current source; The first end of the fifth switching transistor is connected to the first end of the eighth switching transistor, the fourth end of the first control circuit, and the second end of the output circuit. The second end of the fifth switching transistor is connected to an external power supply. The third end of the fifth switching transistor is connected to the first and second ends of the sixth switching transistor, the first end of the seventh switching transistor, the output end of the first comparator, the negative input end of the first comparator, and the second end of the eighth switching transistor. The third end of the eighth switching transistor is connected to an input pin. The positive input end of the first comparator is connected to a first fixed voltage. The third end of the sixth switching transistor is connected to the second end of the seventh switching transistor and the external power supply. The third end of the seventh switching transistor is connected to the positive input end of the second comparator, one end of the third capacitor, and the first end of the ninth switching transistor. The negative input end of the second comparator is connected to a second fixed voltage. The output end of the second comparator is connected to the first end of the tenth switching transistor. The other end of the third capacitor is connected to the second end of the ninth switching transistor and grounded. The second end of the tenth switching transistor is connected to the output end of the first current source, the input end of the fifth inverter, and one end of the fourth capacitor. The other end of the fourth capacitor is connected to the third end of the tenth switching transistor and grounded. The output end of the fifth inverter is connected to the third end of the ninth switching transistor and the first end of the output circuit. The input end of the first current source is connected to the external power supply.

6. The operating frequency control circuit according to claim 1, wherein The output circuit includes a second AND gate, a third AND gate, and a first OR gate. The first input end of the second AND gate is connected to the fifth end of the second control circuit. The second input end of the second AND gate is connected to the fourth end of the first control circuit. The first input end of the third AND gate is connected to the fifth end of the first control circuit. The second input end of the third AND gate is connected to the sixth end of the first control circuit. The output end of the second AND gate is connected to the first input end of the first OR gate. The output end of the third AND gate is connected to the second input end of the first OR gate. The output end of the first OR gate outputs an output signal with the same frequency as the square wave signal or an output signal whose frequency is controlled by the resistance value of the adjustment resistor.

7. The operating frequency control circuit according to claim 4, wherein The first fixed voltage is less than the switching threshold voltage of the first inverter. When the external power supply charges the second capacitor through the third switching transistor and the second resistor, within one period of the square wave signal, the voltage across the second capacitor is less than the switching threshold voltage of the second inverter.

8. The operating frequency control circuit according to claim 4, wherein The lowest frequency of the signal output by the output circuit is controlled according to the parameters of the second resistor and the second capacitor.

9. An integrated circuit control chip, characterized in that, The chip includes the operating frequency control circuit according to any one of claims 1-8.

10. A power supply circuit with a small volume and a wide application range, characterized in that, The power supply circuit includes the integrated circuit control chip according to claim 9.

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