Multi-phase power converter circuit and control circuit thereof

Abstract

The invention discloses a multi-phase power converter circuit and a control circuit thereof. A multiphase power converter circuit receives an input voltage at a voltage input terminal and outputs an output voltage at a voltage output terminal, and includes a power stage circuit and a control circuit. The power stage circuit is coupled to the voltage input terminal and is coupled to the phase output terminal through the inductor. The control circuit is coupled to the power stage circuit, the phase output end and the voltage output end, generates an error signal according to the phase current of the phase output end, the output voltage and the reference voltage, generates a compensation signal according to the reference voltage and the error signal, generates a ramp signal according to the error signal, and outputs the ramp signal when the ramp signal crosses the compensation signal. The power level circuit is controlled to operate according to a preset duty ratio, so that the phase current is increased. The control circuit and the multi-phase power converter circuit have the advantages of better load transient response capability and the like through the compensation signal and the ramp signal which make opposite responses to the change of the output voltage.

Description

Technical Field

[0001] The present application relates to a control circuit, and more particularly to a control circuit applied to a multi-phase power converter circuit. Background Art

[0002] With the development of semiconductor technology, the ability of multi-phase power converter circuits to respond to load transients has become increasingly important. Some related technologies subtract the output voltage from the reference voltage to obtain an error signal, then convert the error signal into a current signal to charge the capacitor to obtain a sawtooth signal, and then compare the sawtooth signal with another reference voltage to obtain a pulse-width modulation (PWM) control signal. However, under the above-mentioned load transient operation, the reference voltage is a constant value, and the sawtooth signal is the result of converting the error signal, which makes the response speed slower and thus has poor transient performance. Therefore, it is necessary to propose a new way to solve the above-mentioned problem. Summary of the invention

[0003] One aspect of the present application is a control circuit suitable for a multi-phase power converter circuit. The control circuit includes an error detection circuit, a compensation generation circuit, a ramp generation circuit, and a comparison circuit. The error detection circuit is coupled to the phase output terminal and the voltage output terminal of the multi-phase power converter circuit, and is used to detect the phase current of the phase output terminal and the output voltage of the voltage output terminal, and is used to output an error signal associated with the phase current, the output voltage, and a reference voltage. The compensation generation circuit is coupled to the error detection circuit, and is used to output a compensation signal based on the error signal and the reference voltage. The ramp generation circuit is coupled to the error detection circuit, and is used to output a ramp signal based on the error signal. The comparison circuit is coupled to the compensation generation circuit and the ramp generation circuit, and is used to receive the compensation signal and the ramp signal, and is used to generate at least one trigger pulse when the ramp signal crosses the compensation signal.

[0004] In some embodiments, the compensation generating circuit includes an amplifier circuit and an operation circuit. The amplifier circuit is coupled to the error detection circuit to receive the error signal and amplify the error signal to output an amplified error signal. The operation circuit is coupled to the amplifier circuit and the comparison circuit to receive the reference voltage and the amplified error signal and output the compensation signal according to the difference between the reference voltage and the amplified error signal.

[0005] In some embodiments, the ramp generating circuit includes a capacitor, an integrating circuit and a transconductance amplifier circuit. The integrating circuit is coupled to the error detecting circuit, and is used to receive the error signal and integrate the error signal to output an integrated error signal. The transconductance amplifier circuit is coupled to the integrating circuit, the capacitor and the comparison circuit, and is used to receive the integrated error signal and convert the integrated error signal into a conversion current, so as to charge the capacitor through the conversion current, thereby outputting the ramp signal.

[0006] In some embodiments, the comparison circuit is used to output a setting signal and to adjust the voltage level of the setting signal based on the compensation signal and the error signal, wherein when the ramp signal is greater than the compensation signal, the comparison circuit switches the voltage level of the setting signal from a first voltage level to a second voltage level at equal time intervals to generate the at least one trigger pulse.

[0007] In some embodiments, the comparison circuit includes a comparator and a delay circuit. The comparator is used to output a setting signal, to compare the ramp signal and the compensation signal, and to adjust the voltage level of the setting signal according to the comparison result of the ramp signal and the compensation signal, wherein the comparator adjusts the setting signal from a first voltage level to a second voltage level when the ramp signal is greater than the compensation signal. The delay circuit is coupled to the comparator and is used to output the setting signal of the second voltage level at equal time intervals to generate the at least one trigger pulse.

[0008] In some embodiments, the error detection circuit includes a resistor, a first operation circuit, and a second operation circuit. The resistor is coupled to the phase output terminal of the multi-phase power converter circuit and is used to generate a conversion voltage dependent on the phase current. The first operation circuit is coupled to the resistor, and is used to receive the conversion voltage and the reference voltage, and is used to generate a dependent reference voltage according to the difference between the reference voltage and the conversion voltage. The second operation circuit is coupled to the first operation circuit, and is used to receive the dependent reference voltage and the output voltage, and is used to generate the error signal according to the difference between the dependent reference voltage and the output voltage.

[0009] In some embodiments, the multi-phase power converter circuit includes an on-time generating circuit and a power stage circuit, and the at least one trigger pulse is used to trigger the on-time generating circuit to control the power stage circuit to operate according to a preset duty cycle.

[0010] Another aspect of the present application is a multi-phase power converter circuit. The multi-phase power converter circuit is used to receive an input voltage at a voltage input terminal, to output an output voltage at a voltage output terminal, and includes a power stage circuit and a control circuit. The power stage circuit is coupled to the voltage input terminal and is coupled to the phase output terminal through an inductor. The control circuit is coupled to the power stage circuit, the phase output terminal, and the voltage output terminal, and is used to generate an error signal based on the phase current of the phase output terminal, the output voltage, and a reference voltage, to generate a compensation signal based on the reference voltage and the error signal, to generate a ramp signal based on the error signal, and to control the power stage circuit to operate according to a preset duty cycle when the ramp signal crosses the compensation signal, so that the phase current increases.

[0011] In some embodiments, the control circuit includes an error detection circuit, a compensation generation circuit, a ramp generation circuit, and a comparison circuit. The error detection circuit is coupled to the phase output terminal and the voltage output terminal, and is used to detect the phase current and the output voltage, and is used to output the error signal associated with the phase current, the output voltage, and the reference voltage. The compensation generation circuit is coupled to the error detection circuit, and is used to amplify the error signal, and is used to output the compensation signal according to a calculated value generated based on the reference voltage and the amplified error signal. The ramp generation circuit is coupled to the error detection circuit, and is used to perform an operation on the error signal, and is used to perform a voltage-to-current conversion on the error signal after the operation is performed, so as to output the ramp signal. The comparison circuit is coupled to the compensation generation circuit and the ramp generation circuit, and is used to receive the compensation signal and the ramp signal, and is used to generate at least one trigger pulse when the ramp signal is greater than the compensation signal.

[0012] In some embodiments, the control circuit further comprises an on-time generating circuit coupled between the comparison circuit and the power stage circuit and configured to be triggered by the at least one trigger pulse to control the power stage circuit to operate according to the preset duty cycle.

[0013] In summary, by providing a compensation signal and a ramp signal that react oppositely to changes in the output voltage, the control circuit and the multi-phase power converter circuit of the present application have advantages such as better load transient response capability compared to related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The invention is a circuit diagram of a multi-phase power converter circuit according to some embodiments of the present application.

[0015] Figure 2 It is a circuit diagram of a control circuit according to some embodiments of the present application.

[0016] Figure 3The following is a timing diagram of some signals in a multi-phase power converter circuit according to some embodiments of the present application.

[0017] Figure 4 The following are timing diagrams of some signals in a multi-phase power converter circuit according to some embodiments of the present application and some signals in related technologies. DETAILED DESCRIPTION

[0018] The following lists the embodiments and the accompanying drawings for detailed description, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the elements to produce a device with equal functions is within the scope of this application.

[0019] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure, and in the specific context, unless otherwise noted.

[0020] As used herein, “coupled” or “connected” may refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, or may refer to two or more elements operating or moving with each other.

[0021] See also Figure 1 , Figure 1 FIG. 1 is a circuit diagram of a multi-phase power converter circuit 100 according to some embodiments of the present application. Specifically, the multi-phase power converter circuit 100 may be, for example, a DC / DC converter such as a multi-phase buck converter. In some embodiments, the multi-phase power converter circuit 100 is used to receive an input voltage VIN at a voltage input terminal NIN and to output an output voltage VOUT at a voltage output terminal NOUT to supply power to a load (not shown) such as a central processing unit (CPU). Figure 1 The load resistor RL coupled to the voltage output terminal NOUT is the equivalent resistance of the load.

[0022] In some embodiments, the multi-phase power converter circuit 100 includes a power stage circuit 10, a control circuit 20, and an on-time generating circuit 30. Figure 1 As shown, the power stage circuit 10 is electrically coupled to the voltage input terminal NIN. The output terminal NPS of the power stage circuit 10 is coupled to the phase output terminal NPHA through the inductor L, and the phase output terminal NPHA is coupled to the voltage output terminal NOUT. The control circuit 20 is coupled to the phase output terminal NPHA, the voltage output terminal NOUT and the on-time generating circuit 30, and the on-time generating circuit 30 is coupled to the power stage circuit 10.

[0023] In some embodiments, the power stage circuit 10 includes a driving circuit 11, a high-side switch 12, and a low-side switch 13. The high-side switch 12 is coupled between the voltage input terminal NIN (or input voltage VIN) and the output terminal NPS, and the low-side switch 13 is coupled between the output terminal NPS and the ground voltage GND. In other words, the high-side switch 12 and the low-side switch 13 are connected in series between the input voltage VIN and the ground voltage GND. The driving circuit 11 is controlled by a control signal (not shown) such as a pulse width modulation (PWM) signal, and the high-side switch 12 and the low-side switch 13 are alternately turned on by a driving signal VGH and a driving signal VGL, so that the phase current IL is output from the inductor L. Specifically, the high-side switch 12 and the low-side switch 13 can each be implemented by a transistor, but the present invention is not limited thereto.

[0024] At Figure 1 In FIG. 1 , the power stage circuit 10 and the inductor L correspond to one phase of the multi-phase power converter circuit 100 . Figure 1 The remaining phases of the multi-phase power converter circuit 100 are not shown in the figure, but it should be understood that the remaining phases of the multi-phase power converter circuit 100 also include a set of power stage circuits and inductors, and the configuration and operation of the power stage circuits and inductors in the remaining phases are similar to those in the embodiment of the present invention. Figure 1 The configuration and operation of the power stage circuit 10 and the inductor L are similar, so their description is omitted here. The outputs of all phases in the multi-phase power converter circuit 100 are summed together at the phase output terminal NPHA to provide an output voltage VOUT at the voltage output terminal NOUT. The sum of all phase outputs in the multi-phase power converter circuit 100 can be, for example, Figure 1 The sum of the phase current IL in and the phase currents of the remaining phases. Figure 1 The remaining phases of the multi-phase power converter circuit 100 are not shown in the figure. Figure 1 The phase current IL in represents the sum of all phase currents.

[0025] In some embodiments, a resistor RCO and a decoupling capacitor CO are connected in series between the phase output terminal NPHA and the voltage output terminal NOUT, and are connected in parallel with the load resistor RL to optimize the responsiveness of the multi-phase power converter circuit 100 to load transients.

[0026] For example, in some practical applications, the load may require a larger operating current due to a temporary task change (e.g., running a specific application and / or software), that is, the multi-phase power converter circuit 100 needs to increase the value of the phase current IL. Due to some non-ideal factors, the phase current IL cannot be immediately increased to the operating current value required by the load. At this time, the decoupling capacitor CO electrically coupled to the voltage output terminal NOUT in the multi-phase power converter circuit 100 will discharge to compensate for the shortage of the phase current IL. However, the discharge of the decoupling capacitor CO causes the output voltage VOUT to undershoot.

[0027] In view of this, in some embodiments, the control circuit 20 and the on-time generating circuit 30 are coupled between the voltage output terminal NOUT and the power stage circuit 10 to form a feedback loop. Through this feedback loop, the multi-phase power converter circuit 100 can improve the undershoot phenomenon of the output voltage VOUT, and this principle will be further explained in the following paragraphs.

[0028] In some embodiments, such as Figure 1 As shown, the control circuit 20 includes an error detection circuit 21, a compensation generation circuit 22, a slope generation circuit 23 and a comparison circuit 24. The error detection circuit 21 is coupled to the phase output terminal NPHA and the voltage output terminal NOUT, and is used to detect the phase current IL and the output voltage VOUT, to receive the reference voltage VDAC, and to output the error signal VERR according to the phase current IL, the output voltage VOUT and the reference voltage VDAC. It can be seen that the error signal VERR is related to the phase current IL, the output voltage VOUT and the reference voltage VDAC. The compensation generation circuit 22 is coupled to the error detection circuit 21, and is used to receive the reference voltage VDAC and the error signal VERR, and is used to output the compensation signal VCOMP according to the reference voltage VDAC and the error signal VERR. The slope generation circuit 23 is coupled to the error detection circuit 21, and is used to receive the error signal VERR, and is used to output the ramp signal VRAMP according to the error signal VERR. Furthermore, the comparison circuit 24 is coupled to the compensation generation circuit 22 , the ramp generation circuit 23 and the on-time generation circuit 30 , and is arranged to receive the compensation signal VCOMP and the ramp signal VRAMP, and to compare the compensation signal VCOMP with the ramp signal VRAMP.

[0029] Following the description of the aforementioned practical application, in some embodiments, the output voltage VOUT is significantly reduced due to changes in the load task (i.e., the output voltage VOUT undershoots), which further affects the error signal VERR output based on the phase current IL, the output voltage VOUT and the reference voltage VDAC. For example, the value of the error signal VERR (e.g., voltage level, etc.) will increase. Then, the change in the error signal VERR affects the compensation signal VCOMP and the ramp signal VRAMP, respectively, causing the value of the compensation signal VCOMP and the value of the ramp signal VRAMP to change. Specifically, the ramp signal VRAMP may cross the compensation signal VCOMP at a certain point in time, which will be discussed in the following paragraphs. Figure 2 and Figure 3 Further explanation: The description of "a signal crossing over another signal" herein means that the voltage level of the signal exceeds or is greater than the voltage level of the other signal.

[0030] In some embodiments, such as Figure 1 As shown, when the ramp signal VRAMP crosses the compensation signal VCOMP, the comparison circuit 24 will generate at least one trigger pulse PTRI to the on-time generation circuit 30. Through the triggering of the trigger pulse PTRI, the on-time generation circuit 30 will, for example, control the power stage circuit 10 to operate according to a preset duty ratio by changing the duty ratio of the aforementioned control signal to increase the phase current IL and stabilize the output voltage VOUT.

[0031] In some embodiments, the magnitude of the error signal VERR decreases as the phase current IL increases and the output voltage VOUT stabilizes (i.e., the undershoot of the output voltage VOUT is improved), so that the compensation signal VCOMP may cross the ramp signal VRAMP at another time point after a certain time point. In response to the compensation signal VCOMP crossing the ramp signal VRAMP, the comparison circuit 24 stops generating the trigger pulse PTRI to the on-time generation circuit 30, and the on-time generation circuit 30 correspondingly controls the power stage circuit 10 to operate according to the original duty cycle, wherein the original duty cycle is lower than the aforementioned preset duty cycle.

[0032] As can be seen from the above-mentioned embodiments, the control circuit 20 is used to generate the error signal VERR according to the phase current IL of the phase output terminal NPHA, the output voltage VOUT and the reference voltage VDAC, to generate the compensation signal VCOMP according to the reference voltage VDAC and the error signal VERR, to generate the ramp signal VRAMP according to the error signal VERR, and to trigger the on-time generation circuit 30 to control the power stage circuit 10 to operate according to a preset duty cycle when the ramp signal VRAMP crosses the compensation signal VCOMP, so that the phase current IL increases. In addition, the control circuit 20 is also used to trigger the on-time generation circuit 30 to control the power stage circuit 10 to operate according to the original duty cycle when the compensation signal VCOMP crosses the ramp signal VRAMP, so that the phase current IL decreases.

[0033] Then match Figure 2 The circuit structures of the error detection circuit 21, the compensation generation circuit 22, the slope generation circuit 23 and the comparison circuit 24 are described. Figure 2 , Figure 2 FIG. 2 is a circuit diagram of a control circuit 20 according to some embodiments of the present application.

[0034] At Figure 2 In some embodiments, the error detection circuit 21 includes a resistor 201, a computing circuit 211, and a computing circuit 221. In some embodiments, the resistor 201 is coupled to Figure 1 The phase output terminal NPHA of the multi-phase power converter circuit 100 is used to generate a conversion voltage VL dependent on the phase current IL, that is, the conversion voltage VL is a dependent power source corresponding to the phase current IL. Figure 2 As shown, the conversion voltage VL may have a voltage level representing the multiplication of the phase current IL and the resistance value RI of the resistor 201. The operation circuit 211 is coupled to the resistor 201, and is used to receive the conversion voltage VL and the reference voltage VDAC, and is used to generate the dependent reference voltage VREF according to the difference between the reference voltage VDAC and the conversion voltage VL. Specifically, the dependent reference voltage VREF may have a voltage level of the reference voltage VDAC minus the conversion voltage VL. As can be seen from the description of the conversion voltage VL, the voltage level of the dependent reference voltage VREF is related to the magnitude of the phase current IL. The operation circuit 221 is coupled to the operation circuit 211, and is used to receive the dependent reference voltage VREF and the output voltage VOUT, and is used to generate the error signal VERR according to the difference between the dependent reference voltage VREF and the output voltage VOUT. Specifically, the error signal VERR may have a voltage level representing the dependent reference voltage VREF minus the output voltage VOUT. In summary, the voltage level of the error signal VERR can be calculated by the following formula (1).

[0035] VERR=(VDAC-(IL×RI))-VOUT…(1)

[0036] In the above formula (1), both the resistance value RI and the reference voltage VDAC are preset to fixed values. For example, the resistance value RI is 0.5-4 milliohms, and the reference voltage VDAC is 0-1.52 volts. In addition, the dependent reference voltage VREF is a reference value set for the output voltage VOUT of the multi-phase power converter circuit 100 to follow.

[0037] At Figure 2 In the embodiment of the present invention, the compensation generating circuit 22 includes an amplifier circuit 202 and an operation circuit 212. The amplifier circuit 202 is coupled to the error detection circuit 21, and is used to receive the error signal VERR, and is used to amplify the error signal VERR to output the amplified error signal VERRA. The operation circuit 212 is coupled to the amplifier circuit 202 and the comparison circuit 24, and is used to receive the reference voltage VDAC and the amplified error signal VERRA, and is used to output the compensation signal VCOMP according to the difference between the reference voltage VDAC and the amplified error signal VERRA. Specifically, the compensation signal VCOMP may have a voltage level of the reference voltage VDAC minus the amplified error signal VERRA. The present invention amplifies the error amount (i.e., the error signal VERR) through the amplifier circuit 202, and then subtracts it from the reference voltage VDAC. In this way, the error amount will be quickly reflected on the compensation signal VCOMP through the amplifier circuit 202 (because the generation of the compensation signal VCOMP does not pass through the integrator and the transconductance amplifier), so that the ramp signal VRAMP and the compensation signal VCOMP cross faster to quickly reduce the error amount (i.e., reduce the value of the error signal VERR). Therefore, the overall control loop (e.g., the control circuit 20 and the on-time generation circuit 30) will have a better transient response.

[0038] Depend on Figure 2 It can be seen from the description of the compensation generating circuit 22 that in some embodiments, the compensation generating circuit 22 is used to receive the reference voltage VDAC and the error signal VERR, to amplify the error signal VERR, and to output the compensation signal VCOMP based on a calculated value generated based on the reference voltage VDAC and the amplified error signal VERR (i.e., the difference between the reference voltage VDAC and the amplified error signal VERR).

[0039] At Figure 2In the embodiment of the present invention, the ramp generating circuit 23 includes a capacitor 223, an integrating circuit 203 and a transconductance amplifier circuit 213. The integrating circuit 203 is coupled to the error detecting circuit 21, and is used to receive the error signal VERR, and is used to integrate the error signal VERR to output the integrated error signal VERRI. The transconductance amplifier circuit 213 is coupled to the integrating circuit 203, the capacitor 223 and the comparing circuit 24, and is used to receive the first power supply voltage VDD, the integrated error signal VERRI and the second power supply voltage VEE, and is used to convert the integrated error signal VERRI into a conversion current IERRI, so as to charge the capacitor 223 through the conversion current IERRI, thereby outputting the ramp signal VRAMP.

[0040] Depend on Figure 2 As can be seen from the description of the ramp generating circuit 23, in some embodiments, the ramp generating circuit 23 is used to receive the error signal VERR, to perform an operation (i.e., an integration operation) on the error signal VERR, and to perform a voltage-to-current conversion on the error signal VERR (i.e., the integrated error signal VERRI) after the operation is performed, so as to output the ramp signal VRAMP.

[0041] At Figure 2 In the embodiment of FIG. 2 , the comparison circuit 24 includes a comparator 204 and a delay circuit 214. Figure 2 As shown, the comparator 204 has an inverting input terminal and a non-inverting input terminal. The compensation generating circuit 22 is coupled to the inverting input terminal of the comparator 204, and the ramp generating circuit 23 is coupled to the non-inverting input terminal of the comparator 204. In other words, the inverting input terminal of the comparator 204 is used to receive the compensation signal VCOMP, and the non-inverting input terminal of the comparator 204 is used to receive the ramp signal VRAMP. Accordingly, the comparator 204 compares the ramp signal VRAMP and the compensation signal VCOMP to output the setting signal SET. In some embodiments, the comparator 204 is used to adjust the voltage level of the setting signal SET according to the comparison result of the ramp signal VRAMP and the compensation signal VCOMP. The delay circuit 214 is coupled to the comparator 204, and is used to receive the setting signal SET, and is used to delay the output of the setting signal SET to output another setting signal SETD.

[0042] Then match Figure 3 The relationship among the ramp signal VRAMP, the compensation signal VCOMP, the setting signal SET and the setting signal SETD is further described. Figure 3 , Figure 3 FIG. 1 is a timing diagram of some signals in the multi-phase power converter circuit 100 according to some embodiments of the present application.

[0043] In some embodiments, such as Figure 3As shown, at time T1, the output voltage VOUT decreases due to the change in load task. Combined with the above formula (1), it can be seen that when the phase current IL has not increased, the decrease in the output voltage VOUT will cause the voltage level of the error signal VERR to increase. Next, from the above description of the compensation signal VCOMP, it can be seen that the increase in the voltage level of the error signal VERR will cause the voltage level of the compensation signal VCOMP to decrease. In addition, as the voltage level of the error signal VERR changes, the voltage level of the ramp signal VRAMP gradually begins to change into a continuous ramp waveform (or a continuous triangle waveform, a sawtooth waveform, etc.). By Figure 3 It can be seen that the compensation signal VCOMP and the ramp signal VRAMP substantially react in opposite ways to the decrease of the output voltage VOUT. Accordingly, at time T1 , the ramp signal VRAMP crosses (or is greater than) the compensation signal VCOMP.

[0044] In the embodiment in which the comparator 204 adjusts the voltage level of the setting signal SET according to the comparison result of the ramp signal VRAMP and the compensation signal VCOMP, as shown in FIG. Figure 2 As shown, when the ramp signal VRAMP is greater than the compensation signal VCOMP, the comparator 204 adjusts the setting signal SET from the first voltage level V1 to the second voltage level V2 higher than the first voltage level V1. Furthermore, the setting signal SET of the second voltage level V2 is delayed by the delay circuit 214 and output at equal time intervals (i.e., output as another setting signal SETD) to generate at least one trigger pulse PTRI.

[0045] Then, if Figure 1 As shown, the trigger pulse PTRI triggers the on-time generating circuit 30 to control the power stage circuit 10 to operate according to a preset duty cycle. For example, in some embodiments, the driving circuit 11 in the power stage circuit 10 is controlled by the on-time generating circuit 30 to adjust the driving signal VGH for driving the high-side switch 12 and the driving signal VGL for driving the low-side switch 13, so that the power stage circuit 10 operates according to the preset duty cycle.

[0046] At Figure 3 In the embodiment, after time T1, each cycle of the driving signal VGH has an enabling period PE and a disabling period PD. Figure 3 It can be seen that the enable period PE of the driving signal VGH after time T1 is substantially equal to the enable period of the driving signal VGH before time T1. However, the disable period PD of the driving signal VGH after time T1 is significantly shorter than the disable period of the driving signal VGH before time T1. In other words, the duty cycle of the driving signal VGH increases after time T1 (i.e., after the trigger pulse PTRI triggers the on-time generating circuit 30).

[0047] At Figure 3 In the embodiment of the present invention, the high-side switch 12 is turned on during the enabling period PE and turned off during the disabling period PD. That is, after time T1, the high-side switch 12 is frequently turned on and off alternately, which also means that the output per unit time of the power stage circuit 10 will increase. Since the high-side switch 12 and the low-side switch 13 are usually turned on alternately, the operation of the low-side switch 13 can be inferred based on the operation of the high-side switch 12, so the description of the low-side switch 13 and the driving signal VGL is omitted here.

[0048] In summary, the power stage circuit 10 operates according to a preset duty cycle (eg, the percentage of the enable period PE to the sum of the enable period PE and the disable period PD), so that Figure 1 The phase current IL increases and the output voltage VOUT decreases at a rate as Figure 3 Shown slowing down.

[0049] In some embodiments, the phase current IL is substantially close to the operating current required by the load, and the output voltage VOUT is substantially close to the aforementioned dependent reference voltage VREF (i.e., the output voltage VOUT is stable, and the undershoot of the output voltage VOUT is improved). The voltage level of the error signal VERR in this case will be significantly lower than the voltage level of the error signal VERR at time T1. Based on the decrease in the voltage level of the error signal VERR, the voltage level of the compensation signal VCOMP will increase, and the voltage level of the ramp signal VRAMP will begin to change from a continuous ramp waveform back to a flat waveform. Accordingly, if Figure 3 As shown, at time T2 , the compensation signal VCOMP crosses (or is greater than) the ramp signal VRAMP.

[0050] As can be seen from the description of the comparison circuit 24, as the compensation signal VCOMP crosses the ramp signal VRAMP, the comparator 204 adjusts the setting signal SET from the second voltage level V2 to the first voltage level V1, and further maintains the setting signal SETD output by the delay circuit 214 at the first voltage level V1 (which is equivalent to not generating the trigger pulse PTRI). It can be seen that the comparison circuit 24 stops generating the trigger pulse PTRI when the compensation signal VCOMP crosses the ramp signal VRAMP. Please note that the first voltage level V1 can be a low logic level, and the second voltage level V2 can be a high logic level.

[0051] See also Figure 4 , Figure 4 The timing diagrams are some signals in the multi-phase power converter circuit 100 and some signals in the related art according to some embodiments of the present application.

[0052] Figure 4The compensation signal VCOMP and the ramp signal VRAMP generated by the aforementioned circuit architecture of the present application are shown, and the ramp signal Vramp and the fixed threshold value VTH generated by the circuit architecture of the related art are shown. Figure 4 It can be seen that, compared to the ramp signal Vramp crossing the threshold value VTH at time T3 (i.e., the ramp signal Vramp crosses the threshold value VTH), the compensation signal VCOMP and the ramp signal VRAMP of the present application have crossed at time T1 earlier than time T3 (i.e., the ramp signal VRAMP crosses the compensation signal VCOMP). Figure 4 As shown, the driving signal VGH of the present application generates a plurality of dense and continuous pulses one step earlier than the driving signal Vgh in the related art (ie, the power stage circuit 10 starts to operate with a preset duty cycle one step earlier).

[0053] It can be seen from the above-mentioned implementation methods of the present application that, by providing the compensation signal VCOMP and the ramp signal VRAMP that react oppositely to the change in the output voltage VOUT, the control circuit 20 and the multi-phase power converter circuit 100 of the present application have advantages such as better load transient response capability compared to the related art.

[0054] It should be understood that the multi-phase power converter circuit 100 of the present application is not limited to Figure 1 The circuit architecture shown in FIG. 1 is a circuit architecture shown in FIG. 2 . For example, the on-time generating circuit 30 can be integrated into the control circuit 20. Accordingly, in some embodiments, the multi-phase power converter circuit 100 includes a power stage circuit 10 and a control circuit 20. The control circuit 20 is coupled to the power stage circuit 10, the phase output terminal NPHA, and the voltage output terminal NOUT. Under this circuit architecture, the control circuit 20 controls the power stage circuit 10 to operate according to a preset duty cycle when the ramp signal VRAMP crosses the compensation signal VCOMP, so that the phase current IL increases.

[0055] In addition, by Figure 2 According to the embodiment of the present invention, the comparison circuit 24 includes a comparator 204 and a delay circuit 214, and when the ramp signal VRAMP is greater than the compensation signal VCOMP, the voltage level of the setting signal SETD is switched from the first voltage level V1 to the second voltage level V2 at equal time intervals to generate at least one trigger pulse PTRI. However, the present application is not limited thereto. For example, the delay circuit 214 can be omitted or integrated into the conduction time generation circuit 30. Accordingly, in some embodiments, the delay circuit 214 is Figure 2 In this circuit structure, when the ramp signal VRAMP crosses the compensation signal VCOMP, the comparison circuit 24 adjusts the setting signal SET from the first voltage level V1 to the second voltage level V2 to generate the trigger pulse PTRI.

[0056] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the following claims.

[0057]

Explanation of symbols

[0058] 10: Power stage circuit

[0059] 11: Driving circuit

[0060] 12: High-side switch

[0061] 13: Low-side switch

[0062] 20: Control circuit

[0063] 21: Error detection circuit

[0064] 22: Compensation generation circuit

[0065] 23: Ramp generation circuit

[0066] 24: Comparison Circuit

[0067] 30: On-time generation circuit

[0068] 100:Multi-phase power converter circuit

[0069] 201,RCO:Resistors

[0070] 202: Amplifier circuit

[0071] 203: Integrator Circuit

[0072] 204: Comparator

[0073] 211,212,221: Operational circuit

[0074] 213: Transduction Amplification Circuit

[0075] 214: Delay circuit

[0076] 223:Capacitor

[0077] CO: Decoupling capacitor

[0078] GND: Ground voltage

[0079] IERRI: conversion current

[0080] IL: Phase current

[0081] L: Inductor

[0082] NIN: voltage input terminal

[0083] NPHA: Phase output terminal

[0084] NPS: Output

[0085] NOUT: voltage output terminal

[0086] PD: Disabled period

[0087] PE: enabling period

[0088] PTRI: Trigger Pulse

[0089] RI: Resistance value

[0090] RL: Load resistor

[0091] SET,SETD: Setting signal

[0092] T1, T2, T3: time

[0093] V1: First voltage level

[0094] V2: Second voltage level

[0095] VCOMP: compensation signal

[0096] VDAC: reference voltage

[0097] VDD: First power supply voltage

[0098] VEE: Second power supply voltage

[0099] VERR: Error signal

[0100] VERRA: Amplify the error signal

[0101] VERRI: integral error signal

[0102] VGH, VGL, Vgh: driving signal

[0103] VIN: Input voltage

[0104] VL: conversion voltage

[0105] VOUT: output voltage

[0106] VRAMP,Vramp: ramp signal

[0107] VREF: Dependent reference voltage

[0108] VTH: Threshold value.

Claims

1. A control circuit, suitable for a multi-phase power converter circuit, characterized in that: Include: an error detection circuit coupled to the phase output terminal and the voltage output terminal of the multi-phase power converter circuit, for detecting the phase current of the phase output terminal and the output voltage of the voltage output terminal, and for outputting an error signal related to the phase current, the output voltage and a reference voltage; A compensation generating circuit is coupled to the error detecting circuit and is used to output a compensation signal according to the error signal and the reference voltage; A ramp generating circuit is coupled to the error detecting circuit and is used to output a ramp signal according to the error signal; and The comparison circuit is coupled to the compensation generating circuit and the ramp generating circuit, and is used for receiving the compensation signal and the ramp signal, and for generating at least one trigger pulse when the ramp signal crosses the compensation signal.

2. The control circuit according to claim 1, characterized in that: The compensation generating circuit comprises: an amplifier circuit, coupled to the error detection circuit, for receiving the error signal and amplifying the error signal to output an amplified error signal; as well as The operation circuit is coupled to the amplifier circuit and the comparison circuit, and is used for receiving the reference voltage and the amplified error signal, and outputting the compensation signal according to the difference between the reference voltage and the amplified error signal.

3. The control circuit according to claim 1, characterized in that: The ramp generating circuit comprises: Capacitors; An integration circuit, coupled to the error detection circuit, for receiving the error signal and integrating the error signal to output an integrated error signal; as well as The transconductance amplifier circuit is coupled to the integration circuit, the capacitor and the comparison circuit, and is used for receiving the integration error signal and converting the integration error signal into a conversion current, so as to charge the capacitor through the conversion current, thereby outputting the ramp signal.

4. The control circuit according to claim 1, characterized in that: The comparison circuit is used to output a setting signal and to adjust the voltage level of the setting signal according to the compensation signal and the error signal, wherein when the ramp signal is greater than the compensation signal, the comparison circuit switches the voltage level of the setting signal from a first voltage level to a second voltage level at equal time intervals to generate the at least one trigger pulse.

5. The control circuit according to claim 1, characterized in that: The comparison circuit comprises: a comparator for outputting a setting signal, for comparing the ramp signal and the compensation signal, and for adjusting a voltage level of the setting signal according to a comparison result of the ramp signal and the compensation signal, wherein the comparator adjusts the setting signal from a first voltage level to a second voltage level when the ramp signal is greater than the compensation signal; as well as The delay circuit is coupled to the comparator and is used for outputting the setting signal of the second voltage level at equal time intervals to generate the at least one trigger pulse.

6. The control circuit according to claim 1, characterized in that: The error detection circuit comprises: A resistor coupled to the phase output terminal of the multi-phase power converter circuit and used to generate a conversion voltage dependent on the phase current; A first operation circuit, coupled to the resistor, for receiving the conversion voltage and the reference voltage, and for generating a dependent reference voltage according to a difference between the reference voltage and the conversion voltage; as well as The second operation circuit is coupled to the first operation circuit, and is used for receiving the dependent reference voltage and the output voltage, and for generating the error signal according to the difference between the dependent reference voltage and the output voltage.

7. The control circuit according to claim 1, characterized in that: The multi-phase power converter circuit includes an on-time generating circuit and a power stage circuit, and the at least one trigger pulse is used to trigger the on-time generating circuit to control the power stage circuit to operate according to a preset duty cycle.

8. A multi-phase power converter circuit, for receiving an input voltage at a voltage input terminal and outputting an output voltage at a voltage output terminal, characterized in that: Include: A power stage circuit is coupled to the voltage input terminal and coupled to the phase output terminal through an inductor; as well as The control circuit is coupled to the power stage circuit, the phase output terminal and the voltage output terminal, and is used to generate an error signal according to the phase current of the phase output terminal, the output voltage and a reference voltage, to generate a compensation signal according to the reference voltage and the error signal, to generate a ramp signal according to the error signal, and to control the power stage circuit to operate according to a preset duty cycle to increase the phase current when the ramp signal crosses the compensation signal.

9. The multi-phase power converter circuit according to claim 8, characterized in that: The control circuit includes: An error detection circuit, coupled to the phase output terminal and the voltage output terminal, for detecting the phase current and the output voltage, and for outputting the error signal associated with the phase current, the output voltage and the reference voltage; A compensation generating circuit, coupled to the error detecting circuit, for amplifying the error signal and for outputting the compensation signal according to a calculated value generated based on the reference voltage and the amplified error signal; A ramp generating circuit is coupled to the error detecting circuit, and is used to perform operation on the error signal, and to perform voltage-current conversion on the error signal after the operation, so as to output the ramp signal; as well as The comparison circuit is coupled to the compensation generating circuit and the ramp generating circuit, and is used for receiving the compensation signal and the ramp signal, and for generating at least one trigger pulse when the ramp signal is greater than the compensation signal.

10. The multi-phase power converter circuit according to claim 9, characterized in that: The control circuit also includes: The on-time generating circuit is coupled between the comparison circuit and the power stage circuit and is used for controlling the power stage circuit to operate according to the preset duty cycle through being triggered by the at least one trigger pulse.

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