Charge and discharge control method and circuit of booster circuit and electronic equipment

Abstract

The embodiment of the invention discloses a charge and discharge control method and circuit of a booster circuit and electronic equipment, and the method comprises the steps: controlling the booster circuit to execute at least one charge and discharge operation based on a charge and discharge clock signal of the booster circuit under the condition that the output voltage of the booster circuit is lower than a reference lower limit voltage through comparison, and based on the charging and discharging clock signal, when the actual execution times of the accumulated charging and discharging operation meet the expected execution times, the boost circuit is controlled to stop executing the charging and discharging operation. By means of the technical scheme, when it is detected that the output voltage of the boost circuit is lower than the reference lower limit voltage, input of excess energy can be avoided by controlling the boost circuit to execute the charging and discharging operation of the expected number of times, so that the ripple size of the output voltage can be reduced, and the light load efficiency of the BOOST boost circuit can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of electronic technology, and in particular to a charge and discharge control method, circuit, and electronic device of a boost circuit. Background Art

[0002] The DC-DC boost circuit (referred to as BOOST boost circuit) is a common switching DC boost circuit. It controls the inductor to store and release energy by turning on and off the switching device, so that the output voltage is higher than the input voltage, thereby achieving boost.

[0003] For a BOOST boost circuit using a peak current control mode (CPCM mode for short), a burst pulse operation mode (BURST mode for short) is usually used to control the output voltage ripple (or PVDD ripple) of the BOOST boost circuit to optimize its efficiency under light load conditions.

[0004] However, the current BURST mode is mainly controlled by the upper and lower voltage limits of the output voltage ripple window. The number of times the inductor is charged and discharged in a single BURST cycle is uncontrollable. In actual circuit operation, since the comparator is susceptible to noise interference, inaccurate comparison results may lead to an increase in the number of times the inductor is charged, which may easily input excess energy, resulting in a lower efficiency of the BOOST boost circuit and an output voltage ripple amplitude exceeding the preset value.

[0005] In addition, since the comparator in the BURST mode has a certain degree of offset, the BURST window size cannot be set too small (that is, the difference between the upper limit voltage and the lower limit voltage of the BURST window cannot be too small), which also causes the output voltage ripple in the BURST mode to become correspondingly larger. Summary of the invention

[0006] In view of this, the embodiments of the present disclosure provide a charge and discharge control scheme suitable for a boost circuit, which can reduce and control the output voltage ripple, avoid the input of excess energy, and improve the light-load efficiency of the boost circuit.

[0007] According to a first aspect of the present disclosure, a charge and discharge control method for a boost circuit is provided, comprising: comparing an output voltage of the boost circuit with a reference lower limit voltage; in response to a comparison result that the output voltage is lower than the reference lower limit voltage, controlling the boost circuit to perform at least one charge and discharge operation based on a charge and discharge clock signal of the boost circuit; based on the charge and discharge clock signal, controlling the boost circuit to stop performing the charge and discharge operation when the actual number of executions of the accumulated charge and discharge operation meets the expected number of executions; and returning to the step of comparing the output voltage of the boost circuit with the reference lower limit voltage.

[0008] According to a second aspect of the present disclosure, a charge and discharge control circuit of a boost circuit is provided, comprising: a control circuit electrically connected to the boost circuit, for detecting the output voltage of the boost circuit, and counting the charge and discharge operations performed by the boost circuit, wherein the control circuit outputs an enabled charge and discharge drive signal when comparing the output voltage of the boost circuit to be lower than a reference lower limit voltage, and outputs a disabled charge and discharge drive signal when detecting that the actual number of executions of the charge and discharge operations of the boost circuit meets the expected number of executions; a drive circuit electrically connected to the control circuit and the boost circuit, for receiving the charge and discharge drive signal of the control circuit, and when detecting that the charge and discharge drive signal is in the enabled state, controlling the boost circuit to perform at least one charge and discharge operation, and when detecting that the charge and discharge control signal is in the disabled state, controlling the boost circuit to stop performing the charge and discharge operation.

[0009] According to a third aspect of the present disclosure, an electronic device is provided, comprising the charge and discharge control circuit as described in the second aspect and a boost circuit connected to the charge and discharge control circuit, so that the charge and discharge operation of the boost circuit is controlled by the charge and discharge control circuit.

[0010] According to the charge and discharge control scheme of the boost circuit provided in each embodiment of the present disclosure, when it is detected that the output voltage of the boost circuit is lower than the reference lower limit voltage, the input energy of the boost circuit can be effectively controlled by controlling the boost circuit to perform the desired number of charge and discharge operations, thereby preventing the output voltage of the boost circuit from exceeding the set value due to the input of excess energy, reducing the ripple size of the traditional BURST mode, and improving the light load efficiency of the boost circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a circuit structure diagram of a charge and discharge control method or a boost circuit applicable to each embodiment of the present disclosure.

[0013] Figure 2 The timing relationship diagram between various control signals in the BOOST boost circuit that implements the traditional charge and discharge control method.

[0014] Figure 3 The present invention is a flowchart of a charge and discharge control method of a boost circuit according to an exemplary embodiment of the present invention.

[0015] Figure 4 The figure is a timing relationship diagram between various control signals in a BOOST boost circuit for implementing an exemplary charge and discharge control method of the present disclosure.

[0016] Figure 5 The present invention is a flowchart of a charge and discharge control method of a boost circuit according to another exemplary embodiment of the present invention.

[0017] Figure 6 FIG. 1 is a structural framework diagram of a charge and discharge control circuit of a boost circuit according to an exemplary embodiment of the present disclosure.

[0018] Figure 7 for Figure 6 The circuit structure diagram of the charge and discharge control circuit shown.

[0019] List of reference numerals:

[0020] 100, DC-DC boost circuit 106, upper power tube

[0021] 102. Energy storage element 108. Power supply

[0022] 104, lower power tube 110, capacitor

[0023] 112, load 719, sampler

[0024] 600, charge and discharge control circuit 720, bandgap reference generator

[0025] 602, drive circuit 722, compensator

[0026] 604, control circuit PVDD, output voltage

[0027] 610, boost circuit VFB, feedback voltage

[0028] 702, energy storage element BURST_FLAG, charge and discharge drive signal

[0029] 704, lower power tube BURST_VREF_IN, upper limit voltage

[0030] 706, upper power tube BURST_VREF_OUT, lower limit voltage

[0031] 708, power supply IL, inductor (energy storage element) current

[0032] 709A, voltage divider resistor BST_CLK, charge and discharge clock signal

[0033] 709B, voltage divider resistor D, power tube drive signal

[0034] 710, capacitor BURST_OUT, charge and discharge control signal

[0035] 712, load LS_GT, lower tube drive signal

[0036] 713, first voltage comparator HS_GT, upper tube drive signal

[0037] 714, counter VSENSE, sampling voltage

[0038] 716, Error amplifier VCOM, error amplifier voltage

[0039] 718, second voltage comparator VREF_OUT, reference lower limit voltage DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be described clearly and in detail below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0041] Reference is made to the accompanying drawings in the following detailed description, which form a part of the detailed description and illustrate exemplary embodiments. In addition, it should be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the accompanying drawings. Therefore, the following detailed description is not to be understood in a limiting sense, and the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

[0042] In the following description, numerous details are set forth. However, it will be apparent to those skilled in the art that the embodiments herein can be practiced without these specific details. In some cases, known methods and devices are shown in block diagram form, rather than in detail, to avoid blurring the embodiments herein. References to "embodiment" or "one embodiment" or "some embodiments" throughout this specification mean that the specific features, structures, functions or characteristics described in conjunction with the embodiment are included in at least one embodiment herein. Therefore, the phrases "in an embodiment" or "in one embodiment" or "some embodiments" appearing throughout this specification do not necessarily refer to the same embodiment. In addition, in one or more embodiments, specific features, structures, functions or characteristics may be combined in any suitable manner. For example, the first embodiment may be combined with the second embodiment in any case where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0043] As used in the description and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0044] The terms "coupled" and "connected" together with their derivatives may be used in this article to describe the functional or structural relationship between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" can be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in direct or indirect (with other intermediate elements between them) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0045] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or materials disposed above or below another material may be in direct contact, or may have one or more intervening materials. Also, a material disposed between two materials or materials may be in direct contact with both layers, or may have one or more intervening layers. In contrast, a first material or material "above" a second material or material is in direct contact with the second material / materials. Similar distinctions are made in the context of component assembly.

[0046] As used throughout the description herein and in the claims, a list of items connected by the term "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0047] The term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired functionality. The term "signal" may refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "close," "approximately," "close to," and "approximately" generally refer to within + / 10% of a target value.

[0048] The charge and discharge control scheme provided by each embodiment of the present disclosure can be applied to a boost circuit. In the following description, a DC-DC boost circuit (or BOOST boost circuit) will be taken as an example to describe the specific implementation of each embodiment of the present disclosure in detail.

[0049] The BOOST boost circuit is a common switching DC boost circuit. It controls the inductor to store and release energy by turning on and off the switching device, so that the output voltage of the circuit is higher than the input voltage to achieve the purpose of boosting.

[0050] like Figure 1 As shown, the BOOST boost circuit 100 mainly includes an energy storage element 102 , a lower power tube 104 , an upper power tube 106 , a power source 108 , a capacitor 110 , and a load 112 .

[0051] The energy storage element 102 is, for example, an inductor, wherein a first end of the energy storage element 102 is connected to the power source 102, and a second end of the energy storage element 102 is respectively connected to the upper power tube 106 and the lower power tube 104. The energy storage element 102 can be controlled to perform charging and discharging operations (for example, Figure 2 The inductor current IL shown completes a rise and fall) to achieve voltage boost.

[0052] like Figure 1 As shown, when the lower power tube 104 is turned on and the upper power tube 106 is turned off, the energy storage element 102 is charged by the input voltage of the power supply 108. In this case, the energy storage element 102 performs a charging operation; when the lower power tube 104 is turned off and the upper power tube 106 is turned on, the capacitor 110 is charged by the input voltage of the power supply 108 and the voltage of the energy storage element 102 together, and the load 112 is powered at the same time. In this case, the energy storage element 102 performs a discharging operation; when both the lower power tube 104 and the upper power tube 106 are turned off (the driving signals of the upper and lower power tubes are both low), the energy storage element 102 stops the charging and discharging operations.

[0053] When the load of the BOOST boost circuit 100 is low (that is, in a light load state), when the input current of the BOOST boost circuit 100 is greater than the output current, the output voltage PVDD of the BOOST boost circuit 100 will gradually increase until the overvoltage protection mechanism (OVP) is triggered, and the BOOST boost circuit 100 will stop working. Therefore, if the input energy of the BOOST boost circuit 100 is not limited, the input of excess energy will not only cause the output voltage PVDD of the BOOST boost circuit 100 to exceed the set value, but also cause the problem of reduced light load efficiency.

[0054] To solve the above problem, for the BOOST boost circuit 100 adopting the peak current control mode (CPCM control mode for short), a burst pulse working mode (or BURST mode) is usually used to control the ripple of the output voltage PVDD of the BOOST boost circuit 100 to optimize its efficiency under light load conditions.

[0055] refer to Figure 1 and Figure 2 In the BURST mode, the feedback voltage VFB of the output voltage PVDD will rise because the input energy of the BOOST boost circuit 100 is greater than the required output energy. In the prior art, when the BOOST boost circuit 100 should obtain energy from the energy storage element 102 (inductor) is achieved by comparing VFB with the BURST voltage window.

[0056] When VFB exceeds the upper limit voltage VREF_IN of the BURST voltage window, the driving signal is high (BURST_FLAG=1), the BOOST boost circuit 100 stops inputting energy, and the energy storage element 102 (inductor) stops performing charging and discharging operations. In this case, the capacitor 110 provides output energy for the BOOST boost circuit 100, and because the energy storage element 102 also provides energy for the load 112 at this time, the output voltage PVDD and the feedback voltage VFB will continue to decrease;

[0057] On the contrary, when VFB is lower than the lower limit voltage VREF_OUT of the BURST voltage window, the driving signal is at a low level (eg, BURST_FLAG=0), the BOOST circuit 100 starts to input energy again, and the energy storage element 102 (inductor) starts to perform charging and discharging operations until VFB exceeds the upper limit voltage of the BURST voltage window.

[0058] By comparing the output voltage PVDD of the BOOST boost circuit 100 with the BURST voltage window pair and controlling the charge and discharge operation of the energy storage element 102 based on the comparison result, the overall input energy of the BOOST boost circuit 100 can be reduced, so that the output voltage PVDD of the BOOST boost circuit 100 is kept within a controllable range, so as to achieve the purpose of improving the light load efficiency. However, this charge and discharge control scheme still has the following problems:

[0059] (1) When the load 112 in the BOOST boost circuit 100 becomes heavier (i.e., the load resistance becomes smaller and the required current becomes larger), after the energy storage element 102 is started to perform charging and discharging operations, if VFB still cannot reach the upper limit voltage, the BOOST boost circuit 100 will continue to operate in the pulse width modulation mode (PWM mode) and cannot enter the BURST mode.

[0060] (2) The current BURST mode is to control the energy storage element 102 to perform charging and discharging operations by comparing the output voltage of the BOOST boost circuit 100 with the BURST voltage window. The energy storage element 102 performs charging and discharging operations in a BURST cycle (wherein the process of the drive signal flipping from a low level to a high level and then flipping from a high level to a low level again is called a BURST cycle, see Figure 2 ) is uncontrollable. However, in actual circuit operation, the comparator is easily affected by noise interference, which affects the accuracy of the comparison result, which will lead to an unnecessary increase in the number of charge and discharge operations, causing the BOOST boost circuit 100 to input excess energy, the light-load efficiency of the BOOST boost circuit to be low, and the size of the output voltage ripple (PVDD ripple) is also unsatisfactory.

[0061] (3) Due to the offset problem of the comparator in the BURST mode, the size of the BURST voltage window (i.e., the difference between the upper limit voltage and the lower limit voltage) cannot be set too small, which will cause the PVDD ripple in the BURST mode to increase accordingly.

[0062] Based on the above technical problems, each embodiment of the present disclosure provides a charge and discharge control scheme suitable for a boost circuit, which can avoid the input of excess energy, make the output voltage ripple of the boost circuit smaller and more controllable, and improve the light load efficiency of the boost circuit. The specific implementation of each embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings:

[0063] Charge and discharge control method of boost circuit

[0064] Figure 3 The present invention provides a process flow of a charge and discharge control method for a voltage boost circuit according to an exemplary embodiment of the present invention.

[0065] In some embodiments, the boost circuit applicable to this embodiment may include Figure 1 The BOOST boost circuit 100 is shown.

[0066] like Figure 3 As shown, the method of this embodiment may include the following processing steps:

[0067] Step 302: Compare the output voltage of the boost circuit with a reference lower limit voltage.

[0068] In some embodiments, the feedback voltage VFB of the output voltage PVDD of the BOOST boost circuit 100 can be detected, and the feedback voltage VFB can be compared with the reference lower limit voltage VREF_OUT (reference Figure 1 and Figure 4 ).exist Figure 4 In the figure, K represents the voltage division ratio of the output voltage PVDD feedback.

[0069] In some embodiments, the bandgap reference generator 720 (reference Figure 7 ) generates the lower limit voltage VREF_OUT.

[0070] Step 304 : In response to the comparison result that the output voltage is lower than the reference lower limit voltage, based on the charge and discharge clock signal of the boost circuit, control the boost circuit to perform at least one charge and discharge operation.

[0071] In some embodiments, in response to the detection result that the output voltage PVDD of the BOOST boost circuit 100 is lower than the reference lower limit voltage VREF_OUT, the charge and discharge clock signal BST_CLK and the power tube drive signal D are used to control the

[0072] [AW20240021ICN1][HS2410861CCN] The boost circuit performs at least one charge and discharge operation.

[0073] For example, reference Figure 1 and Figure 4 When the charge-discharge clock signal BST_CLK turns high, the energy storage element 102 is charged, and the inductor current IL increases; when the power tube drive signal D turns high, the energy storage element 102 is discharged, and the inductor current IL decreases. Therefore, a rise and fall change of the inductor current IL corresponds to a charge and discharge operation of the energy storage element 102.

[0074] Step 306 : Based on the charge and discharge clock signal, when the actual execution times of the accumulated charge and discharge operations meet the expected execution times, control the boost circuit to stop executing the charge and discharge operations, and return to step 302 .

[0075] In some embodiments, reference Figure 1 and Figure 4 When the charge-discharge clock signal BST_CLK turns high, the energy storage element 102 of the BOOST boost circuit 100 is controlled to perform a charging operation. Therefore, during the process of the BOOST boost circuit 100 performing a charge-discharge operation, the rising edges of the charge-discharge clock signal BST_CLK can be counted to count the number of charge-discharge operations performed by the BOOST boost circuit 100.

[0076] In some embodiments, when the actual number of executions of the charge and discharge operations of the BOOST boost circuit 100 meets the expected number of executions, the BOOST boost circuit 100 is controlled to stop executing the charge and discharge operations, and returns to step 302 until it is detected again that the output voltage PVDD of the BOOST boost circuit 100 is lower than the reference lower limit voltage VREF_OUT, so as to start the next round of charge and discharge operations.

[0077] Figure 5 This is a processing flow of a charge and discharge control method of a boost circuit according to another embodiment of the present disclosure. Figure 3 Further implementation means of the embodiment shown. Figure 5As shown, this embodiment mainly includes:

[0078] Step 502: Detect the feedback voltage of the output voltage of the boost circuit.

[0079] In some embodiments, the feedback voltage VFB of the output voltage PVDD of the BOOST circuit 100 may be detected by one or more voltage dividing resistors.

[0080] Step 504 , determine whether the feedback voltage is lower than the reference lower limit voltage, if not, return to step 505 , if yes, execute step 506 .

[0081] In some embodiments, the reference bandgap generator 720 (reference Figure 7 ) provides a reference lower limit voltage VREF_OUT.

[0082] Step 505 , switching the charge and discharge control signal to a disabled state, and returning to step 502 .

[0083] In some embodiments, when the feedback voltage VFB of the output voltage PVDD of the BOOST circuit 100 is detected to be not lower than the reference lower limit voltage VREF_OUS, the charge and discharge control signal is switched to the disabled state BURST_OUT=0.

[0084] Step 506: Switch the charge and discharge control signal to an enabled state, and switch the charge and discharge drive signal to an enabled state.

[0085] Specifically, according to the detection result that the output voltage PVDD of the BOOST boost circuit 100 is lower than the reference lower limit voltage VREF_OUT, the charge and discharge control signal BURST_OUT is switched to the enabled state (reference Figure 4 In response to the determination result that the charge and discharge control signal BURST_OUT is switched to the enabled state, the charge and discharge drive signal BURST_FLAG is switched to the enabled state (refer to Figure 4 The dashed arrow S12).

[0086] In some embodiments, the enabled state of the charge and discharge control signal BURST_OUT corresponds to a high level state (i.e., BURST_OUT=1), the disabled state of the charge and discharge control signal BURST_OUT corresponds to a low level state (i.e., BURST_OUT=0), the enabled state of the charge and discharge drive signal BURST_FLAG corresponds to a low level (i.e., BURST_FLAG=0), and the disabled state of the charge and discharge drive signal BURST_FLAG corresponds to a high level (i.e., BURST_FLAG=1).

[0087] In some embodiments, when the feedback voltage VFB is lower than the reference lower limit voltage VREF_OUT, the charge and discharge control signal BURST_OUT=1, and the rising edge of the charge and discharge control signal BURST_OUT makes the charge and discharge driving signal BURST_FLAG=0.

[0088] Step 508: Based on the charge and discharge clock signal and the power tube drive signal, control the boost circuit to perform charge and discharge operations.

[0089] In some embodiments, the boost circuit 100 may include an energy storage element 102 , an upper power tube 106 , and a lower power tube 104 .

[0090] Among them, the power tube driving signal D can be obtained according to the output voltage PVDD of the boost circuit 100 and the sampling current of the lower power tube 104, and based on the charge and discharge clock signal BST_CLK and the power tube driving signal D, the upper power tube 106 and the lower power tube 104 are driven to alternately perform the first flip and the second flip, so that the energy storage element 102 alternately performs the charging operation and the discharging operation.

[0091] In some embodiments, the output voltage of the boost circuit can be used as a negative feedback input, and the reference voltage can be used as a positive feedback input to perform a voltage error amplification process to obtain the error amplified voltage VCOM of the energy storage element 102. The current flowing through the lower power tube 104 can be sampled, and a current-voltage conversion process can be performed to obtain the sampled voltage VSENSE of the energy storage element 102. The sampled voltage VSENSE can be used as a positive feedback input, and the error amplified voltage VCOM can be used as a negative feedback input to perform a voltage comparison process to obtain the power tube drive signal D.

[0092] In some embodiments, when the charge and discharge drive signal BURST_FLAG=0, the lower tube drive signal LS_GT and the upper tube drive signal HS_GT can be output in parallel based on the charge and discharge clock signal BST_CLK and the power tube drive signal D, and the lower power tube 104 and the upper power tube 106 in the BOOST boost circuit 100 can perform corresponding flipping (i.e., turning on or off) based on the lower tube drive signal LS_GT and the upper tube drive signal HS_GT, respectively, thereby realizing the charge and discharge operation of the energy storage element 102.

[0093] Further, the charge and discharge clock signal BST_CLK and the power tube drive signal D can be detected, wherein, when the charge and discharge clock signal BST_CLK is detected to be turned high, a first flip is performed to connect the lower power tube 104 and disconnect the upper power tube 106, so that the energy storage element 102 performs a charging operation; when the power tube drive signal D is detected to be turned high, a second flip is performed to disconnect the lower power tube 104 and connect the upper power tube 106, so that the energy storage element 102 performs a discharging operation.

[0094] refer to Figure 4 , a rise and fall change of the inductor current IL corresponds to a charge and discharge operation performed by the energy storage element 102, wherein when the inductor current IL rises, the energy storage element 102 performs a charging operation, and when the inductor current IL falls, the energy storage element 102 performs a discharging operation.

[0095] Step 510 , determining whether the actual execution times of the charge and discharge operations meet the expected execution times, if so, proceed to step 512 , otherwise, return to step 508 .

[0096] In some embodiments, whether the actual execution times of the charge and discharge operations meet the expected execution times may be accumulated based on the charge and discharge clock signal BST_CLK.

[0097] For example, when the charge and discharge clock signal BST_CLK turns high and controls the energy storage element 102 to perform a charging operation, during the process of the BOOST boost circuit 100 performing the charge and discharge operation, the rising edge of the charge and discharge clock signal BST_CLK can be counted to count the actual number of executions of the charge and discharge operation of the energy storage element 102.

[0098] For example, in Figure 4 In the example shown, the first rising edge R1 of the charge and discharge clock signal BST_CLK corresponds to the first charge and discharge operation performed by the energy storage element 102 , and the second rising edge R2 of the charge and discharge clock signal BST_CLK corresponds to the second charge and discharge operation performed by the energy storage element 102 .

[0099] Step 512, switch the charge and discharge drive signal to a disabled state to control the boost circuit to stop performing the charge and discharge operation, and in response to the detection result that the feedback voltage is not lower than the reference lower limit voltage, switch the charge and discharge control signal to a disabled state, and clear the actual number of executions of the charge and discharge operation, and return to step 502.

[0100] For example, reference Figure 4 In the example shown, assuming that the expected number of executions of the charge and discharge operation in a single round is 2 times, when the first rising edge R1 of the charge and discharge clock signal BST_CLK is detected, it represents that the energy storage element 102 starts to execute the first charge and discharge operation of the current round, and when the second rising edge R2 of the charge and discharge clock signal BST_CLK is detected, it represents that the energy storage element 102 starts to execute the second charge and discharge operation of the current round. At this time, the actual number of executions of the charge and discharge operation has met the expected number of executions. Therefore, when the third rising edge R3 of the charge and discharge clock signal BST_CLK is detected, the charge and discharge drive signal is switched to the disabled state BURST_FLAG=1 (reference Figure 4The dotted arrow 13) controls the BOOST boost circuit 100 to stop performing the charge and discharge operation, and after clearing the accumulated actual execution times, returns to step 502 to perform the next cycle of charge and discharge control operation (refer to Figure 4 dotted arrows S21 to S23).

[0101] In some embodiments, when the charge and discharge driving signal BURST_FLAG=1 is detected, the lower tube driving signal LS_GT and the upper tube driving signal HS_GT are switched to a low level to disconnect the upper power tube 106 and the lower power tube 104, so that the BOOST boost circuit 100 stops performing the charge and discharge operation.

[0102] In addition, it should be noted that, in the present embodiment, the processing steps of step 502 to step 505 can be executed in parallel with the processing steps of step 508 to step 512, that is, during the execution of the charge and discharge operation (i.e., step 508 to step 512), when it is detected that the feedback voltage VFB of the output voltage PVDD of the BOOST boost circuit 100 is raised to above the reference lower limit voltage VREF_OUT, the charge and discharge control signal is switched to the disabled state BURST_OUT=0.

[0103] In summary, the charge and discharge control method provided by each embodiment of the present disclosure, when the output voltage of the boost circuit is lower than the reference lower limit voltage, controls the boost circuit to perform a predetermined number of charge and discharge operations and then stops the current round of charge and discharge operations, until the output voltage of the boost circuit is detected to be lower than the reference lower limit voltage again, and then repeats a new round of charge and discharge operations. Compared with the prior art, the current round of charge and discharge operations must be stopped when the output voltage of the boost circuit is detected to reach the reference upper limit voltage. The technical solution of this embodiment can effectively avoid the input of excess energy, and can make the output voltage ripple (PVDD ripple) very small and controllable, thereby improving the light load efficiency of the boost circuit.

[0104] In addition, since the charge and discharge control method provided by each embodiment of the present disclosure cancels the BURST voltage window, the size of the output voltage ripple of the boost circuit is no longer affected by the comparator offset voltage, but depends on the number of charge and discharge times set in a single round of charge and discharge operation. Therefore, this solution can not only flexibly adjust the number of charge and discharge times based on factors such as actual circuit design and usage requirements, but also make the output voltage ripple of the boost circuit smaller and more controllable, so as to further improve the light load efficiency of the boost circuit.

[0105] Charge and discharge control circuit

[0106] Figure 6The structure block diagram of the charge and discharge control circuit 600 of the exemplary embodiment of the present disclosure is shown. As shown in the figure, the charge and discharge control circuit 600 of the present embodiment mainly includes: a drive circuit 602 and a control circuit 604.

[0107] The control circuit 604 is electrically connected to the boost circuit 610, and is used to detect the output voltage PVDD of the boost circuit 610, and count the charge and discharge operations performed by the boost circuit 610, wherein the control circuit 604 outputs an enabled state charge and discharge drive signal (i.e., BURST_FLAG=0) when comparing that the output voltage PVDD of the boost circuit 610 is lower than the reference lower limit voltage VREF_OUT, and outputs a disabled state charge and discharge drive signal (i.e., BURST_FLAG=1) when detecting that the actual execution number of the charge and discharge operations of the boost circuit 610 meets the expected execution number;

[0108] The driving circuit 602 is electrically connected to the control circuit 604 and the boost circuit 610, and is used to receive the charge and discharge drive signal (BURST_FLAG) of the control circuit 604, and when the charge and discharge drive signal is detected to be in the enable state BURST_FLAG=0, control the boost circuit 610 to perform at least one charge and discharge operation, and when the charge and discharge control signal is detected to be in the disable state BURST_FLAG=1, control the boost circuit 610 to stop performing the charge and discharge operation.

[0109] Figure 7 for Figure 6 The specific circuit structure diagram of the charge and discharge control circuit 600 is shown in FIG. Figure 7 Taking the circuit diagram shown as an example, the implementation details of the charge and discharge control circuit 600 are described in detail.

[0110] The charge and discharge control circuit 600 of this embodiment may be applicable to a BOOST boost circuit. The BOOST boost circuit mainly includes an energy storage element 702 , a lower power tube 704 , an upper power tube 706 , and a power source 708 .

[0111] A first end of the energy storage element 702 (eg, an inductor) is connected to a power source 708 , and a second end of the energy storage element 702 is connected to a lower power tube 704 and an upper power tube 706 , respectively.

[0112] The charge and discharge control circuit 600 is used to control the connection or disconnection of the upper power tube 704 and the lower power tube 706. The energy storage element 702 can perform a charging operation when the lower power tube 704 is turned on and the upper power tube 706 is turned off, and perform a discharging operation when the lower power tube 704 is turned off and the upper power tube 706 is turned on.

[0113] In addition, the BOOST boost circuit also includes components such as capacitor 710 and load 712. For the control logic between the components in the BOOST boost circuit, please refer to Figure 1 The relevant description of the BOOST boost circuit 100 is not repeated here.

[0114] In some embodiments, the control circuit 604 may include a first voltage comparator 713 and a counter 714 .

[0115] The first voltage comparator 713 is electrically connected to the BOOST boost circuit, and is used to detect the output voltage PVDD of the BOOST boost circuit, and switch the charge and discharge control signal BURST_OUT to an enabled state when the output voltage PVDD of the BOOST boost circuit is lower than the reference lower limit voltage VREF_OUT.

[0116] In some embodiments, the first voltage comparator 713 can determine the feedback voltage VFB of the BOOST boost circuit PVDD by detecting the resistance values ​​of the voltage-dividing resistors 709A and 709B. The first voltage comparator 713 can compare the feedback voltage VFB with the reference lower limit voltage VREF_OUT. If the feedback voltage VFB is lower than the reference lower limit voltage VREF_OUT, the charge and discharge control signal is switched to the enable state BURST_OUT=1 and output to the counter 714.

[0117] In some embodiments, the first voltage comparator 713 is electrically connected to the bandgap reference generator 720 and receives a reference lower limit voltage from the bandgap reference generator 720 .

[0118] The counter 714 is connected between the first voltage comparator 713 and the driving circuit 602, and is used to receive the charge and discharge control signal BURST_OUT of the first voltage comparator 713, and output the charge and discharge driving signal BURST_FLAG=0 in the enabled state when the charge and discharge control signal is judged to be in the enabled state BURST_OUT=1. The counter 714 also receives the charge and discharge clock signal BST_CLK of the BOOST boost circuit, and based on the charge and discharge clock signal BST_CLK, when the actual execution times of the accumulated charge and discharge operation of the BOOST boost circuit meet the expected execution times, outputs the charge and discharge driving signal BURST_FLAG=1 in the disabled state, and clears the accumulated actual execution times.

[0119] Exemplarily, when the charge and discharge control signal BURST_OUT=1, the counter 714 may, based on the rising edge of the charge and discharge control signal BURST_OUT, make the charge and discharge drive signal BURST_FLAG=0 and output it to the drive circuit 602. The drive circuit 602 may, based on the enable state or disable state of the charge and discharge drive signal BURST_FLAG, output the corresponding upper tube drive signal HS_GT and lower tube drive signal LS_GT to the upper power tube 706 and the lower power tube 704, so as to respectively control the flipping of the upper power tube 706 and the lower power tube 704 of the BOOST boost circuit, thereby performing the charge and discharge operation of the energy storage element 702.

[0120] During the process of the energy storage element 702 performing the charge and discharge operation, the counter 714 starts to count the rising edges of the charge and discharge clock signal BST_CLK to accumulate the actual execution times of the charge and discharge operation of the energy storage element 702. When the actual execution times meet the expected execution times, the charge and discharge drive signal BURST_FLAG=1 is output to the drive circuit 602. The drive circuit 602 can output the corresponding upper tube drive signal HS_GT and the lower tube drive signal LS_GT to respectively control the upper power tube 706 and the lower power tube 704 of the BOOST boost circuit to stop flipping, thereby stopping the charge and discharge operation of the energy storage element 702.

[0121] In some embodiments, the charge and discharge control circuit 600 further includes an error amplifier 716 and a second voltage comparator 718 .

[0122] The error amplifier 716 is electrically connected to the BOOST boost circuit, and is used to perform error amplification processing on the output voltage PVDD of the boost circuit and the reference voltage VREF, and output an error amplified voltage VOMP.

[0123] For example, the error amplifier 716 may use the feedback voltage VFB of the output voltage PVDD as a negative feedback input and the reference voltage VREF as a positive feedback input to perform an error amplification process.

[0124] In some embodiments, the error amplifier 716 is electrically connected to the bandgap reference generator 720 to obtain the reference voltage VREF through the bandgap reference generator 720 .

[0125] In some embodiments, the charge and discharge control circuit 600 further includes a compensator 722 connected between the error amplifier 716 and the second voltage comparator 718 for compensating the error amplified voltage output by the error amplifier 716 and outputting the comparator to the second voltage comparator 718 .

[0126] The second voltage comparator 718 is electrically connected to the error amplifier 716 (compensator 722 ), and is used to compare the sampling voltage VSENSE of the lower power tube 704 and the error amplified voltage VCOMP, and output a power tube driving signal D.

[0127] In some embodiments, the second voltage comparator 718 may be electrically connected to the sampler 719 of the lower power tube 704 to sample the current flowing through the lower power tube 704 through the sampler 719, and after performing voltage conversion processing on the sampled current, output the sampled voltage VSENSE of the lower power tube 704 to the second voltage comparator 718.

[0128] In some embodiments, the second voltage comparator 718 may use the error amplified voltage as a negative feedback input and the sampled voltage VSENSE of the lower power tube 704 as a positive feedback input to perform voltage comparison processing to obtain a power tube driving signal.

[0129] The input end of the driving circuit 602 is connected to the second voltage comparator 718 and the counter 714 of the control circuit 604, and the output end of the driving circuit 602 is connected to the upper power tube 706 and the lower power tube 704, and is used to drive the upper power tube 706 and the lower power tube 704 to alternately perform the first flip and the second flip based on the power tube driving signal D output by the second voltage comparator 718 and the charging and discharging clock signal BST_CLK of the BOOST boost circuit when the charging and discharging driving signal output by the counter 714 is in the enabled state (i.e., BURST_FLAG=0), so that the energy storage element 702 alternately performs charging operation and discharging operation.

[0130] In some embodiments, when the charge and discharge drive signal BURST_FLAG=0 output by the counter 714, the drive circuit 602 can output the lower tube drive signal LS_GT and the upper tube drive signal HS_GT in parallel based on the charge and discharge clock signal BST_CLK and the power tube drive signal D, so as to control the lower power tube 704 and the upper power tube 706 to perform flipping (i.e., turning on or off), respectively, thereby realizing the charge and discharge operation of the energy storage element 702.

[0131] Exemplarily, the driving circuit 602 may output a high-potential lower tube driving signal LS_GT and a low-potential upper tube driving signal HS_GT to connect the lower power tube 704 and disconnect the upper power tube 706 when detecting that the charging and discharging clock signal BST_CLK turns high, so as to enable the energy storage element 702 to perform a charging operation, and may output a low-potential lower tube driving signal LS_GT and a high-potential upper tube driving signal HS_GT to disconnect the lower power tube 704 and connect the upper power tube 706 when detecting that the power tube driving signal D turns high, so as to enable the energy storage element 702 to perform a discharging operation.

[0132] In some embodiments, when the charge and discharge drive signal is detected to switch to the disabled state BURST_FLAG=1, the lower tube drive signal LS_GT and the upper tube drive signal HS_GT output by the drive circuit 602 are both low potentials to simultaneously disconnect the upper power tube 706 and the lower power tube 704, so that the BOOST boost circuit stops performing the charge and discharge operations of the energy storage element 702.

[0133] In summary, the charge and discharge control circuit of the boost circuit of the present embodiment can avoid the input of excess energy by controlling the boost circuit to perform a desired number of charge and discharge operations when detecting that the output voltage of the boost circuit is lower than a reference lower limit voltage, thereby reducing the ripple size of the output voltage and improving the light-load efficiency of the BOOST boost circuit.

[0134] Electronic devices

[0135] Another embodiment of the present disclosure further provides an electronic device, comprising the charge and discharge control circuit described in the above embodiments and a boost circuit connected to the charge and discharge control circuit, so that the charge and discharge operation of the boost circuit is controlled by the charge and discharge control circuit.

[0136] In some embodiments, the boost circuit includes an energy storage element 702, a lower power tube 704, an upper power tube 706, and a power supply 708 (see Figure 7 ).

[0137] The first end of the energy storage element 702 is connected to the power source 708 , and the second end of the energy storage element 702 is connected to the upper power tube 706 and the lower power tube 704 .

[0138] The charge and discharge control circuit is used to control the connection or disconnection of the upper power tube 706 and the lower power tube 704 respectively.

[0139] The energy storage element 702 may perform a charging operation when the lower power tube 704 is turned on and the upper power tube 706 is turned off, and may perform a discharging operation when the lower power tube 704 is turned off and the upper power tube 706 is turned on.

[0140] Thus far, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0141] It should also be noted that the improvement of a technology can be a hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or a software improvement (for improvement of the method flow), or it can be a direct improvement of the hardware circuit structure. Therefore, it cannot be said that the improvement of a method flow cannot be realized by hardware entity modules. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming themselves, without having to ask chip manufacturers to design and produce dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0142] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0143] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0144] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0145] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0146] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0150] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0151] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0152] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0153] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0154] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific transactions or implement specific abstract data types. The present application may also be practiced in distributed computing environments where transactions are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0155] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0156] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A charge and discharge control method for a boost circuit, comprising: Compare the output voltage of the boost circuit with the reference lower limit voltage; In response to a comparison result that the output voltage is lower than the reference lower limit voltage, based on a charge and discharge clock signal of the boost circuit, controlling the boost circuit to perform at least one charge and discharge operation; Based on the charge and discharge clock signal, when the accumulated actual execution times of the charge and discharge operations meet the expected execution times, controlling the boost circuit to stop executing the charge and discharge operations; The step of comparing the output voltage of the boost circuit with the reference lower limit voltage is returned to be executed.

2. The method according to claim 1, wherein: In response to the comparison result that the output voltage is lower than the reference lower limit voltage, based on the charge and discharge clock signal of the boost circuit, controlling the boost circuit to perform at least one charge and discharge operation, comprising: In response to a detection result that the output voltage is lower than a reference lower limit voltage, switching a charge and discharge control signal to an enable state; In response to a determination result that the charge-discharge control signal is switched to an enabled state, switching the charge-discharge drive signal to an enabled state; In response to the determination result that the charge and discharge drive signal is switched to the enabled state, the boost circuit is controlled to perform at least one charge and discharge operation using the charge and discharge clock signal and the power tube drive signal.

3. The method according to claim 2, wherein: The boost circuit includes an energy storage element, an upper power tube, and a lower power tube; And wherein, using the charge and discharge clock signal and the power tube drive signal to control the boost circuit to perform at least one charge and discharge operation includes: Obtaining a power tube driving signal according to the output voltage of the boost circuit and the sampling current of the lower power tube; Based on the charge and discharge clock signal and the power tube driving signal, the upper power tube and the lower power tube are driven to alternately perform a first flip and a second flip, so that the energy storage element alternately performs a charging operation and a discharging operation.

4. The method according to claim 3, wherein: The step of obtaining a power tube driving signal according to the output voltage of the boost circuit and the sampling current of the lower power tube comprises: The output voltage of the boost circuit is used as a negative feedback input, and the reference voltage is used as a positive feedback input, and a voltage error amplification process is performed to obtain an error amplified voltage of the energy storage element; Sampling the current flowing through the lower power tube to obtain a sampled voltage of the energy storage element; The sampling voltage is used as a positive feedback input, the error amplified voltage is used as a negative feedback input, and voltage comparison processing is performed to obtain the power tube driving signal.

5. The method according to claim 4, wherein: The method of driving the upper power tube and the lower power tube to alternately perform a first flip and a second flip based on the charge and discharge clock signal and the power tube drive signal, so that the energy storage element alternately performs a charging operation and a discharging operation, includes: Detecting the charge and discharge clock signal and the power tube drive signal; When the charge and discharge clock signal is detected to be turned high, the first flip is performed to connect the lower power tube and disconnect the upper power tube, so that the energy storage element performs a charging operation, or when the power tube drive signal is detected to be turned high, the second flip is performed to disconnect the lower power tube and connect the upper power tube, so that the energy storage element performs a discharging operation.

6. The method according to claim 3 or 5, wherein: The step of controlling the boost circuit to stop executing the charge and discharge operation based on the charge and discharge clock signal when the actual execution times of the charge and discharge operation meet the expected execution times comprises: Counting the rising edges of the charge and discharge clock signal to obtain the actual number of executions of the charge and discharge operation; In response to a determination result that the actual execution number meets the expected execution number, switching the charge-discharge drive signal from an enabled state to a disabled state; In response to the determination result that the charge and discharge driving signal is switched to the disabled state, the upper power tube and the lower power tube are disconnected, so that the boost circuit stops performing the charge and discharge operation, and the actual execution times are cleared.

7. The method according to claim 2, wherein: The method further comprises: In response to a detection result that the output voltage is not lower than the reference lower limit voltage, the charge and discharge control signal is switched to a disabled state.

8. A charge and discharge control circuit for a boost circuit, comprising: a control circuit electrically connected to the boost circuit, and configured to detect an output voltage of the boost circuit and count the charge and discharge operations performed by the boost circuit, wherein the control circuit outputs a charge and discharge drive signal in an enabled state when the output voltage of the boost circuit is lower than a reference lower limit voltage, and outputs a charge and discharge drive signal in a disabled state when the actual execution number of the charge and discharge operations of the boost circuit is detected to meet the expected execution number; A drive circuit is electrically connected to the control circuit and the boost circuit, and is used to receive the charge and discharge drive signal of the control circuit, and control the boost circuit to perform at least one charge and discharge operation when the charge and discharge drive signal is detected to be in an enabled state, and control the boost circuit to stop performing the charge and discharge operation when the charge and discharge control signal is detected to be in a disabled state.

9. The charge and discharge control circuit according to claim 8, wherein: The control circuit comprises: A first voltage comparator, which is electrically connected to the boost circuit, and is used to detect the output voltage of the boost circuit, and output a charge and discharge control signal of an enable state when the output voltage of the boost circuit is lower than the reference lower limit voltage; A counter is connected between the first voltage comparator and the driving circuit, and is used to receive the charge and discharge control signal of the first voltage comparator, and output the charge and discharge driving signal of the enabled state when the charge and discharge control signal is judged to be in the enabled state, and output the charge and discharge driving signal of the disabled state when the actual execution times of the charge and discharge operation of the boost circuit accumulated according to the charge and discharge clock signal of the boost circuit meet the expected execution times, and clear the actual execution times of the charge and discharge operation of the boost circuit to zero.

10. The charge and discharge control circuit according to claim 8 or 9, wherein: The boost circuit includes an energy storage element, an upper power tube and a lower power tube electrically connected to the energy storage element; And wherein, the charge and discharge control circuit further includes: an error amplifier, electrically connected to the boost circuit, for performing error amplification processing on an output voltage of the boost circuit and a reference voltage, and outputting an error amplified voltage; A second voltage comparator, which is electrically connected to the error amplifier and is used to compare the sampled voltage of the lower power tube with the error amplified voltage and output a power tube driving signal; The input end of the drive circuit is electrically connected to the second voltage comparator and the control circuit, and the output end of the drive circuit is electrically connected to the upper power tube and the lower power tube, and is used for outputting a drive signal to the upper power tube and the lower power tube based on the power tube drive signal and the charge and discharge clock signal of the boost circuit when the charge and discharge drive signal is in an enabled state, so as to drive the upper power tube and the lower power tube to alternately perform a first flip and a second flip, so that the energy storage element alternately performs a charging operation and a discharging operation.

11. The charge and discharge control circuit according to claim 10, wherein: The negative feedback input of the error amplifier is the output voltage of the boost circuit, and the positive feedback input of the error amplifier is the reference voltage; The negative feedback input of the second voltage comparator is the error amplified voltage, and the positive feedback input of the error amplifier is the sampling voltage; The driving circuit is used to perform the first flip to turn on the lower power tube and turn on and off the upper power tube when detecting that the charge and discharge clock signal turns high, so that the energy storage element performs a charging operation, or to perform the second flip to turn off the lower power tube and turn on the upper power tube when detecting that the power tube driving signal turns high, so that the energy storage element performs a discharging operation.

12. The charge and discharge control circuit according to claim 9, wherein: The driving circuit is used to disconnect the upper power tube and the lower power tube when detecting that the charge and discharge driving signal is switched to a disabled state, so that the boost circuit stops performing the charge and discharge operation.

13. An electronic device, comprising the charge and discharge control circuit according to any one of claims 8 to 12 and a boost circuit connected to the charge and discharge control circuit, so that the charge and discharge operation of the boost circuit is controlled by the charge and discharge control circuit.

14. The electronic device according to claim 13, wherein: The boost circuit includes a power supply, an energy storage element, a lower power tube, and an upper power tube; The first end of the energy storage element is connected to the power source; The second end of the energy storage element is connected to the upper power tube and the lower power tube respectively; The energy storage element performs a charging operation when the lower power tube is turned on and the upper power tube is turned off, and performs a discharging operation when the lower power tube is turned off and the upper power tube is turned on; The charge and discharge control circuit is used to control the connection or disconnection of the upper power tube and the lower power tube respectively.

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