Bus capacitor voltage-sharing method, inverter, electronic equipment and storage medium

Abstract

The invention discloses a bus capacitor voltage-sharing method, an inverter, electronic equipment and a storage medium, the inverter comprises a power supply circuit, a plurality of bus capacitors, an output circuit and a voltage-sharing circuit, the plurality of bus capacitors are connected in series and arranged between the power supply circuit and the output circuit, the voltage-sharing circuit is suitable for generating a charging voltage according to a preset direct current power supply, and the voltage-sharing circuit is used for outputting the charging voltage. The method is used for charging at least one bus capacitor, and comprises the following steps: determining the current working state of the inverter, and obtaining the voltage of each bus capacitor; determining the output power of the voltage-sharing circuit according to the current working state; and controlling the voltage-sharing circuit according to the output power of the voltage-sharing circuit under the condition of determining that the inverter meets a voltage-sharing starting condition according to at least one of the current working state and the voltage of the at least one bus capacitor, so as to carry out voltage sharing on all the bus capacitors. According to the method, the circuit loss is reduced, and the voltage-sharing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and in particular to a bus capacitor voltage balancing method, an inverter, an electronic device and a storage medium. Background Art

[0002] High-power power electronic devices (such as inverters and frequency converters) have bus capacitors. As the capacity of power electronic devices continues to increase, the bus voltage also tends to increase, so multiple bus capacitors connected in series are required to jointly bear the bus voltage. When multiple bus capacitors are used in series, the bus capacitors have voltage imbalance problems due to differences in the capacitance and leakage current of the capacitor monomers. In the related art, energy-consuming devices such as resistors or voltage regulators are usually connected in parallel to each bus capacitor to improve the problem of uneven voltage by changing the impedance relationship between the capacitors. However, this method has large losses, and due to loss limitations, the voltage balancing ability of this method is poor. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to propose a bus capacitor voltage balancing method, dynamically adjust the output power of the voltage balancing circuit according to the current working state of the inverter, and control the voltage balancing circuit to perform active balancing according to the current working state of the inverter and / or the voltage of each bus capacitor, so that all bus capacitors reach the voltage balancing state, thereby reducing circuit loss and improving voltage balancing efficiency.

[0004] A second object of the present invention is to provide a computer-readable storage medium.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] A fourth objective of the present invention is to provide an inverter.

[0007] To achieve the above-mentioned purpose, a bus capacitor voltage equalization method is proposed according to an embodiment of the first aspect of the present invention, which is applied to an inverter. The inverter includes a power supply circuit, multiple bus capacitors, an output circuit and a voltage equalization circuit. The multiple bus capacitors are connected in series, and between the power supply circuit and the output circuit, the voltage equalization circuit is suitable for generating a charging voltage according to a preset DC power supply to charge at least one bus capacitor. The method includes: determining the current working state of the inverter and obtaining the voltage of each bus capacitor; determining the output power of the voltage equalization circuit according to the current working state; when it is determined that the inverter meets the voltage equalization start-up condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage equalization circuit is controlled according to the output power of the voltage equalization circuit to equalize all bus capacitors.

[0008] According to the bus capacitor voltage balancing method of the embodiment of the present invention, the current working state of the inverter is determined, and the voltage of each bus capacitor is obtained, and the output power of the voltage balancing circuit is determined according to the current working state. When it is determined that the inverter meets the voltage balancing start condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage balancing circuit is controlled according to the output power of the voltage balancing circuit to balance all bus capacitors. Thus, the output power of the voltage balancing circuit is dynamically adjusted according to the current working state of the inverter, and the voltage balancing circuit is controlled according to the current working state of the inverter and / or the voltage of each bus capacitor for active balancing, so that all bus capacitors reach the voltage balancing state, thereby reducing circuit losses and improving voltage balancing efficiency.

[0009] According to one embodiment of the present invention, determining whether the inverter meets the voltage balancing start-up condition is based on at least one of the current working state and the voltage of at least one bus capacitor, including: when the current working state is before grid connection and the bus voltage does not meet the rated voltage, or the current working state is a shutdown state, determining that the inverter meets the voltage balancing start-up condition; or when the current working state is an inverter state, and the voltage of at least one bus capacitor is greater than a first preset voltage value and less than a second preset voltage value, determining that the inverter meets the voltage balancing start-up condition.

[0010] According to one embodiment of the present invention, the inverter also includes an auxiliary power supply unit, which is connected to multiple bus capacitors. The auxiliary power supply unit is configured to generate a DC auxiliary power supply according to the bus voltage to power the load, wherein when the current working state is before grid connection and the bus voltage does not meet the rated voltage, the output power of the voltage balancing circuit is determined according to the current working state, including: obtaining the output power of the auxiliary power supply unit; determining the output power of the voltage balancing circuit according to the output power of the auxiliary power supply unit and the first power extraction efficiency of the auxiliary power supply unit from the bus voltage.

[0011] According to one embodiment of the present invention, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit, including: controlling the voltage equalizing circuit to equalize all bus capacitors according to the output power of the voltage equalizing circuit; maintaining the output power of the voltage equalizing circuit unchanged when the voltage of each bus capacitor is less than or equal to a first preset voltage value; when the voltage of at least one bus capacitor is greater than the first preset voltage value, increasing the output power of the voltage equalizing circuit according to a first preset step size, and increasing the output power of the auxiliary power supply unit according to a second preset step size, wherein the first preset step size is determined based on the second preset step size and the first power extraction efficiency.

[0012] According to an embodiment of the present invention, when the current working state is the inverter state, determining the output power of the voltage balancing circuit according to the current working state includes: determining the output power of the voltage balancing circuit to be a preset output power.

[0013] According to one embodiment of the present invention, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit, including: controlling the voltage equalizing circuit to equalize all bus capacitors according to a preset output power, and controlling the input power of the inverter to decrease according to the preset output power; maintaining the output power of the voltage equalizing circuit unchanged when the voltage of each bus capacitor is less than or equal to a first preset voltage value; increasing the output power of the voltage equalizing circuit according to a third preset step size, and controlling the input power of the inverter to decrease according to a fourth preset step size, when the voltage of at least one bus capacitor is greater than the first preset voltage value and the output power of the voltage equalizing circuit is less than or equal to a preset power threshold.

[0014] According to one embodiment of the present invention, after keeping the output power of the voltage equalizing circuit unchanged, the method also includes: when the current working state changes, increasing the output power of the voltage equalizing circuit according to a third preset step size, and controlling the input power of the inverter to decrease according to a fourth preset step size.

[0015] According to an embodiment of the present invention, when the output power of the voltage balancing circuit is greater than a preset power threshold, the method further includes: performing shutdown control on the inverter.

[0016] According to an embodiment of the present invention, when the voltage of at least one bus capacitor is greater than or equal to a second preset voltage value, the method further includes: performing shutdown control on the inverter.

[0017] According to one embodiment of the present invention, the inverter also includes an auxiliary power supply unit, which is connected to multiple bus capacitors. The auxiliary power supply unit is configured to generate a DC auxiliary power supply according to the bus voltage to power the load, wherein when the current working state is a shutdown state, the output power of the voltage balancing circuit is determined according to the current working state, including: obtaining the output power of the auxiliary power supply unit; determining the output power of the voltage balancing circuit according to the output power of the auxiliary power supply unit and the second power extraction efficiency of the auxiliary power supply unit from the bus voltage, wherein the output power of the voltage balancing circuit is less than or equal to the ratio of the output power of the auxiliary power supply unit to the second power extraction efficiency.

[0018] According to one embodiment of the present invention, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit, including: controlling the voltage equalizing circuit to equalize all bus capacitors according to the output power of the voltage equalizing circuit; maintaining the output power of the voltage equalizing circuit unchanged when the voltage of each bus capacitor is less than or equal to a first preset voltage value; when the voltage of at least one bus capacitor is greater than the first preset voltage value, increasing the output power of the voltage equalizing circuit according to a fifth preset step size, and increasing the output power of the auxiliary power supply unit according to a sixth preset step size, wherein the fifth preset step size is less than or equal to the ratio of the sixth preset step size to the second power extraction efficiency.

[0019] According to one embodiment of the present invention, the voltage equalizing circuit includes a transformer and multiple output units, the transformer includes a primary winding and multiple windings, the primary winding is suitable for connecting to a preset DC power supply, and each output unit is connected to a secondary winding and a bus capacitor to charge the corresponding bus capacitor according to the electric energy coupled to the secondary winding.

[0020] To achieve the above-mentioned purpose, according to a second aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is processed by a processor, the bus capacitor voltage equalization method of any of the above-mentioned embodiments is executed.

[0021] According to the computer-readable storage medium of an embodiment of the present invention, by executing a computer program of the above-mentioned bus capacitor voltage balancing method, the output power of the voltage balancing circuit is dynamically adjusted according to the current working state of the inverter, and the voltage balancing circuit is actively balanced according to the current working state of the inverter and / or the voltage of each bus capacitor so that all bus capacitors reach the voltage balancing state, thereby reducing circuit losses and improving voltage balancing efficiency.

[0022] To achieve the above-mentioned purpose, an electronic device is proposed according to an embodiment of the third aspect of the present invention, comprising a memory, a processor, and a bus capacitor voltage equalization control program stored in the memory and executable on the processor. When the processor executes the bus capacitor voltage equalization program, the bus capacitor voltage equalization method of any of the aforementioned embodiments is implemented.

[0023] According to the electronic device of an embodiment of the present invention, a computer program of the above-mentioned bus capacitor voltage equalization method is executed by a processor, the output power of the voltage equalization circuit is dynamically adjusted according to the current working state of the inverter, and the voltage equalization circuit is actively balanced according to the current working state of the inverter and / or the voltage of each bus capacitor so that all bus capacitors reach the voltage equalization state, thereby reducing circuit losses and improving voltage equalization efficiency.

[0024] To achieve the above-mentioned purpose, an inverter is proposed according to an embodiment of the fourth aspect of the present invention, comprising: a power supply circuit, a plurality of bus capacitors, an output circuit and a voltage equalizing circuit, wherein the plurality of bus capacitors are arranged between the power supply circuit and the output circuit, and the voltage equalizing circuit is suitable for generating a charging voltage according to a preset DC power supply to charge at least one bus capacitor; a controller is configured to determine the current working state of the inverter, obtain the voltage of each bus capacitor, and determine the output power of the voltage equalizing circuit according to the current working state, and when it is determined that the inverter meets the voltage equalization start-up condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit to equalize all bus capacitors.

[0025] According to an inverter of an embodiment of the present invention, it includes a power supply circuit, a plurality of bus capacitors, an output circuit, a voltage equalization circuit and a controller. The current working state of the inverter is determined by the controller, and the voltage of each bus capacitor is obtained. The output power of the voltage equalization circuit is determined according to the current working state. When it is determined that the inverter meets the voltage equalization start condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage equalization circuit is controlled according to the output power of the voltage equalization circuit to equalize all bus capacitors. Thus, the output power of the voltage equalization circuit is dynamically adjusted according to the current working state of the inverter, and the voltage equalization circuit is controlled according to the current working state of the inverter and / or the voltage of each bus capacitor to perform active balancing, so that all bus capacitors reach the voltage equalization state, thereby reducing circuit losses and improving voltage equalization efficiency.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a circuit diagram of an inverter according to an embodiment of the present invention;

[0028] Figure 2 is a circuit diagram of a busbar capacitor bank according to an embodiment of the present invention;

[0029] Figure 3 is a flow chart of a busbar capacitor voltage balancing method according to an embodiment of the present invention;

[0030] Figure 4 is a circuit diagram of a voltage equalizing circuit according to an embodiment of the present invention;

[0031] Figure 5 is a circuit diagram of a forward voltage equalizing circuit according to an embodiment of the present invention;

[0032] Figure 6is a circuit diagram of a flyback voltage equalizing circuit according to an embodiment of the present invention;

[0033] Figure 7 is a circuit diagram of a half-bridge, full-bridge or push-pull voltage equalizing circuit according to an embodiment of the present invention;

[0034] Figure 8 is a circuit diagram of controlling a voltage balancing circuit in a hardware control manner according to an embodiment of the present invention;

[0035] Fig. 9 is a circuit diagram of controlling a voltage balancing circuit using an auxiliary power supply according to an embodiment of the present invention;

[0036] Fig.10 It is a flow chart of a bus capacitor voltage balancing method according to an embodiment of the present invention when the inverter is before being connected to the grid and the bus voltage has not yet been charged to the rated voltage;

[0037] Fig.11 is a flow chart of a bus capacitor voltage balancing method when the inverter is in an inverter state according to an embodiment of the present invention;

[0038] Fig.12 is a flow chart of a bus capacitor voltage balancing method when the inverter is in a shutdown state according to an embodiment of the present invention;

[0039] Fig.13 is a system schematic diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0041] The bus capacitor voltage balancing method, computer-readable storage medium, electronic device, and inverter according to embodiments of the present invention are described below with reference to the accompanying drawings.

[0042] Figure 1 FIG. 1 is a circuit diagram of an inverter according to an embodiment of the present invention. Figure 1 As shown, the inverter includes a power supply circuit 10 , a plurality of bus capacitors, an output circuit 30 and a voltage balancing circuit 20 .

[0043] Among them, a plurality of bus capacitors are connected in series and arranged between the power supply circuit 10 and the output circuit 30, and the voltage equalization circuit 20 is suitable for generating a charging voltage according to a preset DC power supply to charge at least one bus capacitor.

[0044] Specifically, the busbar capacitor voltage balancing method of this embodiment is applied to Figure 1 In the inverter shown, the positive output terminal of the power supply circuit 10, the positive input terminal of the output circuit 30, and the first end of the voltage equalizing circuit 20 are respectively connected to one end of the bus capacitor C1, one end of the bus capacitor C2 and the second end of the voltage equalizing circuit 20 are connected to the other end of the bus capacitor C1, and the negative output terminal of the power supply circuit 10, the negative input terminal of the output circuit 30, and the third end of the voltage equalizing circuit 20 are respectively connected to the other end of the bus capacitor C2 of the voltage equalizing circuit 20. The power supply circuit 10 and the bus capacitor are used to output stable direct current to the output circuit 30, and the output circuit 30 converts the direct current into alternating current for grid connection. The preset DC power supply can be the DC power supply output by the power supply circuit 10, that is, the bus voltage, or it can be generated by rectifying the AC power grid, or it can be a DC power supply generated after voltage conversion of the bus voltage. The number of bus capacitors is not limited to Figure 1 The two shown can also be Figure 2 As shown in the figure, each bus capacitor group is composed of multiple capacitors connected in parallel, the first capacitor group is composed of capacitors C11-C1P connected in parallel, the second capacitor group is composed of capacitors C21-C2P, and the nth capacitor group is composed of capacitors CN1-CNP connected in parallel. Figure 2 As shown, the voltage equalizing circuit 20 may include a transformer and a rectifier circuit 60, the transformer includes a primary winding Wp and a secondary winding W1-Wn, the primary winding Wp is connected to a preset DC power supply, the transformer couples the electric energy of the primary winding Wp to the secondary winding W1-Wn, and the rectifier circuit 60 rectifies the electric energy coupled to the secondary winding W1-Wn to generate a charging voltage to charge the bus capacitor.

[0045] It should be noted that the various circuit components of the inverter of this embodiment are not limited to one type, and may also be an inverter composed of other circuits having the same function, which is not specifically limited here.

[0046] Figure 3 FIG. 1 is a flow chart of a busbar capacitor voltage balancing method according to an embodiment of the present invention. Figure 3 As shown in FIG. 1 , the busbar capacitor voltage balancing method includes:

[0047] S101, determining the current working state of the inverter and obtaining the voltage of each bus capacitor.

[0048] Specifically, determine the current working state of the inverter, and sample the voltage of each bus capacitor through the voltage sampling module. The working state of the inverter includes before grid-connected operation and when the bus voltage has not yet reached the rated voltage, the inverter state, and the shutdown state. When the inverter is in different working states, the voltage characteristics of the bus capacitor are different. Therefore, when the inverter is in different working states, the working mode of the voltage balancing circuit is also different, so it is necessary to determine the current working state of the inverter. According to the voltage of each bus capacitor, it can be judged whether the bus capacitor has voltage imbalance to control the voltage balancing circuit.

[0049] S102, determining the output power of the voltage equalizing circuit according to the current working state.

[0050] Specifically, the output power of the voltage-equalizing circuit is the initial output power of the voltage-equalizing circuit. When the inverter is in different working states, the working mode of its internal circuit is also different, and the method of determining the output power of the voltage-equalizing circuit is also different. For example, before grid-connected operation and when the bus voltage has not reached the rated voltage and shutdown state, the DC auxiliary power supply in the inverter will also participate in the work. Therefore, the output power of the voltage-equalizing circuit needs to be determined according to the power of the DC auxiliary power supply. In the inverter state, the DC auxiliary power supply will not participate in the work. Therefore, the output power of the voltage-equalizing circuit does not need to be determined according to the power of the DC auxiliary power supply.

[0051] S103, when it is determined that the inverter meets the voltage balancing start condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage balancing circuit is controlled according to the output power of the voltage balancing circuit to balance the voltages of all bus capacitors.

[0052] Specifically, when the current working state is before the inverter grid-connected operation and the bus voltage has not yet reached the rated voltage or is in a shutdown state, the bus capacitor is prone to voltage imbalance. At this time, the voltage equalization circuit can be controlled to perform voltage equalization, and whether the bus capacitor has voltage imbalance can also be judged based on the voltage of the bus capacitor. Therefore, based on the current working state and at least one of the voltages of at least one bus capacitor, it can be judged whether the inverter meets the voltage equalization start-up conditions. If the inverter does not meet the voltage equalization start-up conditions, there is no need to turn on the voltage equalization circuit; if the inverter meets the voltage equalization start-up conditions, the voltage equalization circuit is turned on according to the output power of the voltage equalization circuit to charge the corresponding bus capacitors until the capacitor voltages are all balanced.

[0053] In the above embodiment, the output power of the voltage balancing circuit is dynamically adjusted according to the current working state of the inverter, and the voltage balancing circuit is actively balanced according to the current working state of the inverter and / or the voltage of each bus capacitor so that all bus capacitors reach the voltage balancing state, thereby reducing circuit losses and improving voltage balancing efficiency.

[0054] In some embodiments, determining whether the inverter meets the voltage balancing start-up condition is based on at least one of the current working state and the voltage of at least one bus capacitor, including: when the current working state is before grid connection and the bus voltage does not meet the rated voltage, or the current working state is a shutdown state, determining that the inverter meets the voltage balancing start-up condition; or when the current working state is an inverter state, and the voltage of at least one bus capacitor is greater than a first preset voltage value and less than a second preset voltage value, determining that the inverter meets the voltage balancing start-up condition.

[0055] Specifically, before the inverter is connected to the grid, due to the inconsistency of the tolerance and leakage current characteristics of the bus series-parallel capacitor group, the bus voltage is easily uneven. If it is not handled before the inverter output power, the capacitor and switch devices of the inverter circuit are likely to exceed their rated voltage specifications, resulting in device failure; and when the inverter is in the shutdown state, if the discharge is uneven, a single capacitor may be over-discharged and the series capacitor voltage may be over-stressed, so voltage equalization is required; when the inverter is in the inverter output state, the voltage of each bus capacitor is monitored in real time. If the voltage of any bus capacitor is greater than the first preset voltage value and less than the second preset voltage value, then If the bus capacitor has a voltage imbalance problem, voltage equalization is required. The first preset voltage value is the preset imbalance voltage value, and the second preset voltage value is the capacitor voltage threshold. If the voltage of all bus capacitors is less than or equal to the first preset voltage value, there is no imbalance problem in the bus capacitor, or there is an imbalance problem in the bus capacitor but it does not exceed the imbalance voltage value. At this time, the bus capacitor imbalance voltage is within the allowable range and there is no need to start the voltage equalization circuit. If the voltage of any bus capacitor is higher than the imbalance voltage value and less than the capacitor voltage threshold, the imbalance of the bus capacitor will affect the output of the inverter, and the voltage equalization circuit needs to be started to actively balance the bus capacitor.

[0056] In some embodiments, Figure 1 As shown, the inverter also includes an auxiliary power supply unit 40, which is connected to multiple bus capacitors. The auxiliary power supply unit 40 is configured to generate a DC auxiliary power supply according to the bus voltage to power the load 50, wherein when the current working state is before grid connection and the bus voltage does not meet the rated voltage, the output power of the voltage equalizing circuit 20 is determined according to the current working state, including: obtaining the output power of the auxiliary power supply unit 40; determining the output power of the voltage equalizing circuit 20 according to the output power of the auxiliary power supply unit 40 and the first power supply efficiency of the auxiliary power supply unit 40 from the bus voltage.

[0057] Specifically, the inverter also includes an auxiliary power supply unit 40, the positive input end of the auxiliary power supply unit 40 is connected to one end of the bus capacitor C1, the negative input end of the auxiliary power supply unit 40 is connected to the other end of the bus capacitor C2, and the output end of the auxiliary power supply unit 40 is connected to the load 50, and is used to generate a DC auxiliary power supply according to the bus voltage to supply power to the load 50. When the current working state is before grid connection and the bus voltage does not meet the rated voltage, the output power equalizing circuit 20 of the auxiliary power supply unit 40 is obtained, and the output power of the equalizing circuit 20 is determined according to the output power of the auxiliary power supply unit 40 and the first power extraction efficiency of the auxiliary power supply unit 40 from the bus voltage. The equalizing circuit 20 auxiliary power supply unit 40 will not affect the normal voltage rise speed of the bus capacitor.

[0058] In some embodiments, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit, including: controlling the voltage equalizing circuit to equalize all bus capacitors according to the output power of the voltage equalizing circuit; maintaining the output power of the voltage equalizing circuit unchanged when the voltage of each bus capacitor is less than or equal to a first preset voltage value; when the voltage of at least one bus capacitor is greater than the first preset voltage value, increasing the output power of the voltage equalizing circuit according to a first preset step size, and increasing the output power of the auxiliary power supply unit according to a second preset step size, wherein the first preset step size is determined based on the second preset step size and the first power extraction efficiency.

[0059] Specifically, the voltage equalizing circuit is turned on according to the output power control of the voltage equalizing circuit to charge the bus capacitors with lower voltages, and the voltage of each bus capacitor is monitored at the same time. If the voltage of all bus capacitors is less than or equal to the first preset voltage value, the voltage of all bus capacitors is within an acceptable range, and therefore, the output power of the voltage equalizing circuit currently set is maintained unchanged. If the voltage of at least one bus capacitor is still greater than the first preset voltage value, the capacitor imbalance may have an adverse effect on the circuit, and the output power of the voltage equalizing circuit needs to be adjusted so that the voltage of all bus capacitors is less than or equal to the first preset voltage value. The output power of the voltage equalizing circuit can be adjusted in a step-by-step manner. For example, the output power of the voltage equalizing circuit is increased stepwise according to the first preset step size, and the output power of the auxiliary power supply unit is increased according to the second preset step size, wherein the first preset step size can be the ratio of the second preset step size to the first power extraction efficiency. In the process of stepping up the output power of the voltage equalizing circuit, if the voltage of all bus capacitors is less than or equal to the first preset voltage value, the output power of the currently set voltage equalizing circuit is kept unchanged until the bus voltage meets the rated voltage. At this time, the inverter can carry out the flow of main power normally, that is, draw power from the photovoltaic modules, invert and output the electrical energy of the photovoltaic modules.

[0060] In the above embodiment, during the voltage equalization process of the bus capacitor, the power of the voltage equalization circuit is adjusted in steps according to the voltage of the bus capacitor. In this way, while maintaining the original bus voltage rising rate, the voltage equalization capacity of the voltage equalization circuit can be increased, thereby further improving the voltage equalization efficiency.

[0061] In some embodiments, when the current working state is the inverter state, determining the output power of the voltage balancing circuit according to the current working state includes: determining the output power of the voltage balancing circuit to be a preset output power.

[0062] Specifically, when the inverter is currently in the inverter state, the auxiliary power supply unit is not involved. At this time, the capacitor bus capacitance balancing is completed by adjusting the power level loop and cooperating with the voltage equalizing circuit. Therefore, there is no need to determine the output power of the voltage equalizing circuit based on the output power of the auxiliary power supply unit. The output power of the voltage equalizing circuit can be directly set to the preset output power.

[0063] In some embodiments, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit, including: controlling the voltage equalizing circuit to equalize all bus capacitors according to a preset output power, and controlling the input power of the inverter to decrease according to the preset output power; maintaining the output power of the voltage equalizing circuit unchanged when the voltage of each bus capacitor is less than or equal to a first preset voltage value; increasing the output power of the voltage equalizing circuit according to a third preset step size, and controlling the input power of the inverter to decrease according to a fourth preset step size, when the voltage of at least one bus capacitor is greater than the first preset voltage value and the output power of the voltage equalizing circuit is less than or equal to a preset power threshold.

[0064] Specifically, when the inverter performs inverter output, assuming that the input power of the inverter is Pin, the inverter efficiency is η2, and the output power of the inverter is Pout = Pin*η2, when the inverter is in the inverter state, the output power of the inverter needs to remain unchanged. Therefore, when the voltage equalization circuit is turned on according to the preset output power, the input power of the inverter needs to be reduced by the preset output power, so that the voltage equalization circuit balances the capacitor voltage under the condition that the total bus voltage and the original output power remain unchanged.

[0065] If the voltages of all bus capacitors are less than or equal to the first preset voltage value, the voltages of all bus capacitors are within an acceptable range, and therefore the output power of the currently set voltage balancing circuit is kept unchanged.

[0066] When the voltage of at least one bus capacitor is still greater than the first preset voltage value, the capacitor imbalance may have an adverse effect on the circuit, and the output power of the voltage equalizing circuit needs to be adjusted. Before each adjustment of the output power of the voltage equalizing circuit, it is necessary to determine whether the output power of the voltage equalizing circuit is less than or equal to the preset power threshold. If the output power of the voltage equalizing circuit is less than or equal to the preset power threshold, the output power of the voltage equalizing circuit can be adjusted to enhance the voltage equalizing capability of the voltage equalizing circuit. The preset power threshold is the maximum output power of the voltage equalizing circuit. The output power of the voltage equalizing circuit is increased according to the third preset step size, and the input power of the inverter is controlled to decrease according to the fourth preset step size. In the process of stepping the output power of the voltage equalizing circuit, if the voltage of all bus capacitors is less than or equal to the first preset voltage value, the output power of the voltage equalizing circuit currently set is kept unchanged.

[0067] It should be noted that the third preset step size can be a fixed value or a variable value, and the fourth preset step size is equal to the third preset step size. For example, assuming that when the output power of the voltage equalizing circuit is adjusted for the first time, the third preset step size is P0step1, then the fourth preset step size is Pinstep1=P0step1; assuming that when the output power of the voltage equalizing circuit is adjusted for the second time, the third preset step size is P0step2, then the fourth preset step size is Pinstep2=P0step2. In this way, the bus capacitance can be balanced while the bus voltage and the output power of the inverter remain unchanged.

[0068] In an optional embodiment, in a new control cycle, if the inverter enters the inverter state and the voltage of all bus capacitors is less than or equal to the first preset voltage value at this time, it is not necessary to turn on the voltage equalizing circuit. If the voltage equalizing circuit has been turned on before entering the inverter state, the output power of the voltage equalizing circuit can be reduced in a step-by-step manner until the voltage equalizing circuit is turned off. In the process of reducing the output power of the voltage equalizing circuit, if the voltage of at least one bus capacitor is greater than the first preset voltage value, the voltage equalizing circuit is controlled to equalize all bus capacitors according to the preset output power.

[0069] In some embodiments, after keeping the output power of the voltage balancing circuit unchanged, the method also includes: when the current working state changes, increasing the output power of the voltage balancing circuit according to a third preset step size, and controlling the input power of the inverter to decrease according to a fourth preset step size.

[0070] Specifically, when the voltages of all bus capacitors are less than or equal to the first preset voltage value, it can be considered that the voltages of all bus capacitors are balanced, so the output power of the voltage equalization circuit is kept unchanged, that is, the current power loop of the inverter is maintained. After the output power of the voltage equalization circuit is kept unchanged, if the current working state of the inverter changes, such as the inverter stops running, before the inverter is connected to the grid, the load is unbalanced during the inverter operation, or the total bus voltage fluctuates, it will cause the bus capacitor to be unbalanced, and the output power of the voltage equalization circuit needs to be readjusted. At this time, the adjustment method can also be adjusted in a step-by-step increase manner, that is, the output power of the voltage equalization circuit is increased according to the third preset step size, and the input power of the inverter is controlled to decrease according to the fourth preset step size until the bus voltage is balanced.

[0071] In some embodiments, when the output power of the voltage balancing circuit is greater than a preset power threshold, the method further includes: performing shutdown control on the inverter.

[0072] Specifically, when the output power of the voltage balancing circuit is greater than a preset power threshold, the imbalance phenomenon has exceeded the capability range of the voltage balancing circuit, and the inverter needs to be shut down for protection to prevent damage to the inverter and capacitor.

[0073] In some embodiments, when the voltage of at least one bus capacitor is greater than or equal to a second preset voltage value, the method further includes: performing shutdown control on the inverter.

[0074] Specifically, when the voltage of at least one bus capacitor is greater than or equal to a second preset voltage value, that is, the voltage imbalance problem of the bus capacitor is more serious, if the inverter continues to operate, the bus capacitor will be damaged. Therefore, it is necessary to control the inverter shutdown protection to prevent device damage, thereby improving the reliability of the inverter.

[0075] In some embodiments, Figure 1 As shown, the inverter also includes an auxiliary power supply unit 40, which is connected to multiple bus capacitors. The auxiliary power supply unit 40 is configured to generate a DC auxiliary power supply according to the bus voltage to power the load 50, wherein when the current working state is a shutdown state, the output power of the voltage balancing circuit 20 is determined according to the current working state, including: obtaining the output power of the auxiliary power supply unit 40; determining the output power of the voltage balancing circuit according to the output power of the auxiliary power supply unit 40 and the second power supply efficiency of the auxiliary power supply unit 40 from the bus voltage, wherein the output power of the voltage balancing circuit 20 is less than or equal to the ratio of the output power of the auxiliary power supply unit 40 to the second power supply efficiency.

[0076] Specifically, when the inverter is in a power-off or shutdown state, the auxiliary power supply unit 40 will also work, but the flow direction of the output power of the auxiliary power supply unit 40 and the output power of the voltage equalization circuit 20 are opposite, so the voltage equalization method at this time is different from the control method before the inverter is connected to the grid. First, the output power of the auxiliary power supply unit 40 is obtained, and then the output power of the voltage equalization circuit is determined according to the output power of the auxiliary power supply unit 40 and the second power extraction efficiency of the auxiliary power supply unit 40 from the bus voltage. Since the output power of the voltage equalization circuit 20 and the auxiliary power supply unit 40 flows in opposite directions when the inverter is shut down, the output power of the voltage equalization circuit 20 is less than or equal to the ratio of the output power of the auxiliary power supply unit 40 to the second power extraction efficiency, so that while the bus capacitor is voltage-equalized, its normal discharge speed is not affected.

[0077] In some embodiments, the voltage equalizing circuit is controlled according to the output power of the voltage equalizing circuit, including: controlling the voltage equalizing circuit to equalize all bus capacitors according to the output power of the voltage equalizing circuit; maintaining the output power of the voltage equalizing circuit unchanged when the voltage of each bus capacitor is less than or equal to a first preset voltage value; when the voltage of at least one bus capacitor is greater than the first preset voltage value, increasing the output power of the voltage equalizing circuit according to a fifth preset step size, and increasing the output power of the auxiliary power supply unit according to a sixth preset step size, wherein the fifth preset step size is less than or equal to the ratio of the sixth preset step size to the second power extraction efficiency.

[0078] Specifically, the voltage balancing circuit is turned on according to the output power control of the voltage balancing circuit to charge the bus capacitors with lower voltages, and the voltage of each bus capacitor is monitored at the same time. If the voltage of all bus capacitors is less than or equal to the first preset voltage value, the voltage of all bus capacitors is within an acceptable range, so the output power of the voltage balancing circuit currently set is kept unchanged. If the voltage of at least one bus capacitor is still greater than the first preset voltage value, the capacitor imbalance may have an adverse effect on the circuit, and the output power of the voltage balancing circuit needs to be adjusted so that the voltage of all bus capacitors is less than or equal to the first preset voltage value. The output power of the voltage balancing circuit can be adjusted by step-increasing. For example, the output power of the voltage balancing circuit is increased stepwise according to the fifth preset step size, and the output power of the auxiliary power supply unit is increased according to the sixth preset step size, wherein the fifth preset step size is less than or equal to the ratio of the sixth preset step size to the second power extraction efficiency, so that while maintaining the bus voltage drop, the voltage balancing capacity of the voltage balancing circuit can be enhanced. During the process of stepping up the output power of the voltage equalizing circuit, if the voltage of all bus capacitors is less than or equal to the first preset voltage value, the output power of the currently set voltage equalizing circuit is maintained unchanged until the voltage of the bus capacitor drops normally to 0 or a lower value, thereby achieving voltage balancing of the bus capacitor during discharge, and there is no risk of overvoltage on the capacitor.

[0079] In some embodiments, Figure 4 As shown, the voltage equalizing circuit 20 includes a transformer and multiple output units (71 and 72), the transformer includes a primary winding Wp and multiple windings (W1 and W2), the primary winding Wp is suitable for connecting a preset DC power supply, and each output unit is connected to a secondary winding and a bus capacitor to charge the corresponding bus capacitor according to the electric energy coupled to the secondary winding.

[0080] Specifically, the voltage balancing circuit 20 includes a transformer and a plurality of output units (71 and 72), the transformer includes a primary winding Wp and a plurality of windings (W1 and W2), the primary winding Wp is suitable for connecting a preset DC power supply, the output units (71 and 72) can be rectifier circuits, the number of output units is the same as the number of bus capacitors, and when the bus capacitor is Figure 3 When there are two as shown, there are also two output units, namely a first output unit 71 and a second output unit 72. The first output unit 71 is respectively connected to the secondary winding W1 and the bus capacitor C1, and the second output unit 72 is respectively connected to the secondary winding W2 and the bus capacitor C2. The first output unit 71 rectifies the electric energy coupled to the secondary winding W1, and uses the rectified direct current to charge the bus capacitor C1. The second output unit 72 rectifies the electric energy coupled to the secondary winding W2, and uses the rectified direct current to charge the bus capacitor C2.

[0081] The transformer coupling method can adopt forward topology, flyback topology, half-bridge topology, full-bridge topology or push-pull topology.

[0082] by Figure 5 Taking the forward voltage equalizing circuit shown as an example, the primary winding Wp and the secondary windings W1 and W2 have the same coupling direction during excitation, the first output unit 71 and the second output unit 72 have the same structure, the first output unit 71 includes a first diode D1, a second diode D2 and a first filter inductor L1, the second output unit 72 includes a third diode D3, a fourth diode D4 and a second filter inductor L2, the number of turns of each secondary winding is the same, and the inductance of the filter inductor of each output unit is also the same.

[0083] Assume that the input voltage of the primary winding Wp is Vi, and the turns ratio of the primary winding Wp to the secondary winding W1 is Np:N1=N, then the turns ratio setting should be limited to Vi / N>V and Vi / N<=Vbus / 2, where Vbus is the bus voltage and V is the target voltage. Take the problem of unbalanced bus capacitance when N=2 as an example, the induced voltage of the secondary winding is Vi / N, the operating frequency is f, and the forward duty cycle of the primary measurement is D. Control D to gradually increase (step-by-step increase in power) until D=(Vbus / 2) / (Vi / N) and reaches stability.

[0084] Taking Figure 6 the flyback voltage equalizing circuit shown as an example, the coupling directions of the primary winding Wp, the secondary winding W1, and the secondary winding W2 are opposite during magnetization. The first output unit 71 includes a fifth diode D5, the second output unit 72 includes a sixth diode D6, and the number of turns of each secondary winding is the same.

[0085] When there is a problem of voltage imbalance in the bus capacitors, such as the voltage V1 of the bus capacitor C1 > the voltage V2 of the bus capacitor C2, and the input power of the voltage equalizing circuit 20 is P. When the switching transistor (not shown) on the primary winding Wp side is turned on, the excitation inductor stores energy. When the switching transistor on the primary winding Wp side is turned off, the energy stored in the excitation inductor is transferred to the secondary windings (W1 and W2). At this time, the secondary winding W2 is clamped by the voltage V2 of the bus capacitor C2. If the diode voltage drop is ignored, the voltage Vw2 of the secondary winding W2 = V2. Due to the electromagnetic induction law, the voltage of the secondary winding W1 is also clamped by V2, Vw1 = V2. Because V2 < V1, the fifth diode D5 of the first output unit 71 is not turned on. All the excitation energy on the primary winding Wp side flows from the secondary winding W2 into the bus capacitor C2. During this process, the input and load of the DC bus need to be controlled to maintain the bus voltage from overvoltage and constant at Vbus, that is, V1 + V2 = Vbus. Then it takes time t = 1 / 2 * C2 * ((Vbus^2) / 4 - V2) to charge the voltage of the bus capacitor C2 to Vbus / 2. And, due to the bus voltage regulation control, the voltage of the bus capacitor C1 is also equalized to Vbus / 2.

[0086] When using a half-bridge topology, a full-bridge topology, or a push-pull topology, as Figure 7 shown, the connection methods on the primary winding side are different. When using a push-pull topology, there are two primary windings, namely the first primary winding Wp1 and the second primary winding Wp2. When using a half-bridge topology or a full-bridge topology, there can be one primary winding, which is the first primary winding Wp1. The connection methods on the secondary winding side are the same, and the structures of the output units are also the same. The first output unit 71 includes a seventh diode D7, an eighth diode D8, and a third filter inductor L3. The second output unit includes a ninth diode D9, a tenth diode D10, and a fourth filter inductor L4.

[0087] It should be noted that the bus capacitor voltage equalizing method of the present invention controls the voltage equalizing circuit through a software control method. In actual applications, a hardware control method can also be used to control the voltage equalizing circuit. Such as Figure 8As shown, the inverter adopts a hardware (analog) loop for voltage balancing and is controlled by an analog chip 80. The analog chip 80 controls the switch tube Q1 according to the difference between the voltage difference of the two bus capacitors and the given voltage REF. The circuit can limit or adjust the voltage balancing capability of the voltage balancing circuit 20 by designing a hardware over-power point.

[0088] Furthermore, when the inverter includes an auxiliary power supply unit 40, the charging voltage of the voltage balancing circuit 20 can also be limited by the auxiliary power supply unit 40. Fig. 9 As shown, the transformer has three secondary windings (W1, W2, and W3), and the secondary winding W3 is connected to the auxiliary power supply unit 40. The midpoint voltages of the bus capacitors C1 and C2 are sampled, and the sampled midpoint voltage values ​​are processed to obtain a given voltage REF. The analog chip 80 controls the switch tube Q1 according to the difference between the given voltage REF and the voltage of the auxiliary power supply Vo output by the auxiliary power supply unit 40. The voltage of the secondary winding W3 can be adjusted by adjusting the voltage of the auxiliary power supply Vo. The voltage of the secondary winding W1 and the voltage of the secondary winding W2 are respectively proportional to the voltage of the secondary winding W3, so the voltage of the auxiliary power supply Vo can adjust the bus voltage and the midpoint voltage. Therefore, the bus will not have an overvoltage risk due to bus capacitor voltage balancing.

[0089] The technical solution of the present application is further described in detail below in conjunction with specific implementation methods:

[0090] When the inverter is before being connected to the grid and the bus voltage has not yet been charged to the rated voltage Vbus_goal, Fig.10 As shown, the busbar capacitor voltage balancing method includes the following steps:

[0091] S201, setting the output power of the voltage balancing circuit to P0, and setting the output power of the auxiliary power supply unit to P1, wherein P0=P1 / η1, η1 is a first power extraction efficiency.

[0092] S202, determine whether the voltage of all bus capacitors is less than or equal to a first preset voltage value, if yes, execute step S203, if not, execute step S204.

[0093] S203, maintaining the output power of the voltage balancing circuit unchanged until the bus voltage rises to Vbus_goal, at which time the grid-connected operation can be performed.

[0094] S204, increasing the output power of the voltage balancing circuit in a step-by-step manner according to a first preset step length P0step, and increasing the output power of the auxiliary power supply unit in a step-by-step manner according to a second preset step length P1step, wherein P0step=P1step / η1.

[0095] When the inverter is in the inverter state, Fig.11 As shown, the busbar capacitor voltage balancing method includes the following steps:

[0096] S301, obtaining the voltage of each bus capacitor.

[0097] S302, determine whether the voltage of all bus capacitors is less than a second preset voltage value, if yes, execute step S304, if not, execute step S303.

[0098] S303, controlling the inverter to stop working.

[0099] S304, determining whether the voltage of at least one bus capacitor is greater than a first preset voltage value, if yes, executing step S305, if no, returning to step S302.

[0100] S305, controlling the input power of the inverter to reduce Pin0, and setting the output power of the voltage balancing circuit to P0, wherein P0 = Pin0.

[0101] S306, increasing the output power of the voltage balancing circuit in a step-by-step manner according to a third preset step length P0step, and decreasing the input power of the inverter in a step-by-step manner according to a fourth preset step length Pinstep.

[0102] S307, determining whether the output power of the voltage balancing circuit is greater than a preset power threshold, if yes, executing step S303, if no, executing step S308.

[0103] S308, determining whether the voltages of all bus capacitors are less than or equal to a first preset voltage value, if yes, executing step S309, if no, returning to step S306.

[0104] 309, the output power of the voltage equalizing circuit is kept unchanged.

[0105] 310, determine whether the current working state of the inverter has changed, if yes, execute step S306, if no, execute step S309.

[0106] When the inverter is in shutdown state, Fig.12 As shown, the busbar capacitor voltage balancing method includes the following steps:

[0107] 401, setting the output power of the voltage balancing circuit to P0, and setting the output power of the auxiliary power supply unit to P1, wherein P0≤P1 / η3, η3 is the second power extraction efficiency.

[0108] 402, determine whether the voltage of all bus capacitors is less than or equal to a first preset voltage value, if yes, execute step S403, if no, execute step S404.

[0109] 403, the output power of the voltage balancing circuit is kept unchanged until the voltage of all bus capacitors drops to 0.

[0110] 404 , increasing the output power of the voltage balancing circuit in a step-by-step manner according to a fifth preset step length P0step, and increasing the output power of the auxiliary power supply unit in a step-by-step manner according to a sixth preset step length P1step, wherein P0step≤P1step / η3.

[0111] In the above embodiment, the output power of the voltage balancing circuit is dynamically adjusted according to the current working state of the inverter, and the voltage balancing circuit is actively balanced according to the current working state of the inverter and / or the voltage of each bus capacitor so that all bus capacitors reach the voltage balancing state, thereby reducing circuit losses and improving voltage balancing efficiency.

[0112] To summarize, according to the bus capacitor voltage equalization method of an embodiment of the present invention, the current working state of the inverter is first determined, and the voltage of each bus capacitor is obtained. The voltage equalization start condition is that the inverter is currently in the state before the inverter grid-connected operation or is shut down, and that at least one of the bus capacitors of the current inverter has an unbalanced voltage. When any of the conditions is met, the voltage equalization circuit is turned on, and then the output power of the voltage equalization circuit is determined according to the current working state of the inverter to determine the conditions for the bus voltage and bus capacitance to reach a balance. Finally, the voltage equalization circuit is controlled to charge the bus capacitor according to the determined output power of the voltage equalization circuit to make each bus capacitor voltage-equalized, thereby reducing circuit losses and improving voltage equalization efficiency.

[0113] Corresponding to the above-mentioned embodiments, an embodiment of the present invention further proposes a computer-readable storage medium on which a computer program is stored. When the computer program is processed by a processor, the bus capacitor voltage equalization method of any of the above-mentioned embodiments is executed.

[0114] According to the computer-readable storage medium of an embodiment of the present invention, by executing a computer program of the above-mentioned bus capacitor voltage balancing method, the output power of the voltage balancing circuit is dynamically adjusted according to the current working state of the inverter, and the voltage balancing circuit is actively balanced according to the current working state of the inverter and / or the voltage of each bus capacitor so that all bus capacitors reach the voltage balancing state, thereby reducing circuit losses and improving voltage balancing efficiency.

[0115] Corresponding to the above embodiment, the embodiment of the present invention further provides an electronic device. Fig.13 As shown, the electronic device 90 includes a memory 91, a processor 92, and a bus capacitor voltage equalization control program stored in the memory 91 and executable on the processor 92. When the processor 92 executes the bus capacitor voltage equalization program, the bus capacitor voltage equalization method of any of the aforementioned embodiments is implemented.

[0116] According to the electronic device of an embodiment of the present invention, a computer program of the above-mentioned bus capacitor voltage equalization method is executed by a processor, the output power of the voltage equalization circuit is dynamically adjusted according to the current working state of the inverter, and the voltage equalization circuit is actively balanced according to the current working state of the inverter and / or the voltage of each bus capacitor so that all bus capacitors reach the voltage equalization state, thereby reducing circuit losses and improving voltage equalization efficiency.

[0117] Corresponding to the above embodiment, the embodiment of the present invention further proposes an inverter. Figure 1 As shown, the inverter includes: a power supply circuit 10, a plurality of bus capacitors (C1 and C2), an output circuit 30, a voltage balancing circuit 20 and a controller (not shown).

[0118] Among them, multiple bus capacitors (C1 and C2) are arranged between the power supply circuit 10 and the output circuit 30, and the voltage equalizing circuit 20 is suitable for generating a charging voltage according to a preset DC power supply to charge at least one bus capacitor; the controller is configured to determine the current working state of the inverter, and obtain the voltage of each bus capacitor, and determine the output power of the voltage equalizing circuit 20 according to the current working state, and when it is determined that the inverter meets the voltage equalization start-up condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage equalizing circuit 20 is controlled according to the output power of the voltage equalizing circuit 20 to equalize all bus capacitors.

[0119] In some embodiments, the controller is further configured to: determine that the inverter meets the voltage balancing start-up conditions when the current working state is before grid connection and the bus voltage does not meet the rated voltage, or the current working state is a shutdown state; or determine that the inverter meets the voltage balancing start-up conditions when the current working state is an inverter state and the voltage of at least one bus capacitor is greater than a first preset voltage value and less than a second preset voltage value.

[0120] In some embodiments, the inverter also includes an auxiliary power supply unit, which is connected to multiple bus capacitors. The auxiliary power supply unit is configured to generate a DC auxiliary power supply based on the bus voltage to power the load, wherein the controller is further configured to: obtain the output power of the auxiliary power supply unit; determine the output power of the voltage equalization circuit based on the output power of the auxiliary power supply unit and the first power extraction efficiency of the auxiliary power supply unit from the bus voltage.

[0121] In some embodiments, the controller is further configured to: control the voltage equalizing circuit to equalize all bus capacitors according to the output power of the voltage equalizing circuit; when the voltage of each bus capacitor is less than or equal to a first preset voltage value, keep the output power of the voltage equalizing circuit unchanged; when the voltage of at least one bus capacitor is greater than the first preset voltage value, increase the output power of the voltage equalizing circuit according to a first preset step size, and increase the output power of the auxiliary power supply unit according to a second preset step size, wherein the first preset step size is determined based on the second preset step size and the first power extraction efficiency.

[0122] In some embodiments, the controller is further configured to: when the current working state is the inverter state, determine that the output power of the voltage balancing circuit is a preset output power.

[0123] In some embodiments, the controller is further configured to: control the voltage equalizing circuit to equalize all bus capacitors according to a preset output power, and control the input power of the inverter to decrease according to the preset output power; when the voltage of each bus capacitor is less than or equal to a first preset voltage value, keep the output power of the voltage equalizing circuit unchanged; when the voltage of at least one bus capacitor is greater than the first preset voltage value and the output power of the voltage equalizing circuit is less than or equal to a preset power threshold, increase the output power of the voltage equalizing circuit according to a third preset step size, and control the input power of the inverter to decrease according to a fourth preset step size.

[0124] In some embodiments, the controller is further configured to: after keeping the output power of the voltage equalizing circuit unchanged and when the current working state changes, increase the output power of the voltage equalizing circuit according to a third preset step size, and control the input power of the inverter to decrease according to a fourth preset step size.

[0125] In some embodiments, the controller is further configured to: when the output power of the voltage balancing circuit is greater than a preset power threshold, perform shutdown control on the inverter.

[0126] In some embodiments, the controller is further configured to: perform shutdown control on the inverter when the voltage of at least one bus capacitor is greater than or equal to a second preset voltage value.

[0127] In some embodiments, the inverter also includes an auxiliary power supply unit, which is connected to multiple bus capacitors, and the auxiliary power supply unit is configured to generate a DC auxiliary power supply based on the bus voltage to power the load, wherein the controller is further configured to: obtain the output power of the auxiliary power supply unit; determine the output power of the voltage balancing circuit based on the output power of the auxiliary power supply unit and the second power extraction efficiency of the auxiliary power supply unit from the bus voltage, wherein the output power of the voltage balancing circuit is less than or equal to the ratio of the output power of the auxiliary power supply unit to the second power extraction efficiency.

[0128] In some embodiments, the controller is further configured to: control the voltage equalizing circuit to equalize all bus capacitors according to the output power of the voltage equalizing circuit; when the voltage of each bus capacitor is less than or equal to the first preset voltage value, keep the output power of the voltage equalizing circuit unchanged; when the voltage of at least one bus capacitor is greater than the first preset voltage value, increase the output power of the voltage equalizing circuit according to a fifth preset step size, and increase the output power of the auxiliary power supply unit according to a sixth preset step size, wherein the fifth preset step size is less than or equal to the ratio of the sixth preset step size to the second power extraction efficiency.

[0129] In some embodiments, Figure 4 As shown, the voltage equalizing circuit includes a transformer and multiple output units (71 and 72), the transformer includes a primary winding Wp and multiple windings (W1 and W2), the primary winding Wp is suitable for connecting a preset DC power supply, and each output unit is connected to a secondary winding and a bus capacitor to charge the corresponding bus capacitor according to the electric energy coupled to the secondary winding.

[0130] It should be noted that the specific implementation of the inverter in the embodiment of the present invention corresponds one-to-one to the specific implementation of the bus capacitor voltage balancing method in the aforementioned embodiment of the present invention, and will not be repeated here.

[0131] According to an inverter of an embodiment of the present invention, it includes a power supply circuit, a plurality of bus capacitors, an output circuit, a voltage equalization circuit and a controller. The current working state of the inverter is determined by the controller, and the voltage of each bus capacitor is obtained. The output power of the voltage equalization circuit is determined according to the current working state. When it is determined that the inverter meets the voltage equalization start condition according to at least one of the current working state and the voltage of at least one bus capacitor, the voltage equalization circuit is controlled according to the output power of the voltage equalization circuit to equalize all bus capacitors. Thus, the output power of the voltage equalization circuit is dynamically adjusted according to the current working state of the inverter, and the voltage equalization circuit is controlled according to the current working state of the inverter and / or the voltage of each bus capacitor to perform active balancing, so that all bus capacitors reach the voltage equalization state, thereby reducing circuit losses and improving voltage equalization efficiency.

[0132] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0133] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0134] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0135] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0136] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0137] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A busbar capacitor voltage balancing method, characterized in that: Applied to an inverter, the inverter includes a power supply circuit, a plurality of bus capacitors, an output circuit and a voltage balancing circuit, the plurality of bus capacitors are connected in series and arranged between the power supply circuit and the output circuit, the voltage balancing circuit is adapted to generate a charging voltage according to a preset DC power supply to charge at least one of the bus capacitors, and the method includes: Determine the current working state of the inverter, and obtain the voltage of each bus capacitor; Determine the output power of the voltage balancing circuit according to the current working state; When it is determined that the inverter meets the voltage balancing start-up condition based on at least one of the current working state and the voltage of at least one of the bus capacitors, the voltage balancing circuit is controlled according to the output power of the voltage balancing circuit to balance the voltages of all bus capacitors.

2. The method according to claim 1, characterized in that Determining, according to at least one of the current working state and the voltage of at least one of the bus capacitors, that the inverter meets the voltage balancing start condition includes: When the current working state is before grid connection and the bus voltage does not meet the rated voltage, or the current working state is in the shutdown state, determining that the inverter meets the voltage balancing start condition; or When the current working state is the inverter state and the voltage of at least one of the bus capacitors is greater than a first preset voltage value and less than a second preset voltage value, it is determined that the inverter meets the voltage balancing start condition.

3. The method according to claim 2, characterized in that The inverter further includes an auxiliary power supply unit, the auxiliary power supply unit is connected to the multiple bus capacitors, and the auxiliary power supply unit is configured to generate a DC auxiliary power supply according to the bus voltage to supply power to the load, wherein, when the current working state is before grid connection and the bus voltage does not meet the rated voltage, the output power of the voltage balancing circuit is determined according to the current working state, including: Obtaining the output power of the auxiliary power supply unit; The output power of the voltage balancing circuit is determined according to the output power of the auxiliary power supply unit and a first power extraction efficiency of the auxiliary power supply unit in extracting power from the bus voltage.

4. The method according to claim 3, characterized in that Controlling the voltage balancing circuit according to the output power of the voltage balancing circuit includes: Controlling the voltage balancing circuit to balance the voltages of all bus capacitors according to the output power of the voltage balancing circuit; When the voltage of each of the bus capacitors is less than or equal to the first preset voltage value, the output power of the voltage balancing circuit is kept unchanged; When the voltage of at least one of the bus capacitors is greater than the first preset voltage value, the output power of the voltage equalizing circuit is increased according to a first preset step size, and the output power of the auxiliary power supply unit is increased according to a second preset step size, wherein the first preset step size is determined based on the second preset step size and the first power extraction efficiency.

5. The method according to claim 2, characterized in that: When the current working state is an inverter state, determining the output power of the voltage balancing circuit according to the current working state includes: Determine that the output power of the voltage balancing circuit is a preset output power.

6. The method according to claim 5, characterized in that Controlling the voltage balancing circuit according to the output power of the voltage balancing circuit includes: Controlling the voltage balancing circuit to balance the voltages of all bus capacitors according to the preset output power, and controlling the input power of the inverter to decrease according to the preset output power; When the voltage of each of the bus capacitors is less than or equal to the first preset voltage value, the output power of the voltage balancing circuit is kept unchanged; When the voltage of at least one of the bus capacitors is greater than the first preset voltage value and the output power of the voltage balancing circuit is less than or equal to a preset power threshold, the output power of the voltage balancing circuit is increased according to a third preset step size, and the input power of the inverter is controlled to decrease according to a fourth preset step size.

7. The method according to claim 6, characterized in that After maintaining the output power of the voltage balancing circuit unchanged, the method further includes: When the current working state changes, the output power of the voltage balancing circuit is increased according to the third preset step size, and the input power of the inverter is controlled to decrease according to the fourth preset step size.

8. The method according to claim 6, characterized in that When the output power of the voltage balancing circuit is greater than a preset power threshold, the method further includes: The inverter is shut down controlled.

9. The method according to claim 5, characterized in that In a case where the voltage of at least one of the bus capacitors is greater than or equal to the second preset voltage value, the method further includes: The inverter is shut down controlled.

10. The method according to claim 2, characterized in that The inverter further includes an auxiliary power supply unit, the auxiliary power supply unit is connected to the multiple bus capacitors, and the auxiliary power supply unit is configured to generate a DC auxiliary power supply according to the bus voltage to supply power to the load, wherein, when the current working state is a shutdown state, determining the output power of the voltage balancing circuit according to the current working state includes: Obtaining the output power of the auxiliary power supply unit; The output power of the voltage balancing circuit is determined based on the output power of the auxiliary power supply unit and the second power extraction efficiency of the auxiliary power supply unit from the bus voltage, wherein the output power of the voltage balancing circuit is less than or equal to the ratio of the output power of the auxiliary power supply unit to the second power extraction efficiency.

11. The method according to claim 10, characterized in that Controlling the voltage balancing circuit according to the output power of the voltage balancing circuit includes: Controlling the voltage balancing circuit to balance the voltages of all bus capacitors according to the output power of the voltage balancing circuit; When the voltage of each of the bus capacitors is less than or equal to the first preset voltage value, the output power of the voltage balancing circuit is kept unchanged; When the voltage of at least one of the bus capacitors is greater than the first preset voltage value, the output power of the voltage equalizing circuit is increased according to a fifth preset step size, and the output power of the auxiliary power supply unit is increased according to a sixth preset step size, wherein the fifth preset step size is less than or equal to the ratio of the sixth preset step size to the second power extraction efficiency.

12. The method according to any one of claims 1 to 11, characterized in that The voltage balancing circuit includes a transformer and multiple output units, the transformer includes a primary winding and multiple windings, the primary winding is suitable for connecting to the preset DC power supply, and each of the output units is connected to a secondary winding and a bus capacitor to charge the corresponding bus capacitor according to the electric energy coupled to the secondary winding.

13. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is processed by a processor, the bus capacitor voltage equalization method as described in any one of claims 1 to 12 is executed.

14. An electronic device, characterized in that: It includes a memory, a processor, and a bus capacitor voltage balancing control program stored in the memory and executable on the processor. When the processor executes the bus capacitor voltage balancing program, the bus capacitor voltage balancing method described in any one of claims 1 to 12 is implemented.

15. An inverter, characterized in that: include: A power supply circuit, a plurality of bus capacitors, an output circuit and a voltage balancing circuit, wherein the plurality of bus capacitors are arranged between the power supply circuit and the output circuit, and the voltage balancing circuit is adapted to generate a charging voltage according to a preset DC power supply to charge at least one of the bus capacitors; The controller is configured to determine the current working state of the inverter, obtain the voltage of each of the bus capacitors, and determine the output power of the voltage equalization circuit according to the current working state, and when it is determined that the inverter meets the voltage equalization start condition according to at least one of the current working state and the voltage of at least one bus capacitor, control the voltage equalization circuit according to the output power of the voltage equalization circuit to equalize all bus capacitors.

Images