Control method of three-level three-phase four-bridge-arm inverter and electronic equipment

Abstract

The application relates to the technical field of power electronic conversion and control, in particular to a control method of a three-level three-phase four-bridge-arm inverter and electronic equipment. The method comprises the following steps: acquiring a multi-phase first capacitor voltage and a multi-phase first inductor current; acquiring a second inductor current corresponding to a second bridge arm; determining a plurality of first modulation waves corresponding to a plurality of first bridge arms according to the multi-phase first capacitor voltage and the multi-phase first inductor current; acquiring a positive half bus voltage and a negative half bus voltage; determining a plurality of first driving signal groups corresponding to the plurality of first modulation waves according to the positive half bus voltage and the negative half bus voltage; determining a second driving signal group according to the multi-phase first capacitor voltage, the second inductor current and the plurality of first modulation waves; driving the corresponding first bridge arm according to each first driving signal group, and driving the second bridge arm according to the second driving signal group. The stability and safety of the distributed micro-grid system operation can be improved.

Description

Technical Field

[0001] This application relates to the field of power electronic conversion and control technology, and in particular to a control method and electronic equipment for a three-level three-phase four-bridge-arm inverter. Background Technology

[0002] In distributed microgrid systems, the three-level three-phase four-arm inverter is a common power electronic conversion device that can achieve bidirectional conversion between DC and AC power by controlling the switching devices.

[0003] However, the increasingly complex and variable single-phase or multi-phase unbalanced and nonlinear loads in distributed microgrid systems can easily cause asymmetry in the three-phase output current and voltage of the inverter, increase harmonic content, and lead to voltage imbalance at the bus midpoint of three-level four-arm inverters. This reduces the stability and security of the distributed microgrid system, affecting its normal operation. Summary of the Invention

[0004] This application provides a control method, device, chip, electronic equipment, and computer-readable storage medium for a three-level, three-phase, four-bridge-arm inverter. It can avoid the problem of three-phase output voltage asymmetry in distributed microgrid systems, reduce harmonic content, and balance the potential at the bus midpoint, thereby improving the stability and security of the distributed microgrid system.

[0005] In a first aspect, this application provides a control method for a three-level, three-phase, four-arm inverter, applied to an inverter comprising multi-phase arms, including a multi-phase first arm and a second arm. The method includes: acquiring the multi-phase first capacitor voltage and multi-phase first inductor current, wherein each multi-phase first arm, multi-phase first capacitor voltage, and multi-phase first inductor current corresponds one-to-one, the first capacitor voltage of each phase being the voltage across the capacitor on the corresponding first arm, and the first inductor current of each phase being the current generated in the filter inductor when the AC current on the corresponding first arm passes through the filter inductor; acquiring the second inductor current corresponding to the second arm, wherein the second inductor current is the current generated in the filter inductor when the AC current on the second arm passes through the filter inductor; and determining multiple first modulation waves corresponding to the multi-phase first arm based on the multi-phase first capacitor voltage and multi-phase first inductor current, wherein each of the multiple first modulation waves corresponds one-to-one with the multi-phase first arm. The positive and negative half-bus voltages are obtained. The positive half-bus voltage is the voltage difference between the positive bus and the neutral point in the inverter, and the negative half-bus voltage is the voltage difference between the negative bus and the neutral point in the inverter. Based on the positive and negative half-bus voltages, multiple first drive signal groups corresponding to multiple first modulation waves are determined, with each first drive signal group corresponding to one of the multiple first modulation waves. Second drive signal groups are determined based on the multi-phase first capacitor voltage, the second inductor current, and the multiple first modulation waves. The amplitude value of each second drive signal in the second drive signal group is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the multiple first modulation waves. Each first drive signal group drives the corresponding first bridge arm of one phase, and the second drive signal group drives the second bridge arm.

[0006] In some implementations, multiple first modulation waves corresponding to the multiphase first bridge arm are determined based on the multiphase first capacitor voltage and the multiphase first inductor current. This includes: using a second-order generalized integrator to determine the first positive-sequence voltage component and the second positive-sequence voltage component of the multiphase first capacitor voltage in a first preset coordinate system; using a second-order generalized integrator to determine the first positive-sequence current component and the second positive-sequence current component of the multiphase first inductor current in the first preset coordinate system; and using a proportional-integral controller to determine the multiple first modulation waves based on the first positive-sequence voltage component, the second positive-sequence voltage component, the first positive-sequence current component, and the second positive-sequence current component.

[0007] In some implementations, a proportional-integral (PI) controller is used to determine multiple first modulation waves based on a first positive-sequence voltage component, a second positive-sequence voltage component, a first positive-sequence current component, and a second positive-sequence current component. This includes: determining a first voltage difference by subtracting the first positive-sequence voltage component from a first voltage setpoint in a first preset coordinate system; determining a first inner-loop current deviation by subtracting the first positive-sequence current component from the first voltage difference using the PI controller; determining a second voltage difference by subtracting the second positive-sequence voltage component from a second voltage setpoint in the first preset coordinate system; and determining a second inner-loop current deviation by subtracting the second positive-sequence current component from the second voltage difference using the PI controller. The first and second inner-loop current deviations are then converted to a second coordinate system to obtain multiple first modulation waves.

[0008] In some implementations, determining multiple first drive signal groups corresponding to multiple first modulation waves based on the positive and negative half-bus voltages includes: determining a triangular modulation wave based on the multiple first modulation waves, wherein the amplitude of the triangular modulation wave is negatively correlated with the sum of the amplitudes of the largest and smallest modulation waves among the multiple first modulation waves; superimposing the multiple first modulation waves according to the triangular modulation wave to obtain multiple primary superimposed waves, each corresponding one-to-one with the multiple first modulation waves; determining a voltage equalization control output signal at the bus midpoint based on the positive and negative half-bus voltages; superimposing the multiple primary superimposed waves according to the voltage equalization control output signal to obtain multiple secondary superimposed waves, each corresponding one-to-one with the multiple secondary superimposed waves, the multiple primary superimposed waves, and the multi-phase first bridge arm; and performing drive signal conversion on the multiple secondary superimposed waves to obtain multiple first drive signal groups.

[0009] In some implementations, determining the voltage equalization control output signal at the bus midpoint based on the positive half-bus voltage and the negative half-bus voltage includes: determining the difference between the positive half-bus voltage and the negative half-bus voltage as a first voltage deviation; and determining the product of the first voltage deviation and a first transfer function as the voltage equalization control output signal.

[0010] In some implementations, determining the second drive signal group based on the multiphase first capacitor voltage, the second inductor current, and multiple first modulation waves includes: determining the common-mode voltage of the multiphase first capacitor voltage, wherein the common-mode voltage is positively correlated with the sum of the multiphase first capacitor voltages; determining the closed-loop compensation modulation signal of the second bridge arm based on the common-mode voltage and the second inductor current; superimposing the triangular modulation waves based on the closed-loop compensation modulation signal to obtain the second modulation signal; and performing drive signal conversion on the second modulation signal to obtain the second drive signal group.

[0011] In some implementations, determining the closed-loop compensation modulation signal for the second bridge arm based on the common-mode voltage and the second inductor current includes: determining the difference between the common-mode voltage and a preset closed-loop control voltage as a second voltage deviation; determining the product of the second voltage deviation and the second transfer function as the second bridge arm output signal; and determining the difference between the second bridge arm output signal and the second inductor current as the closed-loop compensation modulation signal.

[0012] In some embodiments, the first phase first bridge arm includes a plurality of first switches, and the first phase first bridge arm is any one phase among the multiple phase first bridge arms. The first group of first drive signals includes a plurality of first drive signals, and the first group of first drive signals is a group among the multiple groups of first drive signals corresponding to the first phase first bridge arm. Each of the plurality of first drive signals is used to control a corresponding first switch among the plurality of first switches. The second bridge arm includes a plurality of second switches, and the second drive signal group includes a plurality of second drive signals. Each of the plurality of second drive signals is used to control a corresponding second switch among the plurality of second switches.

[0013] Secondly, this application provides a control device for a three-level three-phase four-arm inverter. The control device for the three-level three-phase four-arm inverter is an inverter itself. The control device for the three-level three-phase four-arm inverter includes multi-phase arms, which include a multi-phase first arm and a second arm. The device includes:

[0014] The acquisition module is used to acquire the multiphase first capacitor voltage and multiphase first inductor current. The multiphase first bridge arm, multiphase first capacitor voltage and multiphase first inductor current are respectively one-to-one. The first capacitor voltage of each phase is the voltage across the capacitor on the corresponding first bridge arm, and the first inductor current of each phase is the current generated in the filter inductor when the AC current on the corresponding first bridge arm passes through the filter inductor.

[0015] The acquisition module is also used to acquire the second inductor current corresponding to the second bridge arm. The second inductor current is the current generated in the filter inductor when the AC current on the second bridge arm passes through the filter inductor.

[0016] The processing module is used to determine multiple first modulation waves corresponding to the first bridge arm of the multiphase based on the voltage of the first multiphase capacitor and the current of the first multiphase inductor. The multiple first modulation waves correspond one-to-one with the first bridge arm of the multiphase.

[0017] The acquisition module is also used to acquire the positive half-bus voltage and the negative half-bus voltage. The positive half-bus voltage is the voltage difference between the positive bus and the neutral point in the inverter, and the negative half-bus voltage is the voltage difference between the negative bus and the neutral point in the inverter.

[0018] The processing module is also used to determine multiple first driving signal groups corresponding to multiple first modulation waves based on the positive half bus voltage and the negative half bus voltage, with each of the multiple first driving signal groups corresponding to a multiple first modulation wave.

[0019] The processing module is also used to determine a second driving signal group based on the multiphase first capacitor voltage, the second inductor current and multiple first modulation waves, wherein the amplitude value of each second driving signal in the second driving signal group is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the multiple first modulation waves.

[0020] The driving module is used to drive a corresponding first bridge arm according to each first driving signal group, and to drive a second bridge arm according to a second driving signal group.

[0021] Thirdly, this application provides a chip for performing the methods described in any of the first aspects above.

[0022] Fourthly, this application provides an electronic device including a processor and a memory, the processor being configured to execute a computer program stored in the memory to implement the method as described in any of the first aspects above. Alternatively,

[0023] Electronic devices include chips, as described in the third aspect.

[0024] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any of the first aspects above.

[0025] In the technical solution provided in this application, the inverter can determine multiple first modulation waves corresponding to the multi-phase first bridge arm through the multi-phase first capacitor voltage and multi-phase first inductor current, and determine multiple first drive signal groups corresponding to the multiple first modulation waves based on the positive half bus voltage and negative half bus voltage. Furthermore, it determines second drive signal groups based on the multi-phase first capacitor voltage, second inductor current, and multiple first modulation waves. The amplitude value of each second drive signal in the second drive signal group is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the multiple first modulation waves. Finally, it drives the corresponding one-phase first bridge arm according to each first drive signal group, and drives the second bridge arm according to the second drive signal group. In a distributed microgrid system, when a three-level three-phase four-bridge-arm inverter carries unbalanced and nonlinear loads, it can avoid the problem of three-phase output voltage asymmetry, reduce harmonic content, and balance the potential at the bus midpoint, thereby improving the stability and safety of the distributed microgrid system. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is an inverter topology diagram of a control method for a three-level, three-phase, four-arm inverter provided in an embodiment of this application;

[0028] Figure 2 This is a flowchart illustrating a control method for a three-level, three-phase, four-arm inverter provided in an embodiment of this application.

[0029] Figure 3 This is a voltage simulation waveform diagram under unbalanced linear load conditions for a control method of a three-level three-phase four-bridge arm inverter provided in this application embodiment;

[0030] Figure 4 This is a voltage simulation waveform diagram under unbalanced nonlinear load conditions for a control method of a three-level three-phase four-bridge-arm inverter provided in this application embodiment;

[0031] Figure 5 This is a schematic diagram of the current simulation waveform under unbalanced linear load conditions for a control method of a three-level three-phase four-bridge arm inverter provided in this application embodiment;

[0032] Figure 6 This is a schematic diagram of the current simulation waveform under unbalanced nonlinear load conditions for a control method of a three-level three-phase four-bridge arm inverter provided in this application embodiment;

[0033] Figure 7 This is a schematic diagram of the structure of a second-order generalized integrator, which is part of a control method for a three-level, three-phase, four-bridge-arm inverter provided in this application embodiment.

[0034] Figure 8 This is a schematic diagram of a voltage conversion module for a control method of a three-level three-phase four-bridge-arm inverter provided in an embodiment of this application;

[0035] Figure 9 This is a schematic diagram of a current conversion module for a control method of a three-level three-phase four-arm inverter provided in this application embodiment;

[0036] Figure 10 This is a schematic diagram of the modulation wave calculation process of a control method for a three-level three-phase four-arm inverter provided in an embodiment of this application;

[0037] Figure 11This is a waveform diagram of a modulation wave for a control method of a three-level three-phase four-arm inverter provided in an embodiment of this application;

[0038] Figure 12 This is a schematic diagram of a triangular modulation wave calculation process for a control method of a three-level three-phase four-arm inverter provided in an embodiment of this application;

[0039] Figure 13 This is a schematic diagram of the drive signal calculation process for a control method of a three-level three-phase four-arm inverter provided in an embodiment of this application;

[0040] Figure 14 This is a waveform diagram of a primary superimposed wave of a control method for a three-level, three-phase, four-arm inverter provided in an embodiment of this application;

[0041] Figure 15 This is a schematic diagram of the voltage deviation waveform under an unbalanced linear load condition, which is a control method for a three-level three-phase four-arm inverter provided in this application embodiment.

[0042] Figure 16 This is a schematic diagram of the voltage deviation waveform under an unbalanced nonlinear load condition, which is a control method for a three-level three-phase four-arm inverter provided in this application embodiment.

[0043] Figure 17 This is a simulation waveform diagram of a control method for a three-level, three-phase, four-arm inverter provided in an embodiment of this application;

[0044] Figure 18 This is a schematic diagram of a signal conversion module for a control method of a three-level three-phase four-arm inverter provided in an embodiment of this application;

[0045] Figure 19 This is a schematic diagram of the structure of a control device for a three-level, three-phase, four-bridge-arm inverter provided in an embodiment of this application;

[0046] Figure 20 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0047] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0048] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0049] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0050] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0051] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0052] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0053] Inverters are crucial electronic devices in distributed microgrid systems, and the three-level, three-phase, four-arm inverter is a common type. In distributed microgrid systems, when handling unbalanced and nonlinear loads, the three-level, three-phase, four-arm inverter can avoid three-phase output voltage asymmetry, reduce harmonic content, and balance the potential at the bus midpoint, thereby improving the stability and security of the distributed microgrid system. However, three-level, three-phase, four-arm inverters often suffer from bus midpoint potential imbalance, which can lead to DC bias or distortion in the output voltage.

[0054] Traditional technical solutions utilize voltage sequence analysis to control the positive-sequence, negative-sequence, and zero-sequence voltage components in a three-level, three-phase, four-arm inverter. This yields a three-phase modulation signal, which is then used for three-dimensional space vector pulse width modulation (3D-SVPWM) to control the inverter and resolve voltage imbalance issues. However, this method suffers from high computational complexity, intricate control mechanisms, and unsatisfactory control performance.

[0055] Alternatively, in traditional technical solutions, PR (Proportional-Resonant Control) can be used to control the AC current output of a three-level, three-phase, four-arm inverter, thereby solving the voltage imbalance problem in the three-level, three-phase, four-arm inverter. However, under the complex load conditions of distributed microgrid systems, a multi-resonant quasi-PR controller is required, and its adaptability to the load and the stability of the system become challenges.

[0056] Alternatively, in traditional technical solutions, a third harmonic injection control method based on equivalent SVPWM can be used to control the three-level three-phase four-arm inverter. That is, based on the voltage and current dual closed-loop control output modulation signal, a third harmonic is injected into the three-phase arms (first, second, and third phase arms) to improve the DC voltage utilization of the three-level three-phase four-arm inverter. The fourth arm is then controlled based on the third harmonic to address voltage imbalance. However, under unbalanced nonlinear load conditions in distributed microgrid systems, this method generally has limited control effectiveness and cannot guarantee the stability of the three-level three-phase four-arm inverter.

[0057] In view of this, the present application provides a control method for a three-level three-phase four-arm inverter, which can be applied to a three-level three-phase four-arm inverter. In a distributed microgrid system with unbalanced and nonlinear loads, it can avoid the problem of three-phase output voltage asymmetry, reduce harmonic content, balance the potential of the bus midpoint, thereby improving the stability and safety of the distributed microgrid system.

[0058] The following is combined Figures 1 to 18 The examples in the document describe the technical solutions of the embodiments of this application.

[0059] The control method for a three-level, three-phase, four-arm inverter provided in this application embodiment can be applied to, for example... Figure 1The inverter shown has a topology and includes four phase arms: the first phase arm, the second phase arm, the third phase arm, and the fourth phase arm. Each phase arm includes four switches: the first phase arm includes switches Sa1, Sa2, Sa3, and Sa4; the second phase arm includes switches Sb1, Sb2, Sb3, and Sb4; the third phase arm includes switches Sc1, Sc2, Sc3, and Sc4; and the fourth phase arm includes switches Sd1, Sd2, Sd3, and Sd4.

[0060] like Figure 2 The diagram shown is a flowchart illustrating a control method for a three-level, three-phase, four-arm inverter according to an embodiment of this application, which may include the following steps:

[0061] Step S201: Obtain the first phase capacitor voltage and the first phase inductor current. The first phase bridge arm, the first phase capacitor voltage, and the first phase inductor current are respectively one-to-one. The first phase capacitor voltage is the voltage across the capacitor on the first phase bridge arm of the corresponding phase. The first phase inductor current is the current generated in the filter inductor when the AC current on the first phase bridge arm of the corresponding phase passes through the filter inductor.

[0062] See also Figure 1 In this embodiment, the multiphase first bridge arm can be a first phase bridge arm, a second phase bridge arm, and a third phase bridge arm. The multiphase first capacitor voltage can include: the capacitor voltage VinA corresponding to the first phase bridge arm, the capacitor voltage VinB corresponding to the second phase bridge arm, and the capacitor voltage VinC corresponding to the third phase bridge arm. The inductors Lfa, Lfb, and Lfc are the inductors corresponding to the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm, respectively. The multiphase first inductor current can include: the inductor current ILa corresponding to the first phase bridge arm, the inductor current ILb corresponding to the second phase bridge arm, and the inductor current ILc corresponding to the third phase bridge arm.

[0063] In this embodiment, the voltage of the multiphase first capacitor can be the output voltage of the inverter under unbalanced linear load conditions. For example, such as... Figure 3 The diagram shown illustrates a voltage simulation waveform under an unbalanced linear load condition, as provided in an embodiment of this application. Phase A, Phase B, and Phase C voltages represent the capacitor voltages corresponding to the first, second, and third phase bridge arms, respectively. Optionally, the multi-phase first capacitor voltage can also be the output voltage of the inverter under an unbalanced nonlinear load condition. For example, as... Figure 4 The diagram shown illustrates a voltage simulation waveform under an unbalanced nonlinear load condition, as provided in an embodiment of this application. The voltages of phase A, phase B, and phase C represent the capacitor voltages corresponding to the first, second, and third phase bridge arms, respectively.

[0064] The first inductor current in a multiphase system can be the output current of the inverter under unbalanced linear load conditions. For example, such as... Figure 5 The diagram shown illustrates a current simulation waveform under an unbalanced linear load condition, as provided in an embodiment of this application. The currents in phases A, B, and C represent the inductor currents corresponding to the first, second, and third phase bridge arms, respectively. Optionally, the multi-phase first inductor current can also be the output current of the inverter under an unbalanced nonlinear load condition. For example, as... Figure 6 The diagram shown is a current simulation waveform diagram under an unbalanced nonlinear load condition provided in an embodiment of this application. The currents in phases A, B, and C represent the inductor currents corresponding to the first, second, and third phase bridge arms, respectively.

[0065] Step S202: Obtain the second inductor current corresponding to the second bridge arm. The second inductor current is the current generated in the filter inductor when the AC current on the second bridge arm passes through the filter inductor.

[0066] See also Figure 1 In this embodiment of the application, the second bridge arm can be Figure 1 The fourth phase bridge arm. Inductor Lfn is the inductance corresponding to the fourth phase bridge arm, and the inductor current corresponding to the second bridge arm can be... Figure 1 ILn in.

[0067] Step S203: Based on the voltage of the first multiphase capacitor and the current of the first multiphase inductor, determine the multiple first modulation waves corresponding to the first multiphase bridge arm, and the multiple first modulation waves correspond one-to-one with the first multiphase bridge arm.

[0068] In this embodiment of the application, the method for a three-level three-phase four-arm inverter to determine multiple first modulation waves corresponding to the multi-phase first arm based on the multi-phase first capacitor voltage and the multi-phase first inductor current may include the following steps:

[0069] A1: Using a second-order generalized integrator, the first positive-sequence voltage component and the second positive-sequence voltage component of the multiphase first capacitor voltage are determined in the first preset coordinate system.

[0070] In this embodiment of the application, the first preset coordinate system can be the dq coordinate system (two-phase rotating coordinate system).

[0071] The SOGI (Second-Order Generalized Integrator) is used to generate a 90° phase shift in the multiphase first capacitor voltage (an AC sinusoidal signal), resulting in a first positive-sequence voltage component and a second positive-sequence voltage component. These first and second positive-sequence voltage components are orthogonal signals. For example, taking voltage as the input quantity... Figure 7This is a schematic diagram of a second-order generalized integrator provided in an embodiment of this application. Figure 7 As shown, the multiphase voltages Ua, Ub, and Uc (i.e., the multiphase first capacitor voltage) in the abc coordinate system (natural coordinate system or three-phase stationary coordinate system) are transformed to the αβ coordinate system (two-phase stationary coordinate system) to obtain the voltage U in the αβ coordinate system. α and voltage U β Integrating the input through a second-order generalized integrator yields the voltage U in the αβ coordinate system. α + and voltage U β + Transform the coordinate system from αβ to dq to obtain the voltage U in the dq coordinate system. d + (i.e., the first positive sequence voltage component) and voltage U q + (i.e., the second positive sequence voltage component).

[0072] Specifically, such as Figure 8 As shown, a three-level, three-phase, four-bridge inverter can input the multiphase first capacitor voltages (VinvA, VinvB, and VinvC) into a second-order generalized integrator. The second-order generalized integrator determines the positive-sequence voltage components of VinvA, VinvB, and VinvC in the dq coordinate system as VinvD. + (Positive sequence voltage component on the D-axis) and VinvQ + (Positive sequence voltage component of the Q axis).

[0073] A2: Using a second-order generalized integrator, the first positive sequence current component and the second positive sequence current component of the multiphase first inductor current are determined in the first preset coordinate system.

[0074] In this embodiment, the three-level three-phase four-arm inverter can input the multiphase first inductor currents IRa, ILb, and ILc into a second-order generalized integrator. For example,... Figure 9 As shown, a three-level, three-phase, four-bridge inverter can use a second-order generalized integrator to determine the positive-sequence current components ILa, ILb, and ILc in the dq coordinate system as IlD. + (Positive sequence current component on the D-axis) and IlQ + (Positive sequence current component on the Q axis).

[0075] A3: The difference between the first voltage quantity and the first positive sequence voltage component in the first preset coordinate system is the first voltage difference.

[0076] In this embodiment, the first positive-sequence voltage component can be the positive-sequence voltage component along the D-axis in the dq coordinate system, and the first voltage setpoint can be the voltage setpoint along the D-axis. For example, as shown... Figure 10As shown, the first voltage component can be Udref, and the first positive sequence voltage component is VinvD. + .

[0077] A4: Using a proportional-integral controller, the first voltage difference minus the first positive sequence current component is determined to be the first inner loop current deviation.

[0078] In this embodiment, the proportional-integral controller can be a PI controller. For example, see below. Figure 10 A three-level, three-phase, four-bridge inverter can measure the first voltage Udref and subtract the first positive-sequence voltage component VinvD. + The differential input to the PI controller is then compared with the output of the PI controller to the first positive sequence current component IlD. + The difference is calculated to obtain the first inner loop current deviation. This first inner loop current deviation is then used as the input for the Park inverse transformation (dq coordinate system → abc coordinate system).

[0079] A5: The difference between the second voltage setpoint and the second positive sequence voltage component in the first preset coordinate system is the second voltage difference.

[0080] In this embodiment, the second positive-sequence voltage component can be the positive-sequence voltage component of the Q-axis in the dq coordinate system, and the second voltage setpoint can be the voltage setpoint of the Q-axis. For example, see below. Figure 10 The second voltage setpoint can be Uqref, and the second positive sequence voltage component is VinvQ. + .

[0081] A6: Using a proportional-integral controller, the second voltage difference minus the second positive sequence current component is determined to be the second inner loop current deviation.

[0082] For example, see [link to example]. Figure 10 A three-level, three-phase, four-arm inverter can subtract the second positive-sequence voltage component VinvQ from the second voltage quantitative component Uqref. + The difference is input to the PI controller, and the output of the PI controller is compared with the second positive sequence current component IlQ. + The difference is calculated to obtain the second inner loop current deviation. This second inner loop current deviation is then used as the input for the inverse Park transform.

[0083] A7: Transform the first inner loop current deviation and the second inner loop current deviation to the second coordinate system to obtain multiple first modulation waves.

[0084] For example, see [link to example]. Figure 10The three-level three-phase four-bridge inverter can input the first inner loop current deviation and the second inner loop current deviation into the Park inverse converter system to obtain multiple first modulation waves UAreg, UBreg and UCreg, and the multiple first modulation waves are symmetrical modulation waves.

[0085] For example, such as Figure 11 The diagram shown is a waveform diagram of a polyphase first modulation wave UAreg, UBreg and UCreg provided in an embodiment of this application. The waveform of the first modulation wave UAreg is the wave corresponding to A, the waveform of the first modulation wave UBreg is the wave corresponding to B, and the waveform of the first modulation wave UCreg is the wave corresponding to C.

[0086] Step S204: Obtain the positive half-bus voltage and the negative half-bus voltage. The positive half-bus voltage is the voltage difference between the positive bus and the neutral point in the inverter, and the negative half-bus voltage is the voltage difference between the negative bus and the neutral point in the inverter.

[0087] In this embodiment, the three-level three-phase four-arm inverter can obtain the positive half-bus voltage and the negative half-bus voltage through a sampling circuit.

[0088] Step S205: Based on the positive half-bus voltage and the negative half-bus voltage, determine multiple first driving signal groups corresponding to multiple first modulation waves, with each of the multiple first driving signal groups corresponding to a single first modulation wave.

[0089] In this embodiment of the application, the method for determining multiple first drive signal groups corresponding to multiple first modulation waves using the positive half-bus voltage and the negative half-bus voltage in a three-level three-phase four-bridge inverter may include:

[0090] B1: Determine the triangular modulation wave based on multiple first modulation waves. The amplitude of the triangular modulation wave is negatively correlated with the sum of the amplitudes of the largest and smallest modulation waves among the multiple first modulation waves.

[0091] In this embodiment, the triangular modulation wave can be the negative of the average of the largest and smallest modulation waves among multiple first modulation waves. That is, the formula for calculating the triangular modulation wave UZreg can be:

[0092] UZreg=-(min{UAreg, UBreg, UCreg}+max{UAreg, UBreg, UCreg}) / 2;

[0093] Where min{UAreg, UBreg, UCreg} represents the maximum modulating wave among multiple first modulating waves, and max{UAreg, UBreg, UCreg} represents the minimum modulating wave among multiple first modulating waves.

[0094] For example, the method for determining the triangular modulation wave UZreg can be as follows: Figure 12 As shown. The three-level three-phase four-bridge inverter determines the negative value of the average of the maximum and minimum modulation waves as the triangular modulation wave UZreg.

[0095] B2: Multiple first modulation waves are superimposed on the triangular modulation wave to obtain multiple first superimposed waves, and the multiple first superimposed waves correspond one-to-one with the multiple first modulation waves.

[0096] For example, such as Figure 13 As shown, Figure 13 In this context, UZreg represents the triangular modulation wave, and UAreg, UBreg, and UCreg represent the first modulation waves corresponding to the first, second, and third phase arms, respectively. Adding the first modulation waves UAreg, UBreg, and UCreg to the triangular modulation wave UZreg yields multiple superimposed waves corresponding to the first, second, and third phase arms.

[0097] For example, such as Figure 14 The diagram shown is a schematic of a primary superimposed wave provided in an embodiment of this application. The primary superimposed wave corresponding to the first phase bridge arm is the wave corresponding to A, the primary superimposed wave corresponding to the second phase bridge arm is the wave corresponding to B, the primary superimposed wave corresponding to the third phase bridge arm is the wave corresponding to C, and the triangular modulation wave is the wave corresponding to N.

[0098] B3: The difference between the positive half-bus voltage and the negative half-bus voltage is defined as the first voltage deviation.

[0099] For example, see [link to example]. Figure 13 The positive half-bus voltage can be represented as UbusP, and the negative half-bus voltage can be represented as UbusN. The first voltage deviation is the difference between UbusP and UbusN.

[0100] For example, Figure 15 This application provides a schematic diagram of the waveform of the first voltage deviation under an unbalanced linear load condition, as shown in the embodiments of this application. The waveform corresponding to the positive half-bus voltage UbusP is as follows. Figure 15 The waveform shown in VbusP is followed by the waveform corresponding to the negative half-bus voltage UbusN. Figure 15 The waveform shown is VbusN. Waveforms VbusP and VbusN partially overlap. The waveform corresponding to the first voltage deviation is... Figure 15 The waveform shown in △Vbus.

[0101] For example, Figure 16 This application provides a schematic diagram of the waveform of the first voltage deviation under an unbalanced nonlinear load condition, as shown in the embodiments of this application. The waveform corresponding to the positive half-bus voltage UbusP is as follows. Figure 16 The waveform shown in VbusP is followed by the waveform corresponding to the negative half-bus voltage UbusN. Figure 16 The waveform shown is VbusN. Waveforms VbusP and VbusN partially overlap. The waveform corresponding to the first voltage deviation is... Figure 16 The waveform shown in △Vbus.

[0102] B4: Determine the product of the first voltage deviation and the first transfer function as the voltage equalization control output signal.

[0103] For example, see [link to example]. Figure 13 The three-level three-phase four-bridge inverter can determine that the product of the first voltage deviation and the first transfer function Gbus(S) is the voltage equalization control output signal Udcout. The voltage equalization control output signal is the voltage equalization control signal at the bus midpoint. In this embodiment, a base frequency and a third harmonic quasi-PR regulator can be used to achieve zero steady-state error control of the suppression of the base frequency and third harmonic components of the bus midpoint potential.

[0104] The representation function of the first transfer function Gbus(S) can be:

[0105]

[0106] Where Kp represents the proportionality coefficient, s represents the complex variable in the Laplace transform, ωc represents the response width of the resonant tuner, ω0 represents the resonant frequency, and Kr represents the resonant coefficient.

[0107] B5: Based on the voltage equalization control output signal, multiple primary superimposed waves are superimposed to obtain multiple secondary superimposed waves. The multiple secondary superimposed waves, multiple primary superimposed waves and the multiphase first bridge arm correspond one-to-one.

[0108] For example, see [link to example]. Figure 13 The voltage equalization control output signal Udcout is superimposed on the primary superposition wave corresponding to the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm, respectively, to obtain multiple secondary superposition waves UAact, UBact, and UCact.

[0109] For example, such as Figure 17 The image shown is a schematic diagram of a simulation waveform provided in an embodiment of this application. The secondary superimposed wave corresponding to the first phase bridge arm is... Figure 17 The waveform shown in phase A is the second superimposed waveform corresponding to the second phase bridge arm. Figure 17 The waveform shown in phase B, the secondary superposition wave corresponding to the third phase bridge arm is Figure 17 The waveform shown is for phase C.

[0110] B6: Perform driving signal conversion on multiple secondary superimposed waves to obtain multiple first driving signal groups.

[0111] For example, such as Figure 18 As shown, a three-level three-phase four-arm inverter can convert multiple superimposed secondary waves (analog signals) into multiple first drive signal groups (digital signals) through a digital signal simulator.

[0112] In a plurality of first drive signal groups, each first drive signal group includes a plurality of first drive signals. For example, such as Figure 18 As shown, after converting multiple superimposed secondary waves UAact, UBact, and UCact into multiple first driving signal groups, the first driving signal group corresponding to the first phase bridge arm includes first driving signal Qa1, first driving signal Qa2, first driving signal Qa3, and first driving signal Qa4. The first driving signal group corresponding to the second phase bridge arm includes first driving signal Qb1, first driving signal Qb2, first driving signal Qb3, and first driving signal Qb4. The first driving signal group corresponding to the third phase bridge arm includes first driving signal Qc1, first driving signal Qc2, first driving signal Qc3, and first driving signal Qc4.

[0113] In this embodiment, the multi-phase first bridge arm may include multiple first switches.

[0114] For example, see continue. Figure 1 The first phase bridge arm includes: first switch Sa1, first switch Sa2, first switch Sa3 and first switch Sa4; the second phase bridge arm includes: first switch Sb1, first switch Sb2, first switch Sb3 and first switch Sb4; and the third phase bridge arm includes: first switch Sc1, first switch Sc2, first switch Sc3 and first switch Sc4.

[0115] The first driving signal Qa1 can be used to control the first switch Sa1, the first driving signal Qa2 can be used to control the first switch Sa2, the first driving signal Qa3 can be used to control the first switch Sa3, and the first driving signal Qa4 can be used to control the first switch Sa4.

[0116] The first driving signal Qb1 can be used to control the first switch Sb1, the first driving signal Qb2 can be used to control the first switch Sb2, the first driving signal Qb3 can be used to control the first switch Sb3, and the first driving signal can be used to control the first switch Qb4.

[0117] The first drive signal Qc1 can be used to control the first switch Sc1, the first drive signal Qc2 can be used to control the first switch Sc2, the first drive signal Qc3 can be used to control the first switch Sc3, and the first drive signal can be used to control the first switch Qc4.

[0118] Step S206: Determine the second driving signal group based on the multiphase first capacitor voltage, the second inductor current and multiple first modulation waves. The amplitude value of each second driving signal in the second driving signal group is negatively correlated with the sum of the amplitude values ​​of the maximum and minimum modulation waves among the multiple first modulation waves.

[0119] In this embodiment of the application, the method for determining the second driving signal group based on the multiphase first capacitor voltage, the second inductor current, and multiple first modulation waves may include:

[0120] C1: Determine the common-mode voltage of the first multiphase capacitor voltage. The common-mode voltage is positively correlated with the sum of the first multiphase capacitor voltages.

[0121] In this embodiment, the common-mode voltage can be the average value of the voltages of the first multiphase capacitors.

[0122] For example, see [link to example]. Figure 13 The common-mode voltage can be Figure 13 VinCM in the middle.

[0123] C2: The difference between the common-mode voltage and the preset closed-loop control voltage is determined as the second voltage deviation.

[0124] In this embodiment, the preset closed-loop control voltage can be 0, meaning the second voltage deviation can be the same as the common-mode voltage.

[0125] C3: Determine the product of the second voltage deviation and the second transfer function, which is the output signal of the second bridge arm.

[0126] For example, see [link to example]. Figure 13 A three-level, three-phase, four-arm inverter can determine the product of the second voltage deviation and the second transfer function Gn(S) as the output signal of the second arm.

[0127] The representation of the second transfer function Gn(S) can be:

[0128]

[0129] Where Kp represents the proportional coefficient, s represents the complex variable of the Laplace transform, ωc represents the response width of the resonant tuner, ω0 represents the resonant frequency, and Kr represents the resonant coefficient.

[0130] C4: Determine the difference between the output signal of the second bridge arm and the current of the second inductor, which is the closed-loop compensation modulation signal.

[0131] For example, see Figure 13 Closed-loop compensation modulation signal such as Figure 13 As shown in UOreg, it is the difference between the output signal of the second bridge arm and the current ILn of the second inductor.

[0132] C5: The triangular modulation wave is superimposed on the closed-loop compensation modulation signal to obtain the second modulation signal.

[0133] For example, see Figure 13 The second modulation signal UNact can be obtained by superimposing the triangular modulation wave UZreg with the closed-loop compensation modulation signal UOreg.

[0134] For example, see Figure 17 The waveform of the second modulation signal UNact can be Figure 17 The waveform shown in the N-phase diagram.

[0135] C6: Perform drive signal conversion on the second modulation signal to obtain the second drive signal group.

[0136] For example, see Figure 18 The three-level three-phase four-bridge inverter can convert the second modulation signal (analog signal) into the second drive signal group (digital signal) through a digital signal simulator.

[0137] The second drive signal group includes multiple second drive signals. For example, such as... Figure 18 As shown, after the second modulation signal UNact is converted into the second drive signal group, the second drive signal group corresponding to the fourth phase bridge arm includes the second drive signal Qn1, the second drive signal Qn2, the second drive signal Qn3, and the second drive signal Qn4.

[0138] In this embodiment, the multiphase second bridge arm may include multiple second switches.

[0139] For example, see continue. Figure 1 The fourth phase bridge arm includes: second switch Sn1, second switch Sn2, second switch Sn3 and second switch Sn4.

[0140] The second drive signal Qn1 can be used to control the second switch Sn1, the second drive signal Qn2 can be used to control the second switch Sn2, the second drive signal Qn3 can be used to control the second switch Sn3, and the second drive signal Qn4 can be used to control the second switch Sn4.

[0141] Step S207: Drive the corresponding first bridge arm according to each first drive signal group, and drive the second bridge arm according to the second drive signal group.

[0142] In the technical solution provided by this application, the inverter can determine multiple first modulation waves corresponding to the multi-phase first bridge arm through the multi-phase first capacitor voltage and multi-phase first inductor current, and determine multiple first drive signal groups corresponding to the multiple first modulation waves based on the positive half bus voltage and negative half bus voltage. Furthermore, it can determine second drive signal groups based on the multi-phase first capacitor voltage, second inductor current, and multiple first modulation waves. The amplitude value of each second drive signal in the second drive signal group is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the multiple first modulation waves. Finally, it drives the corresponding one-phase first bridge arm according to each first drive signal group, and drives the second bridge arm according to the second drive signal group. In a distributed microgrid system, when a three-level three-phase four-bridge-arm inverter carries unbalanced and nonlinear loads, it can avoid the problem of three-phase output voltage asymmetry, reduce harmonic content, and balance the potential at the bus midpoint, thereby improving the stability and safety of the distributed microgrid system. In addition, the technical solution provided by this application can also reduce the computational load of driving multi-phase bridge arms.

[0143] It should be understood that, provided there are no logical conflicts, the above-described embodiments can be combined and implemented to adapt to actual application needs. These combined embodiments or implementation schemes are still within the scope of protection of this application.

[0144] Corresponding to the control method of the three-level three-phase four-arm inverter in the above embodiments, this application provides a control device 190 for a three-level three-phase four-arm inverter. The control device 190 can be an inverter, which includes multi-phase arms, including a multi-phase first arm and a second arm. The control device 190 can be implemented by software, hardware, or a combination of both as part or all of a computer device, used to execute the steps in the control method of the three-level three-phase four-arm inverter in the above embodiments.

[0145] Figure 19 This paper shows a schematic diagram of the control device for a three-level, three-phase, four-arm inverter provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0146] Reference Figure 19 The control device 190 of the three-level three-phase four-bridge inverter includes an acquisition module 1910, a processing module 1920, and a drive module 1930.

[0147] The acquisition module 1910 is used to acquire the multiphase first capacitor voltage and multiphase first inductor current. The multiphase first bridge arm, multiphase first capacitor voltage and multiphase first inductor current are respectively one-to-one. The first capacitor voltage of each phase is the voltage across the capacitor on the corresponding first bridge arm, and the first inductor current of each phase is the current generated in the filter inductor when the AC current on the corresponding first bridge arm passes through the filter inductor.

[0148] The acquisition module 1910 is also used to acquire the second inductor current corresponding to the second bridge arm. The second inductor current is the current generated in the filter inductor when the AC current on the second bridge arm passes through the filter inductor.

[0149] The processing module 1920 is used to determine multiple first modulation waves corresponding to the first bridge arm of the multiphase based on the voltage of the first multiphase capacitor and the current of the first multiphase inductor. The multiple first modulation waves correspond one-to-one with the first bridge arm of the multiphase.

[0150] The acquisition module 1910 is also used to acquire the positive half bus voltage and the negative half bus voltage. The positive half bus voltage is the voltage difference between the positive bus and the neutral point in the inverter, and the negative half bus voltage is the voltage difference between the negative bus and the neutral point in the inverter.

[0151] The processing module 1920 is also used to determine multiple first driving signal groups corresponding to multiple first modulation waves based on the positive half bus voltage and the negative half bus voltage, wherein the multiple first driving signal groups and the multiple first modulation waves correspond one-to-one.

[0152] The processing module 1920 is further configured to determine a second driving signal group based on the multiphase first capacitor voltage, the second inductor current and multiple first modulation waves, wherein the amplitude value of each second driving signal in the second driving signal group is negatively correlated with the sum of the amplitude values ​​of the maximum and minimum modulation waves among the multiple first modulation waves.

[0153] The drive module 1930 is used to drive a corresponding first bridge arm according to each first drive signal group, and to drive a second bridge arm according to a second drive signal group.

[0154] In some embodiments, the processing module 1920 is specifically used to: use a second-order generalized integrator to determine the first positive-sequence voltage component and the second positive-sequence voltage component of the multiphase first capacitor voltage in a first preset coordinate system; use a second-order generalized integrator to determine the first positive-sequence current component and the second positive-sequence current component of the multiphase first inductor current in the first preset coordinate system; and use a proportional-integral controller to determine multiple first modulation waves based on the first positive-sequence voltage component, the second positive-sequence voltage component, the first positive-sequence current component, and the second positive-sequence current component.

[0155] In some embodiments, the processing module 1920 is specifically used to: determine the difference between a first voltage setpoint and a first positive-sequence voltage component in a first preset coordinate system as a first voltage difference; use a proportional-integral controller to determine the first voltage difference minus the first positive-sequence current component as a first inner-loop current deviation; determine the difference between a second voltage setpoint and a second positive-sequence voltage component in the first preset coordinate system as a second voltage difference; use a proportional-integral controller to determine the second voltage difference minus the second positive-sequence current component as a second inner-loop current deviation; and convert the first inner-loop current deviation and the second inner-loop current deviation to a second coordinate system to obtain multiple first modulation waves.

[0156] In some embodiments, the processing module 1920 is specifically used to: determine a triangular modulation wave based on a plurality of first modulation waves, wherein the amplitude value of the triangular modulation wave is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the plurality of first modulation waves; superimpose the plurality of first modulation waves according to the triangular modulation wave to obtain a plurality of primary superimposed waves, wherein the plurality of primary superimposed waves correspond one-to-one with the plurality of first modulation waves; determine the voltage equalization control output signal at the bus midpoint based on the positive half-bus voltage and the negative half-bus voltage; superimpose the plurality of primary superimposed waves according to the voltage equalization control output signal to obtain a plurality of secondary superimposed waves, wherein the plurality of secondary superimposed waves, the plurality of primary superimposed waves, and the multi-phase first bridge arm correspond one-to-one; and convert the plurality of secondary superimposed waves into drive signals to obtain a plurality of first drive signal groups.

[0157] In some implementations, the processing module 1920 is specifically used to: determine the difference between the positive half-bus voltage and the negative half-bus voltage as a first voltage deviation; and determine the product of the first voltage deviation and a first transfer function as the voltage equalization control output signal.

[0158] In some embodiments, the processing module 1920 is specifically used to: determine the common-mode voltage of the multiphase first capacitor voltage, wherein the common-mode voltage is positively correlated with the sum of the multiphase first capacitor voltages; determine the closed-loop compensation modulation signal of the second bridge arm based on the common-mode voltage and the second inductor current; superimpose the triangular modulation wave based on the closed-loop compensation modulation signal to obtain the second modulation signal; and perform drive signal conversion on the second modulation signal to obtain the second drive signal group.

[0159] In some implementations, the processing module 1920 is specifically used to: determine the difference between the common-mode voltage and the preset closed-loop control voltage as a second voltage deviation; determine the product of the second voltage deviation and the second transfer function as the second bridge arm output signal; and determine the difference between the second bridge arm output signal and the second inductor current as the closed-loop compensation modulation signal.

[0160] In some embodiments, the first phase first bridge arm includes a plurality of first switches, and the first phase first bridge arm is any one phase among the multiple phase first bridge arms. The first group of first drive signals includes a plurality of first drive signals, and the first group of first drive signals is a group among the multiple groups of first drive signals corresponding to the first phase first bridge arm. The drive module 1930 is specifically used to: control the corresponding first switch among the plurality of first drive signals for each of the plurality of first drive signals. The second bridge arm includes a plurality of second switches, and the second drive signal group includes a plurality of second drive signals. Each of the plurality of second drive signals is used to control the corresponding second switch among the plurality of second switches.

[0161] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0162] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0163] Based on the same inventive concept, embodiments of this application also provide an electronic device.

[0164] Figure 20 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 20 As shown, the electronic device 200 of this embodiment includes: at least one processor 2010 ( Figure 20 Only one is shown in the diagram. The processor 2010 contains a memory 2020 and a communication module 2040. The memory 2020 stores a computer program 2030 that may run on the processor 2010. When the processor 2010 executes the computer program 2030, it implements the steps in the control method embodiment for the three-level three-phase four-arm inverter described above, for example... Figure 3 Steps S301 to S305 are shown. Alternatively, when processor 2010 executes computer program 2030, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 8 The functions of modules 810 to 820 are shown. The communication module 2040 can be a separate communication unit used to communicate with external servers or terminal devices.

[0165] Electronic device 200 may include, but is not limited to, a processor 2010 and a memory 2020. Those skilled in the art will understand that... Figure 20This is merely an example of electronic device 200 and does not constitute a limitation on electronic device 200. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 200 may also include input transmitting devices, network access devices, buses, etc.

[0166] The processor 2010 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0167] In some embodiments, memory 2020 may be an internal storage unit of electronic device 200, such as a hard disk or memory of electronic device 200. Memory 2020 may also be an external storage device of electronic device 200, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on electronic device 200. Memory 2020 may also include both internal and external storage units of electronic device 200. Memory 2020 is used to store operating system, applications, bootloader, data, and other programs, such as the program code of computer program 2030. Memory 2020 may also be used to temporarily store data that has been sent or will be sent.

[0168] Furthermore, those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. In the various embodiments of this application, each functional unit can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0169] This application provides a computer-readable storage medium storing a computer program that, when run on an electronic device, causes the electronic device to perform the steps described in the various method embodiments above.

[0170] This application provides a chip, which includes a processor and a memory. The memory stores a computer program, which, when executed by the processor, implements the steps in the various method embodiments described above.

[0171] This application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the steps described in the various method embodiments above.

[0172] It should be understood that the processor mentioned in the embodiments of this application can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0173] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0174] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0175] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0176] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0177] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0178] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0179] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0180] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a large-screen device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0181] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A control method for a three-level, three-phase, four-bridge-arm inverter, characterized in that, Applied to an inverter, the inverter including a multi-phase bridge arm, the multi-phase bridge arm including a multi-phase first bridge arm and a second bridge arm, the method includes: The first phase capacitor voltage and the first phase inductor current are obtained. The first phase bridge arm, the first phase capacitor voltage and the first phase inductor current are respectively one-to-one. The first phase capacitor voltage is the voltage across the capacitor on the first phase bridge arm of the corresponding phase. The first phase inductor current is the current generated in the filter inductor when the AC current on the first phase bridge arm of the corresponding phase passes through the filter inductor. Obtain the second inductor current corresponding to the second bridge arm. The second inductor current is the current generated in the filter inductor when the AC current on the second bridge arm passes through the filter inductor. Based on the multiphase first capacitor voltage and the multiphase first inductor current, a plurality of first modulation waves corresponding to the multiphase first bridge arm are determined. The plurality of first modulation waves correspond one-to-one with the multiphase first bridge arm. The plurality of first modulation waves are symmetrical modulation waves. Obtain the positive half-bus voltage and the negative half-bus voltage, wherein the positive half-bus voltage is the voltage difference between the positive bus and the neutral point in the inverter, and the negative half-bus voltage is the voltage difference between the negative bus and the neutral point in the inverter; Based on the positive half-bus voltage and the negative half-bus voltage, a plurality of first driving signal groups corresponding to the plurality of first modulation waves are determined, and the plurality of first driving signal groups and the plurality of first modulation waves correspond one-to-one; The step of determining the plurality of first driving signal groups corresponding to the plurality of first modulation waves based on the positive half-bus voltage and the negative half-bus voltage includes: A triangular modulation wave is determined based on the plurality of first modulation waves. The amplitude value of the triangular modulation wave is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the plurality of first modulation waves. The triangular modulation wave is the negative of the average of the largest and smallest modulation waves among the plurality of first modulation waves. The multiple first modulation waves are superimposed on the triangular modulation wave to obtain multiple first superimposed waves, and the multiple first superimposed waves correspond one-to-one with the multiple first modulation waves. The voltage equalization control output signal at the midpoint of the busbar is determined based on the positive half-busbar voltage and the negative half-busbar voltage. The multiple primary superimposed waves are superimposed according to the equalization control output signal to obtain multiple secondary superimposed waves. The multiple secondary superimposed waves, the multiple primary superimposed waves and the multiphase first bridge arm are respectively in one-to-one correspondence. The plurality of superimposed secondary waves are respectively converted into driving signals to obtain the plurality of first driving signal groups; A second driving signal group is determined based on the multiphase first capacitor voltage, the second inductor current, and the plurality of first modulation waves. The amplitude value of each second driving signal in the second driving signal group is negatively correlated with the sum of the amplitude values ​​of the largest and smallest modulation waves among the plurality of first modulation waves. Drive a corresponding first bridge arm according to each of the first drive signal groups, and drive the second bridge arm according to the second drive signal groups; The first phase first bridge arm includes multiple first switches, and the first phase first bridge arm is any one of the multiple phase first bridge arms. The first group of first drive signal groups includes multiple first drive signals, and the first group of first drive signal groups is a group of multiple first drive signal groups that corresponds to the first phase first bridge arm. Each of the plurality of first driving signals is used to control the corresponding first switch among the plurality of first switches; The second bridge arm includes a plurality of second switches, and the second drive signal group includes a plurality of second drive signals; Each of the plurality of second driving signals is used to control the corresponding second switch among the plurality of second switches.

2. The control method for a three-level, three-phase, four-bridge-arm inverter according to claim 1, characterized in that, The step of determining the multiple first modulation waves corresponding to the multiphase first bridge arm based on the multiphase first capacitor voltage and the multiphase first inductor current includes: A second-order generalized integrator is used to determine the first positive-sequence voltage component and the second positive-sequence voltage component of the multiphase first capacitor voltage in a first preset coordinate system. The second-order generalized integrator is used to determine the first positive-sequence current component and the second positive-sequence current component of the multiphase first inductor current in the first preset coordinate system. A proportional-integral controller is used to determine the plurality of first modulation waves based on the first positive sequence voltage component, the second positive sequence voltage component, the first positive sequence current component, and the second positive sequence current component.

3. The control method for a three-level, three-phase, four-bridge-arm inverter according to claim 2, characterized in that, The method employs a proportional-integral controller to determine the plurality of first modulation waves based on the first positive-sequence voltage component, the second positive-sequence voltage component, the first positive-sequence current component, and the second positive-sequence current component, including: The difference between the first voltage quantity and the first positive sequence voltage component in the first preset coordinate system is determined as the first voltage difference; Using the proportional-integral controller, the first voltage difference minus the first positive-sequence current component is determined to be the first inner-loop current deviation; The difference between the second voltage setpoint and the second positive sequence voltage component in the first preset coordinate system is determined as the second voltage difference; Using the proportional-integral controller, the second voltage difference minus the second positive-sequence current component is determined to be the second inner-loop current deviation; The first inner loop current deviation and the second inner loop current deviation are transformed to the second coordinate system to obtain the plurality of first modulation waves.

4. The control method for a three-level, three-phase, four-bridge-arm inverter according to claim 1, characterized in that, The step of determining the voltage equalization control output signal at the midpoint of the bus based on the positive half-bus voltage and the negative half-bus voltage includes: The difference between the positive half-bus voltage and the negative half-bus voltage is defined as the first voltage deviation. The product of the first voltage deviation and the first transfer function is determined as the voltage equalization control output signal.

5. The control method for a three-level, three-phase, four-bridge-arm inverter according to claim 1, characterized in that, The step of determining the second drive signal group based on the multiphase first capacitor voltage, the second inductor current, and the plurality of first modulation waves includes: Determine the common-mode voltage of the multiphase first capacitor voltage, wherein the common-mode voltage is positively correlated with the sum of the multiphase first capacitor voltages; The closed-loop compensation modulation signal of the second bridge arm is determined based on the common-mode voltage and the second inductor current. The triangular modulation wave is superimposed on the closed-loop compensation modulation signal to obtain the second modulation signal; The second modulation signal is converted into a driving signal to obtain the second driving signal group.

6. The control method for a three-level, three-phase, four-bridge-arm inverter according to claim 5, characterized in that, The step of determining the closed-loop compensation modulation signal of the second bridge arm based on the common-mode voltage and the second inductor current includes: The difference between the common-mode voltage and the preset closed-loop control voltage is determined as the second voltage deviation; The product of the second voltage deviation and the second transfer function is determined as the output signal of the second bridge arm; The difference between the output signal of the second bridge arm and the current of the second inductor is determined as the closed-loop compensation modulation signal.

7. An electronic device, characterized in that, It includes a processor and a memory, the processor being configured to execute a computer program stored in the memory to implement the method as described in any one of claims 1-6 above.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-6 above.

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