Scanning window signal generating circuit

Abstract

The invention provides a scanning window signal generating circuit, which comprises an oscillator for generating an oscillation signal; the scanning logic module is used for generating a plurality of scanning window signals based on the oscillation signals and feeding back the scanning window signals to the oscillator, so that the length of one oscillation period of the oscillation signal generated by the oscillator in the scanning window of each scanning window signal is a corresponding preset time length; the length of the scanning window of each scanning window signal is equal to the corresponding preset duration, and the scanning window of each scanning window signal corresponds to one oscillation period of the oscillation signal. Therefore, the lengths of the scanning windows of various scanning window signals can be flexibly set, and the circuit design complexity is reduced.

Description

[Technical field]

[0001] The invention relates to the field of circuit design, and in particular to a scanning window signal generating circuit. [Background technology]

[0002] The battery protection chip needs to have the lowest possible power consumption. One solution is to perform various protection tests through intermittent scanning to achieve low average power consumption. For the control of intermittent scanning, the current situation is to use the basic clock CLK output by the oscillator to perform combinational timing logic, and the scanning window length of different protection functions needs to be set to an integer multiple of 1 / 2 cycle of the basic clock CLK.

[0003] Figure 1 The following is a block diagram of the existing scanning window signal generation circuit. Figure 1 As shown, the scan window signal generating circuit includes an oscillator OSC and a scan logic module SCAN_LOGIC. The oscillator OSC outputs a basic clock signal CLK, and the scan logic module SCAN_LOGIC generates various scan window signals SCAN_WINDOW1-n based on the basic clock CLK.

[0004] Figure 2 The internal circuit diagram of an oscillator OSC is shown in FIG.

[0005] The current source ibias provides a charging current, and uses the charging current to charge the first connection terminal RAMP of the charging capacitor C. The comparator CMP compares the voltage of the first connection terminal RAMP of the charging capacitor C with the reference voltage VREF, and outputs a comparison signal CMPO as a control signal of the discharge switch SW. The discharge switch SW is connected between the first connection terminal RAMP of the charging capacitor C and the second voltage terminal VSS. When the discharge switch SW is turned on, the capacitor C is discharged. When the discharge switch SW is turned off, the charging current charges the capacitor C. The voltage signal of the first connection terminal RAMP of the charging capacitor C is the oscillation signal, and one charging and discharging process is one oscillation cycle.

[0006] Specifically, the charging capacitor C is charged through the current source ibias. When the voltage of the first connection terminal RAMP of the charging capacitor C exceeds the reference voltage VREF, the comparator CMP outputs a high-potential comparison signal CMPO, and the discharge switch SW is turned on to discharge the charging capacitor C, and pull the voltage of the first connection terminal RAMP of the charging capacitor C back to VSS. Since the voltage of RAMP is lower than VREF, CMPO becomes low, the discharge switch SW is turned off, and the charging capacitor C continues to be charged, starting the next oscillation cycle. Since the comparison signal CMPO is a square wave signal with a very small duty cycle, a frequency division circuit is used in the oscillator OSC to divide the comparison signal CMPO by two, so that a basic clock signal CLK with a duty cycle of 50% can be generated. Figure 2 The frequency division module is not shown.

[0007] Figure 3 for Figure 1 and Figure 2 Waveform diagram of each signal in FIG. It can be seen that half of the clock period of the basic clock CLK is equal to one period of the oscillation signal RAMP, and the scanning window of the scanning window signal SCAN_WINDOW is aligned with the transition edge of the basic clock CLK. Therefore, the width of the scanning window of the scanning window signal SCAN_WINDOW is an integer multiple of the period of the oscillation signal RAMP. Different integer multiples are designed for the scanning window of the scanning window signal SCAN_WINDOW according to the requirements of different scanning functions.

[0008] The above approach makes the scanning window of the scanning window signal SCAN_WINDOW include one or more flip edges of the basic clock, and the scanning window corresponds to the working time period of the analog circuit. This requires special consideration in the layout of the signal routing and power distribution to prevent the digital signal from interfering with the analog signal; and to intentionally distinguish the digital circuit power supply from the analog circuit power supply during circuit design. These processes will increase the design complexity and production cost at the same time.

[0009] Therefore, it is necessary to propose an improved technical solution to overcome the above problems. [Summary of the invention]

[0010] One of the purposes of the present invention is to provide a scanning window signal generating circuit, which can flexibly set the length of the scanning window of various scanning window signals and reduce the complexity of circuit design.

[0011] According to one aspect of the present invention, the present invention provides a scanning window signal generating circuit, which includes: an oscillator, which generates an oscillation signal; a scanning logic module, which generates multiple scanning window signals based on the oscillation signal, and feeds the scanning window signal back to the oscillator, so that the length of an oscillation cycle of the oscillation signal generated by the oscillator in the scanning window of each scanning window signal is the corresponding predetermined time length, thereby making the length of the scanning window of each scanning window signal equal to the corresponding predetermined time length, wherein the scanning window of each scanning window signal corresponds to an oscillation cycle of the oscillation signal.

[0012] In one embodiment, the scanning windows of different scanning window signals are non-overlapping, the scanning window of the scanning window signal is a high level or a low level, the non-scanning window part of the scanning window signal is a low level or a high level, the length of the oscillation period corresponding to the scanning window of each scanning window signal is equal to the length of the scanning window of the scanning window signal, the lengths of the scanning windows of at least two scanning window signals are different, and the lengths of the oscillation periods corresponding to the scanning windows of at least two scanning window signals are different.

[0013] In one embodiment, the oscillator determines the oscillation period of the oscillation signal based on the charging current, the charging capacitance, and the reference voltage, and one or more of the charging current, the charging capacitance, and the reference voltage are adjustable. The oscillator adjusts the oscillation period of the oscillation signal by adjusting one or more of the charging current, the charging capacitance, and the reference voltage. At the beginning of a scanning window of each scanning window signal, the oscillator adjusts one or more of the charging current, the charging capacitance, and the reference voltage to a set of predetermined values ​​corresponding to the scanning window of the scanning window signal, so that in the scanning window of each scanning window signal, the length of the oscillation period of the oscillation signal is the corresponding predetermined time length, the lengths of the scanning windows of at least two scanning window signals are different, and the lengths of the oscillation periods corresponding to the scanning windows of at least two scanning window signals are different.

[0014] Compared with the prior art, the present invention changes the oscillation period of the oscillator and uses the oscillation period as the length of the scanning window of the corresponding scanning window signal. In this way, the length of the scanning window of various scanning window signals can be flexibly set, thereby reducing the complexity of circuit design.

Brief Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0016] Figure 1 It is a structural block diagram of an existing scanning window signal generating circuit;

[0017] Figure 2 It is a schematic diagram of the internal circuit of an oscillator OSC;

[0018] Figure 3 for Figure 1 and Figure 2 Schematic diagram of the waveform of each signal in;

[0019] Figure 4 is a structural block diagram of a scanning window signal generating circuit in one embodiment of the present invention;

[0020] Figure 5 for Figure 4 An internal circuit diagram of an oscillator OSC in one embodiment; and

[0021] Figure 6 for Figure 4 and Figure 5 Schematic diagram of the waveform of each signal in . [Specific implementation method]

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0024] The present invention provides a scanning window signal generating circuit, which changes the oscillation period of an oscillator and uses the oscillation period as the length of the scanning window of the corresponding scanning window signal, so that the length of the scanning window of various scanning window signals can be flexibly set, thereby reducing the complexity of circuit design.

[0025] Figure 4 FIG. 1 is a structural block diagram of a scanning window signal generating circuit in one embodiment of the present invention. Figure 5 for Figure 4 The internal circuit diagram of the oscillator OSC in one embodiment, Figure 6 for Figure 4 and Figure 5 Schematic diagram of the waveform of each signal in .

[0026] like Figure 4As shown, the scan window signal generating circuit includes: an oscillator OSC and a scan logic module SCAN_LOGIC. The oscillator generates an oscillation signal RAMP. The scan logic module generates a plurality of scan window signals SCAN_WINDOW1 to SCAN_WINDOW n based on the oscillation signal, where n is a natural number greater than or equal to 2. The scan logic module feeds back the scan window signals SCAN_WINDOW1 to SCAN_WINDOW n to the oscillator, so that the length of an oscillation cycle of the oscillation signal generated by the oscillator in the scan window of each scan window signal is the corresponding predetermined time length, thereby making the length of the scan window of each scan window signal equal to the corresponding predetermined time length, wherein the scan window of each scan window signal corresponds to an oscillation cycle of the oscillation signal, that is, the length (or duration) of the scan window of each scan window signal is equal to the length (or duration) of the corresponding oscillation cycle. As shown Figure 6 As shown, the scan window signal SCAN_WINDOW1 corresponds to an oscillation period T1 of the oscillation signal, the scan window signal SCAN_WINDOW2 corresponds to an oscillation period T2 of the oscillation signal, and the scan window signal SCAN_WINDOWn corresponds to an oscillation period Tn of the oscillation signal, and the lengths of the oscillation periods of the oscillation signals corresponding to the respective scan window signals SCAN_WINDOW1-n are different. Of course, in some embodiments, two or more scan window signals may correspond to the same length of the oscillation period of the oscillation signal as required. In any case, the lengths of the scan windows of at least two scan window signals are different, that is, the lengths of the oscillation periods corresponding to the scan windows of at least two scan window signals are different, and the predetermined durations corresponding to the oscillation periods corresponding to the scan windows of at least two scan window signals are different.

[0027] like Figure 6 As shown, the scanning windows of different scanning window signals are non-overlapping, the scanning windows of the scanning window signals SCAN_WINDOW1-n are at a high level, and the non-scanning window part of the scanning window signals is at a low level. In other embodiments, the scanning windows of the scanning window signals SCAN_WINDOW1-n may also be at a low level, and the non-scanning window part of the scanning window signals is at a high level.

[0028] The oscillator determines the oscillation period of the oscillation signal RAMP based on the charging current, the charging capacitor C, and the reference voltage VREF. One or more of the charging current, the charging capacitor, and the reference voltage are adjustable. The oscillator adjusts the oscillation period of the oscillation signal by adjusting one or more of the charging current, the charging capacitor, and the reference voltage. Figure 5In the embodiment shown, the charging current is adjustable. In other embodiments, the charging capacitor or the reference voltage may be set to be adjustable, or two or three of the charging current, the charging capacitor, and the reference voltage may be set to be adjustable.

[0029] At the beginning of the scanning window of each scanning window signal, that is, at the rising edge of the scanning window of each scanning window signal, the oscillator adjusts one or more of the charging current, charging capacitance, and reference voltage to a set of predetermined values ​​corresponding to the scanning window of the scanning window signal (for example, the charging current is a predetermined current value corresponding to the scanning window of the scanning window signal, the charging capacitance is a predetermined capacitance value corresponding to the scanning window of the scanning window signal, and the reference voltage is a predetermined reference voltage value corresponding to the scanning window of the scanning window signal), so that in the scanning window of each scanning window signal, the length of the oscillation period of the oscillation signal is the corresponding predetermined duration. Figure 5 In the example shown, at the beginning of the scanning window of each scanning window signal, the oscillator adjusts the charging current to the predetermined current value corresponding to the scanning window of the scanning window signal, so that the length of the scanning window of each scanning window signal is the corresponding predetermined duration. The different groups of predetermined values ​​corresponding to the scanning windows of different scanning window signals may be different, so that the lengths of the corresponding oscillation cycles may be different, that is, the lengths of the oscillation cycles of the oscillation signals may be different corresponding predetermined durations.

[0030] like Figure 5 As shown, the oscillator includes a discharge switch SW, a comparator CMP, a current source ibias and a charging capacitor C. The current source ibias provides the charging current, and uses the charging current to charge the first connection terminal RAMP of the charging capacitor C. The comparator CMP compares the voltage RAMP of the first connection terminal of the charging capacitor C with the reference voltage VREF, and outputs a comparison signal CMPO as a control signal of the discharge switch SW, and the discharge switch SW is connected to the first connection terminal of the charging capacitor C. When the discharge switch SW is turned on, the charging capacitor C is discharged, and when the discharge switch SW is turned off, the charging current charges the charging capacitor C. The voltage signal RAMP of the first connection terminal of the charging capacitor C is the oscillation signal, and one charging and discharging process is one oscillation cycle. The other end of the discharge switch SW is connected to the second voltage terminal VSS, and the first voltage terminal VCC supplies power to the current source.

[0031] Specifically, the charging capacitor C is charged by the current source ibias. When the voltage of the first connection terminal RAMP of the charging capacitor C exceeds the reference voltage VREF, the comparator CMP outputs a high-potential comparison signal CMPO, and the discharge switch SW is turned on to discharge the charging capacitor C, and pull the voltage of the first connection terminal RAMP of the charging capacitor C back to VSS. Since the voltage of RAMP is lower than VREF, CMPO becomes low, the discharge switch SW is turned off, and the charging capacitor C continues to be charged, and the next oscillation cycle begins.

[0032] It can be seen that the oscillation period of the oscillation signal can be adjusted by adjusting one or more of the charging current, the charging capacitor, and the reference voltage.

[0033] In a specific embodiment, the charging capacitor includes a plurality of charging capacitor unit groups connected in parallel, each charging capacitor unit group includes a charging capacitor unit and a control switch, and the capacitance value of the charging capacitor is reduced by disconnecting the control switches in one or more charging capacitor unit groups, and the capacitance value of the charging capacitor is increased by turning on the control switches in one or more charging capacitor unit groups.

[0034] like Figure 6 As shown, the oscillator OSC generates a clock signal CLK based on the comparison signal CMPO or the oscillation signal RAMP, and each clock cycle of the clock signal CLK includes two oscillation cycles. The oscillation cycle of the oscillation signal RAMP or the cycle of the comparison signal CMPO is variable, and the clock cycle of the clock signal CLK is also variable. The predetermined duration corresponding to the oscillation cycle of the oscillation signal RAMP is also variable.

[0035] The scanning logic module sets the timing of the scanning windows of each scanning window signal based on the clock signal CLK, and sets the scanning period of each scanning window signal. For example, the scanning window of the scanning window signal SCAN_WINDOW1 appears first, then the scanning window of the scanning window signal SCAN_WINDOW2 appears, and finally the scanning window of the scanning window signal SCAN_WINDOWn appears. The scanning period of the scanning window signal refers to how long it takes for a scanning window to appear.

[0036] In the present invention, the oscillation period of the oscillator can be changed according to the requirements of different detection functions, and this period is used as the length of the scanning window of the scanning window signal of the corresponding detection function. In this way, the length of the scanning window of various scanning window signals can be flexibly set, and is no longer limited to an integer multiple of half the period of the constant basic clock, which also reduces the complexity of circuit design and chip area, and reduces the purpose of design risk and production cost.

[0037] In the present invention, words such as "connect", "connected", "connect", "coupled", "interconnected" and the like indicating electrical connection, unless otherwise specified, indicate direct or indirect electrical connection. The direct electrical connection indicates a direct connection between two or more objects without any intervening objects, and the indirect electrical connection indicates an electrical connection between two or more objects with one or more objects (such as electrical components or electrical units such as resistors, capacitors, inductors, switches, filters, etc.) intervening.

[0038] It should be noted that any changes made by those skilled in the art to the specific embodiments of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the above specific embodiments.

Claims

1. A scanning window signal generating circuit, characterized in that: It includes: an oscillator that generates an oscillation signal; and A scanning logic module generates multiple scanning window signals based on the oscillation signal, and feeds the scanning window signals back to the oscillator, so that the length of an oscillation cycle of the oscillation signal generated by the oscillator in the scanning window of each scanning window signal is equal to the corresponding predetermined time length, thereby making the length of the scanning window of each scanning window signal equal to the corresponding predetermined time length, wherein the scanning window of each scanning window signal corresponds to an oscillation cycle of the oscillation signal.

2. The scanning window signal generating circuit according to claim 1, characterized in that: The scanning windows of different scanning window signals do not overlap. The length of the scanning window of each scanning window signal is equal to the length of the corresponding oscillation period. The lengths of the scanning windows of at least two scanning window signals are different, the lengths of the oscillation periods corresponding to the scanning windows of at least two scanning window signals are different, and the predetermined time lengths corresponding to the oscillation periods corresponding to the scanning windows of at least two scanning window signals are different, The scanning window of the scanning window signal is at a high level or a low level, and the non-scanning window part of the scanning window signal is at a low level or a high level.

3. The scanning window signal generating circuit according to claim 1, characterized in that: The oscillator determines the oscillation period of the oscillation signal based on a charging current, a charging capacitor, and a reference voltage, one or more of the charging current, the charging capacitor, and the reference voltage are adjustable, and the oscillator adjusts the oscillation period of the oscillation signal by adjusting one or more of the charging current, the charging capacitor, and the reference voltage. At the beginning of a scanning window of each scanning window signal, the oscillator adjusts one or more of the charging current, the charging capacitance, and the reference voltage to a set of predetermined values ​​corresponding to the scanning window of the scanning window signal, so that at the scanning window of each scanning window signal, the length of the oscillation period of the oscillation signal is the corresponding predetermined time length, The lengths of the scanning windows of at least two scanning window signals are different, and the lengths of the oscillation periods corresponding to the scanning windows of at least two scanning window signals are different.

4. The scanning window signal generating circuit according to claim 3, characterized in that: The oscillator includes a discharge switch, a comparator, a current source and a charging capacitor. The current source provides the charging current, and uses the charging current to charge the first connection terminal of the charging capacitor, The comparator compares the voltage of the first connection terminal of the charging capacitor with the reference voltage, and outputs a comparison signal as a control signal of the discharge switch. The discharge switch is connected to the first connection terminal of the charging capacitor. When the discharge switch is turned on, the charging capacitor is discharged. When the discharge switch is turned off, the charging current charges the charging capacitor. The voltage signal of the first connection terminal of the charging capacitor is the oscillation signal. One charge and discharge process is one oscillation cycle. The oscillation period of the oscillation signal can be adjusted by adjusting one or more of the charging current, the charging capacitor, and the reference voltage.

5. The scanning window signal generating circuit according to claim 4, characterized in that: The other end of the discharge switch is connected to the second voltage terminal VSS, and the first voltage terminal VCC supplies power to the current source.

6. The scanning window signal generating circuit according to claim 4, characterized in that: The charging capacitor includes a plurality of charging capacitor unit groups connected in parallel, each charging capacitor unit group includes a charging capacitor unit and a control switch, and the capacitance value of the charging capacitor is reduced by disconnecting the control switches in one or more charging capacitor unit groups, and the capacitance value of the charging capacitor is increased by turning on the control switches in one or more charging capacitor unit groups.

7. The scanning window signal generating circuit according to claim 4, characterized in that: The oscillator generates a clock signal based on the comparison signal or the oscillation signal, each clock cycle of the clock signal includes two oscillation cycles, and the scanning logic module sets the timing of the scanning windows of each scanning window signal and sets the scanning cycle of each scanning window signal based on the clock signal.

Images