SYSREF circuit with programmable fine tuning delay

Abstract

The invention provides an SYSREF circuit with programmable fine-tuning delay, which relates to the technical field of clock synchronization and comprises an output channel frequency divider, an SYSREF frequency divider, a programmable delay module and a plurality of drivers, the output channel frequency divider and the SYSREF frequency divider are both used for carrying out frequency division processing on a voltage-controlled oscillator signal fvco; the output channel frequency divider and the SYSREF frequency divider are reset through reset pulses, so that phase alignment of output signals of the output channel frequency divider and the SYSREF frequency divider is realized; the output end of the output channel frequency divider is connected with the first driver, and the first driver outputs a system main clock DCLK; the output end of the SYSREF frequency divider outputs a pair of differential signals to be connected with the input end of the programmable delay module, and the output end of the programmable delay module is connected with the input end of the second driver. The method has the advantage of solving the problem that a tiny phase difference still exists after the master clock and the reference clock of the system are synchronized.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and in particular to a SYSREF circuit with programmable fine-tuning delay. Background Art

[0002] With the development of communication technology, the signal transmission rate has been greatly improved, and industrial applications and consumer needs have put forward higher requirements for communication technology. Serial communication technology has gradually become the main mode of data communication in ultra-high-speed data transmission applications due to its higher transmission rate, lower noise and stronger anti-interference ability.

[0003] In large data transceiver systems, devices such as AD, DA, and FPGA usually require multiple clock distributors to provide the system master clock (DCLK). The clock distributors all require a system reference signal SYSREF clock (SCLK) to synchronize with the system master clock (DCLK). After each clock distributor is synchronized using the system reference signal SYSREF clock (SCLK), there is still a slight phase difference between different clock distributors, resulting in an uncertain phase relationship. This will undoubtedly complicate the connection of the clock tree network and make clock signal synchronization more difficult.

[0004] Therefore, the circuit needs to be optimized to solve the problem that there is still a slight phase difference between the system master clock and the reference clock after synchronization. Summary of the invention

[0005] The object of the present invention is to provide a SYSREF circuit with programmable fine-tuning delay, which can solve the problem that a system master clock (DCLK) and a reference clock (SCLK) still have a slight phase difference after synchronization.

[0006] The present invention is achieved through the following technical solutions:

[0007] A SYSREF circuit with programmable fine-tuning delay includes an output channel divider, a SYSREF divider, a programmable delay module, and a plurality of drivers;

[0008] The output channel divider and the SYSREF divider are both used to divide the voltage controlled oscillator signal f vcoPerform frequency division processing; the output channel frequency divider and the SYSREF frequency divider are both reset by a reset pulse to achieve phase alignment of the output signals of the output channel frequency divider and the SYSREF frequency divider; the output end of the output channel frequency divider is connected to a first driver, and the first driver outputs a system master clock DCLK; the output end of the SYSREF frequency divider outputs a pair of differential signals CLKP and CLKN and is connected to the input end of the programmable delay module, the output end of the programmable delay module is connected to the input end of a second driver, and the second driver outputs a system reference signal SYSREF clock SCLK synchronized with the system master clock DCLK;

[0009] The programmable delay module includes an orthogonal signal generating module, a plurality of Gilbert units and an amplifier module; the orthogonal signals generated by the orthogonal signal generating module are respectively input to the orthogonal signal input terminals of the first Gilbert unit and the second Gilbert unit; the first Gilbert unit and the second Gilbert unit are respectively connected to the amplifier module;

[0010] The digital logic module is configured to achieve that the tail current sources of the first Gilbert unit and the second Gilbert unit are linearly related to the delay steps, and the final output current remains consistent.

[0011] Preferably, the orthogonal signal generating module comprises a plurality of binary frequency dividers;

[0012] The first two-frequency divider is used to divide the CLKP into an OUTP1 signal and an OUTN1 signal;

[0013] The second frequency divider is used to divide the CLKN into an OUTP2 signal and an OUTN2 signal;

[0014] The OUTP1 signal and the OUTN1 signal are input to the second Gilbert unit;

[0015] The OUTP2 signal and the OUTN2 signal are input to the first Gilbert cell.

[0016] Preferably, the first Gilbert unit includes a plurality of capacitors, a plurality of resistors, a plurality of transistors and a plurality of bias current modules;

[0017] The emitter of the first triode and the emitter of the second triode are connected to the input end of the first bias current module, the output end of the first bias current module is grounded, the base of the first triode is connected to the OUTN2 signal and one end of the first capacitor, the collector of the first triode is connected to the other end of the first capacitor, one end of the zeroth capacitor, one end of the first resistor and the second end of the amplifier module, the base of the second triode is connected to the base of the third triode, one end of the second capacitor and the OUTP2 signal, the collector of the second triode is connected to the other end of the second capacitor, the other end of the zeroth capacitor, one end of the second resistor and the third end of the amplifier module, and the other end of the first resistor and the other end of the second resistor are connected to a DC source and the first end of the amplifier module;

[0018] The emitter of the third triode and the emitter of the fourth triode are connected to the input end of the second bias current module, the output end of the second bias current module is grounded, the base of the third triode is connected to one end of the third capacitor, the collector of the third triode is connected to one end of the first resistor, the other end of the third capacitor and the second end of the amplifier module, the base of the fourth triode is connected to one end of the first capacitor and one end of the fourth capacitor, and the collector of the fourth triode is connected to one end of the second resistor, the other end of the fourth capacitor and the third end of the amplifier module.

[0019] Preferably, the second Gilbert unit comprises a plurality of capacitors, a plurality of resistors, a plurality of transistors and a plurality of bias current modules;

[0020] The emitter of the fifth transistor and the emitter of the sixth transistor are connected to the input end of the third bias current module, the output end of the third bias current module is grounded, the base of the fifth transistor is connected to the OUTP1 signal and one end of the fifth capacitor, the collector of the fifth transistor is connected to one end of the first resistor, the second end of the amplifier module and the other end of the fifth capacitor, the base of the sixth transistor is connected to the base of the seventh transistor, one end of the sixth capacitor and the OUTN1 signal, and the collector of the sixth transistor is connected to one end of the second resistor, the other end of the sixth capacitor and the third end of the amplifier module;

[0021] The emitter of the seventh transistor and the emitter of the eighth transistor are connected to the input end of the fourth bias current module, the output end of the fourth bias current module is grounded, the base of the seventh transistor is connected to one end of the seventh capacitor, the collector of the seventh transistor is connected to one end of the first resistor, the other end of the seventh capacitor and the second end of the amplifier module, the base of the eighth transistor is connected to one end of the eighth capacitor and one end of the fifth capacitor, and the collector of the eighth transistor is connected to one end of the second resistor, the other end of the eighth capacitor and the third end of the amplifier module.

[0022] Preferably, the amplifier module includes a plurality of bias current modules, a plurality of resistors and a plurality of triodes;

[0023] The emitter of the ninth transistor and the emitter of the tenth transistor are connected to the input end of the fifth bias current module, the output end of the fifth bias current module is grounded, the base of the ninth transistor and the base of the tenth transistor are respectively used as the third input end and the second input end of the amplifier module, the collector of the ninth transistor is connected to one end of the third resistor and the base of the eleventh transistor, the collector of the tenth transistor is connected to one end of the fourth resistor and the base of the twelfth transistor, the other end of the third resistor, the other end of the fourth resistor, the collector of the eleventh transistor and the collector of the twelfth transistor are connected and serve as the first input end of the amplifier module, the emitter of the eleventh transistor outputs an OUTP signal and is connected to the input end of the sixth bias current module, the emitter of the twelfth transistor outputs an OUTN signal and is connected to the input end of the seventh bias current module, and the output ends of the sixth bias current module and the seventh bias current module are grounded.

[0024] Preferably, the method of configuring through a digital logic module is:

[0025] The delay time of each step is adjusted by adjusting the size of all the capacitors in the first Gilbert unit and the second Gilbert unit, and the delay time of each step is the time required for the capacitor to charge or discharge;

[0026] The number of delay steps is adjusted by adjusting the number of current steps of all the bias current modules in the first Gilbert cell and the second Gilbert cell.

[0027] Preferably, the method for obtaining the charging and discharging time of the capacitor is:

[0028]

[0029] Among them, t 充电,i and t 放电,i represents the charging time and discharging time of the i-th capacitor, R1 and R2 are the resistance values ​​of the first resistor and the second resistor, respectively. i Represents the capacitance value of the i-th capacitor, V DD is the DC source size, V t,1 and V t,2 The DC point voltages established for the first two frequency dividers and the first two frequency dividers respectively.

[0030] Preferably, the outputs of the first Gilbert cell and the second Gilbert cell are shaped and outputted by the amplifier module.

[0031] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0032] The present invention effectively optimizes the small phase difference after the clock tree network is synchronized, and reduces the difficulty of synchronizing the clock signal;

[0033] The present invention solves the problem of slight phase difference between channels after clock network synchronization through the design of a programmable delay module;

[0034] The present invention can increase the total number of delay steps by increasing the number of complementary current source control signals, so the present invention has the advantages of scalability and adjustable delay;

[0035] Compared with the traditional inverter chain delay link and D flip-flop link, the present invention not only has a smaller delay step, but also has better linearity;

[0036] The invention has reasonable design, simple structure, high cost performance and is easy to promote and implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a SYSREF circuit with programmable fine-tuning delay provided in Embodiment 1 of the present invention;

[0038] Figure 2 A circuit diagram of a programmable delay module provided in Embodiment 1 of the present invention;

[0039] Figure 3 A schematic diagram of fine-tuning the delay after synchronization provided in Embodiment 1 of the present invention;

[0040] Figure 4 A schematic diagram of a vector synthesis delay of orthogonal signals through a Gilbert unit provided in Embodiment 1 of the present invention;

[0041] Figure 5 A schematic diagram of the change of delay with stepping provided in Example 1 of the present invention;

[0042] Icons: R1-first resistor, R2-second resistor, C0-zeroth capacitor, C1-first capacitor, C2-second capacitor, C3-third capacitor, C4-fourth capacitor, C5-fifth capacitor, C6-sixth capacitor, C7-seventh capacitor, C8-eighth capacitor, M1-first triode, M2-second triode, M3-third triode, M4-fourth triode, M5-fifth triode, M6-sixth triode, M7-seventh triode, M8-eighth triode, M9-ninth triode, M10-tenth triode, M11-eleventh triode, M12-twelfth triode, Ibias1-first bias current module, Ibias2-second bias current module, Ibias3-third bias current module, Ibias4-fourth bias current module. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0044] Example 1

[0045] This embodiment provides a SYSREF circuit with programmable fine-tuning delay, see Figure 1 , including output channel dividers, SYSREF dividers, programmable delay blocks, and multiple drivers;

[0046] The output channel divider and the SYSREF divider are both used to divide the voltage controlled oscillator signal f vco Perform frequency division processing; the output channel frequency divider and the SYSREF frequency divider are both reset by a reset pulse to achieve phase alignment of the output signals of the output channel frequency divider and the SYSREF frequency divider; the output end of the output channel frequency divider is connected to a first driver, and the first driver outputs a system master clock DCLK; the output end of the SYSREF frequency divider outputs a pair of differential signals CLKP and CLKN and is connected to the input end of the programmable delay module, the output end of the programmable delay module is connected to the input end of a second driver, and the second driver outputs a system reference signal SYSREF clock SCLK synchronized with the system master clock DCLK;

[0047] See also Figure 2 , the programmable delay module includes an orthogonal signal generating module, a plurality of Gilbert units and an amplifier module; the orthogonal signals generated by the orthogonal signal generating module are respectively input to the orthogonal signal input terminals of the first Gilbert unit and the second Gilbert unit; the first Gilbert unit and the second Gilbert unit are respectively connected to the amplifier module;

[0048] The digital logic module is configured to achieve that the tail current sources of the first Gilbert unit and the second Gilbert unit are linearly related to the delay steps, and the final output current remains consistent.

[0049] The traditional delay method is implemented by an inverter chain, which has poor delay linearity and worsens the jitter of the output signal. There is also a traditional solution that implements the delay method through a D-flip-flop chain, which has a large delay step and can only be half a cycle of the input clock, and has great application limitations.

[0050] The working principle of this embodiment is that when the phase-locked loop starts the synchronization mode, the output channel divider and the SYSREF divider respectively divide f vco The signal is divided. Due to the random phase of the divider, DCLK and SCLK are in an uncertain phase relationship. At this time, the reset pulse from SYNC resets the output channel divider and SYSREF divider at the same time, so that the phase of the output signal of the channel divider and SYSREF divider is aligned, and then DCLK and SCLK are output through the driver. However, due to the inconsistent link delay of the divider, the final synchronized signal still has a slight phase difference. At this time, the phase can be aligned by adjusting the programmable delay circuit to ensure complete synchronization between channels or chips. Figure 3 Schematic diagram of SYSREF synchronization mode and fine-tuning delay after synchronization. In summary, compared with the prior art, this embodiment has a smaller delay step and better linearity.

[0051] In this embodiment, the orthogonal signal generating module includes a plurality of binary frequency dividers;

[0052] The first two-frequency divider is used to divide the CLKP into an OUTP1 signal and an OUTN1 signal;

[0053] The second frequency divider is used to divide the CLKN into an OUTP2 signal and an OUTN2 signal;

[0054] The OUTP1 signal and the OUTN1 signal are input to the second Gilbert unit;

[0055] The OUTP2 signal and the OUTN2 signal are input to the first Gilbert cell.

[0056] As a preferred solution of this embodiment, the first Gilbert unit includes a plurality of capacitors, a plurality of resistors, a plurality of transistors and a plurality of bias current modules;

[0057] The emitter of the first transistor M1 and the emitter of the second transistor M2 are connected to the input end of the first bias current module Ibias1, the output end of the first bias current module Ibias1 is grounded, the base of the first transistor M1 is connected to the OUTN2 signal and one end of the first capacitor C1, the collector of the first transistor M1 is connected to the other end of the first capacitor C1, one end of the zeroth capacitor C0, one end of the first resistor R1 and the second end of the amplifier module, the base of the second transistor M2 is connected to the base of the third transistor M3, one end of the second capacitor C2 and the OUTP2 signal, the collector of the second transistor M2 is connected to the other end of the second capacitor C2, the other end of the zeroth capacitor C0, one end of the second resistor R2 and the third end of the amplifier module, and the other end of the first resistor R1 and the other end of the second resistor R2 are connected to a DC source and the first end of the amplifier module;

[0058] The emitter of the third triode M3 and the emitter of the fourth triode M4 are connected to the input end of the second bias current module Ibias2, the output end of the second bias current module Ibias2 is grounded, the base of the third triode M3 is connected to one end of the third capacitor C3, the collector of the third triode M3 is connected to one end of the first resistor R1, the other end of the third capacitor C3 and the second end of the amplifier module, the base of the fourth triode M4 is connected to one end of the first capacitor C1 and one end of the fourth capacitor C4, and the collector of the fourth triode M4 is connected to one end of the second resistor R2, the other end of the fourth capacitor C4 and the third end of the amplifier module.

[0059] On the other hand, the second Gilbert unit includes a plurality of capacitors, a plurality of resistors, a plurality of triodes and a plurality of bias current modules;

[0060] The emitter of the fifth transistor M5 and the emitter of the sixth transistor M6 are connected to the input end of the third bias current module Ibias3, the output end of the third bias current module Ibias3 is grounded, the base of the fifth transistor M5 is connected to the OUTP1 signal and one end of the fifth capacitor C5, the collector of the fifth transistor M5 is connected to one end of the first resistor R1, the second end of the amplifier module and the other end of the fifth capacitor C5, the base of the sixth transistor M6 is connected to the base of the seventh transistor M7, one end of the sixth capacitor C6 and the OUTN1 signal, and the collector of the sixth transistor M6 is connected to one end of the second resistor R2, the other end of the sixth capacitor C6 and the third end of the amplifier module;

[0061] The emitter of the seventh transistor M7 and the emitter of the eighth transistor M8 are connected to the input end of the fourth bias current module Ibias4, the output end of the fourth bias current module Ibias4 is grounded, the base of the seventh transistor M7 is connected to one end of the seventh capacitor C7, the collector of the seventh transistor M7 is connected to one end of the first resistor R1, the other end of the seventh capacitor C7 and the second end of the amplifier module, the base of the eighth transistor M8 is connected to one end of the eighth capacitor C8 and one end of the fifth capacitor C5, and the collector of the eighth transistor M8 is connected to one end of the second resistor R2, the other end of the eighth capacitor C8 and the third end of the amplifier module.

[0062] Finally, the amplifier module includes a plurality of bias current modules, a plurality of resistors and a plurality of triodes;

[0063] The emitter of the ninth transistor M9 and the emitter of the thirteenth transistor M10 are connected to the input end of the fifth bias current module Ibias5, the output end of the fifth bias current module Ibias5 is grounded, the base of the ninth transistor M9 and the base of the tenth transistor M10 serve as the third input end and the second input end of the amplifier module respectively, the collector of the ninth transistor M9 is connected to one end of the third resistor R3 and the base of the eleventh transistor M11, the collector of the tenth transistor M10 is connected to one end of the fourth resistor R4 and the base of the twelfth transistor M12, and the third The other end of the resistor R3, the other end of the fourth resistor R4, the collector of the eleventh transistor M11 and the collector of the twelfth transistor M12 are connected and serve as the first input end of the amplifier module, the emitter of the eleventh transistor M11 outputs the OUTP signal and is connected to the input end of the sixth bias current module Ibias6, the emitter of the twelfth transistor M12 outputs the OUTN signal and is connected to the input end of the seventh bias current module Ibias7, and the output ends of the sixth bias current module Ibias6 and the seventh bias current module Ibias7 are grounded.

[0064] The programmable delay circuit designed in this embodiment directly uses the differential signal generated by the current mode logic, and the transmission path is the same, so the time delay mismatch between the four signals can be effectively reduced. At the same time, the operating speed of the circuit can be improved. The orthogonal signal generation module can divide the differential signal CLKP and CLKN from the SYSREF divider into two orthogonal frequencies to generate orthogonal differential signals Q1 and Q2, Q1N and Q2N with a phase difference of 90°, and at the same time establish a suitable working point so that the eight capacitors work in the linear region. The zero capacitor is a clamping capacitor, which can eliminate the common-mode interference between the differentials and make the rising edge of the signal slower, making it easier to delay the signal. The first resistor and the second resistor are load resistors, which together with the tail current source determine the size of the output amplitude and provide a working point for the post-amplifier module. The first bias current module Ibias1 and the second bias current module Ibias2 are complementary current sources, the third bias current module Ibias3 and the fourth bias current module Ibias4 are complementary current sources, which are configured through a digital logic module so that the tail current sources of the first Gilbert unit and the second Gilbert unit change linearly with the change of the delay step, and the sum of the currents of the four tail current sources remains consistent. The eight capacitors C1-C8 are the core of the delay circuit. The charging and discharging of the capacitors by complementary current sources allows the rising and falling edges of the orthogonal signals to be delayed simultaneously during the delay process, thereby increasing the linearity of the delay step.

[0065] Therefore, the method of configuring through the digital logic module is:

[0066] The delay time of each step is adjusted by adjusting the size of all the capacitors in the first Gilbert unit and the second Gilbert unit, and the delay time of each step is the time required for the capacitor to charge or discharge;

[0067] The number of delay steps is adjusted by adjusting the number of current steps of all the bias current modules in the first Gilbert cell and the second Gilbert cell.

[0068] When adjusting specifically, the method for obtaining the charging and discharging time of the capacitor is:

[0069]

[0070] Among them, t 充电,i and t 放电,i represents the charging time and discharging time of the i-th capacitor, R1 and R2 are the resistance values ​​of the first resistor and the second resistor, respectively. i Represents the capacitance value of the i-th capacitor, V DD is the DC source size, V t,1 and V t,2 The DC point voltages established for the first two frequency dividers and the first two frequency dividers respectively.

[0071] At the end of the programmable delay module, the outputs of the first Gilbert cell and the second Gilbert cell are shaped and outputted through the amplifier module.

[0072] The schematic diagram of the vector synthesis delay of the orthogonal signal through the Gilbert unit in this embodiment can be found in Figure 4 Q1 and Q2 are orthogonal signals generated by the orthogonal signal generator for Q3. Through Gilbert vector synthesis, each current change will cause a deterministic delay in the phase of Q1 and Q2 signals, and the final synthesized signal will also have a deterministic delay.

[0073] Figure 5 1 is a curve showing the total delay of the programmable fine-tuning delay module of this embodiment changing with the step. It can be seen that the programmable delay circuit of this embodiment has good linearity, and the delay difference between each step does not exceed 1ps.

[0074] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A SYSREF circuit with programmable fine-tuning delay, characterized in that: Includes output channel dividers, SYSREF dividers, programmable delay blocks, and multiple drivers; The output channel divider and the SYSREF divider are both used to divide the voltage controlled oscillator signal f vco Perform frequency division processing; the output channel frequency divider and the SYSREF frequency divider are both reset by a reset pulse to achieve phase alignment of the output signals of the output channel frequency divider and the SYSREF frequency divider; the output end of the output channel frequency divider is connected to a first driver, and the first driver outputs a system master clock DCLK; the output end of the SYSREF frequency divider outputs a pair of differential signals CLKP and CLKN and is connected to the input end of the programmable delay module, the output end of the programmable delay module is connected to the input end of a second driver, and the second driver outputs a system reference signal SYSREF clock SCLK synchronized with the system master clock DCLK; The programmable delay module includes an orthogonal signal generating module, a plurality of Gilbert units and an amplifier module; the orthogonal signals generated by the orthogonal signal generating module are respectively input to the orthogonal signal input terminals of the first Gilbert unit and the second Gilbert unit; the first Gilbert unit and the second Gilbert unit are respectively connected to the amplifier module; The digital logic module is configured to achieve that the tail current sources of the first Gilbert unit and the second Gilbert unit are linearly related to the number of delay steps, and the magnitude of the final output current remains consistent.

2. A SYSREF circuit with programmable fine-tuning delay according to claim 1, characterized in that: The orthogonal signal generating module includes a plurality of binary frequency dividers; The first two-frequency divider is used to divide the CLKP into an OUTP1 signal and an OUTN1 signal; The second frequency divider is used to divide the CLKN into an OUTP2 signal and an OUTN2 signal; The OUTP1 signal and the OUTN1 signal are input to the second Gilbert unit; The OUTP2 signal and the OUTN2 signal are input to the first Gilbert cell.

3. A SYSREF circuit with programmable fine-tuning delay according to claim 2, characterized in that: The first Gilbert unit includes a plurality of capacitors, a plurality of resistors, a plurality of triodes and a plurality of bias current modules; The emitter of the first triode and the emitter of the second triode are connected to the input end of the first bias current module, the output end of the first bias current module is grounded, the base of the first triode is connected to the OUTN2 signal and one end of the first capacitor, the collector of the first triode is connected to the other end of the first capacitor, one end of the zeroth capacitor, one end of the first resistor and the second end of the amplifier module, the base of the second triode is connected to the base of the third triode, one end of the second capacitor and the OUTP2 signal, the collector of the second triode is connected to the other end of the second capacitor, the other end of the zeroth capacitor, one end of the second resistor and the third end of the amplifier module, and the other end of the first resistor and the other end of the second resistor are connected to a DC source and the first end of the amplifier module; The emitter of the third triode and the emitter of the fourth triode are connected to the input end of the second bias current module, the output end of the second bias current module is grounded, the base of the third triode is connected to one end of the third capacitor, the collector of the third triode is connected to one end of the first resistor, the other end of the third capacitor and the second end of the amplifier module, the base of the fourth triode is connected to one end of the first capacitor and one end of the fourth capacitor, and the collector of the fourth triode is connected to one end of the second resistor, the other end of the fourth capacitor and the third end of the amplifier module.

4. A SYSREF circuit with programmable fine-tuning delay according to claim 3, characterized in that: The second Gilbert unit includes a plurality of capacitors, a plurality of resistors, a plurality of triodes and a plurality of bias current modules; The emitter of the fifth transistor and the emitter of the sixth transistor are connected to the input end of the third bias current module, the output end of the third bias current module is grounded, the base of the fifth transistor is connected to the OUTP1 signal and one end of the fifth capacitor, the collector of the fifth transistor is connected to one end of the first resistor, the second end of the amplifier module and the other end of the fifth capacitor, the base of the sixth transistor is connected to the base of the seventh transistor, one end of the sixth capacitor and the OUTN1 signal, and the collector of the sixth transistor is connected to one end of the second resistor, the other end of the sixth capacitor and the third end of the amplifier module; The emitter of the seventh transistor and the emitter of the eighth transistor are connected to the input end of the fourth bias current module, the output end of the fourth bias current module is grounded, the base of the seventh transistor is connected to one end of the seventh capacitor, the collector of the seventh transistor is connected to one end of the first resistor, the other end of the seventh capacitor and the second end of the amplifier module, the base of the eighth transistor is connected to one end of the eighth capacitor and one end of the fifth capacitor, and the collector of the eighth transistor is connected to one end of the second resistor, the other end of the eighth capacitor and the third end of the amplifier module.

5. A SYSREF circuit with programmable fine-tuning delay according to claim 4, characterized in that: The amplifier module includes a plurality of bias current modules, a plurality of resistors and a plurality of triodes; The emitter of the ninth transistor and the emitter of the tenth transistor are connected to the input end of the fifth bias current module, the output end of the fifth bias current module is grounded, the base of the ninth transistor and the base of the tenth transistor are respectively used as the third input end and the second input end of the amplifier module, the collector of the ninth transistor is connected to one end of the third resistor and the base of the eleventh transistor, the collector of the tenth transistor is connected to one end of the fourth resistor and the base of the twelfth transistor, the other end of the third resistor, the other end of the fourth resistor, the collector of the eleventh transistor and the collector of the twelfth transistor are connected and serve as the first input end of the amplifier module, the emitter of the eleventh transistor outputs an OUTP signal and is connected to the input end of the sixth bias current module, the emitter of the twelfth transistor outputs an OUTN signal and is connected to the input end of the seventh bias current module, and the output ends of the sixth bias current module and the seventh bias current module are grounded.

6. A SYSREF circuit with programmable fine-tuning delay according to claim 5, characterized in that: The method of configuring through a digital logic module is: The delay time of each step is adjusted by adjusting the size of all the capacitors in the first Gilbert unit and the second Gilbert unit, and the delay time of each step is the time required for the capacitor to charge or discharge; The number of delay steps is adjusted by adjusting the number of current steps of all the bias current modules in the first Gilbert cell and the second Gilbert cell.

7. A SYSREF circuit with programmable fine-tuning delay according to claim 6, characterized in that: The method for obtaining the charging and discharging time of the capacitor is: Among them, t 充电,i and t 放电,i represents the charging time and discharging time of the i-th capacitor, R1 and R2 are the resistance values ​​of the first resistor and the second resistor, respectively. i Represents the capacitance value of the i-th capacitor, V DD is the DC source size, V t,1 and V t,2 The DC point voltages established for the first two frequency dividers and the first two frequency dividers respectively.

8. A SYSREF circuit with programmable fine-tuning delay according to claim 7, characterized in that: The amplifier module shapes and outputs of the first Gilbert cell and the second Gilbert cell.

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