Digital-to-analog converter and digital-to-analog conversion circuit thereof

Abstract

The invention discloses a digital-to-analog converter and a digital-to-analog conversion circuit thereof, which are applied to the technical field of signal transmission, and comprise a control circuit and a digital-to-analog conversion circuit main body which is connected with the control circuit and is based on an R-2R resistance network, the control circuit is used for reading a DAC sampling signal and a DAC digital input signal, sending the DAC digital input signal to the digital-to-analog conversion circuit main body after reading, and controlling the digital-to-analog conversion circuit main body to be in a high-resistance state; and after the high-resistance state reaches a first duration, controlling the state of the digital-to-analog conversion circuit main body by using the DAC digital input signal, so that the digital-to-analog conversion circuit main body outputs a corresponding analog signal based on the DAC digital input signal. According to the scheme, the precision advantage and the area advantage of R-2R are achieved, and meanwhile, switching burrs can be effectively eliminated through the design that the DAC enters the high resistance state firstly, so that the conversion speed of the DAC is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of signal transmission, and in particular to a digital-to-analog converter and a digital-to-analog conversion circuit thereof. Background Art

[0002] At present, semiconductor technology has higher and higher requirements for the conversion of digital signals and analog signals. Among them, DAC (Digital to Analog Converter) is a very important circuit that can convert digital signals into analog signals, such as voltage or current, and accuracy and speed are important indicators of DAC.

[0003] Figure 1 This is a schematic diagram of the traditional 4-bit R-2R DAC architecture. In the R-2R architecture, since only the resistors R and 2R need to be matched and the number of components is small, it has good accuracy and a small area and has been widely used. However, this architecture has the problem of output burrs, which limits its conversion speed. Figure 2 , is the schematic diagram of the switching glitch generation of the traditional R-2R DAC architecture, Figure 2 In the example, when the digital input signal from SW3 to SW0 changes from 0001 to 0010, due to the process deviation of components and the deviation of physical metal routing, the switching speed of each switch circuit will not be completely consistent. Therefore, in the process of switching from 0001 to 0010, 0000 or 0011 may appear. Figure 2 In the example, the level change process of the switch circuit is: 0001-0000-0010. Figure 2 In this case, a conversion glitch will appear on the DAC output. Figure 3 , is a schematic diagram of the switching glitch of the traditional R-2R DAC architecture. Figure 3 The figure shows the falling burr, and the rising burr may appear in some cases. Due to the existence of the burr, the DAC has a longer settling time after switching the digital input signal, which limits the speed of the DAC.

[0004] In addition, in some cases, an inverter is used as a control switch for the DAC. Figure 4 , is a schematic diagram of an R-2R DAC architecture using an inverter as a switching circuit of a DAC. In addition to the inconsistency of the control signals of the various switching circuits mentioned above, the switching speeds of the inverter output from high to low and from low to high are also inconsistent, resulting in the above-mentioned simultaneous 0 or simultaneous 1 situation during the switching process, that is, the occurrence of a drop glitch or a rise glitch.

[0005] In summary, how to eliminate switching glitches while having the accuracy and area advantages of R-2R, thereby improving the conversion speed of DAC, is a technical problem that technicians in this field urgently need to solve. Summary of the invention

[0006] The object of the present invention is to provide a digital-to-analog converter and a digital-to-analog conversion circuit thereof, which can eliminate switching glitches while having the accuracy and area advantages of R-2R, thereby improving the conversion speed of DAC.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] A digital-to-analog conversion circuit comprises: a control circuit and a digital-to-analog conversion circuit body based on an R-2R resistor network connected to the control circuit;

[0009] The control circuit is used to: read the DAC sampling signal and the DAC digital input signal, and after reading, send the DAC digital input signal to the digital-to-analog conversion circuit body, and control the digital-to-analog conversion circuit body to be in a high-impedance state; after the duration of the digital-to-analog conversion circuit body entering the high-impedance state reaches a first duration, use the DAC digital input signal to control the state of the digital-to-analog conversion circuit body, so that the digital-to-analog conversion circuit body outputs a corresponding analog signal based on the DAC digital input signal.

[0010] In one embodiment, the control circuit includes: a pulse generation circuit, a synchronization circuit and a target switch circuit;

[0011] The pulse generating circuit is used to: read the DAC sampling signal through its own input terminal, and after reading, send a pulse signal lasting a first time length to the digital-to-analog conversion circuit body and the target switch circuit, so that during the first time length of the pulse signal, the target switch circuit is in an off state, and the digital-to-analog conversion circuit body is in a high-impedance state;

[0012] The synchronization circuit is used to: read the DAC sampling signal through its first input terminal, read the DAC digital input signal through its second input terminal, and after reading the DAC sampling signal, send the DAC digital input signal to the digital-to-analog conversion circuit body, so that after the pulse signal ends, the state of the digital-to-analog conversion circuit body is controlled by using the DAC digital input signal, so that the digital-to-analog conversion circuit body outputs a corresponding analog signal based on the DAC digital input signal;

[0013] The digital-to-analog conversion circuit body includes N switch circuits and an R-2R resistor circuit. The ground end of the R-2R resistor circuit is grounded through the target switch circuit. The output end of the R-2R resistor circuit serves as the output end of the digital-to-analog conversion circuit body. The N signal input ends of the R-2R resistor circuit are respectively connected to the N switch circuits. N is a positive integer, which represents the number of bits of the digital-to-analog conversion circuit body.

[0014] In one embodiment, the target switch circuit includes: a first NOT gate and a first target switch;

[0015] The input end of the first NOT gate serves as the input end of the target switch circuit and is connected to the output end of the pulse generating circuit, the output end of the first NOT gate is connected to the control end of the first target switch, the first end of the first target switch is connected to the ground end of the R-2R resistor circuit, and the second end of the first target switch is grounded;

[0016] When the control terminal of the first target switch is at a high level, the first target switch is in an on state, and when the control terminal of the first target switch is at a low level, the first target switch is in an off state.

[0017] In one implementation, the first target switch is an NMOS switch tube.

[0018] In one embodiment, the target switch circuit includes: a second target switch;

[0019] The control end of the second target switch serves as the input end of the target switch circuit, the first end of the second target switch is connected to the ground end of the R-2R resistor circuit, and the second end of the second target switch is grounded;

[0020] When the control terminal of the second target switch is at a low level, the first target switch is in an on state, and when the control terminal of the second target switch is at a high level, the second target switch is in an off state.

[0021] In one embodiment, any one of the N switch circuits includes: a second NOT gate, a third NOT gate, a first OR gate, a first AND gate, a first switch tube, and a second switch tube;

[0022] The input end of the second NOT gate serves as the digital signal input end of the switch circuit, the output end of the second NOT gate is respectively connected to the first input end of the first OR gate and the first input end of the first AND gate, and the output end of the third NOT gate is connected to the second input end of the first AND gate;

[0023] The second input end of the first OR gate is connected to the input end of the third NOT gate, and the connection end serves as the pulse signal input end of the switch circuit, the output end of the first OR gate is connected to the control end of the first switch tube, and the output end of the first AND gate is connected to the control end of the second switch tube;

[0024] The second end of the first switch tube is connected to the first end of the second switch tube, and the connecting end serves as the output end of the switch circuit, the first end of the first switch tube is connected to the positive electrode of the first power supply, and the second end of the second switch tube is grounded;

[0025] The pulse signal input terminals of the N switch circuits are all connected to the pulse generating circuit to receive the pulse signal, the digital signal input terminals of the N switch circuits are all connected to the synchronization circuit to receive the DAC digital input signal of the corresponding bit, and the output terminals of the N switch circuits are connected to the corresponding N signal input terminals of the R-2R resistor circuit;

[0026] Among them, when the control end of the first switch tube is at a high level, the first switch tube is in an off state, and when the control end of the first switch tube is at a low level, the first switch tube is in an on state; when the control end of the second switch tube is at a low level, the second switch tube is in an off state, and when the control end of the second switch tube is at a high level, the second switch tube is in an on state.

[0027] In one implementation, the first switch tube is a PMOS switch tube, and the second switch tube is an NMOS switch tube.

[0028] In one embodiment, any one of the N switching circuits is a relay-based switching circuit, and when the switching circuit receives the pulse signal, its output end is in a floating state; when the switching circuit does not receive the pulse signal and receives a high-level DAC digital input signal, its output end is connected to the positive electrode of the second power supply; when the switching circuit does not receive the pulse signal and receives a low-level DAC digital input signal, its output end is grounded.

[0029] In one implementation, the DAC sampling signal read by the control circuit is a DAC sampling signal sent by the sampling control circuit according to a preset period.

[0030] A digital-to-analog converter comprises the digital-to-analog conversion circuit as described above.

[0031] The technical solution provided in the embodiment of the present invention adopts a digital-to-analog conversion circuit body based on an R-2R resistor network, that is, the digital-to-analog conversion circuit of the present application adopts an RR-2R DAC architecture. Therefore, the solution of the present application can have the accuracy and area advantages of R-2R.

[0032] However, the present application takes into account that in the traditional solution, due to the process deviation of components, the deviation of physical metal routing and other reasons, the control signals of each switch in the R-2R DAC architecture are inconsistent, resulting in output glitches. In this regard, in the solution of the present application, after reading the DAC sampling signal and the DAC digital input signal, the control circuit will send the DAC digital input signal to the digital-to-analog conversion circuit body, but the DAC digital input signal will not take effect at this time, because after reading the DAC sampling signal and the DAC digital input signal, the control circuit will also control the digital-to-analog conversion circuit body to be in a high-impedance state, and the high-impedance state will last for a certain period of time, that is, the first period of time. Therefore, it can be understood that during the period when the digital-to-analog conversion circuit body is in a high-impedance state, it plays a buffering role. Even if there are process deviations in components and deviations in physical metal routing, during the high-impedance period, the DAC digital input signal can be transmitted to each switch circuit in the digital-to-analog conversion circuit body. Of course, since the high-impedance state has not ended, analog-to-digital conversion will not be performed at this time. After the first time period, the high impedance state of the digital-to-analog conversion circuit body ends. Therefore, under the control of the DAC digital input signal, the state of the digital-to-analog conversion circuit body will be changed accordingly, so that the digital-to-analog conversion circuit body 20 outputs the corresponding analog signal based on the DAC digital input signal, so that the digital-to-analog conversion circuit completes the digital-to-analog conversion function.

[0033] Due to the presence of parasitic capacitance in the circuit, when the main body of the digital-to-analog conversion circuit is in a high-impedance state, its output will not change, that is, it has a clamping effect and therefore no glitches will occur. It should also be noted that in the traditional scheme, when the switch circuit in the main body of the digital-to-analog conversion circuit is switched, it undergoes the process of "connecting to a high level-switching to grounding" or "grounding-switching to connecting to a high level". As described above, the speeds of these two processes are not consistent, so glitches will also occur. In the scheme of the present application, since the state of the main body of the digital-to-analog conversion circuit will be controlled to be a high-impedance state, it can be understood that in the high-impedance state, each switch circuit in the main body of the digital-to-analog conversion circuit is in a suspended state, that is, it is neither connected to a high level nor to ground, and after the high-impedance state ends, the switch circuit undergoes the process of "high-impedance state-switching to connecting to a high level" or "high-impedance state-switching to grounding". The speed difference between these two processes is very small and will not cause glitches.

[0034] In summary, the solution of the present application can have the accuracy and area advantages of R-2R. At the same time, for the glitch problem caused by inconsistent control signals of the switching circuit and inconsistent switching speed in the traditional solution, the solution of the present application can effectively eliminate the switching glitch by first entering the high-impedance state, thereby improving the conversion speed of the DAC. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the traditional 4-bit R-2R DAC architecture;

[0037] Figure 2 This is the schematic diagram of the switching glitch generation of the traditional R-2R DAC architecture.

[0038] Figure 3 This is a schematic diagram of the switching glitch of the traditional R-2R DAC architecture;

[0039] Figure 4 A schematic diagram of an R-2R DAC architecture using an inverter as a switching circuit of a DAC;

[0040] Figure 5 It is a structural schematic diagram of a digital-to-analog conversion circuit in the present invention;

[0041] Figure 6 A schematic diagram of the structure of a control circuit in a specific implementation manner of the present invention;

[0042] Figure 7 It is a structural schematic diagram of a single switch circuit in a specific implementation manner of the present invention;

[0043] Figure 8 This is a working timing diagram of a switch circuit in a specific implementation mode of the present invention;

[0044] Fig. 9 Schematic diagram for comparison of ideal DAC conversion, traditional DAC switching and the digital-to-analog conversion circuit conversion of the present application. DETAILED DESCRIPTION

[0045] The core of the present invention is to provide a digital-to-analog conversion circuit that has the accuracy and area advantages of R-2R. At the same time, for the glitch problem caused by inconsistent control signals of the switching circuit and inconsistent switching speed in the traditional solution, the solution of the present application can effectively eliminate the switching glitch by first entering the high-impedance state, thereby improving the conversion speed of the DAC.

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0047] Please refer to Figure 5 , Figure 5 Schematic diagram of a digital-to-analog conversion circuit in the present invention, the digital-to-analog conversion circuit may include: a control circuit 10 and a digital-to-analog conversion circuit body 20 based on an R-2R resistor network connected to the control circuit 10;

[0048] The control circuit 10 is used to: read the DAC sampling signal and the DAC digital input signal, and after reading, send the DAC digital input signal to the digital-to-analog conversion circuit body 20, and control the digital-to-analog conversion circuit body 20 to be in a high-impedance state; after the duration of the digital-to-analog conversion circuit body 20 entering the high-impedance state reaches a first duration, use the DAC digital input signal to control the state of the digital-to-analog conversion circuit body 20, so that the digital-to-analog conversion circuit body 20 outputs a corresponding analog signal based on the DAC digital input signal.

[0049] In the scheme of the present application, a digital-to-analog conversion circuit body 20 based on an R-2R resistor network is used. Therefore, the scheme of the present application can have the accuracy and area advantages of R-2R. The digital-to-analog conversion circuit body 20 is usually composed of N switch circuits and R-2R resistor circuits, with a simple structure and high reliability. Of course, the digital-to-analog conversion circuit body 20 in some occasions can also be adjusted to a certain extent on this basis. As long as it is based on an R-2R resistor network, it does not affect the implementation of the present invention. N represents the number of bits of the digital-to-analog conversion circuit body 20. Figure 6 In the implementation mode, N=4, that is, a 4-bit R-2R resistor circuit.

[0050] The specific structure of the control circuit 10 of the present application can be set and adjusted according to actual needs, as long as the functional requirements of the scheme of the present application for the control circuit 10 can be achieved. Specifically, the control circuit 10 must be able to read the DAC sampling signal and the DAC digital input signal. It can be understood that the DAC digital input signal plays the role of data input so that the digital-to-analog conversion circuit body 20 can achieve the corresponding digital-to-analog conversion based on it, and the DAC sampling signal plays the role of triggering, that is, only after the DAC sampling signal is read, the DAC digital input signal is allowed to be sent to the digital-to-analog conversion circuit body 20.

[0051] After reading the DAC sampling signal and the DAC digital input signal, the control circuit 10 will send the DAC digital input signal to the digital-to-analog conversion circuit body 20. However, at this time, the digital-to-analog conversion circuit body 20 will not directly perform digital-to-analog conversion. This is because after reading the DAC sampling signal and the DAC digital input signal, the control circuit 10 will also control the digital-to-analog conversion circuit body 20 to be in a high-impedance state.

[0052] The digital-to-analog conversion circuit body 20 is controlled to be in a high-impedance state, that is, the digital-to-analog conversion circuit is in a suspended state, that is, for any switch circuit in the digital-to-analog conversion circuit, the switch circuit is neither connected to a high level nor to the ground, and is in a high-impedance state.

[0053] When the digital-to-analog conversion circuit body 20 is in a high-impedance state, the output of the digital-to-analog conversion circuit body 20 does not change due to the presence of parasitic capacitance in the circuit, that is, the parasitic capacitance has the effect of short-time clamping the output of the digital-to-analog conversion circuit body 20.

[0054] Under the control of the control circuit 10, the duration of the digital-to-analog conversion circuit body 20 entering the high-impedance state will last for a first duration. The specific value of the first duration can be set and adjusted according to actual needs, but it can be understood that in order to achieve a higher conversion speed of the DAC, the first duration will be set shorter.

[0055] After the first period of time, the digital-to-analog conversion circuit main body 20 can exit the high-impedance state. At this time, since the DAC digital input signal has been sent to the digital-to-analog conversion circuit main body 20, the state of the digital-to-analog conversion circuit main body 20 can be controlled based on the DAC digital input signal, so that the digital-to-analog conversion circuit main body 20 outputs the corresponding analog signal based on the DAC digital input signal, that is, the digital-to-analog conversion circuit main body 20 realizes the digital-to-analog conversion function according to the DAC digital input signal.

[0056] See also Figure 6 , is a schematic diagram of the structure of a control circuit 10 in a specific implementation mode, in which the control circuit 10 includes: a pulse generating circuit 11, a synchronization circuit 12 and a target switching circuit;

[0057] The pulse generating circuit 11 is used to: read the DAC sampling signal through its own input terminal, and after reading, send a pulse signal lasting a first time length to the digital-to-analog conversion circuit main body 20 and the target switch circuit, so that during the first time length of the pulse signal, the target switch circuit is in an off state, and the digital-to-analog conversion circuit main body 20 is in a high-impedance state;

[0058] The synchronization circuit 12 is used to: read the DAC sampling signal through its first input terminal, read the DAC digital input signal through its second input terminal, and after reading the DAC sampling signal, send the DAC digital input signal to the digital-to-analog conversion circuit body 20, so that after the pulse signal ends, the DAC digital input signal is used to control the state of the digital-to-analog conversion circuit body 20, so that the digital-to-analog conversion circuit body 20 outputs a corresponding analog signal based on the DAC digital input signal;

[0059] The digital-to-analog conversion circuit main body 20 includes N switching circuits and an R-2R resistor circuit. The ground end of the R-2R resistor circuit is grounded through the target switching circuit. The output end of the R-2R resistor circuit serves as the output end of the digital-to-analog conversion circuit main body 20. The N signal input ends of the R-2R resistor circuit are respectively connected to the N switching circuits. N is a positive integer, which represents the number of bits of the digital-to-analog conversion circuit main body 20.

[0060] In this implementation, the pulse generating circuit 11 can read the DAC sampling signal through its own input terminal, and after reading, it will generate a pulse signal lasting a first time length. Figure 6 The pulse signal is marked as VP in FIG. 1 , and the pulse generating circuit 11 sends the pulse signal to the digital-to-analog conversion circuit body 20 and the target switch circuit.

[0061] When the pulse generating circuit 11 sends a pulse signal to the digital-to-analog conversion circuit body 20, it can specifically send a pulse signal to all N switch circuits in the digital-to-analog conversion circuit body 20, so that all N switch circuits in the digital-to-analog conversion circuit body 20 are in a high-impedance state. Figure 6 In the figure, N=4, so four switch circuits are shown, which are called SW0, SW1, SW2 and SW3 respectively.

[0062] In addition, it should be noted that since in the digital-to-analog conversion circuit main body 20, in addition to the N switch circuits that can be grounded, the digital-to-analog conversion circuit main body 20 also has a ground terminal, that is, the ground terminal of the R-2R resistance circuit. Therefore, in order to make the digital-to-analog conversion circuit main body 20 in a high-impedance state, in addition to controlling the N switch circuits in the digital-to-analog conversion circuit main body 20 in a high-impedance state through a pulse signal, this ground terminal also needs to be left floating.

[0063] In this regard, in this implementation, it is achieved by setting up a target switching circuit, and the ground end of the R-2R resistor circuit is grounded through the target switching circuit. During the duration of the pulse signal, the target switching circuit is in the off state, so that the ground end of the R-2R resistor circuit is not grounded at this time, thereby realizing the high impedance state of the digital-to-analog conversion circuit main body 20.

[0064] The first input end of the synchronization circuit 12 can read the DAC sampling signal, and the second input end of the synchronization circuit 12 can read the DAC digital input signal. As described above, the DAC sampling signal plays a triggering role, that is, after reading the DAC sampling signal, the synchronization circuit can send the DAC digital input signal to the digital-to-analog conversion circuit body 20. And from the above description, it can be seen that before the end of the pulse signal, although the DAC digital input signal has been transmitted to the corresponding switch circuit in the digital-to-analog conversion circuit body 20, the digital-to-analog conversion circuit body 20 is in a high-impedance state at this time. Therefore, only after the end of the pulse signal can the state of the digital-to-analog conversion circuit body 20 be controlled based on the DAC digital input signal, so that the digital-to-analog conversion circuit body 20 outputs the corresponding analog signal based on the DAC digital input signal.

[0065] In a specific implementation of the present invention, the DAC sampling signal read by the control circuit 10 is a DAC sampling signal sent by the sampling control circuit according to a preset period.

[0066] It can be understood that the DAC digital input signal usually includes multiple bits, and different bits may be transmitted to the control circuit 10 in sequence. Therefore, in the solution of the present application, the DAC sampling signal is used to trigger, and in actual applications it is usually triggered periodically, that is, the DAC sampling signal read by the control circuit 10 can be a DAC sampling signal sent by the sampling control circuit according to a preset period.

[0067] It can be seen from the above description that the target switch circuit of the present application is in the off state when receiving the pulse signal. The specific structure can be set and adjusted according to actual needs. For example, in a specific implementation of the present invention, refer to Figure 6 , the target switch circuit may include: a first inverter INV1 and a first target switch SWZ;

[0068] The input end of the first NOT gate INV1 is used as the input end of the target switch circuit and is connected to the output end of the pulse generating circuit 11. The output end of the first NOT gate INV1 is connected to the control end of the first target switch SWZ. The first end of the first target switch SWZ is connected to the ground end of the R-2R resistor circuit. The second end of the first target switch SWZ is grounded.

[0069] When the control terminal of the first target switch SWZ is at a high level, the first target switch SWZ is in an on state, and when the control terminal of the first target switch SWZ is at a low level, the first target switch SWZ is in an off state.

[0070] In this embodiment, when the pulse generating circuit 11 outputs a pulse signal, the pulse signal is sent to the input end of the first invertor INV1, so the output end of the first invertor INV1 is at a low level. Since the output end of the first invertor INV1 is connected to the control end of the first target switch SWZ, and the first target switch SWZ is a switch that is turned on at a high level at the control end, the first target switch SWZ is in an off state at this time, which makes the ground end of the R-2R resistor circuit in a high impedance state at this time, achieving the purpose of this application. Correspondingly, after the pulse signal ends, the control end of the first target switch SWZ becomes a high level, and the first target switch SWZ is in a conducting state, so that the ground end of the R-2R resistor circuit can be normally grounded at this time, so that the digital-to-analog conversion circuit body 20 can normally realize its digital-to-analog conversion function.

[0071] In practical applications, considering that the first target switch SWZ needs to switch the on-off state at a high frequency, and the MOS tube has the advantages of high input impedance, low driving power, and fast switching speed, the first target switch SWZ can usually be selected as an NMOS switch tube. Figure 6 This implementation method is also adopted in .

[0072] In another specific embodiment of the present invention, the target switch circuit includes: a second target switch;

[0073] The control end of the second target switch serves as the input end of the target switch circuit, the first end of the second target switch is connected to the ground end of the R-2R resistor circuit, and the second end of the second target switch is grounded;

[0074] When the control terminal of the second target switch is at a low level, the first target switch is in an on state, and when the control terminal of the second target switch is at a high level, the second target switch is in an off state.

[0075] This embodiment takes into account that the target switch circuit can be composed of a second target switch. When the pulse generating circuit 11 outputs a pulse signal, the pulse signal is sent to the control end of the second target switch. Since the second target switch is a switch that is turned on when the control end is at a low level, the second target switch is in an off state at this time, which makes the ground end of the R-2R resistor circuit in a high impedance state at this time, thereby achieving the purpose of this application. Correspondingly, after the pulse signal ends, the control end of the second target switch becomes a low level, and the second target switch is in a conducting state, so that the ground end of the R-2R resistor circuit can be normally grounded at this time, so that the digital-to-analog conversion circuit body 20 can normally realize its digital-to-analog conversion function.

[0076] For example, in practical applications, a PMOS tube may be used to implement the second target switch in this implementation.

[0077] In a specific implementation of the present invention, any one of the N switch circuits may include: a second NOT gate INV2, a third NOT gate INV3, a first OR gate OR, a first AND gate AND, a first switch tube M1 and a second switch tube M2. Figure 7 , showing the structure of a single switch circuit among the N switch circuits in this implementation.

[0078] The input end of the second NOT gate INV2 is used as the digital signal input end of the switch circuit, the output end of the second NOT gate INV2 is connected to the first input end of the first OR gate OR and the first input end of the first AND gate AND respectively, and the output end of the third NOT gate INV3 is connected to the second input end of the first AND gate AND;

[0079] The second input end of the first OR gate OR is connected to the input end of the third NOT gate INV3, and the connection end serves as the pulse signal input end of the switch circuit, the output end of the first OR gate OR is connected to the control end of the first switch tube M1, and the output end of the first AND gate AND is connected to the control end of the second switch tube M2;

[0080] The second end of the first switch tube M1 is connected to the first end of the second switch tube M2, and the connecting end serves as the output end of the switch circuit. The first end of the first switch tube M1 is connected to the positive electrode of the first power supply, and the second end of the second switch tube M2 is grounded.

[0081] The pulse signal input terminals of the N switch circuits are all connected to the pulse generating circuit 11 to receive the pulse signal, the digital signal input terminals of the N switch circuits are all connected to the synchronization circuit 12 to receive the DAC digital input signal of the corresponding bit, and the output terminals of the N switch circuits are connected to the corresponding N signal input terminals of the R-2R resistor circuit;

[0082] Among them, when the control end of the first switch tube M1 is at a high level, the first switch tube M1 is in an off state, and when the control end of the first switch tube M1 is at a low level, the first switch tube M1 is in an on state; when the control end of the second switch tube M2 is at a low level, the second switch tube M2 is in an off state, and when the control end of the second switch tube M2 is at a high level, the second switch tube M2 is in an on state.

[0083] Specifically, the input end of the second NOT gate INV2 serves as the digital signal input end of the switch circuit. Figure 7 In the example, the digital signal input terminal of the switch circuit is marked as DI, and the output terminal of the switch circuit is marked as DO. For example, DI can be specifically Figure 6 If DI0 or DI1 or DI2 or DI3 is in the DO, then DO can be Figure 6 DO0 or DO1 or DO2 or DO3 in the .

[0084] It can be seen from the structure of the switch circuit in this embodiment that the second input terminal of the first OR gate OR is connected to the input terminal of the third NOT gate INV3, and the connection terminal serves as the pulse signal input terminal of the switch circuit, that is, the pulse signal input terminal is used to receive the pulse signal. Figure 7 Marked as VP in the middle, when VP is received, the output of the first OR gate OR is 1, that is, a high level, and the output of the first AND gate AND is 0, that is, a low level.

[0085] The first switch tube M1 is a switch tube that is turned on when the control end is at a low level, and the second switch tube M2 is a switch tube that is turned on when the control end is at a high level. Since the output of the first OR gate OR is 1 when the pulse signal is not over, the first switch tube M1 is in the off state at this time, and since the output of the first AND gate AND is 0, the second switch tube M2 is also in the off state at this time, so that at this time, the output end of the switch circuit is neither connected to the positive electrode of the first power supply nor to the ground, that is, it is in a high impedance state at this time.

[0086] After the pulse signal ends, the conduction states of the first switch tube M1 and the second switch tube M2 are determined by the digital signal received by the switch circuit, that is, by the level of the digital signal input terminal DI.

[0087] For example, when the digital signal input terminal DI is at a high level, it can be seen from the circuit connection relationship that at this time, the control terminal of the first switch tube M1 is at a low level, so that the first switch tube M1 is in a conducting state. Since the first switch tube M1 is turned on, the output end of the switch circuit is connected to the positive electrode of the first power supply. The control terminal of the second switch tube M2 is also at a low level at this time, so that the second switch tube M2 continues to be in an off state. It can be seen that after the pulse signal ends, when the digital signal input terminal DI is at a high level, the switch circuit switches from a high impedance state to a state connected to the positive electrode of the first power supply, that is, switches to a high level state.

[0088] Correspondingly, if after the pulse signal ends, the digital signal input terminal DI is at a low level, it can be seen from the circuit connection relationship that at this time, the control terminal of the first switch tube M1 is at a high level, so that the first switch tube M1 continues to be in the off state. The control terminal of the second switch tube M2 is also at a high level at this time, so that the second switch tube M2 is turned on. Since the second switch tube M2 is turned on, the output end of the switch circuit is grounded. It can be seen that after the pulse signal ends, when the digital signal input terminal DI is at a low level, the switch circuit switches from a high impedance state to a state connected to the ground, that is, it switches to a grounded state.

[0089] In this embodiment of the present application, the specific types of the first switch tube M1 and the second switch tube M2 can be set and adjusted according to actual needs, but it can be understood that the first switch tube M1 in this embodiment needs to be a switch tube that is turned on when the control terminal is at a low level, and the second switch tube M2 is a switch tube that is turned on when the control terminal is at a high level. In a specific embodiment of the present invention, considering that the first switch tube M1 and the second switch tube M2 need to switch the switch state at a high frequency, the first switch tube M1 can be specifically selected as a PMOS switch tube, and the second switch tube M2 is an NMOS switch tube. Figure 7 This implementation method is adopted in .

[0090] See also Figure 8 , is a working timing diagram of the switching circuit in this embodiment, which represents, from top to bottom, the DAC sampling signal, the signal at the digital signal input terminal DI of the switching circuit, the pulse signal VP, the signal at the output terminal DO of the switching circuit, and the output signal of the digital-to-analog conversion circuit body 20.

[0091] In a specific embodiment of the present invention, any one of the N switching circuits is a relay-based switching circuit. When the switching circuit receives a pulse signal, its output end is in a floating state. When the switching circuit does not receive a pulse signal and receives a high-level DAC digital input signal, its output end is connected to the positive electrode of the second power supply. When the switching circuit does not receive a pulse signal and receives a low-level DAC digital input signal, its output end is grounded.

[0092] In this implementation, any one of the N switch circuits can be implemented based on a relay, that is, the switch circuit is a switch circuit based on a relay. When the switch circuit receives a pulse signal, it is necessary to control its own output end to be suspended, thereby realizing a high impedance state of the switch circuit. Correspondingly, after the pulse signal ends, if a high-level DAC digital input signal is received, its own output end needs to be connected to the positive electrode of the second power supply, and if a low-level DAC digital input signal is received, its own output end is grounded.

[0093] See also Fig. 9 , from top to bottom are the ideal DAC conversion schematic diagram, the burr schematic diagram of the traditional DAC switching solution, and the conversion schematic diagram of the digital-to-analog conversion circuit of the present application in one occasion. It can be seen that, Fig. 9 The first time duration Tz represents the timing duration of the high impedance state, that is, the duration of the pulse signal. It can be seen that the solution of the present application can effectively eliminate glitches, thereby improving the conversion speed of the DAC.

[0094] The technical solution provided in the embodiment of the present invention adopts a digital-to-analog conversion circuit body 20 based on an R-2R resistor network, that is, the digital-to-analog conversion circuit of the present application adopts an RR-2R DAC architecture. Therefore, the solution of the present application can have the accuracy and area advantages of R-2R.

[0095] The present application takes into account that in the traditional solution, due to the process deviation of components, the deviation of physical metal routing and other reasons, the control signals of each switch in the R-2R DAC architecture are inconsistent, resulting in output glitches. In this regard, in the solution of the present application, after reading the DAC sampling signal and the DAC digital input signal, the control circuit 10 will send the DAC digital input signal to the digital-to-analog conversion circuit body 20, but the DAC digital input signal will not take effect at this time, because after reading the DAC sampling signal and the DAC digital input signal, the control circuit 10 will also control the digital-to-analog conversion circuit body 20 to be in a high-impedance state, and the high-impedance state will last for a certain period of time, that is, the first period of time. Therefore, it can be understood that during the period of time when the digital-to-analog conversion circuit body 20 is in the high-impedance state, it plays a buffering role. Even if there are process deviations in components and deviations in physical metal routing, during the period of the high-impedance state, the DAC digital input signal can be transmitted to each switch circuit in the digital-to-analog conversion circuit body 20. Of course, since the high-impedance state has not ended, analog-to-digital conversion will not be performed at this time. After the first time period, the high impedance state of the digital-to-analog conversion circuit body 20 ends. Therefore, under the control of the DAC digital input signal, the state of the digital-to-analog conversion circuit body 20 will be changed accordingly, so that the digital-to-analog conversion circuit body 20 outputs the corresponding analog signal based on the DAC digital input signal, so that the digital-to-analog conversion circuit completes the digital-to-analog conversion function.

[0096] Due to the presence of parasitic capacitance in the circuit, when the main body 20 of the digital-to-analog conversion circuit is in a high-impedance state, its output will not change, that is, it has a clamping effect and therefore no burrs will appear. It should also be noted that in the conventional scheme, when the switch circuit in the main body 20 of the digital-to-analog conversion circuit is switched, it undergoes a process of "connecting to a high level-switching to grounding" or a process of "grounding-switching to connecting to a high level". As described above, the speeds of these two processes are not consistent, and thus burrs will also be caused. In the scheme of the present application, since the state of the main body 20 of the digital-to-analog conversion circuit is controlled to be a high-impedance state, it can be understood that in the high-impedance state, each switch circuit in the main body 20 of the digital-to-analog conversion circuit is in a suspended state, that is, it is neither connected to a high level nor to grounding, and after the high-impedance state ends, the switch circuit undergoes a process of "high-impedance state-switching to connecting to a high level" or a process of "high-impedance state-switching to grounding". The speed difference between these two processes is very small and will not cause burrs.

[0097] In summary, the solution of the present application can have the accuracy and area advantages of R-2R. At the same time, for the glitch problem caused by inconsistent control signals of the switching circuit and inconsistent switching speed in the traditional solution, the solution of the present application can effectively eliminate the switching glitch by first entering the high-impedance state, thereby improving the conversion speed of the DAC.

[0098] Corresponding to the above digital-to-analog conversion circuit embodiments, an embodiment of the present invention further provides a digital-to-analog converter, which may include a digital-to-analog conversion circuit as in any of the above embodiments, which will not be described again here.

[0099] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0100] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0101] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A digital-to-analog conversion circuit, characterized in that: include: A control circuit and a digital-to-analog conversion circuit body based on an R-2R resistor network connected to the control circuit; The control circuit is used to: read the DAC sampling signal and the DAC digital input signal, and after reading, send the DAC digital input signal to the digital-to-analog conversion circuit body, and control the digital-to-analog conversion circuit body to be in a high-impedance state; After the duration of the digital-to-analog conversion circuit body entering the high-impedance state reaches a first duration, the state of the digital-to-analog conversion circuit body is controlled using the DAC digital input signal so that the digital-to-analog conversion circuit body outputs a corresponding analog signal based on the DAC digital input signal.

2. The digital-to-analog conversion circuit according to claim 1, characterized in that: The control circuit includes: a pulse generating circuit, a synchronization circuit and a target switching circuit; The pulse generating circuit is used to: read the DAC sampling signal through its own input terminal, and after reading, send a pulse signal lasting a first time length to the digital-to-analog conversion circuit body and the target switch circuit, so that during the first time length of the pulse signal, the target switch circuit is in an off state, and the digital-to-analog conversion circuit body is in a high-impedance state; The synchronization circuit is used to: read the DAC sampling signal through its first input terminal, read the DAC digital input signal through its second input terminal, and after reading the DAC sampling signal, send the DAC digital input signal to the digital-to-analog conversion circuit body, so that after the pulse signal ends, the state of the digital-to-analog conversion circuit body is controlled by using the DAC digital input signal, so that the digital-to-analog conversion circuit body outputs a corresponding analog signal based on the DAC digital input signal; The digital-to-analog conversion circuit body includes N switch circuits and an R-2R resistor circuit. The ground end of the R-2R resistor circuit is grounded through the target switch circuit. The output end of the R-2R resistor circuit serves as the output end of the digital-to-analog conversion circuit body. The N signal input ends of the R-2R resistor circuit are respectively connected to the N switch circuits. N is a positive integer, which represents the number of bits of the digital-to-analog conversion circuit body.

3. The digital-to-analog conversion circuit according to claim 2, characterized in that: The target switch circuit comprises: a first NOT gate and a first target switch; The input end of the first NOT gate serves as the input end of the target switch circuit and is connected to the output end of the pulse generating circuit, the output end of the first NOT gate is connected to the control end of the first target switch, the first end of the first target switch is connected to the ground end of the R-2R resistor circuit, and the second end of the first target switch is grounded; When the control terminal of the first target switch is at a high level, the first target switch is in an on state, and when the control terminal of the first target switch is at a low level, the first target switch is in an off state.

4. The digital-to-analog conversion circuit according to claim 3, characterized in that: The first target switch is an NMOS switch tube.

5. The digital-to-analog conversion circuit according to claim 2, characterized in that: The target switch circuit includes: a second target switch; The control end of the second target switch serves as the input end of the target switch circuit, the first end of the second target switch is connected to the ground end of the R-2R resistor circuit, and the second end of the second target switch is grounded; When the control terminal of the second target switch is at a low level, the first target switch is in an on state, and when the control terminal of the second target switch is at a high level, the second target switch is in an off state.

6. The digital-to-analog conversion circuit according to any one of claims 2 to 5, characterized in that: Any one of the N switch circuits comprises: a second NOT gate, a third NOT gate, a first OR gate, a first AND gate, a first switch tube and a second switch tube; The input end of the second NOT gate serves as the digital signal input end of the switch circuit, the output end of the second NOT gate is respectively connected to the first input end of the first OR gate and the first input end of the first AND gate, and the output end of the third NOT gate is connected to the second input end of the first AND gate; The second input end of the first OR gate is connected to the input end of the third NOT gate, and the connection end serves as the pulse signal input end of the switch circuit, the output end of the first OR gate is connected to the control end of the first switch tube, and the output end of the first AND gate is connected to the control end of the second switch tube; The second end of the first switch tube is connected to the first end of the second switch tube, and the connecting end serves as the output end of the switch circuit, the first end of the first switch tube is connected to the positive electrode of the first power supply, and the second end of the second switch tube is grounded; The pulse signal input terminals of the N switch circuits are all connected to the pulse generating circuit to receive the pulse signal, the digital signal input terminals of the N switch circuits are all connected to the synchronization circuit to receive the DAC digital input signal of the corresponding bit, and the output terminals of the N switch circuits are connected to the corresponding N signal input terminals of the R-2R resistor circuit; Among them, when the control end of the first switch tube is at a high level, the first switch tube is in an off state, and when the control end of the first switch tube is at a low level, the first switch tube is in an on state; when the control end of the second switch tube is at a low level, the second switch tube is in an off state, and when the control end of the second switch tube is at a high level, the second switch tube is in an on state.

7. The digital-to-analog conversion circuit according to claim 6, characterized in that: The first switch tube is a PMOS switch tube, and the second switch tube is an NMOS switch tube.

8. The digital-to-analog conversion circuit according to any one of claims 2 to 5, characterized in that: Any one of the N switching circuits is a switching circuit based on a relay. When the switching circuit receives the pulse signal, its output end is in a floating state. When the switching circuit does not receive the pulse signal and receives a high-level DAC digital input signal, its output end is connected to the positive electrode of the second power supply. When the switching circuit does not receive the pulse signal and receives a low-level DAC digital input signal, its output end is grounded.

9. The digital-to-analog conversion circuit according to claim 1, characterized in that: The DAC sampling signal read by the control circuit is a DAC sampling signal sent by the sampling control circuit according to a preset period.

10. A digital-to-analog converter, characterized in that: The method comprises the digital-to-analog conversion circuit as claimed in any one of claims 1 to 9.

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