Semiconductor device with adjustable switching speed

Abstract

The invention provides a semiconductor device with adjustable switching speed, and belongs to the technical field of semiconductor devices. The semiconductor device comprises a cascode semiconductor device and a switching speed regulation unit, wherein the switching speed regulation unit comprises a first resistor, a second resistor and a first diode. The grid electrode of the high-voltage depletion type gallium nitride power transistor is connected with one end of the first resistor and one end of the second resistor, the other end of the first resistor is connected with the input end of the first diode, and the output end of the first diode and the other end of the second resistor are connected with the source electrode of the low-voltage enhancement type metal oxide semiconductor field effect transistor; and the second resistor triggers the transient voltage change rate between the source electrode and the drain electrode of the low-voltage enhanced metal oxide semiconductor field effect transistor to adjust under the control of the controller. According to the invention, the switching speed of the cascode semiconductor device can be controlled, so that the stress and electromagnetic compatibility of a rectifier tube of an application system can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device with adjustable switching speed. Background Art

[0002] Cascode semiconductor devices are usually composed of a low-voltage enhancement-mode metal-oxide-semiconductor field-effect transistor (MOS) and a high-voltage depletion-mode gallium nitride power transistor in series. The cascode semiconductor device enables the high-voltage depletion-mode gallium nitride power transistor to obtain the switching characteristics of the enhancement-mode MOS tube, but because the switching speed of the high-voltage depletion-mode gallium nitride power transistor cannot be directly controlled, the application system cannot well improve the stress and electromagnetic compatibility of the rectifier tube.

[0003] In the related art, there are two main ways to adjust the switching speed of a common-source and common-gate semiconductor device. The first is to adjust the gate drive resistance of a low-voltage enhancement-mode MOS tube. The second is to add a cascade device Miller capacitor to the common-source and common-gate semiconductor device so that a direct controlled relationship is formed between the drive of the low-voltage enhancement-mode MOS tube and the cascade device, so as to reduce the transient voltage change rate between the source and the drain of the low-voltage enhancement-mode MOS tube by directly adjusting the gate drive resistance of the low-voltage enhancement-mode MOS tube, so as to control the switching speed of the high-voltage depletion-mode gallium nitride power transistor.

[0004] However, when adjusting the switching speed of the common-source and common-gate semiconductor devices based on the relevant technology, the gate drive resistance of the low-voltage enhancement MOS tube in the first solution is too large, causing the common-source and common-gate semiconductor device to fail, and the gate drive resistance of the low-voltage enhancement MOS tube cannot directly adjust the switching speed of the high-voltage depletion-type gallium nitride power transistor, resulting in poor switching speed adjustment effect; the second solution will introduce drive oscillation, resulting in reduced reliability of the application system. Summary of the invention

[0005] The purpose of the present application is to provide a semiconductor device with adjustable switching speed, which can control the switching speed of the common-source and common-gate semiconductor device to improve the stress and electromagnetic compatibility of the rectifier tube of the application system.

[0006] The embodiment of the present application is implemented as follows:

[0007] According to a first aspect of an embodiment of the present application, a semiconductor device with adjustable switching speed is provided, the semiconductor device comprising: a common-source common-gate semiconductor device and a switching speed adjustment unit, the common-source common-gate semiconductor device comprising: a low-voltage enhancement metal oxide semiconductor field effect transistor and a high-voltage depletion-mode gallium nitride power transistor, the common-source common-gate semiconductor device is packaged on a chip, and the switching speed adjustment unit comprises: a first resistor, a second resistor and a first diode;

[0008] The drain of the low-voltage enhancement mode metal oxide semiconductor field effect transistor in the common source and common gate semiconductor device is connected to the source of the high-voltage depletion mode gallium nitride power transistor, and the source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor is connected to the gate of the high-voltage depletion mode gallium nitride power transistor;

[0009] The gate of the high-voltage depletion-mode gallium nitride power transistor is also connected to one end of a first resistor and one end of a second resistor in the switching speed adjustment unit, the other end of the first resistor is connected to the input end of the first diode, the output end of the first diode and the other end of the second resistor are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor, and the first resistor and the second resistor are also used for an external controller;

[0010] The gate of the low-voltage enhancement mode metal oxide semiconductor field effect transistor is externally connected to a driving circuit, and the source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor and the drain of the high-voltage depletion mode gallium nitride power transistor are both externally connected to a power loop;

[0011] The resistance value of the second resistor in the switching speed adjustment unit is adjusted under the control of the controller to trigger the transient voltage change rate between the source and the drain of the low-voltage enhancement metal oxide semiconductor field effect transistor to adjust the switching speed of the low-voltage enhancement metal oxide semiconductor field effect transistor and the high-voltage depletion-type gallium nitride power transistor.

[0012] As a possible implementation manner, the first resistor, the second resistor, and the first diode in the switching speed adjustment unit are all packaged on the same chip as the common-source and common-gate semiconductor device.

[0013] As a possible implementation manner, the first resistor, the second resistor, and the first diode are all integrated on a high-voltage depletion-mode gallium nitride power transistor in a common-source common-gate semiconductor device.

[0014] As a possible implementation manner, the first resistor, the second resistor, and the first diode are packaged together on a silicon substrate of a chip where the cascode semiconductor device is located.

[0015] As a possible implementation manner, the first resistor, the second resistor, and the first diode are all integrated on a low-voltage enhancement mode metal oxide semiconductor field effect transistor in a common source and common gate semiconductor device.

[0016] As a possible implementation manner, the first resistor, the second resistor, and the first diode in the switching speed adjustment unit are packaged on a printed circuit board outside the chip where the common-source and common-gate semiconductor device is located.

[0017] As a possible implementation, the second resistor in the switching speed adjustment unit is packaged on a printed circuit board outside the chip where the common source and common gate semiconductor device is located, and the first resistor and the first diode in the switching speed adjustment unit are packaged on the same chip as the common source and common gate semiconductor device.

[0018] As a possible implementation manner, the first resistor and the first diode are both integrated on a high-voltage depletion-mode gallium nitride power transistor in a common-source and common-gate semiconductor device.

[0019] As a possible implementation manner, the first resistor and the first diode are both integrated on a low-voltage enhancement mode metal oxide semiconductor field effect transistor in a cascode semiconductor device.

[0020] As a possible implementation manner, the first resistor and the first diode are packaged together on a silicon substrate of a chip where the cascode semiconductor device is located.

[0021] As a possible implementation, the first resistor and the first diode in the switching speed adjustment unit are packaged on a printed circuit board outside the chip where the common source and common gate semiconductor device is located, and the second resistor in the switching speed adjustment unit is packaged on the same chip as the common source and common gate semiconductor device.

[0022] As a possible implementation manner, the second resistor is integrated on a high-voltage depletion-mode gallium nitride power transistor in a cascode semiconductor device.

[0023] As a possible implementation manner, the second resistor is integrated on a low-voltage enhancement mode metal oxide semiconductor field effect transistor in the cascode semiconductor device.

[0024] As a possible implementation manner, the second resistor is packaged on a silicon substrate of a chip where the cascode semiconductor device is located.

[0025] As a possible implementation, the switching speed adjustment unit also includes: a second diode, an input end of the first diode and one end of the second resistor are both connected to the gate of the high-voltage depletion-type gallium nitride power transistor, an output end of the first diode is connected to one end of the first resistor, the other end of the second resistor is connected to the output end of the second diode, and the other end of the first resistor and the input end of the second diode are both connected to the source of the low-voltage enhancement-type metal oxide semiconductor field effect transistor.

[0026] The beneficial effects of the embodiments of the present application include:

[0027] The embodiment of the present application provides a semiconductor device with adjustable switching speed, which is composed of a common source and common gate semiconductor device and a switching speed adjustment unit, and the switching speed adjustment unit includes: a first resistor, a second resistor and a first diode. Among them, the source of the high-voltage depletion-type gallium nitride power transistor in the common source and common gate semiconductor device is connected to the drain of the low-voltage enhancement-type metal oxide semiconductor field effect transistor, and the gate of the high-voltage depletion-type gallium nitride power transistor is connected to the source of the low-voltage enhancement-type metal oxide semiconductor field effect transistor, so that the high-voltage depletion-type gallium nitride power transistor obtains the characteristics of an enhancement-type switch; the gate of the high-voltage depletion-type power transistor is also connected to one end of the first resistor and one end of the second resistor, the other end of the first resistor is connected to the input end of the first diode, and the output end of the first diode and the other end of the second resistor are both connected to the low-voltage enhancement-type metal oxide semiconductor field effect transistor. The source of the conductor field effect tube is connected, and the first resistor and the second resistor are also externally connected to a controller. The controller can adjust the resistance value of the second resistor, which directly causes the driving resistance value of the high-voltage depletion-type gallium nitride power transistor to change, thereby changing the transient voltage change rate between the source and drain of the low-voltage enhancement-type metal oxide semiconductor field effect tube, so that the switching speed of the common source and common gate semiconductor device is adjusted; the drain of the high-voltage depletion-type gallium nitride power transistor and the source of the low-voltage enhancement-type metal oxide semiconductor field effect tube are both externally connected to the power loop, and the gate of the low-voltage enhancement-type metal oxide semiconductor field effect tube is externally connected to the driving circuit. In this way, the switching speed of the common source and common gate semiconductor device can be controlled to improve the stress and electromagnetic compatibility of the rectifier tube of the application system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of a cascade structure of an existing common-source and common-gate semiconductor device;

[0030] Figure 2 A schematic diagram of a circuit structure for adjusting the switching speed of a common-source and common-gate semiconductor device;

[0031] Figure 3 A schematic structural diagram of a first semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0032] Figure 4A schematic diagram of the structure of a second semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of the structure of a third semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0034] Figure 6 A schematic structural diagram of a fourth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0035] Figure 7 A schematic structural diagram of a fifth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0036] Figure 8 A schematic structural diagram of a sixth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0037] Fig. 9 A schematic structural diagram of a seventh semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0038] Fig.10 A schematic structural diagram of an eighth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0039] Fig.11 A schematic diagram of the structure of a ninth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0040] Fig.12 A schematic diagram of the structure of a tenth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0041] Fig.13 A schematic structural diagram of an eleventh semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0042] Fig.14 A schematic structural diagram of a twelfth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0043] Fig.15 A schematic structural diagram of a thirteenth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0044] Fig.16 A schematic structural diagram of a fourteenth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0045] Fig.17 A voltage waveform diagram of each node in the first semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0046] Fig.18A voltage waveform diagram of each node in the second semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0047] Fig.19 A schematic diagram of a first operating mode of a semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0048] Fig. 20 A schematic diagram of a second working mode of a semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0049] Fig.21 A schematic diagram of a third working mode of a semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0050] Fig. 22 A schematic diagram of a fourth operating mode of a semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0051] Fig.23 A schematic diagram of a fifth working mode of a semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0052] Fig.24 A schematic diagram of an extended structure of a semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0053] Fig.25 A schematic structural diagram of a fifteenth semiconductor device with adjustable switching speed provided in an embodiment of the present application;

[0054] Fig.26 A schematic diagram of an extended structure of another semiconductor device with adjustable switching speed provided in an embodiment of the present application.

[0055] Description of the drawings: 10: a semiconductor device with adjustable switching speed; 101: a common-source common-gate semiconductor device; 1011: a low-voltage enhancement-mode metal-oxide-semiconductor field-effect transistor; 1012: a high-voltage depletion-mode gallium nitride power transistor; 102: a switching speed adjustment unit; 1021: a first resistor; 1022: a second resistor; 1023: a first diode; 1024: a second diode; 20: a chip; 201: a silicon substrate; 30: a printed circuit board. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0058] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0059] In the description of the present application, it should be noted that the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. It should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, and it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0060] At present, there are usually two ways to adjust the switching speed of a cascode semiconductor device. One is to adjust the switching speed of the cascode semiconductor device by adjusting the gate drive resistance of the low-voltage enhancement metal oxide semiconductor field effect transistor in the cascode semiconductor device; the other is to add a cascade device Miller capacitor in the cascode semiconductor device, that is, to add a Miller band content between the gate of the low-voltage enhancement metal oxide semiconductor field effect transistor and the source of the high-voltage depletion-type gallium nitride power transistor, so that a direct controlled relationship is formed between the drive of the low-voltage enhancement metal oxide semiconductor field effect transistor and the cascade Miller capacitor, so as to reduce the transient voltage change rate between the source and the drain of the low-voltage enhancement metal oxide semiconductor field effect transistor by directly adjusting the gate drive resistance of the low-voltage enhancement metal oxide semiconductor field effect transistor, so as to control the switching speed of the high-voltage depletion-type gallium nitride power transistor. However, the scheme of adjusting the switching speed of the cascode semiconductor device by adjusting the gate drive resistance of the low-voltage enhancement metal oxide semiconductor field effect transistor has the problem that the gate drive resistance is too large, which will cause the cascode semiconductor device to fail, and the gate drive resistance of the low-voltage enhancement metal oxide semiconductor field effect transistor cannot directly adjust the switching speed of the high-voltage depletion-type gallium nitride power transistor, resulting in poor switching speed adjustment effect. In addition, adjusting the switching speed of the cascode semiconductor device by adding a cascaded Miller capacitor will introduce drive oscillation, resulting in reduced reliability of the application system.

[0061] To this end, the embodiment of the present application provides a semiconductor device with adjustable switching speed, which is composed of a common source and common gate semiconductor device and a switching speed adjustment unit, and the switching speed adjustment unit includes: a first resistor, a second resistor and a first diode, one end of the first resistor and one end of the second resistor are both connected to the gate of the high-voltage depletion-type gallium nitride power transistor in the common source and common gate semiconductor device, the other end of the first resistor is connected to the input end of the first diode, the output end of the first diode and the other end of the second resistor are both connected to the source of the low-voltage enhancement-type metal oxide semiconductor field effect transistor in the common source and common gate semiconductor device, the first resistor and the second resistor are both externally connected to a controller, when the common source and common gate semiconductor device is turned on, the resistance value of the second resistor is adjusted under the control of the controller to trigger the transient voltage change rate between the source and the drain of the low-voltage enhancement-type metal oxide semiconductor field effect transistor to adjust the switching speed of the low-voltage enhancement-type metal oxide semiconductor field effect transistor and the high-voltage depletion-type gallium nitride power transistor. In this way, the switching speed of the common source and common gate semiconductor device can be controlled to improve the stress and electromagnetic compatibility of the rectifier tube of the application system.

[0062] Figure 1 is a schematic diagram of a cascade structure of an existing common-source and common-gate semiconductor device, see Figure 1 The existing common-source common-gate semiconductor device is formed by cascading a high-voltage depletion-type power transistor Q1 and a low-voltage enhancement-type metal oxide semiconductor field effect transistor Q2, wherein the gate of the high-voltage depletion-type power transistor Q1 is connected to the source of the low-voltage enhancement-type metal oxide semiconductor field effect transistor Q2, the source of the high-voltage depletion-type power transistor Q1 is connected to the drain of the low-voltage enhancement-type metal oxide semiconductor field effect transistor Q2, the drain of the high-voltage depletion-type power transistor Q1 and the source of the low-voltage enhancement-type metal oxide semiconductor field effect transistor Q2 are both externally connected to a power loop, and the gate of the low-voltage enhancement-type metal oxide semiconductor field effect transistor Q2 is externally connected to a driving circuit.

[0063] Optionally, when the low voltage enhancement metal oxide semiconductor field effect transistor Q2 is turned off, the normally open high voltage device Q1 will generate a negative gate voltage, so that the high voltage depletion type gallium nitride power transistor Q1 is passively turned off. Among them, the high voltage depletion type gallium nitride power transistor Q1 cannot be used alone, and the common source and common gate semiconductor device enables the high voltage depletion type gallium nitride power transistor Q1 to obtain the characteristics of an enhancement type switch, but because the high voltage depletion type gallium nitride power transistor Q1 cannot be directly controlled, the common source and common gate semiconductor device cannot well adjust the transient voltage change rate dv / dt between the drain and the source of the low voltage enhancement type metal oxide semiconductor field effect transistor Q2, and cannot well improve the stress and electromagnetic compatibility of the rectifier tube in the application system.

[0064] Figure 2FIG. 1 is a schematic diagram of a circuit structure for adjusting the switching speed of a common-source common-gate semiconductor device. Figure 2 , the gate of the low-voltage enhancement metal oxide semiconductor field effect transistor Q2 is connected to a driving resistor Rg_M, and the switching speed of the common source and common gate semiconductor device is controlled by adjusting the gate driving resistor Rg_M of the low-voltage enhancement metal oxide semiconductor field effect transistor Q2. However, an excessively large gate driving resistor Rg_M will cause the low-voltage enhancement metal oxide semiconductor field effect transistor Q2 to operate outside the SQA region, that is, the low-voltage enhancement metal oxide semiconductor field effect transistor Q2 exceeds the safe operating area, making the common source and common gate semiconductor device fail, and the gate driving resistor Rg_M of the low-voltage enhancement metal oxide semiconductor field effect transistor Q2 cannot directly adjust the switching speed of the depletion transistor, resulting in little effect on the switching speed adjustment of the common source and common gate semiconductor device.

[0065] Optionally, a cascade device Miller capacitor Cgd is added to the common-source and common-gate semiconductor device, one end of the Miller capacitor Cgd is connected to the gate of the low-voltage enhancement metal oxide semiconductor field effect transistor Q2, and the other end of the Miller capacitor Cgd is connected to the drain of the high-voltage depletion-type gallium nitride power transistor Q1. The Miller capacitor Cgd directly forms a controlled relationship between the driving resistance of the low-voltage enhancement metal oxide semiconductor field effect transistor Q1 and the cascade device Miller capacitor Cgd, thereby directly adjusting the gate driving resistance Rg_M of the low-voltage enhancement metal oxide semiconductor field effect transistor Q2 to reduce the dv / dt of the low-voltage enhancement metal oxide semiconductor field effect transistor Q2. However, the Miller capacitor Cgd will introduce driving oscillation.

[0066] The semiconductor device with adjustable switching speed provided in the embodiments of the present application is explained in detail below with reference to the accompanying drawings.

[0067] Figure 3 A schematic diagram of a semiconductor device with adjustable switching speed provided in this application, see Figure 3 The embodiment of the present application provides a semiconductor device 10 with adjustable switching speed, including: a common source and common gate semiconductor device 101 and a switching speed adjustment unit 102, the common source and common gate semiconductor device 101 includes: a low-voltage enhancement metal oxide semiconductor field effect transistor 1011 and a high-voltage depletion-type gallium nitride power transistor 1012, the common source and common gate semiconductor device 101 is packaged on a chip 20, and the switching speed adjustment unit 102 includes: a first resistor 1021, a second resistor 1022 and a first diode 1023.

[0068] In the cascode semiconductor device 101 , the drain of the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 is connected to the source of the high voltage depletion mode gallium nitride power transistor 1012 , and the source of the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 is connected to the gate of the high voltage depletion mode gallium nitride power transistor 1012 .

[0069] Optionally, in the cascode semiconductor device 101, the drain of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 is connected to the source of the high-voltage depletion-mode gallium nitride power transistor 1012, and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 is connected to the gate of the high-voltage depletion-mode gallium nitride power transistor 1012. This structure enables the high-voltage depletion-mode gallium nitride power transistor 1012 to obtain the characteristics of an enhancement-mode switch.

[0070] The gate of the high-voltage depletion-mode gallium nitride power transistor 1012 is also connected to one end of the first resistor 1021 and one end of the second resistor 1022 in the switching speed adjustment unit 102. The other end of the first resistor 1021 is connected to the input end of the first diode 1023. The output end of the first diode 1023 and the other end of the second resistor 1022 are both connected to the source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011. The first resistor 1021 and the second resistor 1022 are also used for an external controller.

[0071] Optionally, the gate of the high-voltage depletion-mode gallium nitride power transistor 1012 is connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 via the switching speed adjustment unit 102, one end of the first resistor 1021 and one end of the second resistor 1022 in the switching speed adjustment unit 102 are both connected to the gate of the high-voltage depletion-mode gallium nitride power transistor 1012, the other end of the first resistor 1021 in the switching speed adjustment unit 102 is connected to the input end of the first diode 1023, the output end of the first diode 1023 in the switching speed adjustment unit 102 and the other end of the second resistor 1022 are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011, and the first resistor 1021 and the second resistor 1022 are also externally connected to a controller.

[0072] Optionally, the controller may be a control unit built into the chip 20, or a microcontroller disposed on the printed circuit board 30 where the chip 20 is located, etc., and this application does not make specific limitations on this. It is worth noting that the first resistor 1021 and the second resistor 1022 may not be externally connected to a controller, and the first resistor 1021 and the second resistor 1022 may also achieve voltage division and current division under the condition that the common source and common gate semiconductor device 101 is running, thereby changing the voltage change rate between the drain and the source of the low voltage enhancement metal oxide semiconductor field effect transistor 1011.

[0073] The gate of the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 is externally connected to a driving circuit, and the source of the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 and the drain of the high voltage depletion mode gallium nitride power transistor 1012 are both externally connected to a power loop.

[0074] Optionally, the power circuit is used to indicate a power circuit using the cascode semiconductor device 101. The cascode semiconductor device 101 can be regarded as a switching device of the power circuit. The driving circuit is used to drive the conduction and shutdown of the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 in the cascode semiconductor device 101. The driving circuit can directly apply a driving voltage to the gate of the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011.

[0075] The resistance of the second resistor 1022 in the switching speed adjustment unit 102 is adjusted under the control of the controller to trigger the transient voltage change rate between the source and the drain of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011 to adjust the switching speed of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011 and the high-voltage depletion mode gallium nitride power transistor 1012.

[0076] Optionally, the first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 only function when the cascode semiconductor device 101 is turned off, and the high-voltage depletion-mode gallium nitride power transistor 1012 is turned off by utilizing the unidirectional conductivity of the first diode 1023 .

[0077] Optionally, the controller directly changes the gate drive resistance of the high-voltage depletion-mode GaN power transistor 1012 by mainly adjusting the resistance value of the second resistor 1022 in the switching speed adjustment unit 102, so as to trigger the change of the transient voltage change rate between the source and the drain of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011, thereby adjusting the switching speeds of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 and the high-voltage depletion-mode GaN power transistor 1012, mainly adjusting the switching speed of the high-voltage depletion-mode GaN power transistor 1012.

[0078] It is worth noting that the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed adjustment unit 102 can be packaged inside the chip 20 or independently distributed on the printed circuit board 30 where the chip 20 is located. When the switching speed adjustment unit 102 is packaged inside the chip, the number of external devices can be reduced, and the switching speed adjustment unit 102 is electrically connected to the common source and common gate semiconductor device 101; when the switching speed adjustment unit 102 is deployed on the printed circuit board 30 where the chip 20 is located, the various electronic devices in the switching speed adjustment unit 102 are connected via the layer wiring of the printed circuit board 30, and the switching speed adjustment unit 102 is connected to the common source and common gate semiconductor device 101 via the pin pins of the chip 20. This application does not make specific limitations on this.

[0079] In an embodiment of the present application, a semiconductor device with adjustable switching speed is formed by a common source and common gate semiconductor device and a switching speed adjustment unit, and the switching speed adjustment unit includes: a first resistor, a second resistor and a first diode. Among them, the source of the high-voltage depletion-type gallium nitride power transistor in the common source and common gate semiconductor device is connected to the drain of the low-voltage enhancement-type metal oxide semiconductor field effect transistor, and the gate of the high-voltage depletion-type gallium nitride power transistor is connected to the source of the low-voltage enhancement-type metal oxide semiconductor field effect transistor, so that the high-voltage depletion-type gallium nitride power transistor obtains the characteristics of an enhancement-type switch; the gate of the high-voltage depletion-type power transistor is also connected to one end of the first resistor and one end of the second resistor, the other end of the first resistor is connected to the input end of the first diode, and the output end of the first diode and the other end of the second resistor are both connected to the low-voltage enhancement-type metal oxide semiconductor field effect transistor. The source of the conductor field effect tube is connected, and the first resistor and the second resistor are also externally connected to a controller. The controller can adjust the resistance value of the second resistor, which directly causes the driving resistance value of the high-voltage depletion-type gallium nitride power transistor to change, thereby changing the transient voltage change rate between the source and drain of the low-voltage enhancement-type metal oxide semiconductor field effect tube, so that the switching speed of the common source and common gate semiconductor device is adjusted; the drain of the high-voltage depletion-type gallium nitride power transistor and the source of the low-voltage enhancement-type metal oxide semiconductor field effect tube are both externally connected to the power loop, and the gate of the low-voltage enhancement-type metal oxide semiconductor field effect tube is externally connected to the driving circuit. In this way, the switching speed of the common source and common gate semiconductor device can be controlled to improve the stress and electromagnetic compatibility of the rectifier tube of the application system.

[0080] In an optional embodiment, see Figure 4 The first resistor 1021 , the second resistor 1022 , and the first diode 1023 in the switching speed adjustment unit 102 are all packaged on the same chip 20 as the cascode semiconductor device 101 .

[0081] Optionally, when the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed adjustment unit 102 are packaged in the same chip 20 as the common source and common gate semiconductor device 101, external devices of the semiconductor device 10 with adjustable switching speed can be effectively reduced.

[0082] In an optional embodiment, see Figure 5 The first resistor 1021 , the second resistor 1022 , and the first diode 1023 in the switching speed adjustment unit 102 are all integrated on the high-voltage depletion-mode gallium nitride power transistor 1012 in the common-source common-gate semiconductor device 101 .

[0083] Optionally, the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed regulating unit 102 are all integrated and packaged on the high-voltage depletion-type gallium nitride power transistor 1012 in the common-source common-gate semiconductor device 101, that is, the high-voltage depletion-type gallium nitride power transistor 1012 and the switching speed regulating unit 102 are regarded as a whole, and the high-voltage depletion-type gallium nitride power transistor 1012 has the function of the switching speed regulating unit 102.

[0084] In an optional embodiment, see Figure 6 The first resistor 1021 , the second resistor 1022 , and the first diode 1023 in the switching speed adjustment unit 102 are packaged together on the silicon substrate 201 of the chip 20 where the cascode semiconductor device 101 is located.

[0085] Optionally, the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed adjustment unit 102 are all integrated and packaged on the silicon substrate 201 of the chip 20 where the common source and common gate semiconductor device 101 is located, that is, the switching speed adjustment unit 102 and the common source and common gate semiconductor device 101 are both packaged in the chip 20, but the electronic devices in the switching speed adjustment unit 102 are packaged together as a whole.

[0086] In an optional embodiment, see Figure 7 The first resistor 1021 , the second resistor 1022 , and the first diode 1023 in the switching speed adjustment unit 102 are all integrated on the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 in the common source and common gate semiconductor device 101 .

[0087] Optionally, the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed adjustment unit 102 are all integrated and packaged on the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 in the common source and common gate semiconductor device 101, that is, the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 and the switching speed adjustment unit 102 are regarded as a whole, and the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 has the function of the switching speed adjustment unit 102.

[0088] In an optional embodiment, see Figure 8 The first resistor 1021 , the second resistor 1022 , and the first diode 1023 in the switching speed adjustment unit 102 are packaged on a printed circuit board 30 outside the chip 20 where the cascode semiconductor device 101 is located.

[0089] Optionally, the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed regulating unit 102 are disposed as discrete devices on a printed circuit board 30 to which the chip 20 where the cascode semiconductor device 101 is inserted is plugged. The high-voltage depletion-mode gallium nitride power transistor 1012 in the cascode semiconductor device 101 is connected to an external pin pin of the chip 20 via a pin, and the first resistor 1021, the second resistor 1022 and the first diode 1023 in the switching speed regulating unit 102 are connected between the gate of the high-voltage depletion-mode gallium nitride power transistor 1012 and the source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011 via the external pin pin.

[0090] In an optional embodiment, see Fig. 9 The second resistor 1022 in the switching speed adjustment unit 102 is packaged on a printed circuit board 30 outside the chip 20 where the common source and common gate semiconductor device 101 is located, and the first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are packaged on the same chip 20 as the common source and common gate semiconductor device 101.

[0091] Optionally, the second resistor 1022 in the switching speed regulating unit 102 is packaged on a printed circuit board 30 to which the chip 20 where the common source and common gate semiconductor device 101 is located is plugged. The second resistor 1022 in the switching speed regulating unit 102 is a discrete device, and the second resistor 1022 is connected between the gate of the high-voltage depletion-mode gallium nitride power transistor 1012 and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 through an external pin pin of the chip 20.

[0092] Optionally, the first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are packaged on the same chip 20 as the cascode semiconductor device 101 , that is, the first resistor 1021 and the first diode 1023 do not need to be connected to the cascode semiconductor device 101 via external pins of the chip 20 .

[0093] In an optional embodiment, see Fig.10 The first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are both integrated on the high-voltage depletion-mode gallium nitride power transistor 1012 in the cascode semiconductor device 101 .

[0094] Optionally, the first resistor 1021 and the first diode 1023 in the switching speed regulating unit 102 are both integrated and packaged on the high-voltage depletion-type gallium nitride power transistor 1012 in the common-source common-gate semiconductor device 101, that is, the high-voltage depletion-type gallium nitride power transistor 1012, the first resistor 1021 and the first diode 1023 are regarded as a whole, and the high-voltage depletion-type gallium nitride power transistor 1012 has the functions of the first resistor 1021 and the first diode 1023 in the switching speed regulating unit 102.

[0095] In an optional embodiment, see Fig.11 The first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are both integrated on the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 in the common source and common gate semiconductor device 101.

[0096] Optionally, the first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are both integrated and packaged on the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 in the common source and common gate semiconductor device 101, that is, the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011, the first resistor 1021 and the first diode 1023 are regarded as a whole, and the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 has the functions of the first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102.

[0097] In an optional embodiment, see Fig.12 The first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are packaged together on the silicon substrate 201 of the chip 20 where the cascode semiconductor device 101 is located.

[0098] Optionally, the first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are integrated and packaged on the silicon substrate 201 of the chip 20 where the common source and common gate semiconductor device 101 is located, that is, the first resistor 1021 and the first diode 1023 are considered as a whole packaged inside the chip 20.

[0099] In an optional embodiment, see Fig.13 The first resistor 1021 and the first diode 1023 in the switching speed adjustment unit 102 are packaged on a printed circuit board 30 outside the chip 20 where the common source and common gate semiconductor device 101 is located, and the second resistor 1022 in the switching speed adjustment unit 102 is packaged on the same chip 20 as the common source and common gate semiconductor device 101.

[0100] Optionally, the first resistor 1021 and the first diode 1023 in the switching speed regulating unit 102 are deployed as discrete devices on a printed circuit board 30 to which the chip 20 where the common source and common gate semiconductor device 101 is located is plugged, and the first resistor 1021 and the first diode 1023 in the switching speed regulating unit 102 are connected between the gate of the high-voltage depletion-mode gallium nitride power transistor 1012 and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 through external pin pins of the chip 20.

[0101] Optionally, the second resistor 1022 in the switching speed adjustment unit 102 and the cascode semiconductor device 101 are packaged on the same chip 20 , that is, the second resistor 1022 does not need to be connected to the cascode semiconductor device 101 via an external pin of the chip 20 .

[0102] In an optional embodiment, see Fig.14 The second resistor 1022 in the switching speed adjustment unit 102 is integrated on the high-voltage depletion-mode gallium nitride power transistor 1012 in the cascode semiconductor device 101 .

[0103] Optionally, the second resistor 1022 in the switching speed regulating unit 102 is integrated and packaged on the high-voltage depletion-type gallium nitride power transistor 1012 in the common-source common-gate semiconductor device 101, that is, the high-voltage depletion-type gallium nitride power transistor 1012 and the second resistor 1022 are regarded as a whole, and the high-voltage depletion-type gallium nitride power transistor 1012 has the function of the second resistor 1022 in the switching speed regulating unit 102.

[0104] In an optional embodiment, see Fig.15 The second resistor 1022 in the switching speed adjustment unit 102 is integrated on the low voltage enhancement mode metal oxide semiconductor field effect transistor 1011 in the common source and common gate semiconductor device 101.

[0105] Optionally, the second resistor 1022 in the switching speed adjustment unit 102 is integrated and packaged on the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 in the common source and common gate semiconductor device 101, that is, the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 and the second resistor 1022 are regarded as a whole, and the low-voltage enhancement type metal oxide semiconductor field effect transistor 1011 has the function of the second resistor 1022 in the switching speed adjustment unit 102.

[0106] In an optional embodiment, see Fig.16 The second resistor 1022 in the switching speed adjustment unit 102 is packaged on the silicon substrate 201 of the chip 20 where the cascode semiconductor device 101 is located.

[0107] Optionally, the second resistor 1022 in the switching speed adjustment unit 102 is separately packaged on the silicon substrate 201 of the chip 20 where the cascode semiconductor device 101 is located, that is, the second resistor 1022 is separately regarded as an integral package inside the chip 20 .

[0108] Fig.17 For the voltage waveform diagram of each node in the first semiconductor device with adjustable switching speed provided by the present application, see Fig.17 , a switching waveform diagram of a cascode semiconductor device within a working cycle provided by an embodiment of the present application, the present application connects a first resistor 1021, a second resistor 1022 and a first diode 1023 in series on the gate of a high-voltage depletion-mode gallium nitride power transistor 1012 in the cascode semiconductor device 101, so that the cascode semiconductor device 101 can control the switching speed of the cascode semiconductor device 101 by adjusting the gate drive resistance of the high-voltage depletion-mode gallium nitride power transistor 1012.

[0109] It is worth noting that the capacitor Cgd-si is a parasitic capacitor between the gate and drain of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011, the capacitor Cgs-si is a parasitic capacitor between the gate and source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011, and the capacitor Cds-si is a parasitic capacitor between the drain and gate of the low-voltage enhancement mode metal oxide semiconductor field effect transistor 1011; the capacitor Cds-GaN is a parasitic capacitor between the drain and source of the high-voltage depletion mode gallium nitride power transistor, the capacitor Cgd-GaN is a parasitic capacitor between the gate and drain of the high-voltage depletion mode gallium nitride power transistor, and the capacitor Cgs-GaN is a parasitic capacitor between the gate and source of the high-voltage depletion mode gallium nitride power transistor.

[0110] Fig.18 For the voltage waveform diagram of each node in the second semiconductor device with adjustable switching speed provided by the present application, see Fig.18The switching waveform diagram of the common-source common-gate semiconductor device provided in the embodiment of the present application is used to demonstrate the turn-on process of the semiconductor device with adjustable switching speed. The turn-on process of the semiconductor device with adjustable switching speed provided in the embodiment of the present application is as follows:

[0111] 1. In the t0-t1 stage, the semiconductor device with adjustable switching speed is in the first working mode, and the gate capacitance of the low-voltage enhancement type metal oxide semiconductor field effect transistor is in the charging stage. At this time, the gate-source voltage Vgs of the low-voltage enhancement type metal oxide semiconductor field effect transistor rises linearly, and the common source and common gate semiconductor device is in the off state. Fig.19 In the first working mode, the driving current output by the driving circuit flows into the capacitor Cgs-si to charge the capacitor Cgs-si.

[0112] 2. In the t1-t2 stage, the semiconductor device with adjustable switching speed is in the second working mode, the gate-source voltage Vgs of the low-voltage enhancement metal oxide semiconductor field effect transistor has reached the turn-on voltage VTH of the low-voltage enhancement metal oxide semiconductor field effect transistor, the low-voltage enhancement metal oxide semiconductor field effect transistor is turned on, the parasitic capacitance Cgs-si of the low-voltage enhancement metal oxide semiconductor field effect transistor continues to charge, the parasitic capacitance Cgd-si of the low-voltage enhancement metal oxide semiconductor field effect transistor begins to discharge, and the parasitic capacitance Cds-si of the low-voltage enhancement metal oxide semiconductor field effect transistor and the parasitic capacitance Cgs-GaN of the high-voltage depletion-mode gallium nitride power transistor also begin to discharge. Among them, see Fig. 20 In the second working mode, the driving current output by the driving circuit flows into the parasitic capacitor Cds-si, the second resistor and the capacitor Cgd-si respectively through the capacitor Cgs-si, and the driving current flowing out of the second resistor flows into the drain of the low-voltage enhancement metal oxide semiconductor field effect transistor through the capacitor Cgs-GaN. At the same time, the current flowing out of the capacitor Cgd-si and the current flowing out of the capacitor Cds-si both flow into the drain of the low-voltage enhancement metal oxide semiconductor field effect transistor.

[0113] 3. In the t2-t3 stage, the semiconductor device with adjustable switching speed is in the third working mode, the low-voltage enhancement metal oxide semiconductor field effect transistor is in a saturated conduction state, and the high-voltage depletion-type gallium nitride power transistor begins to conduct. At this time, the parasitic capacitance Cgd-GaN of the high-voltage depletion-type gallium nitride power transistor begins to discharge. Since the semiconductor device with adjustable switching speed introduces the second resistor, the gate voltage of the high-voltage depletion-type gallium nitride power transistor is a negative gate voltage relative to the source voltage of the low-voltage enhancement metal oxide semiconductor field effect transistor. The voltage of the parasitic capacitance Cgs-GaN of the high-voltage depletion-type gallium nitride power transistor remains unchanged, and the high-voltage depletion-type gallium nitride power transistor turns on the Miller platform. By changing the resistance value of the second resistor, the duration of the Miller platform can be adjusted, thereby changing the dv / dt of Vds when the high-voltage depletion-type gallium nitride power transistor is turned on. Wherein, refer to Fig.21 In the third working mode, the driving current output by the driving circuit flows into the capacitor Cgs-si and the capacitor Cgd-si respectively, the current flowing out of the capacitor Cgd-si flows to the capacitor Cds-GaN, the current flowing out of the capacitor Cgs-si flows into the parasitic capacitor Cds-si and the second resistor respectively, the current flowing out of the second resistor flows to the capacitor Cgd-GaN, the current flowing out of the capacitor Cgd-GaN and the current flowing out of the capacitor Cds-GaN are transmitted to the drain of the high-voltage depletion-mode gallium nitride power transistor, and the current flowing out of the source of the high-voltage depletion-mode gallium nitride transistor, the current flowing out of the capacitor Cgd-si and the current flowing out of the capacitor Cds-si all flow into the drain of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor.

[0114] 4. During the t3-t4 phase, the semiconductor device with adjustable switching speed is in the fourth working mode, the high-voltage depletion-mode GaN power transistor is fully turned on, the low-voltage enhancement-mode metal oxide semiconductor field effect transistor is still in the Miller conduction state, and the gate-source voltage Vgs-si of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor remains unchanged. Fig. 22 In the fourth working mode, the driving current output by the driving circuit flows into the capacitor Cgs-si and the capacitor Cgd-si respectively, the current flowing out of the capacitor Cgs-si flows into the parasitic capacitor Cds-si and the second resistor respectively, the current flowing out of the second resistor flows through the capacitor Cgd-GaN and the capacitor Cgs-GaN respectively, the current flowing out of the capacitor Cgd-GaN is transmitted to the drain of the high-voltage depletion-type gallium nitride power transistor, and the current flowing out of the source of the high-voltage depletion-type gallium nitride transistor, the current flowing out of the capacitor Cgd-si, the current flowing out of the capacitor Cgs-GaN and the current flowing out of the capacitor Cds-si all flow into the drain of the low-voltage enhancement-type metal oxide semiconductor field effect transistor.

[0115] 5. In the t4-t5 stage, the semiconductor device with adjustable switching speed is in the fifth working mode, the Miller time of the low-voltage enhancement metal oxide semiconductor field effect transistor ends, the low-voltage enhancement metal oxide semiconductor field effect transistor is fully turned on, the gate-source voltage Vgs-si of the low-voltage enhancement metal oxide semiconductor field effect transistor continues to rise, and the open state of the common source and common gate semiconductor device ends. Fig.23 In the fifth working mode, the current transmitted by the power circuit flows into the drain of the low-voltage enhancement type metal oxide semiconductor field effect transistor through the drain and source of the high-voltage depletion type gallium nitride power transistor, and is output to the power circuit through the source of the low-voltage enhancement type metal oxide semiconductor field effect transistor. The driving current input by the driving circuit charges the parasitic capacitance Cgs-si of the low-voltage enhancement type metal oxide.

[0116] In an optional implementation manner, the semiconductor device 10 with adjustable switching speed provided in the embodiment of the present application further has other extended structures, see Fig.24 The switching speed adjustable semiconductor device 10 provided in the embodiment of the present application includes: a common source and common gate semiconductor device 101 and a switching speed adjustment unit 102 , and the switching speed adjustment unit 102 includes: a second resistor 1022 and a first diode 1023 . The gate of the high-voltage depletion-mode gallium nitride power transistor 1012 in the cascode semiconductor device 101 is respectively connected to the input end of the first diode 1023, one end of the second resistor 1022, and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 in the cascode semiconductor device 101; the output end of the first diode 1023 and the other end of the second resistor 1022 are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 in the cascode semiconductor device 101; the source of the high-voltage depletion-mode gallium nitride power transistor 1012 is connected to the drain of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011; the drain of the high-voltage depletion-mode gallium nitride power transistor 1012 and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 are both externally connected to a power loop; and the gate of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 is externally connected to a driving circuit.

[0117] In an optional embodiment, see Fig.25The switching speed regulating unit 102 in the semiconductor device 10 with adjustable switching speed provided in the embodiment of the present application further includes: a second diode 1024, an input end of the first diode 1023 and one end of the second resistor 1022 are both connected to the gate of the high-voltage depletion-mode gallium nitride power transistor 1012, an output end of the first diode 1023 is connected to one end of the first resistor 1021, the other end of the second resistor 1022 is connected to the output end of the second diode 1024, and the other end of the first resistor 1021 and the input end of the second diode 1024 are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011.

[0118] In an optional implementation manner, the semiconductor device 10 with adjustable switching speed provided in the embodiment of the present application further has other extended structures, see Fig.26 The switching speed adjustable semiconductor device 10 provided in the embodiment of the present application includes: a common source and common gate semiconductor device 101 and a switching speed adjustment unit 102, and the switching speed adjustment unit 102 includes: a second resistor 1022, a first diode 1023 and a second diode 1024. The gate of the high-voltage depletion-mode gallium nitride power transistor 1012 in the cascode semiconductor device 101 is respectively connected to the input end of the first diode 1023, one end of the second resistor 1022, and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 in the cascode semiconductor device 101, the other end of the second resistor 1022 is connected to the output end of the second diode 1024, the output end of the first diode 1023 and the input end of the second diode 1024 are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 in the cascode semiconductor device 101, the source of the high-voltage depletion-mode gallium nitride power transistor 1012 is connected to the drain of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011, the drain of the high-voltage depletion-mode gallium nitride power transistor 1012 and the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 are both externally connected to a power loop, and the gate of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor 1011 is externally connected to a driving circuit.

[0119] It is worth noting that the above Fig.24 , 25 The electronic devices in the switching speed regulating unit 102 in 26 can be separately arranged outside the common source and common gate semiconductor device 101, or can be integrated in the high-voltage depletion-mode gallium nitride power transistor 1012 or the low-voltage enhancement-mode metal oxide semiconductor field effect transistor in the common source and common gate semiconductor device 101. The electronic devices in the switching speed regulating unit 102 can be fully or partially arranged on the silicon substrate 201 of the chip 20 where the common source and common gate semiconductor device 101 is located. The technical effect produced by the switching speed regulating unit 102 will not change, and the present application does not make specific limitations on this.

[0120] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0121] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device with adjustable switching speed, characterized in that: The semiconductor device comprises: a common source and common gate semiconductor device and a switching speed adjustment unit, the common source and common gate semiconductor device comprises: a low voltage enhancement mode metal oxide semiconductor field effect transistor and a high voltage depletion mode gallium nitride power transistor, the common source and common gate semiconductor device is packaged on a chip, and the switching speed adjustment unit comprises: a first resistor, a second resistor and a first diode; The drain of the low-voltage enhancement mode metal oxide semiconductor field effect transistor in the cascode semiconductor device is connected to the source of the high-voltage depletion mode gallium nitride power transistor, and the source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor is connected to the gate of the high-voltage depletion mode gallium nitride power transistor; The gate of the high-voltage depletion-mode gallium nitride power transistor is also connected to one end of a first resistor and one end of a second resistor in the switching speed adjustment unit, the other end of the first resistor is connected to the input end of the first diode, the output end of the first diode and the other end of the second resistor are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor, and the first resistor and the second resistor are also used for an external controller; The gate of the low-voltage enhancement mode metal oxide semiconductor field effect transistor is externally connected to a driving circuit, and the source of the low-voltage enhancement mode metal oxide semiconductor field effect transistor and the drain of the high-voltage depletion mode gallium nitride power transistor are both externally connected to a power loop; The resistance value of the second resistor in the switching speed adjustment unit is adjusted under the control of the controller to trigger the transient voltage change rate between the source and the drain of the low-voltage enhancement mode metal oxide semiconductor field effect transistor to be adjusted, so as to adjust the switching speed of the low-voltage enhancement mode metal oxide semiconductor field effect transistor and the high-voltage depletion mode gallium nitride power transistor.

2. The semiconductor device with adjustable switching speed according to claim 1, characterized in that: The first resistor, the second resistor and the first diode in the switching speed adjustment unit are all packaged on the same chip as the common-source and common-gate semiconductor device.

3. The semiconductor device with adjustable switching speed according to claim 2, characterized in that: The first resistor, the second resistor, and the first diode are all integrated on a high-voltage depletion-mode gallium nitride power transistor in the cascode semiconductor device.

4. The semiconductor device with adjustable switching speed according to claim 2, characterized in that: The first resistor, the second resistor, and the first diode are packaged together on a silicon substrate of a chip where the cascode semiconductor device is located.

5. The semiconductor device with adjustable switching speed according to claim 2, characterized in that: The first resistor, the second resistor, and the first diode are all integrated on a low-voltage enhancement mode metal oxide semiconductor field effect transistor in the cascode semiconductor device.

6. The semiconductor device with adjustable switching speed according to claim 1, characterized in that: The first resistor, the second resistor and the first diode in the switching speed adjustment unit are packaged on a printed circuit board outside the chip where the common-source and common-gate semiconductor device is located.

7. The semiconductor device with adjustable switching speed according to claim 1, characterized in that: The second resistor in the switching speed regulating unit is packaged on a printed circuit board outside the chip where the cascode semiconductor device is located, and the first resistor and the first diode in the switching speed regulating unit are packaged on the same chip as the cascode semiconductor device.

8. The semiconductor device with adjustable switching speed according to claim 7, characterized in that: The first resistor and the first diode are both integrated on a high-voltage depletion-mode gallium nitride power transistor in the cascode semiconductor device.

9. The semiconductor device with adjustable switching speed according to claim 7, characterized in that: The first resistor and the first diode are both integrated on a low-voltage enhancement mode metal oxide semiconductor field effect transistor in the cascode semiconductor device.

10. The semiconductor device with adjustable switching speed according to claim 7, characterized in that: The first resistor and the first diode are packaged together on a silicon substrate of a chip where the cascode semiconductor device is located.

11. The semiconductor device with adjustable switching speed according to claim 1, characterized in that: The first resistor and the first diode in the switching speed regulating unit are packaged on a printed circuit board outside the chip where the cascode semiconductor device is located, and the second resistor in the switching speed regulating unit is packaged on the same chip as the cascode semiconductor device.

12. The semiconductor device with adjustable switching speed according to claim 11, characterized in that: The second resistor is integrated on a high-voltage depletion-mode gallium nitride power transistor in the cascode semiconductor device.

13. The semiconductor device with adjustable switching speed according to claim 11, characterized in that: The second resistor is integrated on a low voltage enhancement mode metal oxide semiconductor field effect transistor in the cascode semiconductor device.

14. The semiconductor device with adjustable switching speed according to claim 11, characterized in that: The second resistor is packaged on a silicon substrate of a chip where the cascode semiconductor device is located.

15. The semiconductor device with adjustable switching speed according to claim 1, characterized in that: The switching speed adjustment unit further includes: a second diode, an input end of the first diode and one end of the second resistor are both connected to the gate of the high-voltage depletion-mode gallium nitride power transistor, an output end of the first diode is connected to one end of the first resistor, the other end of the second resistor is connected to the output end of the second diode, and the other end of the first resistor and the input end of the second diode are both connected to the source of the low-voltage enhancement-mode metal oxide semiconductor field effect transistor.

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