High-linearity grid voltage bootstrapped switch circuit

Abstract

The invention relates to the technical field of integrated circuits, in particular to a high-linearity grid voltage bootstrapped switch circuit. In the holding stage, a clock signal CK2 controls the pull-down module and MOS tubes M4 and M19 to be switched on, clock signals CK1 and CK2 are matched to control the first bootstrap module and the second bootstrap module to be switched off, the first bootstrap interlocking module and the second bootstrap interlocking module are respectively in interlocking linkage with the MOS tubes M10 and M12 to be switched off, and finally the MOS tube M11 is switched off; in a sampling stage, a clock signal CK2 controls the pull-down module and the MOS tubes M4 and M19 to be switched off, clock signals CK1 and CK2 cooperate to control the first bootstrap module and the second bootstrap module to be switched on, the first bootstrap interlocking module and the second bootstrap interlocking module are in interlocking linkage with the MOS tubes M10 and M12 to be switched on, and finally the MOS tube M11 is switched on; the problem that the switching speed is slowed down due to the fact that the linearity of the MOS tube cannot be improved while the substrate bias effect of the MOS tube is suppressed is solved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a high-linearity gate voltage bootstrap switch circuit. Background Art

[0002] The sampling switch circuit is one of the key modules of the analog-to-digital converter (ADC). It is a switch circuit that converts external continuous analog signals into discrete analog signals. The working process of the sampling switch circuit is divided into a sampling stage and a holding stage. In the sampling stage, the sampling switch samples a certain instantaneous voltage value of the continuous analog input voltage. In the holding stage, the sampled voltage value is kept on the sampling capacitor and output to the next level circuit for processing. However, when the sampling switch circuit uses a single NMOS tube or a single PMOS tube as a sampling switch, when transmitting a high level or a low level (especially when working in the linear region), there is inevitably a threshold loss, that is, the input voltage common mode range of the sampling switch is limited, the on-resistance is related to the input signal, the resistance value changes with the input voltage signal amplitude, and there is a substrate bias effect, which causes the output of the sampling switch to be linearly distorted.

[0003] To this end, the existing scheme proposes a gate voltage bootstrap switch circuit, the circuit principle of which reduces the substrate bias effect is as follows Figure 1 As shown, a three-switch structure is adopted, which consists of three MOS tubes, of which the sources of two MOS tubes are connected to the same node, and the other MOS tube is used to control the potential of the point to prevent the parasitic diode generated by the process from turning on. When CLK=1, the gate voltage is a constant voltage value, both switches are turned on, and the substrates of the two tubes are connected to the source end respectively, without substrate bias effect; and the substrate potential is the same as Vin, the parasitic diodes of the source and drain are not turned on, and no leakage current is generated. When CLK=0, both MOS are disconnected, the lower MOS tube is turned on, and the substrate is pulled down to 0 to prevent the parasitic diode from turning on. The principle is to use a charge pump to maintain the gate-source voltage VGS value of the MOS tube (NMOS tube or PMOS tube) at a constant value when CLK=1, so as to ensure that the analog-to-digital converter (ADC) can maintain conduction under different input voltages, and pull the substrate down to 0 when CLK=0, so that the gate-source voltage is independent of the input voltage, effectively suppressing the influence of the substrate bias effect, and avoiding linear distortion of the output.

[0004] However, the above-mentioned gate voltage bootstrap switching circuit solution has parasitic capacitance on the gate node of the MOS tube in the signal path (Vin to Vout). The parasitic capacitance will make VGS slightly smaller than the theoretical value VDD (i.e., the power supply voltage), and the more charge injected into the parasitic capacitance in the circuit, the more serious the linear distortion of the MOS tube, resulting in a slower switching speed. Summary of the invention

[0005] In view of the above defects, the purpose of the present invention is to provide a high linearity gate voltage bootstrap switch circuit, which solves the problem that while suppressing the substrate bias effect of the MOS tube, the linearity of the MOS tube cannot be improved, resulting in a slow switching speed.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A high-linearity gate voltage bootstrap switch circuit, comprising a MOS tube M4, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M19, a first bootstrap module, a second bootstrap module, a pull-down module, a first bootstrap interlocking module, and a second bootstrap interlocking module; the source and drain of the MOS tube M11 are respectively used as the input end and the output end of the gate voltage bootstrap switch circuit;

[0008] The gate of the MOS tube M4 receives the clock signal CK2, the first input end of the first bootstrap module 1 and the input end of the first bootstrap interlocking module are electrically connected to the gate of the MOS tube M4, the second input end of the first bootstrap module receives the clock signal CK1, the source of the MOS tube M4 is grounded, the first start-up end of the first bootstrap module, the second start-up end of the first bootstrap module, and the drain of the MOS tube M10 are electrically connected to the drain of the MOS tube M4, the interlocking end of the first bootstrap interlocking module is electrically connected to the interlocking end of the first bootstrap module, and the output end of the first bootstrap interlocking module is electrically connected to the gate of the MOS tube M10;

[0009] The gate of the MOS tube M19 receives the clock signal CK2, the first input end of the second bootstrap module and the input end of the second bootstrap interlocking module are electrically connected to the gate of the MOS tube M19, the second input end of the second bootstrap module receives the clock signal CK1, the source of the MOS tube M19 is grounded, the first start end of the second bootstrap module, the second start end of the second bootstrap module, and the drain of the MOS tube M12 are electrically connected to the drain of the MOS tube M19, the interlocking end of the second bootstrap interlocking module is electrically connected to the interlocking end of the second bootstrap module, and the output end of the second bootstrap interlocking module is electrically connected to the gate of the MOS tube M12;

[0010] The ground end of the first bootstrap module and the ground end of the second bootstrap module are electrically connected to the first end of the pull-down module, the output end of the first bootstrap module, the output end of the second bootstrap module, and the gate of the MOS tube M11 are electrically connected to the second end of the pull-down module, the third end of the pull-down module is grounded, the control end of the pull-down module receives the clock signal CK2, the source of the MOS tube M11 is electrically connected to the source of the MOS tube M10, and the drain of the MOS tube M11 is electrically connected to the drain of the MOS tube M12;

[0011] During the holding stage, the clock signal CK2 controls the pull-down module, the MOS tube M4 and the MOS tube M19 to be turned on, the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module and the second bootstrap module to be turned off, and the first bootstrap interlock module and the second bootstrap interlock module are respectively interlocked to turn off the MOS tube M10 and the MOS tube M12, and finally the MOS tube M11 is turned off;

[0012] During the sampling phase, the clock signal CK2 controls the pull-down module, the MOS tube M4 and the MOS tube M19 to be turned off, the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module and the second bootstrap module to be turned on, and the MOS tube M10 and the MOS tube M12 are interlocked and turned on through the first bootstrap interlock module and the second bootstrap interlock module, and finally the MOS tube M11 is turned on.

[0013] Furthermore, the first bootstrap module and the second bootstrap module use capacitors to provide bootstrap voltages, and the capacitance value of the first bootstrap module or the second bootstrap module is greater than the gate capacitance of the MOS tube M11.

[0014] Furthermore, the circuit structures of the first bootstrap module and the second bootstrap module are the same, and the circuit structures of the first bootstrap interlocking module and the second bootstrap interlocking module are the same.

[0015] Further, the first bootstrap module includes a first charge pump, a first capacitor module, a MOS tube M3, a MOS tube M5, a MOS tube M6 and a MOS tube M7; the first control end and the second control end of the first charge pump are respectively used as the first input end and the second input end of the first bootstrap module, one end of the first capacitor module is used as the first start-up end of the first bootstrap module, the other end of the first capacitor module is used as the interlocking end of the first bootstrap module, the source of the MOS tube M7 is used as the second start-up end of the first bootstrap module, the source of the MOS tube M5 is used as the output end of the first bootstrap module, and the ground end of the first charge pump is used as the ground end of the first bootstrap module;

[0016] The gate of the MOS tube M6 and the gate of the MOS tube M7 are both electrically connected to the second control end of the first charge pump, the drain of the MOS tube M6 and the drain of the MOS tube M7 are both electrically connected to the gate of the MOS tube M5, the source of the MOS tube M3 and the other end of the first capacitor module are both electrically connected to the drain of the MOS tube M5, the gate of the MOS tube M3 is electrically connected to the output end of the first charge pump, and the drain of the MOS tube M3 and the source of the MOS tube M6 are both electrically connected to the ground end of the first charge pump;

[0017] When the MOS tube M3 is turned off and the MOS tube M5 is turned on, the first bootstrap module is turned on; when the MOS tube M3 is turned on and the MOS tube M5 is turned off, the first bootstrap module is turned off.

[0018] Further, the pull-down module includes a MOS tube M22, a MOS tube M23 and a MOS tube M24; the source of the MOS tube M24 is used as the first end of the pull-down module, the source of the MOS tube M22 is used as the second end of the pull-down module, the drain of the MOS tube M23 is used as the third end of the pull-down module, and the gate of the MOS tube M24 is used as the control end of the pull-down module;

[0019] The gate of the MOS tube M22 is electrically connected to the source of the MOS tube M24, the drain of the MOS tube M22 and the drain of the MOS tube M24 are both electrically connected to the source of the MOS tube M23, and the gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M24;

[0020] When the MOS tube M24 is turned off and the MOS tube M22 and the MOS tube M23 are both turned on, the pull-down module is turned on; when the MOS tube M24 is turned on and the MOS tube M22 and the MOS tube M23 are both turned off, the pull-down module is turned off.

[0021] Further, the first bootstrap interlocking module includes a MOS tube M8 and a MOS tube M9; the gate of the MOS tube M8 is used as the input end of the first bootstrap interlocking module, the source of the MOS tube M8 is used as the interlocking end of the first bootstrap interlocking module, and the drain of the MOS tube M8 is used as the output end of the first bootstrap interlocking module;

[0022] The gate of the MOS tube M8 is electrically connected to the gate of the MOS tube M9, the drain of the MOS tube M8 is electrically connected to the drain of the MOS tube M9, and the source of the MOS tube M9 is grounded.

[0023] Furthermore, the first bootstrap interlocking module further includes a first charge absorption circuit; an input end of the first charge absorption circuit is electrically connected to a source of the MOS tube M8, and a control end of the first charge absorption circuit receives the clock signal CK1;

[0024] The first charge absorption circuit is used to absorb the channel charge generated by the MOS transistor M8.

[0025] Furthermore, the first charge absorption circuit includes a MOS tube M25; the drain of the MOS tube M25 is used as the input end of the first charge absorption circuit, and the gate of the MOS tube M25 is used as the control end of the first charge absorption circuit; the drain and source of the MOS tube M25 are electrically connected.

[0026] Further, the first charge pump includes a capacitor C1, a capacitor C2, a MOS transistor M1 and a MOS transistor M2; one end of the capacitor C1 is used as a first control end of the first charge pump, one end of the capacitor C2 is used as a second control end of the first charge pump, the other end of the capacitor C1 is used as an output end of the first charge pump, and the drain of the MOS transistor M2 is used as a ground end of the first charge pump;

[0027] The other end of the capacitor C1 and the source of the MOS tube M1 are electrically connected to the gate of the MOS tube M2, the other end of the capacitor C2 and the source of the MOS tube M2 are electrically connected to the gate of the MOS tube M1, and the drain of the MOS tube M1 is electrically connected to the drain of the MOS tube M2.

[0028] Furthermore, the first capacitor module includes a capacitor C3; one end of the capacitor C3 is used as one end of the first capacitor module, and the other end of the capacitor C3 is used as the other end of the first capacitor module.

[0029] The technical solution provided by the present invention may have the following beneficial effects: a gate voltage bootstrap switch circuit is formed with MOS tube M10, MOS tube M11 and MOS tube M12 as the core, similar to Figure 1 According to the principle of the present invention, the MOS tube M10 and the MOS tube M12 are controlled simultaneously to control the MOS tube M10, so as to suppress the substrate bias effect of the MOS tube M11; at the same time, the MOS tube M4, the MOS tube M10, the first bootstrap module and the first bootstrap interlocking module form a bootstrap group on one side, and the MOS tube M19, the MOS tube M12, the first bootstrap module and the first bootstrap interlocking module form a bootstrap group on the other side. The two bootstrap groups are used to provide a bootstrap voltage for the gate of the MOS tube M11, so that the gate parasitic capacitance of the MOS tube M11 is reduced, thereby reducing the amount of charge in the circuit shared by the parasitic capacitance, so that the VGS of the MOS tube M11 is infinitely close to the VDD, thereby improving the linearity of the switch circuit and the switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit schematic diagram (or equivalent circuit diagram) of an existing gate voltage bootstrap switch circuit.

[0031] Figure 2 The invention is a circuit diagram of a high linearity gate voltage bootstrap switch circuit according to one embodiment of the present invention.

[0032] Among them: MOS tube M4, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M19, a first bootstrap module 1, a second bootstrap module 2, a pull-down module 3, a first bootstrap interlocking module 4, a second bootstrap interlocking module 5, a first charge pump 11, a first capacitor module 12, MOS tube M3, MOS tube M5, MOS tube M6, MOS tube M7, a second charge pump 21, a second capacitor module 22, MOS tube M18, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M22, MOS tube M23, MOS tube M24, MOS tube M8, MOS tube M9, MOS tube M16, MOS tube M17, a first charge absorption circuit 41, a second charge absorption circuit 51, MOS tube M25, MOS tube M26, capacitor C1, capacitor C2, MOS tube M1, MOS tube M2, capacitor C6, capacitor C5, MOS tube M21, MOS tube M20, capacitor C3, capacitor C4. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0034] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0036] Combine the following Figure 1 to Figure 2 , describing a high linearity gate voltage bootstrap switching circuit according to an embodiment of the present invention.

[0037] A high-linearity gate voltage bootstrap switch circuit comprises a MOS tube M4, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M19, a first bootstrap module 1, a second bootstrap module 2, a pull-down module 3, a first bootstrap interlocking module 4 and a second bootstrap interlocking module 5; a source and a drain of the MOS tube M11 are respectively used as an input end and an output end of the gate voltage bootstrap switch circuit;

[0038] The gate of the MOS tube M4 receives the clock signal CK2, the first input end of the first bootstrap module 1 and the input end of the first bootstrap interlocking module 4 are electrically connected to the gate of the MOS tube M4, the second input end of the first bootstrap module 1 receives the clock signal CK1, the source of the MOS tube M4 is grounded, the first start-up end of the first bootstrap module 1, the second start-up end of the first bootstrap module 1, and the drain of the MOS tube M10 are electrically connected to the drain of the MOS tube M4, the interlocking end of the first bootstrap interlocking module 4 is electrically connected to the interlocking end of the first bootstrap module 1, and the output end of the first bootstrap interlocking module 4 is electrically connected to the gate of the MOS tube M10;

[0039] The gate of the MOS tube M19 receives the clock signal CK2, the first input end of the second bootstrap module 2 and the input end of the second bootstrap interlocking module 5 are electrically connected to the gate of the MOS tube M19, the second input end of the second bootstrap module 2 receives the clock signal CK1, the source of the MOS tube M19 is grounded, the first start end of the second bootstrap module 2, the second start end of the second bootstrap module 2, and the drain of the MOS tube M12 are electrically connected to the drain of the MOS tube M19, the interlocking end of the second bootstrap interlocking module 5 is electrically connected to the interlocking end of the second bootstrap module 2, and the output end of the second bootstrap interlocking module 5 is electrically connected to the gate of the MOS tube M12;

[0040] The ground end of the first bootstrap module 1 and the ground end of the second bootstrap module 2 are electrically connected to the first end of the pull-down module 3, the output end of the first bootstrap module 1, the output end of the second bootstrap module 2, and the gate of the MOS tube M11 are electrically connected to the second end of the pull-down module 3, the third end of the pull-down module 3 is grounded, the control end of the pull-down module 3 receives the clock signal CK2, the source of the MOS tube M11 is electrically connected to the source of the MOS tube M10, and the drain of the MOS tube M11 is electrically connected to the drain of the MOS tube M12;

[0041] During the holding stage, the clock signal CK2 controls the pull-down module 3, the MOS tube M4 and the MOS tube M19 to be turned on, the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module 1 and the second bootstrap module 2 to be turned off, and the first bootstrap interlock module 4 and the second bootstrap interlock module 5 are respectively interlocked to turn off the MOS tube M10 and the MOS tube M12, and finally the MOS tube M11 is turned off;

[0042] During the sampling phase, the clock signal CK2 controls the pull-down module 3, the MOS tube M4 and the MOS tube M19 to be turned off, the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module 1 and the second bootstrap module 2 to be turned on, and the first bootstrap interlock module 4 and the second bootstrap interlock module 5 are interlocked to respectively turn on the MOS tube M10 and the MOS tube M12, and finally turn on the MOS tube M11.

[0043] The present invention proposes a preferred embodiment of a high linearity gate voltage bootstrap switch circuit, as Figure 2 As shown, the gate voltage bootstrap switch circuit is formed with MOS tube M10, MOS tube M11 and MOS tube M12 as the core, similar to Figure 1 According to the principle of the invention, the MOS tube M10 and the MOS tube M12 are controlled simultaneously to control the MOS tube M10, so as to suppress the substrate bias effect of the MOS tube M11; at the same time, the MOS tube M4, the MOS tube M10, the first bootstrap module 1 and the first bootstrap interlocking module 4 form a bootstrap group on one side, and the MOS tube M19, the MOS tube M12, the second bootstrap module 2 and the second bootstrap interlocking module 5 form a bootstrap group on the other side. The two bootstrap groups are used to provide a bootstrap voltage for the gate of the MOS tube M11, so that the gate parasitic capacitance of the MOS tube M11 is reduced, thereby reducing the amount of charge in the circuit shared by the parasitic capacitance, so that the VGS of the MOS tube M11 is infinitely close to the VDD, thereby improving the linearity of the switch circuit and the switching speed.

[0044] The working process of this high linearity gate voltage bootstrap switch circuit is:

[0045] When in the holding stage (for example, CK1=0, CK2=1), the clock signal CK2 controls the pull-down module 3 to turn on, so that the first bootstrap module 1, the second bootstrap module 2 and the MOS tube M11 are all grounded, and the substrate of the MOS tube M11 is pulled down to 0, thereby suppressing the substrate bias effect; at the same time, the clock signal CK2 also controls the MOS tube M4 and the MOS tube M13 to turn on, and when the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module 1 and the second bootstrap module 2 to turn off (no bootstrap voltage is provided to the gate of the MOS tube M11), the first bootstrap interlock module 4 and the second bootstrap interlock module 5 are respectively interlocked to turn off the MOS tube M10 and the MOS tube M12.

[0046] During the sampling phase (for example, CK1=1, CK2=0), the clock signal CK2 controls the pull-down module 3 to turn off, so that the first bootstrap module 1, the second bootstrap module 2 and the MOS tube M11 are all disconnected from the ground, and the bootstrap voltage of the first bootstrap module 1, the bootstrap voltage of the second bootstrap module 2 and the substrate of the MOS tube M11 are not pulled down; at the same time, the clock signal CK2 also controls the MOS tube M4 and the MOS tube M13 to turn off, and when the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module 1 and the second bootstrap module 2 to be turned on (the first bootstrap module 1 and the second bootstrap module 2 both provide bootstrap voltages for the gate of the MOS tube M11), the first bootstrap interlock module 4 and the second bootstrap interlock module 5 are respectively interlocked to turn on the MOS tube M10 and the MOS tube M12, and finally the MOS tube M11 is turned on.

[0047] Furthermore, the first bootstrap module 1 and the second bootstrap module 2 use capacitors to provide bootstrap voltages, and the capacitance value of the first bootstrap module 1 or the second bootstrap module 2 is greater than the gate capacitance of the MOS tube M11.

[0048] In this embodiment, in order to reduce the gate parasitic capacitance of the MOS tube M11, the first bootstrap module 1 and the second bootstrap module 2 preferably use capacitors to provide the bootstrap voltage, and the gate parasitic capacitance of the MOS tube M11 is reduced as much as possible by designing the capacitance value of the charge pump capacitor to be much larger than the gate capacitance of the MOS tube M11. Therefore, when the capacitance value of the first bootstrap module 1 or the second bootstrap module 2 is larger than the gate capacitance of the MOS tube M11, the total charge pump capacitance will be much larger than the gate capacitance of the MOS tube M11.

[0049] Furthermore, the circuit structures of the first bootstrap module 1 and the second bootstrap module 2 are the same, and the circuit structures of the first bootstrap interlocking module 4 and the second bootstrap interlocking module 5 are the same.

[0050] In the present embodiment, in order to facilitate circuit design and calculation of the total capacitance value (because when the internal charge pump capacitance of the first bootstrap module 1 or the second bootstrap module 2 is more complex, calculation is difficult), the circuit structure of the first bootstrap module 1 and the second bootstrap module 2 is set to be the same, forming a mirror image structure (i.e., 2 times the capacitance value), and the circuit structure of the first bootstrap interlocking module 4 and the second bootstrap interlocking module 5 should also be set to be the same.

[0051] Further, the first bootstrap module 1 includes a first charge pump 11, a first capacitor module 12, a MOS tube M3, a MOS tube M5, a MOS tube M6 and a MOS tube M7; the first control end and the second control end of the first charge pump 11 are respectively used as the first input end and the second input end of the first bootstrap module 1, one end of the first capacitor module 12 is used as the first start-up end of the first bootstrap module 1, the other end of the first capacitor module 12 is used as the interlocking end of the first bootstrap module 1, the source of the MOS tube M7 is used as the second start-up end of the first bootstrap module 1, the source of the MOS tube M5 is used as the output end of the first bootstrap module 1, and the ground end of the first charge pump 11 is used as the ground end of the first bootstrap module 1;

[0052] The gate of the MOS tube M6 and the gate of the MOS tube M7 are both electrically connected to the second control end of the first charge pump 11, the drain of the MOS tube M6 and the drain of the MOS tube M7 are both electrically connected to the gate of the MOS tube M5, the source of the MOS tube M3 and the other end of the first capacitor module 12 are both electrically connected to the drain of the MOS tube M5, the gate of the MOS tube M3 is electrically connected to the output end of the first charge pump 11, and the drain of the MOS tube M3 and the source of the MOS tube M6 are both electrically connected to the ground end of the first charge pump 11;

[0053] When the MOS tube M3 is turned off and the MOS tube M5 is turned on, the first bootstrap module 1 is turned on; when the MOS tube M3 is turned on and the MOS tube M5 is turned off, the first bootstrap module 1 is turned off.

[0054] In this embodiment, the MOS tube M3 is a charge and discharge switch of the first capacitor module 12 (i.e., the capacitor of the charge pump, which is not limited to the circuit structure and can be used as a capacitor), which is controlled by the first charge pump 11 controlled by two clock signals; the MOS tube M5 is a switch for whether the first bootstrap module 1 provides a bootstrap voltage for the MOS tube M11; the MOS tube M6 and the MOS tube M7 constitute an inverter, which is used to coordinate and control the MOS tube M5 according to the clock signal CK1 and the MOS tube M4 (indirectly controlled by the clock signal CK2). Therefore, in the holding stage, the MOS tube M3 needs to be turned off and the MOS tube M5 needs to be turned on, so that the first bootstrap module 1 is turned on, and the first capacitor module 12 provides a bootstrap voltage for the gate of the MOS tube M11.

[0055] It should be noted that, since the circuit structures of the first bootstrap module 1 and the second bootstrap module 2 are the same, the second bootstrap module 2 includes a second charge pump 21 (corresponding to the first charge pump 11), a second capacitor module 22 (corresponding to the first capacitor module 12), a MOS tube M18 (corresponding to the MOS tube M3), a MOS tube M13 (corresponding to the MOS tube M5), a MOS tube M14 (corresponding to the MOS tube M6) and a MOS tube M15 (corresponding to the MOS tube M7).

[0056] Further, the pull-down module 3 includes a MOS tube M22, a MOS tube M23 and a MOS tube M24; the source of the MOS tube M24 is used as the first end of the pull-down module 3, the source of the MOS tube M22 is used as the second end of the pull-down module 3, the drain of the MOS tube M23 is used as the third end of the pull-down module 3, and the gate of the MOS tube M24 is used as the control end of the pull-down module 3;

[0057] The gate of the MOS tube M22 is electrically connected to the source of the MOS tube M24, the drain of the MOS tube M22 and the drain of the MOS tube M24 are both electrically connected to the source of the MOS tube M23, and the gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M24;

[0058] When the MOS tube M24 is turned off and the MOS tubes M22 and M23 are both turned on, the pull-down module 3 is turned on; when the MOS tube M24 is turned on and the MOS tubes M22 and M23 are both turned off, the pull-down module 3 is turned off.

[0059] In this embodiment, the pull-down module 3 is controlled by the clock signal CK2, turned on in the holding phase and turned off in the sampling phase, and is composed of a MOS transistor M22, a MOS transistor M23 and a MOS transistor M24 to form a logic circuit.

[0060] Further, the first bootstrap interlocking module 4 includes a MOS tube M8 and a MOS tube M9; the gate of the MOS tube M8 is used as the input end of the first bootstrap interlocking module 4, the source of the MOS tube M8 is used as the interlocking end of the first bootstrap interlocking module 4, and the drain of the MOS tube M8 is used as the output end of the first bootstrap interlocking module 4;

[0061] The gate of the MOS tube M8 is electrically connected to the gate of the MOS tube M9 , the drain of the MOS tube M8 is electrically connected to the drain of the MOS tube M9 , and the source of the MOS tube M9 is grounded.

[0062] In this embodiment, the first bootstrap interlocking module 4 is configured to realize the function of interlocking with the first bootstrap module 4 (i.e., the MOS tube M10 and the first bootstrap module 4 are turned off or turned on at the same time). The inverter formed by the MOS tube M8 and the MOS tube M9 is respectively connected to the clock signal CK2 and the drain of the MOS tube M5 (because it determines whether to provide a bootstrap voltage for the MOS tube M11).

[0063] Similarly, the second bootstrap interlocking module 5 having the same circuit structure as the first bootstrap interlocking module 4 is also composed of an inverter, including a MOS tube M16 (corresponding to the MOS tube M8 ) and a MOS tube M17 (corresponding to the MOS tube M9 ).

[0064] Furthermore, the first bootstrap interlock module 4 further includes a first charge absorption circuit 41; the input end of the first charge absorption circuit 41 is electrically connected to the source of the MOS tube M8, and the control end of the first charge absorption circuit 41 receives the clock signal CK1;

[0065] The first charge absorption circuit 41 is used to absorb the channel charges generated by the MOS transistor M8.

[0066] In this embodiment, at the moment of switching between the holding phase and the sampling phase, the on or off state of the MOS tube M8 or the MOS tube M9 of the first bootstrap interlock module 4 will also switch, but when the MOS tube M8 starts to turn off, the MOS tube M5 will still remain on, and the channel charge generated by the MOS tube M8 will be injected into the gate of the MOS tube M11 through the MOS tube M5, affecting the linearity; therefore, a first charge absorption circuit 41 controlled by the clock signal CK1 is set at the source of the MOS tube M8 to absorb the channel charge generated by the MOS tube M8. The second bootstrap interlock module 5 is similarly provided with a second charge absorption circuit 51.

[0067] Furthermore, the first charge absorption circuit 41 includes a MOS tube M25; the drain of the MOS tube M25 is used as the input end of the first charge absorption circuit 41, and the gate of the MOS tube M25 is used as the control end of the first charge absorption circuit 41; the drain and source of the MOS tube M25 are electrically connected.

[0068] In this embodiment, in order to simplify the circuit structure of the first charge absorption circuit 41 or the second charge absorption circuit 51 and realize the absorption of channel charges under the control of the clock signal CK1, the source and drain of the MOS tube M25 (or MOS tube M26) are short-circuited to serve as a controlled capacitor.

[0069] Further, the first charge pump 11 includes a capacitor C1, a capacitor C2, a MOS transistor M1 and a MOS transistor M2; one end of the capacitor C1 is used as a first control end of the first charge pump 11, one end of the capacitor C2 is used as a second control end of the first charge pump 11, the other end of the capacitor C1 is used as an output end of the first charge pump 11, and the drain of the MOS transistor M2 is used as a ground end of the first charge pump 11;

[0070] The other end of the capacitor C1 and the source of the MOS tube M1 are electrically connected to the gate of the MOS tube M2, the other end of the capacitor C2 and the source of the MOS tube M2 are electrically connected to the gate of the MOS tube M1, and the drain of the MOS tube M1 is electrically connected to the drain of the MOS tube M2.

[0071] In this embodiment, in order to enable the first charge pump 11 to be controlled by the clock signal CK1 and the clock signal CK2, the MOS tube M3 is controlled to be turned on in the holding stage and to be turned off in the sampling stage, and the first charge pump 11 is composed of a capacitor C1, a capacitor C2, a MOS tube M1 and a MOS tube M2. Similarly, the second charge pump 21 includes a capacitor C6 (corresponding to the capacitor C1), a capacitor C5 (corresponding to the capacitor C2), a MOS tube M21 (corresponding to the MOS tube M1) and a MOS tube M20 (corresponding to the MOS tube M2).

[0072] Furthermore, the first capacitor module 12 includes a capacitor C3 ; one end of the capacitor C3 is used as one end of the first capacitor module 12 , and the other end of the capacitor C3 is used as the other end of the first capacitor module 12 .

[0073] In this embodiment, in order to simplify the circuit design and facilitate the calculation of the total capacitance value, the first capacitor module 12 is designed to be composed of a single capacitor, and the capacitance value of the capacitor C3 can be increased by selecting different capacitor specifications. Similarly, the second capacitor module 22 is composed of capacitor C4.

[0074] Other structures and operations of a high-linearity gate voltage bootstrap switch circuit according to an embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0075] In the description of this specification, the description with reference to the terms "embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0076] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A high linearity gate voltage bootstrap switch circuit, characterized in that: It includes a MOS tube M4, a MOS tube M10, a MOS tube M11, a MOS tube M12, a MOS tube M19, a first bootstrap module, a second bootstrap module, a pull-down module, a first bootstrap interlocking module and a second bootstrap interlocking module; the source and drain of the MOS tube M11 are used as the input end and the output end of the gate voltage bootstrap switch circuit respectively; The gate of the MOS tube M4 receives the clock signal CK2, the first input end of the first bootstrap module 1 and the input end of the first bootstrap interlocking module are electrically connected to the gate of the MOS tube M4, the second input end of the first bootstrap module receives the clock signal CK1, the source of the MOS tube M4 is grounded, the first start-up end of the first bootstrap module, the second start-up end of the first bootstrap module, and the drain of the MOS tube M10 are electrically connected to the drain of the MOS tube M4, the interlocking end of the first bootstrap interlocking module is electrically connected to the interlocking end of the first bootstrap module, and the output end of the first bootstrap interlocking module is electrically connected to the gate of the MOS tube M10; The gate of the MOS tube M19 receives the clock signal CK2, the first input end of the second bootstrap module and the input end of the second bootstrap interlocking module are electrically connected to the gate of the MOS tube M19, the second input end of the second bootstrap module receives the clock signal CK1, the source of the MOS tube M19 is grounded, the first start end of the second bootstrap module, the second start end of the second bootstrap module, and the drain of the MOS tube M12 are electrically connected to the drain of the MOS tube M19, the interlocking end of the second bootstrap interlocking module is electrically connected to the interlocking end of the second bootstrap module, and the output end of the second bootstrap interlocking module is electrically connected to the gate of the MOS tube M12; The ground end of the first bootstrap module and the ground end of the second bootstrap module are electrically connected to the first end of the pull-down module, the output end of the first bootstrap module, the output end of the second bootstrap module, and the gate of the MOS tube M11 are electrically connected to the second end of the pull-down module, the third end of the pull-down module is grounded, the control end of the pull-down module receives the clock signal CK2, the source of the MOS tube M11 is electrically connected to the source of the MOS tube M10, and the drain of the MOS tube M11 is electrically connected to the drain of the MOS tube M12; During the holding stage, the clock signal CK2 controls the pull-down module, the MOS tube M4 and the MOS tube M19 to be turned on, the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module and the second bootstrap module to be turned off, and the first bootstrap interlock module and the second bootstrap interlock module are respectively interlocked to turn off the MOS tube M10 and the MOS tube M12, and finally the MOS tube M11 is turned off; During the sampling phase, the clock signal CK2 controls the pull-down module, the MOS tube M4 and the MOS tube M19 to be turned off, the clock signal CK1 and the clock signal CK2 cooperate to control the first bootstrap module and the second bootstrap module to be turned on, and the MOS tube M10 and the MOS tube M12 are interlocked and turned on through the first bootstrap interlock module and the second bootstrap interlock module, and finally the MOS tube M11 is turned on.

2. A high linearity gate voltage bootstrap switch circuit according to claim 1, characterized in that: The first bootstrap module and the second bootstrap module use capacitors to provide bootstrap voltages, and the capacitance value of the first bootstrap module or the second bootstrap module is greater than the gate capacitance of the MOS tube M11.

3. The high linearity gate voltage bootstrap switch circuit according to claim 1, characterized in that: The circuit structures of the first bootstrap module and the second bootstrap module are the same, and the circuit structures of the first bootstrap interlocking module and the second bootstrap interlocking module are the same.

4. The high linearity gate voltage bootstrap switch circuit according to claim 3, characterized in that: The first bootstrap module includes a first charge pump, a first capacitor module, a MOS tube M3, a MOS tube M5, a MOS tube M6 and a MOS tube M7; the first control end and the second control end of the first charge pump are respectively used as the first input end and the second input end of the first bootstrap module, one end of the first capacitor module is used as the first start end of the first bootstrap module, the other end of the first capacitor module is used as the interlocking end of the first bootstrap module, the source electrode of the MOS tube M7 is used as the second start end of the first bootstrap module, the source electrode of the MOS tube M5 is used as the output end of the first bootstrap module, and the ground end of the first charge pump is used as the ground end of the first bootstrap module; The gate of the MOS tube M6 and the gate of the MOS tube M7 are both electrically connected to the second control end of the first charge pump, the drain of the MOS tube M6 and the drain of the MOS tube M7 are both electrically connected to the gate of the MOS tube M5, the source of the MOS tube M3 and the other end of the first capacitor module are both electrically connected to the drain of the MOS tube M5, the gate of the MOS tube M3 is electrically connected to the output end of the first charge pump, and the drain of the MOS tube M3 and the source of the MOS tube M6 are both electrically connected to the ground end of the first charge pump; When the MOS tube M3 is turned off and the MOS tube M5 is turned on, the first bootstrap module is turned on; when the MOS tube M3 is turned on and the MOS tube M5 is turned off, the first bootstrap module is turned off.

5. The high linearity gate voltage bootstrap switch circuit according to claim 1, characterized in that: The pull-down module includes a MOS tube M22, a MOS tube M23 and a MOS tube M24; the source of the MOS tube M24 is used as the first end of the pull-down module, the source of the MOS tube M22 is used as the second end of the pull-down module, the drain of the MOS tube M23 is used as the third end of the pull-down module, and the gate of the MOS tube M24 is used as the control end of the pull-down module; The gate of the MOS tube M22 is electrically connected to the source of the MOS tube M24, the drain of the MOS tube M22 and the drain of the MOS tube M24 are both electrically connected to the source of the MOS tube M23, and the gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M24; When the MOS tube M24 is turned off and the MOS tube M22 and the MOS tube M23 are both turned on, the pull-down module is turned on; when the MOS tube M24 is turned on and the MOS tube M22 and the MOS tube M23 are both turned off, the pull-down module is turned off.

6. The high linearity gate voltage bootstrap switch circuit according to claim 3, characterized in that: The first bootstrap interlocking module includes a MOS tube M8 and a MOS tube M9; the gate of the MOS tube M8 is used as the input end of the first bootstrap interlocking module, the source of the MOS tube M8 is used as the interlocking end of the first bootstrap interlocking module, and the drain of the MOS tube M8 is used as the output end of the first bootstrap interlocking module; The gate of the MOS tube M8 is electrically connected to the gate of the MOS tube M9, the drain of the MOS tube M8 is electrically connected to the drain of the MOS tube M9, and the source of the MOS tube M9 is grounded.

7. The high linearity gate voltage bootstrap switch circuit according to claim 6, characterized in that: The first bootstrap interlocking module further includes a first charge absorption circuit; an input end of the first charge absorption circuit is electrically connected to a source of the MOS tube M8, and a control end of the first charge absorption circuit receives the clock signal CK1; The first charge absorption circuit is used to absorb the channel charge generated by the MOS transistor M8.

8. The high linearity gate voltage bootstrap switch circuit according to claim 7, characterized in that: The first charge absorption circuit includes a MOS tube M25; the drain of the MOS tube M25 is used as the input end of the first charge absorption circuit, and the gate of the MOS tube M25 is used as the control end of the first charge absorption circuit; the drain and source of the MOS tube M25 are electrically connected.

9. The high linearity gate voltage bootstrap switch circuit according to claim 4, characterized in that: The first charge pump comprises a capacitor C1, a capacitor C2, a MOS transistor M1 and a MOS transistor M2; one end of the capacitor C1 is used as a first control end of the first charge pump, one end of the capacitor C2 is used as a second control end of the first charge pump, the other end of the capacitor C1 is used as an output end of the first charge pump, and the drain of the MOS transistor M2 is used as a ground end of the first charge pump; The other end of the capacitor C1 and the source of the MOS tube M1 are electrically connected to the gate of the MOS tube M2, the other end of the capacitor C2 and the source of the MOS tube M2 are electrically connected to the gate of the MOS tube M1, and the drain of the MOS tube M1 is electrically connected to the drain of the MOS tube M2.

10. The high linearity gate voltage bootstrap switch circuit according to claim 4, characterized in that: The first capacitor module includes a capacitor C3; one end of the capacitor C3 is used as one end of the first capacitor module, and the other end of the capacitor C3 is used as the other end of the first capacitor module.

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