Device and method for detecting current, composite power switch and power supply

Abstract

The invention provides a device and a method for detecting current, a compound power switch and a power supply. The power switch comprises a control end, a reference end and a channel end. A control signal on the control end can turn on the power switch and electrically connect the reference end with the channel end, or turn off the power switch and electrically isolate the reference end from the channel end. The conduction current flows through the reference end and the channel end. The system further comprises a voltage detector, a current detector and a closed loop controller. The voltage detector is electrically connected to the channel end. When the power switch is turned on, the voltage detector transmits the channel voltage on the channel end to the voltage detection end, and the channel voltage becomes detection voltage. When the power switch is turned off, the voltage detector makes the detection voltage different from the channel voltage. The current detector is electrically connected to the reference end and the control end and provides a current detection end. The closed loop controller is electrically connected to the current detection end and the voltage detection end and provides the simulation current to the current detection end, so that the controlled voltage on the current detection end is approximately equal to the detection voltage.

Description

Technical Field

[0001] The present invention relates to a method and a related device for detecting a conduction current flowing through a power switch, and more particularly to a method for generating an output current proportional to the conduction current. Background Art

[0002] Power switches are used to conduct large currents and are often used to control the current flowing through an inductor or capacitor. In terms of control, the current flowing through the power switch should be accurately detected, for example, to ensure that an inductor does not fail due to magnetic saturation caused by excessive current.

[0003] Figure 1 The following shows how the prior art detects the on-current IN1 flowing through the power switch N1. The power switches N1 and N2 (two NMOS transistors) have roughly similar structures. Basically, under the same gate-to-source voltage and drain-to-source voltage, the currents conducted by the power switches N1 and N2 should be proportional, for example, 100:1. When the power controller 102 provides a control signal VG of about 20 volts through the control terminal DRV to turn on the power switches N1 and N2, the current detection signal VCS approximately reflects the detection current ICS. Through the proportional relationship between the current IN1 and the detection current ICS, the inductor current flowing through the inductor L (equal to the sum of the current IN1 and the detection current ICS) can be roughly inferred.

[0004] only, Figure 1 In the example, power switches N1 and N2 do not share exactly the same gate-to-source voltage V GS and drain-to-source voltage V DS Therefore, it is not possible to fully confirm that the currents conducted by power switches N1 and N2 are proportional. Figure 1 It can be seen that when the power switches N1 and N2 are turned on, the source S1 of the power switch N1 is grounded (0V), while the source S2 of the power switch N2 is the current detection signal VCS, which changes with the detection current ICS. For example, if the gate voltage VG is 20V and the current detection signal VCS is 0.4V, then the gate-to-source voltage V GS is 20V, and the gate-to-source voltage of power switch N2 is V GS is 19.6V, and the gate-to-source voltage V GS are not the same. Similarly, Figure 1 When the current detection signal VCS is not 0V, the power switches N1 and N2 do not have exactly the same drain-to-source voltage V DS .so, Figure 1The power controller 102 in the embodiment cannot accurately estimate the inductor current flowing through the inductor L through the current detection signal VCS. Summary of the invention

[0005] An embodiment of the present invention provides a device capable of detecting a conduction current flowing through a power switch. The power switch includes a control terminal, a reference terminal, and a channel terminal. A control signal on the control terminal can turn on the power switch to electrically connect the reference terminal and the channel terminal, or turn off the power switch to electrically isolate the reference terminal and the channel terminal. The conduction current flows through the reference terminal and the channel terminal. The device includes a voltage detector, a current detector, and a closed loop controller. The voltage detector is electrically connected to the channel terminal. When the power switch is turned on, the voltage detector is used to transfer a channel voltage on the channel terminal to a voltage detection terminal to become a detection voltage. When the power switch is turned off, the voltage detector makes the detection voltage different from the channel voltage. The current detector is electrically connected to the reference terminal and the control terminal, and provides a current detection terminal. The closed loop controller is electrically connected to the current detection terminal and the voltage detection terminal, and provides a simulation current to the current detection terminal so that a controlled voltage on the current detection terminal is approximately equal to the detection voltage.

[0006] The embodiment of the present invention further provides a method for detecting a conduction current of a power switch. The power switch includes a control terminal, a reference terminal, and a channel terminal. The method includes: turning on the power switch, electrically connecting the reference terminal and the channel terminal; when the power switch is turned on, transmitting a channel voltage on the channel terminal to a voltage detection terminal as a detection voltage; turning off the power switch, electrically isolating the reference terminal from the channel terminal; when the power switch is turned off, making the detection voltage on the voltage detection terminal different from the channel voltage; electrically connecting a current detector to the reference terminal and the control terminal, wherein the current detector provides a current detection terminal; and providing a simulated current to the current detection terminal so that a controlled voltage on the current detection terminal is approximately equal to the detection voltage.

[0007] The embodiment of the present invention further provides a composite power switch, comprising a first power switch, a second power switch, and a third power switch, which are formed on the same substrate. Each power switch has a gate, a drain, and a source. The three gates of the first, second, and third power switches are electrically connected to each other as a control terminal. The two drains of the first and third power switches are electrically connected to each other as a channel terminal. The two sources of the first and second power switches are electrically connected to each other as a reference terminal. A source of the third power switch serves as a voltage detection terminal of the composite power switch. A drain of the second power switch serves as a current detection terminal of the composite power switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It shows how the prior art detects the on-current IN1 flowing through the power switch N1.

[0009] Figure 2 The device 200 according to an embodiment of the present invention is shown for detecting the on-current INM flowing through the power switch NM2 .

[0010] Figure 3 A top view of a composite power switch 204 formed on a substrate 260 of a semiconductor chip according to the present invention is shown.

[0011] Figure 4 The device 300 according to the embodiment of the present invention is shown to be used to detect the on-state current INMR flowing through the power switch NM3 .

[0012] Figure 5 The device 400 implemented according to the present invention is shown to realize the current detection of the lower arm power switch.

[0013] Figure 6 An asymmetric half-bridge power supply according to the present invention is shown.

[0014] Figure 7 An apparatus 700 according to an embodiment of the present invention is shown for detecting an on-current IPM flowing through a power switch PM7.

[0015]

Explanation of symbols

[0016] 102 Power Controller

[0017] 200, 300, 400, 700 units

[0018] 202, 302, 402, 502, 602, 702 closed loop controller

[0019] 204, 304, 404, 504, 604, 704 composite power switches

[0020] 206, 306, 406, 506, 606, 706 voltage detectors

[0021] 208, 308, 408, 508, 608, 708 current detectors

[0022] 220, 320, 420, 520, 620, 720 operational amplifiers

[0023] 222, 322, 422, 522, 622, 722 current mirror

[0024] 260 Base

[0025] 261 Common Active Area

[0026] 428, 528 resistors

[0027] 480 GAN transistor

[0028] C5 capacitor

[0029] CH Channel terminal

[0030] D Drain

[0031] DA drain area

[0032] DT Voltage detection terminal

[0033] DRV, DRVH, DRVL control terminal

[0034] EM current sensing terminal

[0035] F1~F7 fingers

[0036] G Gate

[0037] ICS detection current

[0038] IL4, IL5 inductor current

[0039] IN1, INM, INMR, INM4, INM5, INMR6, IPM on-state current

[0040] IOUT, IOUTH, IOUTL output current

[0041] IRZ, IRZH, IRZL simulation current

[0042] L, L4, L5 inductors

[0043] N1, N2, NC2, NM2, NV2, NC3, NM3, NV3, NC4, NM4, NV4, NM5, NM6 power switches

[0044] NCC, NCCH, NCCL NMOS transistors

[0045] PM7, PC7, PV7 power switches

[0046] RF Reference

[0047] S Source

[0048] SA source area

[0049] VCH channel voltage

[0050] VCS current detection signal

[0051] VDT detection voltage

[0052] VEM controlled voltage

[0053] VG control signal

[0054] VIN input power line DETAILED DESCRIPTION

[0055] In order to make the purpose, implementation and advantages of the embodiments of the present invention clearer, the implementation in the embodiments will be described clearly and completely in conjunction with the drawings of the embodiments. The embodiments described in this specification are only part of the embodiments of the present invention, not all of the embodiments. Those with ordinary knowledge in the relevant fields of the present invention can make various modifications and variations to the embodiments described in this specification without departing from the spirit and scope of the present invention.

[0056] Figure 2 The device 200 is shown according to an embodiment of the present invention, and is used to detect the on-current INM flowing through the power switch NM2 . The device 200 includes a voltage detector 206 , a current detector 208 , and a closed loop controller 202 . Figure 2 The power switch NM2 in the embodiment is an NMOS transistor, but the present invention is not limited thereto. In other embodiments, the power switch NM2 may be a PMOS transistor, a field effect transistor, a gallium nitride (GAN) transistor, a silicon carbide (SiC) transistor, or other semiconductor power switch.

[0057] The drain D, source S, and gate G of the power switch NM2 serve as the channel terminal CH, the reference terminal RF, and the control terminal DRV, respectively. The control signal VG of the control terminal DRV can turn on or off the power switch NM2. When the power switch NM2 is turned on, the power switch NM2 provides a low-impedance conductive channel, electrically connecting the channel terminal CH and the reference terminal RF. When the power switch NM2 is turned off, the conductive channel becomes high-impedance, and the power switch NM2 electrically isolates the channel terminal CH from the reference terminal RF.

[0058] as Figure 2 As shown, the voltage detector 206 and the current detector 208 are the power switch NV2 and the power switch NC2 respectively. In one embodiment, the power switches NM2, NV2 and NC2 can be formed together on the same semiconductor substrate to form a composite power switch 204, providing a control terminal DRV, a channel terminal CH, a reference terminal RF, a voltage detection terminal DT, and a current detection terminal EM. Figure 2 In the embodiment of FIG. 1 , each power switch NM2 , NV2 and NC2 is an NMOS transistor, and has a gate G, a drain D, and a source S. Figure 2In the embodiment, the gates G of the power switches NM2, NV2 and NC2 are electrically connected to each other, serving as the control terminal DRV of the composite power switch 204. The drains D of the power switches NM2 and NV2 are electrically connected to each other to serve as the channel terminal CH of the composite power switch 204. The source S of the power switch NV2 serves as the voltage detection terminal DT of the composite power switch 204. The sources S of the power switches NM2 and NC2 are electrically connected to each other, serving as the reference terminal RF of the composite power switch 204. The drain D of the power switch NC2 serves as the current detection terminal EM of the composite power switch 204.

[0059] as Figure 2 As shown, the voltage detector 206 is electrically connected to the channel terminal CH and the control terminal DRV. When the control signal VG turns on the power switch NM2, the power switch NV2 in the voltage detector 206 is also turned on, so the channel voltage VCH on the channel terminal CH can be transmitted to the voltage detection terminal DT to become the detection voltage VDT. When the control signal VG turns off the power switch NM2, the power switch NV2 in the voltage detector 206 is also turned off, so the detection voltage VDT is different from the channel voltage VCH.

[0060] The current detector 208 is electrically connected to the reference terminal RF and the control terminal DRV, and provides a current detection terminal EM. Figure 2 In the embodiment, when the control signal VG turns on / off the power switch NM2, the power switch NC2 is also turned on / off at the same time.

[0061] The closed loop controller 202 is electrically connected to the current detection terminal EM and the voltage detection terminal DT, and provides an emulation current IRZ to the current detection terminal EM so that the controlled voltage VEM on the current detection terminal EM is approximately equal to the detection voltage VDT. Figure 2As shown, the closed loop controller 202 has an operational amplifier 220, an NMOS transistor NCC, and a current mirror 222. The operational amplifier 220 acts as a differential amplifier. When the detection voltage VDT on the two inverse differential input terminals is different from the controlled voltage VEM, the operational amplifier 220 controls the NMOS transistor NCC, which acts as a controllable current source to change the emulation current IRZ provided by the NMOS transistor NCC, which flows to the power switch NC2 through the current detection terminal EM, so that the controlled voltage VEM is approximately the same as the detection voltage VDT. For example, if the detection voltage VDT is greater than the controlled voltage VEM, the operational amplifier 220 increases the gate voltage of the NMOS transistor NCC, and the emulation current IRZ increases, causing the controlled voltage VEM to increase and approach the detection voltage VDT. In this way, the closed loop provided by the closed loop controller 202 can roughly keep the controlled voltage VEM approximately equal to the detection voltage VDT. The current mirror 222 mirrors the emulation current IRZ to generate an output current IOUT as the output of the closed loop controller 202.

[0062] When the control signal VG turns on the power switch NM2, the output current IOUT can be quite accurately proportional to the conduction current INM flowing through the power switch NM2. When the control signal VG turns on the power switch NM2, the power switches NV2 and NC2 are also turned on, the detection voltage VDT is approximately equal to the channel voltage VCH, and the closed loop controller 202 makes the controlled voltage VEM approximately equal to the detection voltage VDT. Therefore, the power switch NM2 and the power switch NC2 will share approximately the same gate-to-source voltage (V GS ) and the drain-to-source voltage (V DS As long as the power switch NM2 and the power switch NC2 have similar structures, the power switch NM2 and the power switch NC2 can become a current mirror, and the conduction current INM and the simulation current IRZ will be linearly proportional, so the output current IOUT is also linearly proportional to the conduction current INM.

[0063] When the control signal VG turns off the power switch NM2, the voltage detector 206 can prevent the excessively high channel voltage VCH on the channel terminal CH from damaging the electronic components in the closed-loop controller 202. For example, when the control signal VG and the reference terminal RF are both 0V, the power switch NM2 is turned off. At this time, the channel voltage VCH may be as high as 500V due to the charging of an inductor current. At this time, the power switch NV2 in the voltage detector 206 is also turned off, so the detection voltage VDT on the source S of the power switch NV2 may be only 0V, which is completely different from the channel voltage VCH of 500V. As long as the power switch NV2 is a high-voltage-resistant component, the power switch NV2 and the closed-loop controller 202 will not be damaged by the excessively high channel voltage VCH.

[0064] Figure 3 The top view of the composite power switch 204 formed on the substrate 260 of a semiconductor chip according to the present invention is shown. The finger gate structure has a plurality of fingers F1 to F7, which serve as the control terminal DRV of the composite power switch 204. Each finger can be used as a gate of a transistor, separating a drain area DA and a source area SA, and is also used to control the electrical connection between the drain area DA and the source area SA. All drain areas DA and source areas SA are located in a common active area 261 on the substrate 260, and Figure 3 In the top view of FIG, the common active region 261 is surrounded by a field oxide layer or a shallow trench isolation layer. Figure 3 In FIG. 2 , the fingers F1 to F7 can be regarded as dividing the common active region 261 into the drain region DA and the source region SA. Figure 3 As shown, finger F1 roughly serves as the gate G of power switch NV2, and the source area SA on the left side of finger F1 is the source S of power switch NV2, serving as the voltage detection terminal DT. Similarly, finger F7 roughly serves as the gate G of power switch NC2, and the drain area DA on the right side of finger F7 is the drain D of power switch NC2, serving as the current detection terminal EM. Fingers F2 to F6 serve as the gate G of power switch NM2, and the source area SA between fingers F2 and F7 is electrically connected as the reference terminal RF, and the drain area DA between fingers F1 and F6 is electrically connected as the channel terminal CH. Figure 3 From the cross-sectional view of FIG. 1 , it can be seen that the power switches NM2, NC2, and NV2 have similar structures. Therefore, as long as the power switches NM2, NC2, and NV2 have the same gate-to-source voltage V GS The drain-to-source voltage V DS , the currents flowing through the power switches NM2, NC2, and NV2 will be approximately in a fixed proportional relationship, forming a current mirror.

[0065] Figure 2 The device 200 in the embodiment can be used to detect the state when the on-current INM flowing through the power switch NM2 is positive. Figure 4 It is shown that the device 300 according to the embodiment of the present invention can be used to detect the on-current INMR flowing through the power switch NM3 , whose direction is opposite to the on-current INM of the power switch NM2 . Figure 4 and Figure 2 There are many identical or similar parts, which can be known from the previous explanations and will not be repeated here.

[0066] As is known in the industry, electrically speaking, the source of an NMOS transistor generally refers to the end with a lower voltage between the two ends of the controllable channel. Figure 2In the case of a power switch NM2, due to the direction of the conduction current INM, the channel voltage VCH on the drain D (channel terminal CH) of the power switch NM2 is higher than the voltage on the source S (reference terminal RF) of the power switch NM2. Figure 4 In the example, because the on-current INMR flows from the source S to the drain D of the power switch NM3, the drain D of the power switch NM3 acts as the electrical source, and the source S of the power switch NM3 acts as the electrical drain. Figure 4 As shown, the drain D of the power switch NM3 becomes the reference terminal RF, the source S of the power switch NM3 becomes the channel terminal CH, the power switch NV3 becomes the current detector 308, and the power switch NC3 becomes the voltage detector 306. Figure 2 As explained in the operation Figure 4 In the embodiment, the closed loop controller 302 is electrically connected to the current detection terminal EM and the voltage detection terminal DT, and provides an emulation current IRZ to the current detection terminal EM so that the controlled voltage VEM on the current detection terminal EM is approximately equal to the detection voltage VDT. The output current IOUT generated by the current mirror 322 is linearly proportional to the conduction current INMR.

[0067] Figure 2 The device 200 and Figure 4 Any of the devices 300 can be applied to upper arm power switch current detection or lower arm power switch current detection. Generally, the upper arm power switch refers to a power switch used to control the current flowing into / out of a high voltage power line, and the lower arm power switch refers to a power switch used to control the current flowing into / out of a ground line.

[0068] Figure 5 The device 400 implemented according to the present invention is shown to realize the current detection of the lower arm power switch. Figure 5 and Figure 2 There are many identical or similar parts, which can be known from the previous explanations and will not be repeated here.

[0069] The power switch NM4 and the depletion mode gallium nitride (GAN) transistor 480 form a cascode configuration as a lower arm power switch, connected between the inductor L4 and the ground line. The gate G of the GAN transistor 480 is connected to the source S of the power switch NM4. The inductor L4 is connected to the input power line VIN. The composite power switch 404 includes the power switch NM4, NV4 and NC4. The output current IOUT provided by the closed loop controller 402 flows through the resistor 428 to generate an output voltage VOUT. According to the previous description, when the power switch NM4 is turned on, the output voltage VOUT is roughly proportional to the conduction current INM4 flowing through the power switch NM4, which is equal to the inductor current IL4 flowing through the inductor L4.

[0070] Figure 6 According to one embodiment of the present invention, an asymmetric half-bridge (AHB) power supply is shown. Power switches NM5 and NM6 are the upper arm and lower arm of the half bridge, respectively, connected between the input power line VIN and the ground line. Power switches NM5 and NM6 drive a resonant circuit composed of inductor L5 and capacitor C5. Closed loop controller 502 and composite power switch 504 implement upper arm switch current detection, many parts of which can be explained previously. Figure 2 The closed loop controller 602 and the composite power switch 604 implement the lower arm switch current detection, many parts of which can be explained in the previously explained Figure 4 The above description can be understood by referring to the device 300 in the figure and will not be repeated here.

[0071] exist Figure 6 , when the power switch NM5 is turned on and the power switch NM6 is turned off, the power switch NM5 provides a conduction current INM5 to charge the inductor L5 and the capacitor C5, and the inductor current IL5 is equal to the conduction current INM5. The output current IOUTH provided by the current mirror 522 is proportional to the inductor current IL5. The output current IOUTL provided by the current mirror 622 is equal to 0A because no current flows through the current detector 608. The output current IOUTH and IOUTL flow through the resistor 528 together, so when the power switch NM5 is turned on and the power switch NM6 is turned off, the output voltage VOUT is approximately proportional to the inductor current IL5.

[0072] When the power switch NM5 is turned off and the power switch NM6 is turned on, the power switch NM6 provides a conduction current INMR6 as the inductor current IL5 flowing through the inductor L5. At this time, the output current IOUTL provided by the current mirror 622 is proportional to the inductor current IL5. The output current IOUTH provided by the current mirror 522 is equal to 0A because no current flows through the current detector 508. The output current IOUTH flows through the resistor 528 together with IOUTL. Therefore, when the power switch NM5 is turned off and the power switch NM6 is turned on, the output voltage VOUT is still roughly proportional to the inductor current IL5.

[0073] In other words, the output voltage VOUT can faithfully reflect the charging process of the inductor L5 and the inductor current IL5 during the discharging process.

[0074] Figure 7 The device 700 according to an embodiment of the present invention is used to detect the on-current IPM flowing through the power switch PM7, wherein the power switch PM7 is a PMOS transistor. The similar or identical parts of the device 700 and 200 can be known from the previous description and may not be repeated.

[0075] The device 700 has a voltage detector 706, a current detector 708, and a closed loop controller 702. The composite power switch 704 is formed on a semiconductor substrate of an integrated circuit, and has power switches PM7, PC7, and PV7, which are all PMOS transistors. The operational amplifier 720 in the closed loop controller 702 controls the NMOS transistor NCC to provide an emulation current IRZ, which flows through the power switch PC7 in the current detector 708, so that the controlled voltage VEM is approximately equal to the detection voltage VDT. Through a current mirror formed by the power switches PM7 and PC7, the emulation current IRZ is proportional to the conduction current IPM. The current mirror 722 makes the output current IOUT proportional to the emulation current IRZ. Therefore, the output current IOUT is proportional to the conduction current IPM.

[0076] The present invention can accurately detect a conduction current of a power switch when the power switch is turned on, and can also prevent an excessively high channel voltage on the power switch from damaging an internal circuit when the power switch is turned off.

[0077] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A device for detecting a conduction current flowing through a power switch, wherein: The power switch includes a control terminal, a reference terminal and a channel terminal. A control signal on the control terminal can turn on the power switch to electrically connect the reference terminal and the channel terminal, or turn off the power switch to electrically isolate the reference terminal and the channel terminal. The conduction current flows through the reference terminal and the channel terminal. The device includes: a voltage detector electrically connected to the channel end, wherein when the power switch is turned on, the voltage detector is used to transfer a channel voltage on the channel end to a voltage detection end to become a detection voltage, and when the power switch is turned off, the detection voltage is different from the channel voltage; a current detector electrically connected to the reference terminal and the control terminal and providing a current detection terminal; as well as A closed loop controller is electrically connected to the current detection terminal and the voltage detection terminal, and provides a simulated current to the current detection terminal so that a controlled voltage on the current detection terminal is approximately equal to the detection voltage.

2. The device of claim 1, wherein: The power switch is a first power switch, and the current detector includes a second power switch. Each power switch has a gate, a source and a drain. The two gates of the first and second power switches are electrically connected as the control end, the two sources of the first and second power switches are electrically connected as the reference end, and the drain of the second power switch serves as the current detection end.

3. The device of claim 2, wherein: The voltage detector includes a third power switch, the two drains of the first and third power switches are electrically connected as the channel end, the three gates of the first, second and third power switches are electrically connected as the control end, and the source of the third power switch is used as the voltage detection end.

4. The device of claim 1, wherein: The closed-loop controller includes a differential amplifier and a controllable current source. The differential amplifier has two inverse differential input terminals and an output terminal. The two differential input terminals are electrically connected to the current detection terminal and the voltage detection terminal respectively. The output terminal controls the controllable current source, which generates the simulation current to the current detection terminal.

5. The device of claim 1, wherein: When the power switch is turned on, the current detector and the power switch can form a first current mirror, and the closed loop controller further includes a second current mirror that mirrors the simulated current to generate an output current as an output of the closed loop controller.

6. The device of claim 1, wherein: The power switch is an N-type transistor. The control terminal, the reference terminal and the channel terminal are respectively a gate, a source and a drain of the N-type transistor.

7. The device of claim 1, wherein: The power switch is an N-type metal oxide semiconductor transistor, a P-type metal oxide semiconductor transistor, a field effect transistor, or a gallium nitride transistor.

8. The device of claim 1, wherein: The power switch is a first power switch, the voltage detector includes a second power switch, the current detector includes a third power switch, and the first, second and third power switches are formed together on the same substrate to form a composite power switch.

9. A method for detecting a conduction current of a power switch, wherein: The power switch includes a control terminal, a reference terminal and a channel terminal, including: Turning on the power switch to electrically connect the reference end and the channel end; When the power switch is turned on, a channel voltage on the channel end is transmitted to a voltage detection end as a detection voltage; Turning off the power switch to electrically isolate the reference end from the channel end; When the power switch is turned off, the detection voltage on the voltage detection terminal is different from the channel voltage; Electrically connecting a current detector to the reference terminal and the control terminal, wherein the current detector provides a current detection terminal; as well as A simulated current is provided to the current detection terminal so that a controlled voltage on the current detection terminal is approximately equal to the detection voltage.

10. The method of claim 9, wherein: The power switch is an N-type transistor. The control terminal, the reference terminal and the channel terminal are respectively a gate, a source and a drain of the N-type transistor.

11. The method of claim 9, further comprising: The controlled voltage is compared with the detection voltage to control the emulation current.

12. The method of claim 9, further comprising: The emulated current is mirrored to generate an output current.

13. A composite power switch, comprising: a control terminal, a channel terminal, a reference terminal, a voltage detection terminal, and a current detection terminal; and A first power switch, a second power switch, and a third power switch, each power switch having a gate, a drain, and a source, formed on a same substrate; in, The three gates of the first, second and third power switches are electrically connected to each other to form the control terminal; The two drain electrodes of the first and third power switches are electrically connected to each other to form the channel end; The two sources of the first and second power switches are electrically connected to each other to form the reference terminal; A source electrode of the third power switch serves as the voltage detection terminal of the composite power switch; and A drain electrode of the second power switch serves as the current detection terminal of the composite power switch.

14. The composite power switch according to claim 13, wherein: The substrate has a common active region, and the first, second and third power switches are all formed in the common active region.

15. The composite power switch according to claim 14, wherein: The common active region has a plurality of drain regions and a plurality of source regions, which are separated from each other by a plurality of fingers, which serve as the gates of the first, second, and third power switches, one of the drain regions serves as the two drains of the first and third power switches, and one of the source regions serves as the two sources of the first and second power switches.

16. A power supply comprising: The composite power switch as claimed in claim 13; an inductor connected to one of the channel terminal and the reference terminal of the composite power switch; and A closed loop controller is electrically connected to the current detection end and the voltage detection end. When the first power switch is turned on, the closed loop controller provides a simulated current to the current detection end so that a controlled voltage on the current detection end is approximately equal to a detection voltage on the voltage detection end.

17. The power supply of claim 16, wherein: The closed-loop controller includes a differential amplifier and a controllable current source. The differential amplifier has two reverse differential input terminals and an output terminal. The two differential input terminals are electrically connected to the current detection terminal and the voltage detection terminal respectively. The output terminal controls the controllable current source, which generates the simulation current to the current detection terminal.

18. The power supply of claim 17, wherein: The closed loop controller includes a current mirror, which mirrors the emulation current to generate an output current as an output of the closed loop controller.

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