Grid control circuit and motor control system

Abstract

The invention provides a grid control circuit and a motor control system, and relates to the technical field of motor driving. The grid control circuit comprises an on-off control unit, a logic control unit, a power management unit and a grid driving unit, the power supply end of the on-off control unit is used for being connected with a preset high-voltage power supply, and the first output end of the on-off control unit is connected with the enabling end of the power management unit and used for enabling the on-off control unit to output enabling current based on the key signal; the second output end of the on-off control unit is connected with the input end of the logic control unit, so that the logic control unit generates a logic signal of an on-off state based on the key signal, and the output end of the logic control unit is connected with the gate driving unit; and the gate driving unit generates and outputs a corresponding gate driving signal based on the logic signal of the logic control unit. According to the grid control circuit, shutdown zero current can be realized.

Description

Technical Field

[0001] The present application relates to the field of motor drive technology, and in particular to a gate control circuit and a motor control system. Background Art

[0002] In the power management system of modern electronic devices, the gate drive circuit plays a vital role. The traditional gate drive architecture generally adopts a mode in which the logic control unit is directly connected to the gate drive unit. The signal generated by the logic control unit is used to directly control the working state of the gate drive unit, thereby achieving effective drive of the gate of the power device, and then controlling the conduction and shutdown of the power device to meet the circuit's needs for power conversion and control.

[0003] However, the power consumption requirements for electronic devices in the shutdown state are becoming more and more stringent. The gate drive circuit usually directly controls the gate drive unit through a logic control unit. Some methods rely on the logic controller software to keep running at all times. Even when the device is in the shutdown state, the logic controller software continues to monitor and process related signals so that it can quickly control the gate drive unit to achieve zero current consumption when needed. However, this method will inevitably consume a certain amount of electrical energy and cannot truly achieve zero current consumption when shutting down. Another method is for the user to flip the switch to cut off the power of the entire system to achieve zero current, but the operation is inconvenient and the control method is not flexible. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present application provides a gate control circuit and a motor control system to solve the problems existing in the prior art.

[0005] The technical solution adopted in the embodiment of the present application is as follows: In a first aspect, an embodiment of the present application provides a gate control circuit, including: a switch control unit, a logic control unit, a power management unit, and a gate driving unit; The power supply terminal of the power on / off control unit is used to connect to a preset high voltage power supply, and the first output terminal of the power on / off control unit is connected to the enable terminal of the power management unit, so that the power on / off control unit outputs an enable current based on a key signal; The first output end of the power management unit is connected to the power supply end of the logic control unit to provide power supply, and the second output end of the power management unit is connected to the driving end of the gate driving unit to provide driving power; The second output end of the power on / off control unit is connected to the input end of the logic control unit, so that the logic control unit generates a logic signal of the power on / off state based on the key signal, and the output end of the logic control unit is connected to the gate driving unit, so that the gate driving unit generates and outputs a corresponding gate driving signal based on the logic signal of the logic control unit.

[0006] In one embodiment, the power on / off control unit includes: a key control circuit, a power on / off detection circuit, a bias current generating circuit, and an enabling current output circuit; The first end of the key control circuit is the power supply end of the power on / off control unit, and is used to connect the preset high-voltage power supply. The second end of the key control circuit is connected to the input end of the power on / off detection circuit, so that the power on / off detection circuit generates a detection current based on the key signal output by the key control circuit. The output end of the power on / off detection circuit is connected to the input end of the bias current generating circuit, so that the bias current generating circuit generates a bias current based on the detection current. The output end of the bias current generating circuit is connected to the enable current output circuit, so that the enable current output circuit generates and outputs the enable current based on the bias current. The third terminal of the button control circuit is the second output terminal of the power on / off control unit, which is used to connect to the input terminal of the logic control unit.

[0007] In one embodiment, the key control circuit includes: a first resistor, a second resistor and a single-key switch; One end of the first resistor is the first end of the button control circuit, the other end of the first resistor is connected to one end of the single-key switch, the other end of the single-key switch is the second end of the button control circuit, and is used to connect the input end of the power on / off detection circuit, and the other end of the single-key switch is also connected to the input end of the logic control unit through the second resistor.

[0008] In one embodiment, the power on / off detection circuit includes: a first current mirror unit, a second current mirror unit, a voltage regulator tube and a third resistor; The power supply end of the first current mirror unit is the input end of the power on / off detection circuit, the current input end of the first current mirror unit is grounded through the third resistor, the current output end of the first current mirror unit is the output end of the power on / off detection circuit, the power supply end of the first current mirror unit is connected to the cathode of the Zener diode, the anode of the Zener diode is grounded, the power supply end of the first current mirror unit is also connected to the current output end of the second current mirror unit, and the current input end of the second current mirror unit is connected to the output end of the bias current generating circuit.

[0009] In one embodiment, the first current mirror unit is a P-type current mirror unit composed of a P-type triode, or a P-type current mirror unit composed of a PMOS tube; The second current mirror unit is a P-type current mirror unit composed of P-type triodes, or a P-type current mirror unit composed of PMOS tubes.

[0010] In one embodiment, the bias current generating circuit includes: a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fourth resistor; One end of the fourth resistor is connected to the emitter of the second N-type transistor, the other end of the fourth resistor is grounded, the base of the second N-type transistor is connected to the collector of the first N-type transistor and the emitter of the third N-type transistor, and the collector of the second N-type transistor is connected to the base of the first N-type transistor and the emitter of the fourth N-type transistor; The emitter of the first N-type transistor is grounded, the collector of the third N-type transistor, the base of the third N-type transistor and the base of the fourth N-type transistor are connected, and the collector of the third N-type transistor is the input end of the bias current generating circuit; The collector of the fourth N-type transistor is connected to the current input end of the second current mirror unit.

[0011] In one embodiment, the enabling current output circuit includes: a P-type switch tube; The control end of the P-type switch tube is the input end of the enable current output circuit, one end of the P-type switch tube is used to connect to the preset high voltage power supply, and the other end of the P-type switch tube is the output end of the enable current output circuit.

[0012] In one embodiment, the gate control circuit further includes: a state monitoring unit; The state monitoring unit is connected to the power management unit and the gate driving unit.

[0013] In one embodiment, the on / off control unit, the logic control unit, the power management unit, the gate driving unit, and the state monitoring unit are integrated on one chip.

[0014] In a second aspect, an embodiment of the present application further provides a motor control system, comprising at least the gate control circuit described in any of the above embodiments.

[0015] The beneficial effects of the present application are as follows: the present application provides a gate control circuit, including a power-on / off control unit, a logic control unit, a power management unit and a gate driving unit; the power supply end of the power-on / off control unit is used to connect a preset high-voltage power supply, and the first output end of the power-on / off control unit is connected to the enable end of the power management unit, so that the power-on / off control unit outputs an enable current based on a key signal; the first output end of the power management unit is connected to the power supply end of the logic control unit to provide a power supply, and the second output end of the power management unit is connected to the drive end of the gate driving unit to provide a drive power supply; the second output end of the power-on / off control unit is connected to the input end of the logic control unit, so that the logic control unit generates a logic signal of the power-on / off state based on the key signal, and the output end of the logic control unit is connected to the gate driving unit, so that the gate driving unit generates and outputs a corresponding gate driving signal based on the logic signal of the logic control unit.

[0016] Among them, the power on / off control unit outputs an enabling current to the power management unit based on the key signal. When the enabling current is zero, the power management unit will be disabled, the power output will be turned off, and the system will not consume current, thus achieving the purpose of zero current shutdown. In addition, there is no need for the user to manually flip the switch to cut off the power, which effectively solves the problems of inconvenient operation and insufficient control flexibility of traditional power-off methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 One of the structural schematic diagrams of the gate control circuit provided in the embodiment of the present application; Figure 2 A schematic diagram of the structure of a power on / off control unit provided in an embodiment of the present application; Figure 3 A schematic diagram of the circuit principle of the gate control circuit provided in an embodiment of the present application; Figure 4 The second structural schematic diagram of the gate control circuit provided in the embodiment of the present application; Figure 5 A simplified flow chart of the on / off state of the gate control circuit; Figure 6 The waveforms of the voltage and power supply current at the key nodes when the gate control circuit is running; Figure 7 This is the third structural schematic diagram of the gate control circuit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0020] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0021] In the description of the present application, it should be noted that if the terms "upper", "lower", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the application is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0022] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection, it can be a direct connection, it can be an indirect connection through an intermediate medium, and it can be the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0025] In the power management system of modern electronic devices, the gate drive circuit plays a vital role. The traditional gate drive architecture generally adopts a mode in which the logic control unit is directly connected to the gate drive unit, and the signal generated by the logic control unit is used to directly control the working state of the gate drive unit, so as to effectively drive the gate of the power device (such as MOSFET, etc.), and then control the conduction and shutdown of the power device to meet the circuit's needs for power conversion and control.

[0026] However, as the concept of energy efficiency becomes more and more popular, the power consumption requirements of electronic devices in the shutdown state are becoming more and more stringent. Under the existing technical framework, there are many challenges to achieve the goal of zero current consumption when shutting down. On the one hand, some methods rely on the logic controller software to keep running all the time. Even when the device is in the shutdown state, the logic controller software continues to monitor and process related signals so that it can quickly control the gate drive unit to achieve zero current consumption when needed. However, this method will inevitably consume a certain amount of power and cannot truly achieve zero current consumption when shutting down. It also increases the complexity of software design and the instability of the system, and the continuously running software may also bring potential safety risks. On the other hand, some solutions attempt to achieve this by designing extremely complex hardware circuits for switching on and off. Such designs often require the introduction of a large number of additional electronic components, such as special switching circuits, energy storage components, and complex signal detection and switching circuits, which not only greatly increases the complexity, cost, and space occupied by the circuit board, but also reduces the reliability of the system due to the increase in the number of components. The failure of any newly added component may cause abnormalities in the entire system.

[0027] Therefore, the present application provides a gate control circuit that can solve the above-mentioned technical problems. The gate control circuit provided by the present application is specifically described below through multiple examples in combination with the accompanying drawings.

[0028] Figure 1 One of the structural schematic diagrams of the gate control circuit provided in the embodiment of the present application is as follows Figure 1 As shown, the gate control circuit includes a switch control unit, a logic control unit, a power management unit and a gate driving unit.

[0029] The power supply terminal of the switch control unit is used to connect the preset high voltage power supply V M The first output terminal of the power on / off control unit is connected to the enable terminal of the power management unit, so that the power on / off control unit outputs an enable current I based on the key signal. EN , the power management unit receives the enable current I EN Then the power management unit starts to work. Specifically, the power management unit works as follows: the first output terminal of the power management unit is connected to the power supply terminal of the logic control unit to provide the power supply V to the logic control unit.DD The second output terminal of the power management unit is connected to the driving terminal of the gate driving unit to provide a driving power supply V to the gate driving unit. CC .

[0030] The second output end of the power on / off control unit is connected to the input end of the logic control unit, so that the logic control unit generates a logic signal of the power on / off state based on the key signal, and the output end of the logic control unit is connected to the gate driving unit, so that the gate driving unit generates and outputs a corresponding gate driving signal based on the logic signal of the logic control unit.

[0031] In the shutdown state, the power on / off control unit consumes zero current, enabling current I EN When the power-on state is triggered by a key signal, the power-on control unit will automatically lock the power-on state, enabling the current I EN The power management unit will remain valid and keep working until the shutdown signal output by the logic control unit is detected. It should be noted that, according to the design structure of the power management unit, the enable current I EN Converted into a voltage signal and sent to the power management unit to enable it.

[0032] In summary, the embodiment of the present application provides a gate control circuit, and the switch control unit outputs an enabling current I to the power management unit based on the key signal. EN , when the enable current I EN When it reaches zero, the power management unit will be disabled, the power output will be turned off, and the system will not consume current, achieving the purpose of zero current shutdown. In addition, there is no need for the user to manually flip the switch to cut off the power, which effectively solves the problems of inconvenient operation and insufficient control flexibility of traditional power-off methods.

[0033] Figure 2 A schematic diagram of the structure of the power on / off control unit provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, in one embodiment, the power on / off control unit includes a key control circuit, a power on / off detection circuit, a bias current generating circuit, and an enabling current output circuit.

[0034] The first terminal of the key control circuit is the power supply terminal of the switch control unit, which is used to connect the preset high voltage power supply V MThe second end of the key control circuit is connected to the input end of the power on / off detection circuit, so that the power on / off detection circuit generates a detection current based on the key signal output by the key control circuit. The output end of the power on / off detection circuit is connected to the input end of the bias current generating circuit, so that the bias current generating circuit generates a bias current based on the detection current; the output end of the bias current generating circuit is connected to the enable current output circuit, so that the enable current output circuit generates and outputs an enable current based on the bias current. The third end of the key control circuit is the second output end of the power on / off control unit, which is used to connect to the input end of the logic control unit.

[0035] Figure 3 A schematic diagram of the circuit principle of the gate control circuit provided in the embodiment of the present application is shown in FIG. Figure 3 As shown, the key control circuit includes a first resistor R1, a second resistor R2 and a single-key switch S1. The first resistor R1 is a preset high-voltage power supply V M The current-limiting resistor between the switch control unit prevents excessive current from damaging components in the circuit; the second resistor R2 is the protective resistor between the switch control unit and the logic control unit, which plays a role in protecting the components; a single-key switch refers to a switch with only one operating button. Its structure is relatively simple and is mainly composed of a button, a shell, a contact, a spring and other parts. When the button is pressed, the internal contacts will close or open, thereby realizing the on-off control of the circuit. The single-key switch has the advantage of simple operation. The user only needs to press or release the button to complete the circuit control without complicated operating procedures.

[0036] One end of the first resistor R1 is the first end of the key control circuit, which is used to connect to the preset high voltage power supply V M The other end of the first resistor R1 is connected to one end of the single-key switch S1, and the other end of the single-key switch is the second end of the key control circuit, which is used to connect the input end of the power on / off detection circuit. The other end of the single-key switch is also connected to the input end of the logic control unit through the second resistor R2, that is, one end of the second resistor R2 is the third end of the key control circuit.

[0037] Assuming that the initial state of the gate control circuit is the shutdown state, the power-on / off control unit and the logic control unit work together to flexibly implement a variety of power-on / off modes of the gate control circuit, including but not limited to the following: a: the user presses the single-key switch S1 to turn on, and presses S1 again to turn off; b: the user presses the single-key switch S1 to turn on, and the logic control unit autonomously controls the shutdown; c: the user presses the single-key switch S1 to turn on, and after pressing S1 again, the logic control unit controls the delayed shutdown; d: the user presses the single-key switch S1 to turn on, and then presses S1 multiple times to turn off. The advantage of setting the single-key switch S1 in the power-on / off control unit is that after the chip is integrated, only one external pin needs to be reserved to realize the flexible power-on / off function.

[0038] Continue to refer to Figure 3 The power on / off detection circuit includes a first current mirror unit, a second current mirror unit, and a voltage regulator tube V Z And the third resistor R EN The first current mirror unit is a P-type current mirror unit composed of P-type transistors or a P-type current mirror unit composed of PMOS tubes, and the second current mirror unit can also be a P-type current mirror unit composed of P-type transistors or a P-type current mirror unit composed of PMOS tubes.

[0039] Figure 3 The first current mirror unit shown includes a P-type transistor Q P1 And P-type transistor Q P2 The second current mirror unit includes a P-type transistor Q P3 And P-type transistor Q P4 , the power supply terminal of the first current mirror unit (ie, Q P1 The emitter and Q P2 The emitter of the first current mirror unit (i.e., Q P1 The collector of EN The current output terminal of the first current mirror unit (ie, Q P2 The collector of the first current mirror unit (i.e., Q P1 The emitter and Q P2 The emitter of the voltage regulator is connected to V Z The cathode of the voltage regulator tube V Z The anode of the first current mirror unit is grounded, and the power supply terminal (Q P1 The emitter and Q P2 The emitter of the second current mirror unit is also connected to the current output terminal (Q P3 The collector of the second current mirror unit (Q P4 The collector of the bias current generating circuit is connected to the output end of the bias current generating circuit.

[0040] The bias current generating circuit includes a first N-type transistor Q N1 , the second N-type transistor Q N2 、The third N-type transistor Q N3 、The fourth N-type transistor Q N4 And the fourth resistor R B , the fourth resistor R B One end of the second N-type transistor Q N2 The emitter connection of the fourth resistor R B The other end of the second N-type transistor Q N2 The base of the first N-type transistor Q N1The collector and the third N-type transistor Q N3 The emitter of the second N-type transistor Q N2 The collector of the first N-type transistor Q N1 The base and the fourth N-type transistor Q N4 The emitter of the first N-type transistor Q N1 The emitter of the third N-type transistor Q N3 The collector of the third N-type transistor Q N3 The base of the fourth N-type transistor Q N4 The base of the third N-type transistor Q N3 The collector of is the input end of the bias current generating circuit; the fourth N-type transistor Q N4 The collector of is connected to the current input terminal of the second current mirror unit.

[0041] The enabling current output circuit includes a P-type switch tube, the control end of the P-type switch tube is the input end of the enabling current output circuit, one end of the P-type switch tube is used to connect to a preset high voltage power supply, and the other end of the P-type switch tube is the output end of the enabling current output circuit.

[0042] Among them, the P-type switch tube can be Figure 3 The P-type transistor Q shown P5 , or it can be a P-type MOS tube (not shown in the figure).

[0043] Figure 4 The second structural diagram of the gate control circuit provided in the embodiment of the present application is as follows: Figure 4 As shown, the gate control circuit may further include a status monitoring unit, which is connected to the power management unit and the gate drive unit to monitor the system operation status and shut down the power management unit or the gate drive unit when the system is abnormal. The monitored abnormal status includes but is not limited to system over-temperature, over-current, over-voltage, under-voltage, etc.

[0044] The condition monitoring unit improves the reliability of the system, plays a role in protecting the safety of equipment, and ensures the safety of personnel.

[0045] The working principle of the entire gate control circuit is: in the shutdown state, all units are not working, at this time Q P3 , Q P4 , Q P5 All are in the cut-off state, and the switch control unit consumes zero current. P5 The current is zero, the power management unit does not work, and the output V CC and V DD The voltage is zero, the gate drive unit, the status monitoring unit and the logic control unit are not working, and the entire system does not consume current. When you want to turn on the machine, press S1 and preset the high voltage power supply VM Generates current, flows into V through resistor R1 and S1 EN Node, when V EN The voltage reaches the PNP tube Q P1 The on-state voltage V BEP After that, Q P1 With resistor R EN The branch will be turned on and the mirror current will be given to Q P2 Tube, Q P2 The tube current is injected into Q as the starting current N3 Tube, when V EN Continue to increase to more than 2×V BEN After that, Q N1 , Q N2 , Q N3 , Q N4 and R B The bias current generating circuit formed is turned on, R B The branch current I RB for: , where V T is the thermoelectric potential, N is Q N2 With Q N4 ratio of the emitter area, the current is determined by Q P4 Mirror image to Q P3 and Q P5 Tube, Q P5 The tube will enable current I EN Sent to the power management unit to make the power management unit work and output power V CC With V DD The entire gate control circuit starts to start running.

[0046] Since V EN There is a voltage regulator V at the node Z , after S1 is pressed, V EN The voltage will reach V Z The clamp voltage V1, if S1 is released, the power supply V M To V EN The path is cut off, but due to Q P3 The tube is already turned on, generating a pull-up current that is injected into V EN Node, so that V EN The node is maintained at the turn-on voltage 2×V BEN Above, the entire gate control circuit still works normally, and the power-on state is locked.

[0047] Among them, V EN The locking voltage is determined by Q P3 Tube current and resistance R EN Resistance value determines, locked state V EN The lock voltage V0 should be between the start voltage 2×VBEP and the clamping voltage V1 of the voltage regulator. After the gate control circuit is turned on, the logic control unit works, outputs logic signals to the gate drive unit according to user instructions to make it operate as required, and outputs the converted gate drive signal.

[0048] The gate control circuit shutdown control can be flexibly implemented in a variety of ways. One is direct control by the logic control unit. When the user does not operate for a long time, the pin connected to R2 by the logic control unit can directly output a low level, which will turn V EN The node discharges when V EN The voltage is less than the starting voltage 2×V BEP After that, Q P2 Branch and Q N2 All branches are cut off, making Q P3 Pull-up current and Q P5 The enable current is zero, and the power management unit will turn off V CC With V DD Output, the entire gate drive unit does not work and returns to the shutdown state. At this time, even if the logic control unit is connected to the pin of R2 at a low level, it will fail due to V EN Without pull-up branch, V EN Still maintain low level.

[0049] The other is that after the single-button switch S1 is pressed again, the logic control unit decides when to shut down the system. At this time, the logic control unit needs to detect V EN Level, specifically: after power-on self-locking, V EN The voltage is the locking voltage V0. After the logic control unit is powered on, it starts to monitor V EN Voltage, when the single-button switch S1 is pressed again, V EN The resistor R1 is pulled up to the clamping voltage V1 again. The logic control unit detects the level flip from V0 to V1, which means that the single-button switch S1 is pressed, but it needs to continue to monitor V EN voltage until the single-button switch S1 is released, V EN becomes the locking voltage V0, and the logic control unit detects V EN The change from V1 to V0 indicates that the single-button switch S1 is released. After detecting this key operation, the logic control unit will decide when to shut down the system. When shutting down, the logic control unit only needs to output a low level at the I / O port connected to R2 to turn V EN Pull low to turn off the gate control circuit. Figure 5 It is a simplified flow chart of the above-mentioned power on and off states.

[0050] Figure 6The waveforms of the key node voltage and power supply current when the gate control circuit is running are shown from top to bottom: the state of the single-key switch S1 (high level represents pressing, low level represents releasing), V EN Node voltage, V CC Power supply voltage, V DD Supply voltage, overall system current I Q Waveform. It can be seen that the gate control circuit is in the off state at the beginning, V EN The voltage is 0.4V (starting voltage is 1.4V), the switch control unit is in the off state, V CC 、V DD Both output 0V, and the total current of the gate control circuit is 10nA, which can be basically ignored. When the single-button switch S1 is pressed for the first time, V EN The voltage is pulled up to 5V (V Z The clamping voltage of the tube is 5V), the gate control circuit starts to start, V CC 、V DD The gate control circuit outputs 12V and 5V voltages respectively. The gate control circuit consumes 30mA of stable working current when it is turned on. After the single-button switch S1 is released, V EN The voltage is locked at 3V. When the single-button switch S1 is pressed again, V EN It is pulled up to 5V again. After the logic control unit detects the rising edge from 3V to 5V, it continues to monitor the button status. When the single-button switch S1 is released, V EN The voltage will drop, and the logic control unit detects that V EN After the falling edge, a low level will be output to V EN Directly pull to 0V, then V CC and V DD is turned off, the current of the gate control circuit is reduced to 10nA, and it is in the off state again.

[0051] It should also be noted that the gate drive signal output by the gate drive unit can be single-channel or multi-channel, and the single-channel or multi-channel is determined by the number of gate drive units, for example Figure 1 As shown, when there is only one gate drive unit, a single-channel gate drive signal is output, which can be used to drive a single-phase motor; for example Figure 7 As shown, when there are three gate driving units, three-channel gate driving signals are output, which can be used to drive a three-phase motor.

[0052] In one embodiment, the power on / off control unit, logic control unit, power management unit, gate drive unit, and status monitoring unit described in the above embodiments of the present application are integrated on one chip, which has the following functions: 1. Reduce the size: Integrating multiple units on one chip eliminates the need to use multiple discrete components and circuit boards to implement these functions like traditional circuits, greatly reducing the size of the entire system and helping to achieve miniaturization and thinness of the equipment.

[0053] 2. Reduce costs: Integrated design reduces the number of discrete components used, as well as the corresponding circuit board area, packaging materials, etc., reducing raw material costs. At the same time, assembly, testing and other links in the production process are also simpler and more efficient, reducing labor costs and time costs, improving production efficiency, and thus reducing overall production costs.

[0054] 3. Improve performance: Each unit is connected and communicated through a high-speed, low-latency internal bus or circuit inside the chip, with fast signal transmission speed, and can better achieve collaborative work and precise synchronization between units. For example, the control signal can be quickly transmitted between the logic control unit and the gate drive unit to achieve precise control of the power device and improve the response speed and stability of the system; the power management unit can quickly adjust the supply voltage and current according to the actual needs of the system, provide stable and efficient power supply for other units, and help improve the performance of the entire system.

[0055] 4. Reduce power consumption: Integrated chips can use more advanced low-power design technologies and processes to optimize the power consumption management of each unit. For example, the power management unit can dynamically adjust the power supply according to the working status of the system, so that the chip can maintain low power consumption under different load conditions; the status monitoring unit can monitor the working status of the chip in real time. When it is found that some units are in an idle state, it notifies the power management unit to reduce the power consumption of this part, thereby effectively reducing the energy consumption of the entire chip and extending the use time of battery-powered devices.

[0056] 5. Improve reliability: The connection lines and interfaces between discrete components are reduced, and the probability of failure caused by poor connection, line interference and other factors is reduced. Moreover, chip manufacturers can carry out overall reliability design and testing of integrated chips during the design and production process to ensure the compatibility and stability between various units and improve the reliability and anti-interference ability of chips in various working environments. For example, the status monitoring unit can monitor the temperature, voltage and other key parameters of the chip in real time, and take protective measures in time when abnormalities are found to prevent the chip from being damaged due to overheating, overvoltage and other problems.

[0057] 6. Simplify the design and production process: For equipment manufacturers, the use of chips that integrate multiple functional units simplifies the circuit design process and reduces the complexity and workload of the design. At the same time, it also reduces the difficulty of quality management and control in the production process, because only a single chip needs to be purchased, inspected and assembled, rather than multiple discrete components, which helps to improve product consistency and production efficiency.

[0058] Based on the gate control circuit provided in the above embodiments, the present application also provides a motor control system, which at least includes the gate control circuit described in any one of the above embodiments.

[0059] Optionally, the motor control system may also include a power drive circuit and a motor, wherein the gate control circuit is mainly used to control the gate voltage of the power switch device (such as MOSFET, IGBT, etc.), thereby controlling the on and off of the power switch device to achieve precise control of the current in the motor winding. It can generate a suitable pulse width modulation (PWM) signal to drive the power switch device according to the needs of motor control, and then adjust the speed, torque and other parameters of the motor; the power drive circuit is connected between the gate control circuit and the motor, and converts the weak current signal output by the gate control circuit into a strong current signal that can drive the motor, providing sufficient power for the motor. It usually contains components such as power amplifiers and freewheeling diodes to ensure that the motor can operate normally under various working conditions; the motor, as the actuator of the system, converts electrical energy into mechanical energy to achieve rotation or linear motion to drive the load. According to different application scenarios, different types of motors such as DC motors, AC induction motors, and permanent magnet synchronous motors can be selected.

[0060] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A gate control circuit, characterized in that: include: Switch control unit, logic control unit, power management unit and gate drive unit; The power supply terminal of the power on / off control unit is used to connect to a preset high voltage power supply, and the first output terminal of the power on / off control unit is connected to the enable terminal of the power management unit, so that the power on / off control unit outputs an enable current based on a key signal; The first output end of the power management unit is connected to the power supply end of the logic control unit to provide power supply, and the second output end of the power management unit is connected to the driving end of the gate driving unit to provide driving power; The second output end of the power on / off control unit is connected to the input end of the logic control unit, so that the logic control unit generates a logic signal of the power on / off state based on the key signal, and the output end of the logic control unit is connected to the gate driving unit, so that the gate driving unit generates and outputs a corresponding gate driving signal based on the logic signal of the logic control unit.

2. The gate control circuit according to claim 1, characterized in that: The power on / off control unit includes: a key control circuit, a power on / off detection circuit, a bias current generating circuit, and an enabling current output circuit; The first end of the key control circuit is the power supply end of the power on / off control unit, and is used to connect the preset high-voltage power supply. The second end of the key control circuit is connected to the input end of the power on / off detection circuit, so that the power on / off detection circuit generates a detection current based on the key signal output by the key control circuit. The output end of the power on / off detection circuit is connected to the input end of the bias current generating circuit, so that the bias current generating circuit generates a bias current based on the detection current. The output end of the bias current generating circuit is connected to the enable current output circuit, so that the enable current output circuit generates and outputs the enable current based on the bias current. The third end of the button control circuit is the second output end of the power on / off control unit, which is used to connect to the input end of the logic control unit.

3. The gate control circuit according to claim 2, characterized in that: The key control circuit comprises: a first resistor, a second resistor and a single-key switch; One end of the first resistor is the first end of the button control circuit, the other end of the first resistor is connected to one end of the single-key switch, the other end of the single-key switch is the second end of the button control circuit, and is used to connect the input end of the power on / off detection circuit, and the other end of the single-key switch is also connected to the input end of the logic control unit through the second resistor.

4. The gate control circuit according to claim 2, characterized in that: The power on / off detection circuit comprises: a first current mirror unit, a second current mirror unit, a voltage regulator tube and a third resistor; The power supply end of the first current mirror unit is the input end of the power on / off detection circuit, the current input end of the first current mirror unit is grounded through the third resistor, the current output end of the first current mirror unit is the output end of the power on / off detection circuit, the power supply end of the first current mirror unit is connected to the cathode of the Zener diode, the anode of the Zener diode is grounded, the power supply end of the first current mirror unit is also connected to the current output end of the second current mirror unit, and the current input end of the second current mirror unit is connected to the output end of the bias current generating circuit.

5. The gate control circuit according to claim 4, characterized in that: The first current mirror unit is a P-type current mirror unit composed of a P-type triode, or a P-type current mirror unit composed of a PMOS tube; The second current mirror unit is a P-type current mirror unit composed of P-type triodes, or a P-type current mirror unit composed of PMOS tubes.

6. The gate control circuit according to claim 4, characterized in that: The bias current generating circuit comprises: a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a fourth resistor; One end of the fourth resistor is connected to the emitter of the second N-type transistor, the other end of the fourth resistor is grounded, the base of the second N-type transistor is connected to the collector of the first N-type transistor and the emitter of the third N-type transistor, and the collector of the second N-type transistor is connected to the base of the first N-type transistor and the emitter of the fourth N-type transistor; The emitter of the first N-type transistor is grounded, the collector of the third N-type transistor, the base of the third N-type transistor and the base of the fourth N-type transistor are connected, and the collector of the third N-type transistor is the input end of the bias current generating circuit; The collector of the fourth N-type transistor is connected to the current input end of the second current mirror unit.

7. The gate control circuit according to claim 2, characterized in that: The enabling current output circuit comprises: a P-type switch tube; The control end of the P-type switch tube is the input end of the enable current output circuit, one end of the P-type switch tube is used to connect to the preset high voltage power supply, and the other end of the P-type switch tube is the output end of the enable current output circuit.

8. The gate control circuit according to claim 1, characterized in that: The gate control circuit further includes: a state monitoring unit; The state monitoring unit is connected to the power management unit and the gate driving unit.

9. The gate control circuit according to claim 8, characterized in that: The on / off control unit, the logic control unit, the power management unit, the gate driving unit and the state monitoring unit are integrated on one chip.

10. A motor control system, characterized in that: At least: The gate control circuit according to any one of claims 1 to 9.

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