Semiconductor module

Abstract

A semiconductor module includes a high-potential-side drive circuit and a low-potential-side drive circuit. The high-potential-side drive circuit includes: a first reception terminal that receives a first data signal, an enable signal, and a first clock signal; a first shift register; and a first output terminal that outputs the first clock signal as a second clock signal to the low-potential-side drive circuit. The low-potential-side drive circuit includes: a second reception terminal that receives a second data signal, an enable signal, and a second clock signal; a second shift register; and a second output terminal that outputs, as a first data signal, a second data signal stored in the last-stage flip-flop of the second shift register to a high-potential-side drive circuit.

Description

Technical Field

[0001] The present invention relates to a semiconductor module, and in particular, to a semiconductor module having a power transistor and a drive circuit for driving the power transistor built therein. Background Art

[0002] A semiconductor module is known that has a built-in MPU (micro processing unit) having a function of generating a PWM (pulse width modulation) signal. The semiconductor module internally generates a PWM signal for controlling a switching device based on a signal from an external controller.

[0003] On the other hand, there is the following problem, namely, in order to be able to change the operating characteristics of the semiconductor module, communication is required between the external controller and the internal controller, data for the change is received from the outside, and a trigger signal for specifying the timing of the change is also required from the outside. Terminals are required for this, and the module cannot be miniaturized.

[0004] In this regard, Japanese Patent Application Laid-Open No. 2020-205702 discloses a semiconductor module that can be miniaturized and have changeable operating characteristics.

[0005] Specifically, in the structure of the semiconductor module disclosed in Japanese Patent Application Laid-Open No. 2020-205702, a structure is disclosed in which two shift registers provided on the high potential side and the low potential side are connected in series, and the clock is made common to miniaturize the semiconductor module.

[0006] On the other hand, if parasitic capacitance is generated in the clock line by connecting the clock lines for sharing the clock, data may be read incorrectly due to delay caused by the parasitic capacitance. Therefore, there is a problem that the drive capability setting is not at a normal value. Summary of the invention

[0007] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor module capable of performing normal driving capability setting.

[0008] One embodiment of the semiconductor module of the present invention comprises: a first switching element and a second switching element, which are connected in series between a first potential and a second potential lower than the first potential and operate complementarily; a high potential side driving circuit, which includes a first driver, which is connected to a first gate of the first switching element, and the first driver can receive an input of a first driving signal and adjust the output to the first gate; and a low potential side driving circuit, which includes a second driver, which is connected to a second gate of the second switching element, and the second driver can receive an input of a second driving signal and adjust the output to the second gate. The high potential side driving circuit includes: a first receiving terminal, which receives a first data signal, an enable signal and a first clock signal respectively; a first shift register, which is composed of a plurality of flip-flops connected in cascade, and records the first data signal in the flip-flop according to the first clock signal and the enable signal, and moves the recorded data to an adjacent flip-flop each time a data signal is stored in the flip-flop; a first setting value storage unit, which records the recorded contents of the plurality of flip-flops of the first shift register according to the enable signal extraction; a first decoder, which is used to make the output current capacity of the first driver variable according to the records of the first setting value storage unit; and a first output terminal, which outputs the first clock signal to the low potential side driving circuit as a second clock signal. The low potential side driving circuit includes: a second receiving terminal, which receives a second data signal, an enable signal and a second clock signal respectively; a second shift register, which is composed of a plurality of flip-flops connected in cascade, and records the second data signal in the flip-flop according to the second clock signal and the enable signal, and moves the recorded data to an adjacent flip-flop each time the second data signal is stored in the flip-flop; a second set value storage unit, which records the recorded contents of the plurality of flip-flops of the second shift register according to the enable signal extraction; a second decoder, which is used to make the output current capacity of the second driver variable according to the records of the second set value storage unit; and a second output terminal, which outputs the second data signal stored in the flip-flop of the last stage of the second shift register to the high potential side driving circuit as the first data signal.

[0009] The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a diagram for explaining the outline of the structure of the semiconductor module according to the first embodiment.

[0011] Figure 2 This is a diagram for explaining the circuit configuration of the first level shifter 10 according to the first embodiment.

[0012] Figure 3This is a diagram for explaining the configuration of the driver 30 and the shift register unit 38 according to the first embodiment.

[0013] Figure 4 This is a diagram for explaining the configuration of the high-voltage side set value storage unit 16 and the second level shift unit 18 according to the first embodiment.

[0014] Figure 5 This is a diagram for explaining setting information stored in the controller (MCU) 2 according to the first embodiment.

[0015] Figure 6 This is a timing chart for setting the driving capability of the semiconductor module according to the first embodiment.

[0016] Figure 7 This is a timing chart for another setting of the driving capability of the semiconductor module according to the first embodiment.

[0017] Figure 8 This is a diagram for explaining the configuration of the shift register unit 22 and the shift register unit 38 according to the first embodiment.

[0018] Fig. 9 The diagrams are for explaining the shifting of data in the shift register unit 22 and the shift register unit 38 according to the comparative example.

[0019] Fig.10 This is a diagram for explaining the shifting of data in the shift register unit 22 and the shift register unit 38 according to the first embodiment.

[0020] Fig.11 This is a diagram for explaining the outline of the structure of a semiconductor module according to the second embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.

[0022] Implementation Method 1

[0023] Figure 1 FIG. 2 is a diagram for explaining the schematic structure of the semiconductor module according to the first embodiment. Figure 1, the semiconductor module includes power transistors (switching elements) Q1, Q2, and a driving circuit for driving the gates of the power transistors Q1, Q2. The power transistor Q1 is arranged between the high potential HV and the output node OUT. The power transistor Q2 is arranged between the output node OUT and the ground potential VSS side. The driving circuit includes a high potential side output capacity variable gate device HVIC (high potential side driving circuit) and a low potential side output capacity variable gate device LVIC (low potential side driving circuit). The high potential side output capacity variable gate device HVIC is arranged corresponding to the gate of the power transistor Q1. The low potential side output capacity variable gate device LVIC is arranged corresponding to the gate of the power transistor Q2. The power transistors Q1 and Q2 operate complementarily through the gate drive of the high potential side output capacity variable gate device HVIC and the low potential side output capacity variable gate device LVIC. As an example, the output node OUT is connected to a motor or the like as a load.

[0024] The controller (MCU) 2 outputs a data communication signal for driving the power transistors Q1 and Q2 to the high potential side output capability variable gate device HVIC and the low potential side output capability variable gate device LVIC. The high potential side output capability variable gate device HVIC and the low potential side output capability variable gate device LVIC drive the power transistors Q1 and Q2 respectively according to the data communication signal from the controller 2. The high potential side output capability variable gate device HVIC has input terminals P0 to P3 and output terminals P4 and P5. The high potential side drive signal HIN is input from the controller 2 to the input terminal P0. The data signal SIL from the shift register unit 38 is input to the input terminal P1. The clock signal CK is input from the controller 2 to the input terminal P2. The enable signal EN is input from the controller 2 to the input terminal P3. The output terminal P4 is connected to the gate of the power transistor Q1 and outputs the high potential side drive signal HIN level-shifted to a high potential. The output terminal P5 is connected to the output terminal P8 and outputs the clock signal CKL to the shift register unit 38.

[0025] The high potential side output capability variable gate device HVIC includes a first level shift unit 10 for level-shifting a high potential side drive signal to a high potential, a shift register unit 22, a low voltage side setting value storage unit 20, a second level shift unit 18, a high voltage side setting value storage unit 16, a decoder 14, a driver 12 and a write signal generating unit 15.

[0026] The shift register section 22 is composed of a plurality of DT flip-flops connected in cascade. The shift register section 22 records the input data signal according to the data signal SIL, the clock signal CK and the enable signal EN, and moves (shifts) the data signal to the adjacent DT flip-flop. In this example, the 3-bit data signal (DH1 to DH3) is stored in the shift register section 22 and output to the low voltage side set value storage section 20.

[0027] The low-voltage side set value storage unit 20 stores the information stored in the shift register unit 22 in accordance with the write signal WT1 .

[0028] The second level shifter 18 level-shifts the data signal, which is 3-bit information stored in the low-voltage side set value storage unit 20 , to a high potential in accordance with the enable signal EN.

[0029] The high-voltage side set value storage unit 16 stores information of the 3-bit data signal (DH1 to DH3) level-shifted by the second level shift unit 18 in accordance with the write signal WT2.

[0030] The decoder 14 performs decoding processing based on the data signals ( DH1 to DH3 ) stored in the high-voltage side set value storage unit 16 , and outputs the decoding processing to the driver 12 .

[0031] The write signal generating section 15 generates write signals WT1 and WT2 for storing data signals in the low voltage side set value storing section 20 and the high voltage side set value storing section 16 in accordance with the enable signal EN.

[0032] In this example, a high voltage region HVR is shown, in which the first level shifter 10 and part of the second level shifter 18 , the driver 12 , the decoder 14 , and the high voltage side set value storage section 16 are provided.

[0033] The low potential side output capability variable gate device LVIC has input terminals P6 to P9 and output terminals P10 and P11. The input terminal P6 receives the low potential side drive signal LIN from the controller 2. The input terminal P7 receives the data signal SI from the controller 2. The input terminal P8 is connected to the output terminal P5 and receives the clock signal CKL output from the shift register section 22. The input terminal P9 receives the enable signal EN from the controller 2. The output terminal P10 is connected to the gate of the power transistor Q2 and outputs the low potential side drive signal. The output terminal P11 is connected to the input terminal P1 and outputs the data signal SIL to the shift register section 22.

[0034] The low potential side output capability variable gate device LVIC includes a shift register section 38 , a set value storage section 36 , a decoder 34 , and a driver 30 .

[0035] The shift register section 38 is composed of a plurality of DT flip-flops connected in cascade. The shift register section 38 records the input data signal according to the data signal, the clock signal and the enable signal, and moves (shifts) the data signal to the adjacent DT flip-flop. In this example, the 3-bit data signal (DL1 to DL3) is stored in the shift register section 38 and output to the set value storage section 36.

[0036] The set value storage unit 36 ​​stores the information stored in the shift register unit 38 in response to the enable signal EN. The set value storage unit 36 ​​stores the information stored in the shift register unit 38 in response to the fall of the enable signal EN.

[0037] The decoder 34 performs decoding processing based on the data signals ( DL1 to DL3 ) stored in the setting value storage unit 36 ​​, and outputs the decoding processing to the driver 30 .

[0038] In this example, the shift register section 22 and the shift register section 38 are connected in series.

[0039] Figure 2 FIG. 2 is a diagram for explaining the circuit configuration of the first level shifter 10 according to the first embodiment. Figure 2 The first level shifter 10 includes an on-off one-shot pulse circuit 100 , high withstand voltage MOS transistors 102 , 104 , an SR flip-flop 106 , inverters 114 , 116 , diodes 112 , 118 , and resistors 108 , 110 .

[0040] The on-off one-shot pulse circuit 100 outputs a one-shot pulse when turned on / off (when the high potential side drive signal HIN as the input signal rises / falls). The on-off one-shot pulse circuit 100 outputs a one-shot pulse to the gate of the high withstand voltage MOS transistor 102 when turned on (when the input signal rises). The on-off one-shot pulse circuit 100 outputs a one-shot pulse to the gate of the high withstand voltage MOS transistor 104 when turned off (when the high potential side drive signal HIN as the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High withstand voltage MOS transistors 102 and 104 are connected in parallel between node N0 and node N1. Resistor element 108 is provided between the source side of the high withstand voltage MOS transistor 102 and node N0. Resistor element 110 is provided between the source side of the high withstand voltage MOS transistor 104 and node N0. The anode side of the diode 112 is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor 108 and the high withstand voltage MOS transistor 102. The anode side of the diode 118 is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor 110 and the high withstand voltage MOS transistor 104. The diodes 112 and 118 clamp the cathode voltage to a voltage drop from the voltage of the terminal VS to the VF voltage of the diode, and adjust it not to exceed the withstand voltage of the inverters 114 and 116 and the resistors 108 and 110.

[0041] When the high withstand voltage MOS transistor 102 is turned off, the potential of the connection node between the resistor element 108 and the high withstand voltage MOS transistor 102 is set to a high potential. Therefore, the output signal of the inverter 114 is set to an "L" level. Similarly, when the high withstand voltage MOS transistor 104 is turned off, the potential of the connection node between the resistor element 110 and the high withstand voltage MOS transistor 104 is set to a high potential. Therefore, the output signal of the inverter 116 is set to an "L" level.

[0042] When the high-voltage MOS transistor 102 is driven (turned on), the potential of the connection node between the resistor element 108 and the high-voltage MOS transistor 102 decreases. In conjunction with this, the output signal of the inverter 114 is set to the "H" level. Similarly, when the high-voltage MOS transistor 104 is driven (turned on), the potential of the connection node between the resistor element 110 and the high-voltage MOS transistor 104 decreases. Therefore, the output signal of the inverter 116 is set to the "H" level.

[0043] The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102 is turned on. As a result, the connection node between the resistor element 108 becomes an "L" level, and the inverter 114 outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100 outputs a one-shot pulse when it is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104 is turned on. As a result, the connection node between the resistor element 110 becomes an "L" level, and the inverter 116 outputs an "H" level. That is, the RS flip-flop is reset to "0".

[0044] With this configuration, the driving signal input to the on-off one-shot pulse circuit 100 is level-shifted to a high potential and stored in the RS flip-flop 106. The RS flip-flop 106 outputs the stored data signal from the terminal D0OUT.

[0045] Figure 3 1 is a diagram for explaining the configuration of the driver 30 and the shift register unit 38 according to the first embodiment. Figure 3 , the shift register section 38 is formed by cascading a plurality of flip-flops (DT-FF) 200 to 202 to form a shift register. The data signal input from the input terminal P7 is input to the D input of the starting flip-flop 200, and the Q output of the starting flip-flop 200 is input to the D input of the next-stage flip-flop 201. The Q output of the next-stage flip-flop 201 is input to the D input of the next-stage flip-flop 202. The Q outputs of the flip-flops 200 to 202 are output to the set value storage section 36 as data DL3, DL2, and DL1. In addition, in this example, the Q output of the last-stage flip-flop 202 is input to the terminal P1 of the shift register section 22 via the terminal P11 as the data signal SIL.

[0046] The clock signal CKL input from the input terminal P8 is input to the clock inputs of all the flip-flops 200 to 202. The data signal input in accordance with the input of the clock signal CKL is transferred to the flip-flop of the next stage and stored in the flip-flop of the next stage.

[0047] The set value storage unit 36 ​​includes a plurality of flip-flops (DT-FF) 203 to 205. The output of the flip-flop 200, i.e., data DL3, is input to the D input of the flip-flop 203. The output of the flip-flop 201, i.e., data DL2, is input to the D input of the flip-flop 204. The output of the flip-flop 202, i.e., data DL1, is input to the D input of the flip-flop 205. The enable signal input from the input terminal ENL is input to the clock inputs of all the flip-flops 203 to 205.

[0048] Therefore, the flip-flops 203 to 205 of the setting value storage unit 36 ​​store the Q outputs of the flip-flops 200 to 202, i.e., data DL3, DL2, and DL1, according to the enable signal EN input from the input terminal P9, and output them to the decoder 34. The setting value storage unit 36 ​​stores 3-bit information (DL1 to DL3). The decoder 34 decodes the 3-bit information into an 8-mode signal.

[0049] The driver 30 has a plurality of drivers DD connected in parallel to the gate of the power transistor Q2. All of the plurality of drivers DD except one are connected to the gate of the power transistor Q2 via a switch SW, and the connection and disconnection to the gate of the power transistor Q2 are controlled by turning the switch SW on and off. The on / off control of the switch SW is controlled by the Q output of the flip-flops 200 to 202, i.e., the set value. The decoder 34 decodes the 3-bit information of the set value storage unit 36 ​​into an 8-mode signal, and performs on / off control of the switch SW.

[0050] The switch SW of the driver 30 is turned on according to the 8-mode signal output from the decoder 34. If the number of switches SW of the driver 30 is increased, the number of drivers DD driving the power transistor Q2 can be increased. Therefore, the driving capability of the driver 30 can be improved. As described above, the driving capability can be variably set according to the set value. In addition, although Figure 3 1 and 2 have been described with reference to the configuration of the driver 30 of the low potential side output capability variable gate device LVIC. However, the configurations of the shift register unit 22 and the driver 12 of the high potential side output capability variable gate device HVIC are also the same.

[0051] Figure 4 FIG. 2 is a diagram for explaining the configuration of the high voltage side set value storage unit 16 and the second level shift unit 18 according to the first embodiment. Figure 4 The high voltage side set value storage unit 16 includes a plurality of flip-flops 106A to 106C.

[0052] The second level shift unit 18 includes a plurality of flip-flops (DT-FF) 101A to 101C, on-off single-shot pulse circuits 100A to 100C, high-voltage MOS transistors 102A to 102C, 104A to 104C, SR flip-flops 106A to 106C, inverters 114A to 114C, 116A to 116C, diodes 112A to 112C, 118A to 118C, and resistors 108A to 108C, 110A to 110C.

[0053] The flip-flop 101A is triggered by the write signal WT2 to store the data DH3 stored in the low voltage side set value storage unit 20. The flip-flop 101B is triggered by the write signal WT2 to store the data DH2 stored in the low voltage side set value storage unit 20. The flip-flop 101C is triggered by the write signal WT2 to store the data DH1 stored in the low voltage side set value storage unit 20.

[0054] The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data DH3 is turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100A outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102A when turned on (when the input signal rises). The on-off one-shot pulse circuit 100A outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104A when turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102A and 104A are connected in parallel between node N0 and node N1. Resistor element 108A is provided between the source side of the high-withstand voltage MOS transistor 102A and node N0. Resistor element 110A is provided between the source side of the high-withstand voltage MOS transistor 104A and node N0. The anode side of the diode 112A is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 108A and the high withstand voltage MOS transistor 102A. The anode side of the diode 118A is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 110A and the high withstand voltage MOS transistor 104A.

[0055] When the high withstand voltage MOS transistor 102A is turned off, the potential of the connection node between the resistor element 108A and the high withstand voltage MOS transistor 102A is set to a high potential. Therefore, the output signal of the inverter 114A is set to an "L" level. Similarly, when the high withstand voltage MOS transistor 104A is turned off, the potential of the connection node between the resistor element 110A and the high withstand voltage MOS transistor 104A is set to a high potential. Therefore, the output signal of the inverter 116A is set to an "L" level.

[0056] When the high-voltage MOS transistor 102A is driven (turned on), the potential of the connection node between the resistor element 108A and the high-voltage MOS transistor 102A decreases. In association with this, the output signal of the inverter 114A is set to the "H" level. Similarly, when the high-voltage MOS transistor 104A is driven (turned on), the potential of the connection node between the resistor element 110A and the high-voltage MOS transistor 104A decreases. Therefore, the output signal of the inverter 116A is set to the "H" level.

[0057] The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data DH3 is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102A is turned on. As a result, the connection node with the resistor element 108A becomes an "L" level, and the inverter 114A outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100A outputs a one-shot pulse when the data DH3 is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104A is turned on. As a result, the connection node with the resistor element 110A becomes an "L" level, and the inverter 116A outputs an "H" level. That is, the RS flip-flop 106A is reset to "0".

[0058] With this configuration, the data DH3 input to the on-off one-shot pulse circuit 100A is level-shifted to a high potential and stored in the RS flip-flop 106A. The RS flip-flop 106A outputs the stored data signal from the terminal D3OUT.

[0059] The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data DH2 is turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100B outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102B when turned on (when the input signal rises). The on-off one-shot pulse circuit 100B outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104B when turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102B and 104B are connected in parallel between node N0 and node N1. Resistor element 108B is provided between the source side of the high-withstand voltage MOS transistor 102B and node N0. Resistor element 110B is provided between the source side of the high-withstand voltage MOS transistor 104B and node N0. The anode side of the diode 112B is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 108B and the high withstand voltage MOS transistor 102B. The anode side of the diode 118B is connected to the terminal VS which is the intermediate potential, and the cathode side is connected to the connection node between the resistor element 110B and the high withstand voltage MOS transistor 104B.

[0060] When the high withstand voltage MOS transistor 102B is turned off, the potential of the connection node between the resistor element 108B and the high withstand voltage MOS transistor 102B is set to a high potential. Therefore, the output signal of the inverter 114B is set to an "L" level. Similarly, when the high withstand voltage MOS transistor 104B is turned off, the potential of the connection node between the resistor element 110B and the high withstand voltage MOS transistor 104B is set to a high potential. Therefore, the output signal of the inverter 116B is set to an "L" level.

[0061] When the high-voltage MOS transistor 102B is driven (turned on), the potential of the connection node between the resistor element 108B and the high-voltage MOS transistor 102B decreases. In association with this, the output signal of the inverter 114B is set to the "H" level. Similarly, when the high-voltage MOS transistor 104B is driven (turned on), the potential of the connection node between the resistor element 110B and the high-voltage MOS transistor 104B decreases. Therefore, the output signal of the inverter 116B is set to the "H" level.

[0062] The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data DH2 is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102B is turned on. As a result, the connection node with the resistor element 108B becomes an "L" level, and the inverter 114B outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100B outputs a one-shot pulse when the data DH2 is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104B is turned on. As a result, the connection node with the resistor element 110B becomes an "L" level, and the inverter 116B outputs an "H" level. That is, the RS flip-flop is reset to "0".

[0063] With this configuration, the data DH2 input to the on-off one-shot pulse circuit 100B is level-shifted to a high potential and stored in the RS flip-flop 106B. The RS flip-flop 106B outputs the stored data signal from the terminal D2OUT.

[0064] The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data DH1 is turned on / off (when the input signal rises / falls). The on-off one-shot pulse circuit 100C outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 102C when it is turned on (when the input signal rises). The on-off one-shot pulse circuit 100C outputs a one-shot pulse to the gate of the high-withstand voltage MOS transistor 104C when it is turned off (when the input signal falls). Node N0 is connected to terminal VB. The floating power supply 120 is connected between terminal VB and terminal VS. Terminal VSS connected to the ground potential GND is connected to node N1. High-withstand voltage MOS transistors 102C and 104C are connected in parallel between node N0 and node N1. Resistor element 108C is provided between the source side of the high-withstand voltage MOS transistor 102C and node N0. Resistor element 110C is provided between the source side of the high-withstand voltage MOS transistor 104C and node N0. The anode side of the diode 112C is connected to the terminal VS at the intermediate potential, and the cathode side is connected to the connection node between the resistor element 108C and the high withstand voltage MOS transistor 102C. The anode side of the diode 118C is connected to the terminal VS at the intermediate potential, and the cathode side is connected to the connection node between the resistor element 110C and the high withstand voltage MOS transistor 104C.

[0065] When the high-voltage MOS transistor 102C is turned off, the potential of the connection node between the resistor element 108C and the high-voltage MOS transistor 102C is set to a high potential. Therefore, the output signal of the inverter 114C is set to an "L" level. Similarly, when the high-voltage MOS transistor 104C is turned off, the potential of the connection node between the resistor element 110C and the high-voltage MOS transistor 104C is set to a high potential. Therefore, the output signal of the inverter 116C is set to an "L" level.

[0066] When the high-voltage MOS transistor 102C is driven (turned on), the potential of the connection node between the resistor element 108C and the high-voltage MOS transistor 102C decreases. In association with this, the output signal of the inverter 114C is set to the "H" level. Similarly, when the high-voltage MOS transistor 104C is driven (turned on), the potential of the connection node between the resistor element 110C and the high-voltage MOS transistor 104C decreases. Therefore, the output signal of the inverter 116C is set to the "H" level.

[0067] The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data DH1 is turned on (when the input signal rises). As a result, the high-voltage MOS transistor 102C is turned on. As a result, the connection node with the resistor element 108C becomes an "L" level, and the inverter 114C outputs an "H" level. That is, the RS flip-flop is set to "1". The on-off one-shot pulse circuit 100C outputs a one-shot pulse when the data DH1 is turned off (when the input signal falls). As a result, the high-voltage MOS transistor 104C is turned on. As a result, the connection node with the resistor element 110C becomes an "L" level, and the inverter 116C outputs an "H" level. That is, the RS flip-flop is reset to "0".

[0068] With this configuration, the data DH1 input to the on-off one-shot pulse circuit 100C is level-shifted to a high potential and stored in the RS flip-flop 106C. The RS flip-flop 106C outputs the stored data signal from the terminal D1OUT.

[0069] Figure 5 This is a diagram for explaining the setting information stored in the controller (MCU) 2 according to the first embodiment. Figure 5 A driving force table is provided in the memory of the controller (MCU) 2. For example, a plurality of setting value data for defining the driving capabilities of the drivers of the high potential side output capability variable gate device HVIC (upper gate) and the low potential side output capability variable gate device LVIC (lower gate) are stored.

[0070] In this example, the set value data of the driving capability of the driver stores data P1 and P2 for the driver on the upper arm side, and stores data P3 and P4 for the driver on the lower arm side.

[0071] In addition, in addition to the driving capability of the driver, “Other 1” that specifies other capabilities is exemplified, but this is not particularly limited in the present embodiment.

[0072] The controller 2 uses the driving force table to read data as needed, and stores the data in the shift register section 22 of the high potential side output capability variable gate device HVIC (upper gate) and the shift register section 38 of the low potential side output capability variable gate device LVIC (lower gate).

[0073] Thereby, the driving capabilities of the driver 12 and the driver 30 can be made variable.

[0074] Thus, the data signals (DH1 to DH3) stored in the low voltage setting value storage unit 20 are stored in the high voltage setting value storage unit 16 via the second level shift unit 18. After being converted into 8-mode signals by the decoder 14, the driving capability of the driver 12 is changed.

[0075] Figure 6 1 is a timing chart for setting the driving capability of the semiconductor module according to the first embodiment. Figure 6 At time T30, the low potential side drive signal LIN of the input terminal P6 falls, and a gate signal of "L" level is output from the output terminal P10, turning off the power transistor Q2.

[0076] Next, at time T31, the high potential side drive signal HIN of the input terminal P0 rises complementarily. Next, a gate signal of "H" level is output from the output terminal P4, and the power transistor Q1 is turned on.

[0077] In this example, the driving capability is set at time T32 after time T31. Specifically, at time T32, the clock signal CK is input to the input terminal P2. In addition, the data signal SI is input to the input terminal P7. The clock signal CK is input from the output terminal P5 to the input terminal P8 as the clock signal CKL.

[0078] The shift register section 38 sequentially stores the data signal SI input from the input terminal P7 in synchronization with the clock signal CKL in a plurality of flip-flops.

[0079] At time T33, the output of the flip-flop 202 of the shift register section 38 is input to the input terminal P1 via the output terminal P11 as the data signal SIL. At time T34, the three flip-flops of the shift register section 22 store data.

[0080] Next, at time T35, the enable signal EN rises, and the write signal generation unit 15 sets the write signal WT1 to the "H" level according to the enable signal EN. The low voltage side setting value storage unit 20 stores the data signal stored in the shift register unit 22 according to the write signal WT1. Next, at time T36, the write signal generation unit 15 sets the write signal WT2 to the "H" level. The data signals (DH1 to DH3) stored in the low voltage side setting value storage unit 20 are stored in the high voltage side setting value storage unit 16 via the second level shift unit 18 according to the write signal WT2 ("H" level). Thus, after being converted into an 8-mode signal by the decoder 14, the driving capability of the driver 12 is changed.

[0081] Figure 7 1 is a timing chart for other settings of the driving capability of the semiconductor module according to the first embodiment. Figure 7 At time T40, the high potential side drive signal HIN of the input terminal P0 falls, and a gate signal of "L" level is output from the output terminal P4, turning off the power transistor Q1.

[0082] Next, at time T41, the low potential side drive signal LIN of the input terminal P6 rises complementarily. Next, a gate signal of "H" level is output from the output terminal P10, and the power transistor Q2 is turned on.

[0083] In this example, the driving capability is set at time T42 after time T41. Specifically, at time T42, the clock signal CK is input to the input terminal P2. In addition, the data signal SI is input to the input terminal P7. The clock signal CK is input from the output terminal P5 to the input terminal P8 as the clock signal CKL.

[0084] The shift register section 38 sequentially stores the data signal SI input from the input terminal P7 in synchronization with the clock signal CKL in a plurality of flip-flops.

[0085] At time T43, the output of the flip-flop 202 of the shift register section 38 is input to the input terminal P1 via the output terminal P11 as the data signal SIL. At time T44, the three flip-flops of the shift register section 22 store data.

[0086] Next, at time T45, the enable signal EN rises, and the write signal generation unit 15 sets the write signal WT1 to the "H" level according to the enable signal EN. The low voltage side setting value storage unit 20 stores the data signal stored in the shift register unit 22 according to the write signal WT1. Next, at time T46, the write signal generation unit 15 sets the write signal WT2 to the "H" level. The data signals (DH1 to DH3) stored in the low voltage side setting value storage unit 20 are stored in the high voltage side setting value storage unit 16 via the second level shift unit 18 according to the write signal WT2 ("H" level). Thus, after being converted into an 8-mode signal by the decoder 14, the driving capability of the driver 12 is changed.

[0087] Figure 8 1 is a diagram for explaining the configuration of the shift register unit 22 and the shift register unit 38 according to the first embodiment. Figure 8 , the shift register section 22 has a plurality of flip-flops (DT-FF) 300 to 302. The shift register section 22 forms a shift register by cascading a plurality of flip-flops (DT-FF) 300 to 302. The data signal SIL input from the input terminal P1 is input to the D input of the starting flip-flop 300, and the Q output of the starting flip-flop 300 is input to the D input of the next-stage flip-flop 301. The Q output of the next-stage flip-flop 301 is input to the D input of the next-stage flip-flop 302. The Q outputs of the flip-flops 300 to 302 are output to the low-voltage side set value storage section 20.

[0088] The structure of the shift register section 38 is similar to that in Figure 3 The structure is the same as that described in , so the detailed description will not be repeated.

[0089] Fig. 9 1 is a diagram for explaining the shifting of data in the shift register unit 22 and the shift register unit 38 according to the comparative example. Fig. 9 In this example, the case where the clock signal CK is input from the shift register unit 38 side is described.

[0090] In this example, the focus is on the flip-flop 202 of the shift register section 38 and the flip-flop 300 of the shift register section 22. The input of the flip-flop 202, i.e., the data signal Da, is stored and stored internally according to the rise of the clock signal Ta. Therefore, the output of the flip-flop 202, i.e., the data signal Qa, changes. In addition, the input of the flip-flop 300, i.e., the data signal Db, is also stored and stored internally according to the rise of the clock signal Tb. Therefore, the output of the flip-flop 300, i.e., the data signal Qb, also changes.

[0091] On the other hand, since the wiring length of the clock signal is set to be relatively long between the registers, there is a possibility that the timing delay of the clock signal may occur due to the influence of the parasitic capacitance C1.

[0092] Specifically, the flip-flop 202 stores the output of the flip-flop 201, that is, the data signal Da, in response to the rise of the clock signal Ta. In this example, the flip-flop 200 stores the data at the "L" level. The flip-flop 201 stores the data at the "H" level. The flip-flop 202 stores the data at the "L" level.

[0093] Due to the rise of the clock signal Ta, the flip-flop 202 stores the data signal Da ("H" level) output from the flip-flop 201. Next, the output of the flip-flop 202, that is, the data signal Qa, changes from the "L" level to the "H" level. Next, the data signal Db also changes from the "L" level to the "H" level in accordance with this change.

[0094] On the other hand, it is assumed that when there is no delay in the clock signal, the flip-flop 300 stores the output of the flip-flop 202 , that is, the data signal Qa (“L” level).

[0095] However, when the clock signal is delayed by parasitic capacitance C1, the flip-flop 300 may store the changed data signal Db according to the rising of the clock signal. In this case, data racing occurs, and the flip-flop 300 stores the data signal Db at the "H" level instead of the "L" level.

[0096] That is, in this example, the clock signal Tb is delayed due to the timing delay. As a result, data cannot be acquired at an appropriate timing, and data contention occurs. As a result, data may not be correctly stored.

[0097] Fig.10 1 is a diagram for explaining the shifting of data in the shift register unit 22 and the shift register unit 38 according to the first embodiment. Fig. 9 In this example, a case where the clock signal CK is input from the shift register unit 22 side will be described.

[0098] In this example, the focus is on the flip-flop 202 of the shift register section 38 and the flip-flop 300 of the shift register section 22. Specifically, the flip-flop 202 stores the output of the flip-flop 201, that is, the data signal Da, in response to the rise of the clock signal Ta. In this example, the flip-flop 200 stores data at an "L" level. The flip-flop 201 stores data at an "H" level. The flip-flop 202 stores data at an "L" level.

[0099] The clock signal Tb is input from the terminal P2.

[0100] Due to the rise of the clock signal Tb, the flip-flop 300 stores the data signal Db ("L" level) output from the flip-flop 202. In response to this, the data signal Qb, which is the output of the flip-flop 300, changes to the "L" level.

[0101] Next, as described above, the clock signal is delayed due to the parasitic capacitance C1.

[0102] In this example, the rising edge of the clock signal Ta is slightly delayed compared to the clock signal Tb. The clock signal Ta is input to the flip-flops 200 to 202 at substantially the same time.

[0103] The flip-flop 202 obtains the data signal Da ("H" level), which is the output of the flip-flop 201, by the clock signal Ta. Accordingly, the data signal Qa, which is the output of the flip-flop 202, is set to "H" level. In addition, at the same time, the data signal Db is also set to "H" level.

[0104] In addition, the flip-flop 201 obtains the data signal which is the output of the flip-flop 200 by the clock signal Ta. Thus, the data signal Da which is the output of the flip-flop 201 is set to the "L" level.

[0105] With this configuration, the flip-flops 300 to 302 of the shift register section 22 can store data at appropriate timing by the clock signal Tb. Also, the flip-flops 200 to 202 of the shift register section 38 can store data at appropriate timing by the delayed clock signal Ta.

[0106] That is, even when the clock signal Ta is delayed due to a timing delay, data contention does not occur, and data can be acquired at an appropriate timing, thereby enabling data to be correctly stored.

[0107] This structure can suppress data contention in data transfer between registers, realize signal transmission of a setting value for setting the driving capability, and set the driving capability to a normal value. That is, the semiconductor module of the present invention can be miniaturized and set the driving capability to a normal value.

[0108] In addition, in this example, a structure in which a data signal is input from the shift register section 38 side and a clock signal is input from the shift register section 22 side is described, but the same structure can be achieved in a case where the structure is replaced and a clock signal is input from the shift register section 38 side and a data signal is input from the shift register section 22 side.

[0109] Implementation Method 2

[0110] Fig.11FIG. 2 is a diagram for explaining the outline of the structure of a semiconductor module according to Embodiment 2. Fig.11 , compared with the structure of the semiconductor module according to the first embodiment, the difference is that the terminal connection relationship of the shift register unit 22 and the shift register unit 38 is changed. The other structures are the same as the structure of the semiconductor module according to the first embodiment, so the detailed description thereof will not be repeated.

[0111] The high potential side output capability variable gate device HVIC has input terminals P0 to P3 and output terminals P4 and P5. The high potential side drive signal HIN is input from the controller 2 to the input terminal P0. The data signal SIL from the controller 2 is input to the input terminal P1. The input terminal P2 is connected to the output terminal P11 of the shift register section 38 and receives the input of the clock signal CKL. The enable signal EN is input to the input terminal P3 from the controller 2. The output terminal P4 is connected to the gate of the power transistor Q1 and outputs the high potential side drive signal HIN level-shifted to a high potential. The output terminal P5 is connected to the input terminal P7 and outputs the data signal SIL to the shift register section 38.

[0112] The low potential side output capability variable gate device LVIC has input terminals P6 to P9 and output terminals P10 and P11. The input terminal P6 receives the low potential side drive signal LIN from the controller 2. The input terminal P7 is connected to the output terminal P5 and receives the input of the data signal SIL. The input terminal P8 receives the clock signal CK from the controller 2. The input terminal P9 receives the enable signal EN from the controller 2. The output terminal P10 is connected to the gate of the power transistor Q2 and outputs the low potential side drive signal. The output terminal P11 is connected to the input terminal P2 and outputs the clock signal CKL to the shift register unit 22.

[0113] This structure can suppress data contention in data transfer between registers, realize signal transmission of a setting value for setting the driving capability, and set the driving capability to a normal value. That is, the semiconductor module of the present invention can be miniaturized and set the driving capability to a normal value.

[0114] For each embodiment disclosed this time, it is also envisioned that it can be appropriately combined and implemented within the scope of no contradiction. It should be considered that the embodiments disclosed this time are illustrative in all aspects, rather than restrictive. The scope of the present invention is not indicated by the above description but by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor module comprising: a first switching element and a second switching element connected in series between a first potential and a second potential lower than the first potential and operating in a complementary manner; a high potential side driving circuit, comprising a first driver connected to a first gate of the first switching element, the first driver being capable of receiving an input of a first driving signal and adjusting an output to the first gate; as well as a low potential side driving circuit including a second driver connected to a second gate of the second switching element, the second driver being capable of receiving an input of a second driving signal and adjusting an output to the second gate, The high potential side driving circuit comprises: a first receiving terminal for receiving a first data signal, an enable signal and a first clock signal respectively; a first shift register, which is composed of a plurality of flip-flops connected in cascade, and records the first data signal in the flip-flops according to the first clock signal and the enable signal, and shifts the recorded data to an adjacent flip-flop each time the data signal is stored in the flip-flops; a first set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the first shift register according to the enable signal; a first decoder for making the output current capability of the first driver variable according to the record of the first setting value storage unit; as well as a first output terminal for outputting the first clock signal to the low potential side drive circuit as a second clock signal, The low potential side driving circuit comprises: a second receiving terminal for receiving a second data signal, the enable signal and the second clock signal respectively; a second shift register, which is composed of a plurality of flip-flops connected in cascade, records the second data signal in the flip-flops according to the second clock signal and the enable signal, and shifts the recorded data to an adjacent flip-flop each time the second data signal is stored in the flip-flops; a second set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the second shift register according to the enable signal; a second decoder for making the output current capability of the second driver variable according to the record of the second setting value storage unit; as well as The second output terminal outputs the second data signal held in the flip-flop of the final stage of the second shift register to the high potential side driving circuit as the first data signal.

2. The semiconductor module according to claim 1, wherein: The second clock signal at the second receiving terminal is a signal delayed compared to the first clock signal.

3. The semiconductor module according to claim 1, wherein: The high potential side driving circuit further includes a first level shifter that level-shifts the first driving signal to a high potential and outputs the first driving signal to the first driver.

4. The semiconductor module according to claim 3, wherein: The first setting value storage unit includes: a low voltage side set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the first shift register according to the enable signal; a second level shifting unit for level-shifting the stored information of the low voltage side set value storing unit to a high potential; as well as The high voltage side set value storage unit is connected via the level shift unit and records the same information as the information recorded in the low voltage side set value storage unit.

5. A semiconductor module, comprising: a first switching element and a second switching element connected in series between a first potential and a second potential lower than the first potential and operating in a complementary manner; a high potential side driving circuit, comprising a first driver connected to a first gate of the first switching element, the first driver being capable of receiving an input of a first driving signal and adjusting an output to the first gate; as well as a low potential side driving circuit including a second driver connected to a second gate of the second switching element, the second driver being capable of receiving an input of a second driving signal and adjusting an output to the second gate, The high potential side driving circuit comprises: a first receiving terminal for receiving a first data signal, an enable signal and a first clock signal respectively; a first shift register, which is composed of a plurality of flip-flops connected in cascade, and records the first data signal in the flip-flops according to the first clock signal and the enable signal, and shifts the recorded data to an adjacent flip-flop each time the data signal is stored in the flip-flops; a first set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the first shift register according to the enable signal; a first decoder for making the output current capability of the first driver variable according to the record of the first setting value storage unit; as well as a first output terminal for outputting the first clock signal stored in the flip-flop of the last stage of the first shift register to the low potential side drive circuit as a second clock signal, The low potential side driving circuit comprises: a second receiving terminal for receiving the second data signal, the enable signal and the second clock signal respectively; a second shift register, which is composed of a plurality of flip-flops connected in cascade, records the second data signal in the flip-flops according to the second clock signal and the enable signal, and shifts the recorded data to an adjacent flip-flop each time the second data signal is stored in the flip-flops; a second set value storage unit that extracts and records the recorded contents of the plurality of flip-flops of the second shift register according to the enable signal; a second decoder for making the output current capability of the second driver variable according to the record of the second setting value storage unit; as well as The second output terminal outputs the second clock signal to the high potential side drive circuit as the first clock signal.

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