Ultra-wideband time delay transceiver chip working at 2-18GHz

Abstract

The invention discloses an ultra-wideband time delay transceiver chip working at 2-18GHz, which is applied to the technical field of radio frequency microwave integrated circuits and aims to solve the problem of high-frequency gain roll-off of the transceiver chip. According to the invention, a common-leg architecture in which a transmitting module and a receiving module share two driving amplifiers and a 80ps delay unit is adopted, and the common-leg architecture comprises a single-pole double-throw switch, a low-noise amplifier, the driving amplifiers, a power amplifier, the delay unit and a resistance-capacitance attenuation compensation network for compensating delay additional attenuation; therefore, the problem of additional insertion loss in different time delay states is solved, and gain roll-off is compensated by adopting an inductance resistance gain equalizer. Finally, the chip provided by the invention can realize a time delay function with a unit time delay amount of 5ps and a maximum time delay amount of 315ps in a working frequency band of 2-18GHz, and has good switch switching time and good in-band gain flatness at the same time. The input 1dB compression of the receiving channel is superior to-10dBm, the gain is superior to-2dB, the output 1dB compression of the transmitting channel is superior to 2dBm, and the gain is superior to 2dB.

Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency microwave integrated circuits, and in particular relates to a broadband time-delay multifunctional chip. Background Art

[0002] In recent years, with the widespread application of phased array technology in military radars and wireless communication systems, phased array systems with amplitude and phase control are core technologies and have received increasing attention. The transceiver front end is a key component of the phased array system, which is responsible for the transceiver switching, amplitude and phase adjustment of the RF signal. Traditional phased array antenna systems generally use phase shifters as key modules of the transceiver components. This system has the problem that the effective delay time varies with the operating frequency, resulting in the beam squint phenomenon of broadband signals. Replacing the phase shifter with TTD can provide a constant delay response within the broadband and compensate for the dispersion, alleviating the above problems of broadband systems such as high-resolution imaging radars. Therefore, TTD has become a key module in broadband phased array antenna systems. On the other hand, due to the effects of many passive components such as inductors and capacitors, high-frequency gain roll-off has become an unavoidable problem for transceiver chips. Summary of the invention

[0003] In order to solve the above technical problems, the present invention proposes an ultra-wideband delay transceiver chip operating at 2-18GHz, which adopts a common-leg architecture in which the transmitting module and the receiving module share two driving amplifiers and an 80ps delay unit, thereby realizing a multifunctional delay chip that can switch between transmitting and receiving.

[0004] The technical solution adopted by the present invention is: an ultra-wideband time-delay transceiver chip operating at 2-18 GHz, comprising a first receiving path, a second receiving path, a first transmitting path, a second transmitting path and a common path; the first receiving path is connected to the second receiving path through the common path, and the first transmitting path is connected to the second transmitting path through the common path;

[0005] The antenna is connected to the input end of the first receiving path or the output end of the second transmitting path through a first single-pole double-throw switch; the common path input end is connected to the output end of the first receiving path or the output end of the first transmitting path through a second single-pole double-throw switch; the common path output end is connected to the input end of the second transmitting path or the input end of the second receiving path through a third single-pole double-throw switch; the serial communication interface (Serial Communication Interface, COM) is connected to the input end of the first transmitting path or the output end of the second receiving path through a fifth single-pole double-throw switch;

[0006] The first receiving path includes a low noise amplifier and a first 160ps delay unit connected in sequence;

[0007] The second receiving path includes a first 5ps delay unit, a first gain equalizer, a first 10ps delay unit, a first driver amplifier, a second gain equalizer, a first 40ps delay unit, a third gain equalizer, and a first 20ps delay unit connected in sequence;

[0008] The first transmission path includes a second 20ps delay unit, a fourth gain equalizer, a second 40ps delay unit, a fifth gain equalizer, a second driver amplifier, a second 10ps delay unit, a sixth gain equalizer, and a second 5ps delay unit connected in sequence;

[0009] The second end transmission path includes a second 160ps delay unit and a power amplifier connected in sequence;

[0010] The common path includes a seventh gain equalizer, a third driving amplifier, an eighth gain equalizer, an 80ps delay unit, a fourth driving amplifier, and a ninth gain equalizer which are connected in sequence.

[0011] Beneficial effects of the present invention: The ultra-wideband delayed transceiver chip of the present invention adopts a common-leg architecture in which the transmitting module and the receiving module share two driver amplifiers and an 80ps delay unit, including single-pole double-throw switches (SPDT1, SPDT2, SPDT3, SPDT4), low noise amplifiers (Low Noise Amplifier, LNA), driver amplifiers (Driver Amplifier, DA), power amplifiers (Power Amplifier, PA), delay units (True-Time Delayer, TTD), and resistor and capacitor attenuation compensation networks to compensate for the additional attenuation of the delay (included in the delay unit), so as to solve the problem of additional insertion loss under different delay states, and at the same time use an inductor resistor gain equalizer to compensate for the gain roll-off. Finally, the chip can achieve a delay function of a unit delay of 5ps and a maximum delay of 315ps in the 2-18GHz operating frequency band, and has good switch switching time and good in-band gain flatness. The receiving channel input 1dB compression is better than -10dBm, and the gain is better than -2dB. The transmitting channel output 1dB compression is better than 2dBm, and the gain is better than 2dB. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the circuit architecture of the present invention.

[0013] Figure 2 It is the circuit schematic diagram of a four-stage distributed amplifier unit.

[0014] Figure 3 This is the schematic diagram of the gain equalizer circuit.

[0015] Figure 4It is the schematic diagram of the coupled all-pass network circuit.

[0016] Figure 5 It is the schematic diagram of the single-pole double-throw switch circuit. DETAILED DESCRIPTION

[0017] To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is further explained below with reference to the accompanying drawings.

[0018] The specific structure of the chip of the present invention is as follows Figure 1 As shown, the receiving channel includes: a single-pole double-throw switch (SPDT), a low-noise amplifier (LNA), a 160ps delay unit, a gain equalizer, a driver amplifier (DA), a gain equalizer, an 80ps delay unit, a driver amplifier (DA), a gain equalizer, a single-pole double-throw switch (SPDT), a 5ps delay unit, a gain equalizer, a 10ps delay unit, a driver amplifier (DA), a gain equalizer, a 40ps delay unit, a gain equalizer, a 20ps delay unit, and a single-pole double-throw switch (SPDT); the transmitting channel is similar to the receiving channel, wherein:

[0019] (1) The low noise amplifier (LNA), driver amplifier (DA), and power amplifier (PA) all adopt a distributed amplifier structure, and are used to amplify the input signal to improve the system linearity, compensate the system gain, and amplify the output signal power.

[0020] For the distributed amplifier, the parasitic capacitance Cin of the input end of the CMOS transistor is connected in series with the on-chip inductor Lg to form a gate input artificial transmission line; the parasitic capacitance Cout of the output end of the CMOS transistor is connected in series with the on-chip inductor Ld to form a drain output artificial transmission line; the gate input and drain output artificial transmission lines are coupled through the transconductance of the CMOS tube and realize the amplification of the input signal. The CMOS tube circuit with this function is called a gain unit circuit. Figure 2As shown, the gain unit in the present invention adopts a structure in which three transistors M1, M2, and M3 are stacked, and its output voltage swing is 3 times that of the common source structure and 1.5 times that of the common source common gate structure (Cascode). This structure can greatly improve the output power. Resistors R1, R2, and R3 form a voltage divider network to provide gate voltage bias for M2 and M3, and the M1 gate voltage bias is provided by an external switch control circuit. C1 and C2 are bypass capacitors for removing stray. Lg1, Lg2, Lg3, Lg4, and Lg5 form a gate transmission line with the transistor gate input parasitic capacitance, and Ld1, Ld2, Ld3, Ld4, and Ld5 form a drain transmission line with the transistor drain output parasitic capacitance, so as to achieve good matching, thereby achieving the purpose of bandwidth expansion. One end of the peaking inductor Ld is connected to VDD, and the other end is connected to the drain of M3 in the second-stage gain unit to avoid the problem of gain roll-off. Ld1 and Lg5 are connected to a 50 ohm resistor Rd and Rg respectively, and Rd and Rg are connected to a large capacitor Cd and Cg to ground, so as to achieve good port matching. The input and output ports are connected to a DC blocking capacitor Cin and Cout respectively, which isolates the DC signal, solves the problems of DC offset and DC coupling, and improves the signal transmission quality.

[0021] Since there are resistive parasitics between the gain unit and the on-chip inductor in the actual application process, there will be an attenuation effect, so the gain of the distributed amplifier will not increase infinitely with the increase of the number of gain unit cascades. According to this characteristic and the relevant requirements of the present invention, the distributed amplifier in the present invention adopts a four-stage gain unit cascade. After simulation verification, the distributed amplifier has a gain greater than 15dB, a noise figure less than 4dB, an input and output port return loss better than 10dB, and an output P-1dB greater than 12dBm in the 2-18GHz frequency band.

[0022] (2) The gain equalizer uses a resistor, capacitor and inductor network to improve the problem of the slope roll-off of the insertion loss of the delay chip. Figure 3 As shown in the figure, the resistor Re1 is connected in parallel with the inductor Ce1, Re2 and Re3 are connected to the inductor, and the other end is connected to the parallel network of Re1 and Ce1, and one end of the inductor is grounded. The insertion loss of this gain amplifier at low frequency is greater than that of the high frequency part, which is opposite to the insertion loss trend of the delay chip. Therefore, the problem of excessive insertion loss slope of the delay chip can be solved by simply adjusting the parameters of each component in the circuit.

[0023] (3) The basic structures of the 160ps, 80ps, 40ps, 20ps, 10ps and 5ps delay units are as follows: Figure 4The magnetically coupled all-pass network (APN) unit is shown. The passive all-pass network delay unit is a second-order all-pass filter, which is composed of two capacitors and two inductors, and there is mutual inductance between the inductors. The circuit can achieve good delay-bandwidth compromise performance, and the intrinsic input and output are matched. The delay units in the present invention all adopt this structure. According to the requirements of the delay index, different delay amounts can be achieved by changing the number of cascade units.

[0024] (4) The single-pole double-throw switch (SPDT) adopts Figure 5 In the structure shown, the gates of M1 and M2 are connected to the substrate in series with large resistors Rg and Rb, and then the drains are connected to the drains; the gates of M3 and M4 are connected to the substrate in series with large resistors Rg and Rb, and then their drains are connected to the source ends of M1 and M2 respectively. The sources of M3 and M4 are grounded, and the gates of M3 and M4 are connected to the gate of M2 and the gate resistance branch of M1 respectively through resistor Rg. Port1, Port2 and Port3 are used as the input and output ends of the signal, and are respectively connected to an inductor and then led out. Vctr1 and Vctr2 are respectively used as the control voltage ends, and are led out from the gates of M1 and M2 connected to resistor Rg. When Vctr1 inputs a high level and Vctr2 inputs a low level, transistors M1 and M4 are turned on, transistors M2 and M3 are turned off, and the single-pole double-throw switch circuit forms a signal path from Port1 to Port2; when Vctr1 inputs a low level and Vctr2 inputs a high level, transistors M1 and M4 are turned off, transistors M2 and M3 are turned on, and the single-pole double-throw switch circuit forms a signal path from Port1 to Port3. In the present invention, the SPDT insertion loss is better than 1.2dB, and the input return loss is better than 25dB.

[0025] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of the claims of the present invention.

Claims

1. An ultra-wideband delay transceiver chip operating at 2-18 GHz, characterized in that: It includes a first receiving path, a second receiving path, a first transmitting path, a second transmitting path and a common path; the first receiving path is connected to the second receiving path through the common path, and the first transmitting path is connected to the second transmitting path through the common path; The antenna is connected to the input end of the first receiving path or the output end of the second transmitting path through a first single-pole double-throw switch; the common path input end is connected to the output end of the first receiving path or the output end of the first transmitting path through a second single-pole double-throw switch; the common path output end is connected to the input end of the second transmitting path or the input end of the second receiving path through a third single-pole double-throw switch; The serial communication interface is connected to the input end of the first end transmission path or the output end of the second section receiving path through a fourth single-pole double-throw switch; The first receiving path includes a low noise amplifier and a first 160ps delay unit connected in sequence; The second receiving path includes a first 5ps delay unit, a first gain equalizer, a first 10ps delay unit, a first driver amplifier, a second gain equalizer, a first 40ps delay unit, a third gain equalizer, and a first 20ps delay unit connected in sequence; The first transmission path includes a second 20ps delay unit, a fourth gain equalizer, a second 40ps delay unit, a fifth gain equalizer, a second driver amplifier, a second 10ps delay unit, a sixth gain equalizer, and a second 5ps delay unit connected in sequence; The second end transmission path includes a second 160ps delay unit and a power amplifier connected in sequence; The common path includes a seventh gain equalizer, a third driving amplifier, an eighth gain equalizer, an 80ps delay unit, a fourth driving amplifier, and a ninth gain equalizer which are connected in sequence.

2. The ultra-wideband delay transceiver chip operating at 2-18 GHz according to claim 1, characterized in that: The low noise amplifier, the first driving amplifier, the second driving amplifier, the third driving amplifier, the fourth driving amplifier and the power amplifier all adopt a distributed amplifier structure.

3. The ultra-wideband delay transceiver chip operating at 2-18 GHz according to claim 2, characterized in that: The distributed amplifier structure specifically adopts a four-stage gain unit cascade, and each stage of the gain unit is implemented by a CMOS transistor. Specifically: the parasitic capacitance at the input end of the CMOS transistor is connected in series with the on-chip inductance at the input end to form a gate input artificial transmission line; the parasitic capacitance at the output end of the CMOS transistor is connected in series with the on-chip inductance at the output end to form a drain output artificial transmission line; the gate input artificial transmission line and the drain output artificial transmission line are coupled through the transconductance of the CMOS tube to achieve amplification of the input signal.

4. The ultra-wideband delay transceiver chip operating at 2-18 GHz according to claim 3, characterized in that: Each level of gain unit specifically includes: a first transistor, a second transistor, and a third transistor that are stacked; The gate voltage bias of the first transistor is provided by an external switch control circuit; It also includes a voltage divider network composed of a first resistor, a second resistor, and a third resistor, which is used to provide a gate voltage bias for the second transistor and the third transistor.

5. The ultra-wideband delay transceiver chip operating at 2-18 GHz according to claim 4, characterized in that: The first to eighth gain equalizers all adopt a resistor-capacitor-inductor network, specifically including: a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor and a fifth inductor; the first end of the fifth resistor is connected to the first end of the third capacitor, the second end of the fifth resistor is connected to the second end of the third capacitor, the first end of the fifth resistor serves as the input end of the gain equalizer, the first end of the fifth resistor is also connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the first end of the fifth inductor, the second end of the fifth inductor is grounded, the first end of the fifth inductor is also connected to the first end of the seventh resistor, the second end of the seventh resistor is connected to the second end of the fifth resistor, and the second end of the fifth resistor serves as the output end of the gain equalizer.

6. The ultra-wideband delay transceiver chip operating at 2-18 GHz according to claim 5, characterized in that: The first 160ps delay unit, the first 5ps delay unit, the first 10ps delay unit, the 40ps delay unit, the first 20ps delay unit, the second 20ps delay unit, the first 40ps delay unit, the second 40ps delay unit, the second 10ps delay unit, the second 5ps delay unit, the second 160ps delay unit and the 80ps delay unit are all implemented by a magnetically coupled all-pass network unit; The magnetically coupled all-pass network unit specifically includes: a fourth capacitor, a fifth capacitor, a fifth inductor, and a sixth inductor; the first end of the fourth capacitor serves as the input end of the magnetically coupled all-pass network unit, the first end of the fourth capacitor is connected to the first end of the fifth inductor, the second end of the fifth inductor is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the second end of the fourth capacitor serves as the output end of the magnetically coupled all-pass network unit, the second end of the fourth capacitor is connected to the first end of the sixth inductor, and the second end of the sixth inductor is connected to the first end of the fifth capacitor.

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