A method for forming a digital beam architecture supporting flexible expansion

Abstract

A digital beam forming architecture forming method supporting flexible expansion decouples the rapid change of market demand and the development of digital processing chips, uses a single digital processing chip as the basic computing power of the digital beam forming system, realizes the system architecture through large-scale chip stacking, and quickly adapts to different system requirements with efficient resource utilization, shortens the product market cycle, and ensures the quality reliability and consistency of batch production. Breaks the traditional development thinking and design concept, adapts the chip capacity according to the system index demand and the actual function of the chip, realizes the flexible expansion of any digital beam forming system, and accelerates the system design personnel to design the architecture of the system. For large-scale satellite phased array systems, a general system template can be gradually formed, and the development framework of the entire satellite system can be quickly built based on it.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of large-scale satellite digital beam forming, and particularly relates to a digital beam forming method supporting flexible expansion. BACKGROUND

[0002] A large-scale satellite phased array system usually adopts analog beam forming, digital beam forming or hybrid beam forming. With the continuous improvement of market demand for satellite communication capacity and flexibility, the market demand for satellite load products based on digital beam forming technology has increased dramatically. The core indicators of digital beam forming technology mainly include phased array channel quantity, channel bandwidth and system beam capacity. Under the condition of a determined communication system, the beam capacity is proportional to the number of beams.

[0003] The core technical indicators of a large-scale satellite phased array digital beam forming system are chip processing frequency and hardware resources, which are usually realized by using parallel digital processing chips (FPGA or ASIC, etc.). According to the current domestic and foreign technology development, the resources of a single digital processing chip cannot meet the system requirements. For a digital processing chip, its resource distribution is optimal for system A, but not for system B. To achieve the optimal solution of chip resource distribution for system B, the digital processing chip needs to be redesigned. In the field of satellite load products, the digital processing chip has the characteristics of long development cycle, high software quality standard and difficult batch production. The development of the digital processing chip cannot keep up with the market demand and realize it quickly. In order to meet different market demands, the digital processing chip must be designed and fixed, and the chip function and system demand must be decoupled.

[0004] The difference in system requirements makes the number of chips required by the system vary from several hundred to thousands. Therefore, a reasonable system architecture must be adopted to build such a large-scale digital processing chip. Based on the digital beam forming system of the digital processing chip such as FPGA or ASIC, it is considered that no matter how the system requirements change, the digital beam forming algorithm has no essential difference, and only the adjustment of the system scale is needed. Therefore, it is necessary to propose a method in which a single digital processing chip is used as a basic hardware unit, and the system is stacked by a large number of chips, and a unified system architecture is used to carry out engineering implementation, which becomes a technical problem that must be solved. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a digital beam forming method supporting flexible expansion, which realizes that the system architecture is quickly adapted to different system requirements with high resource utilization rate through simple hardware expansion or reduction, shortens the product market cycle, and ensures the quality reliability and consistency of batch production

[0006] To achieve the above purpose, the technical scheme adopted by the present application includes:

[0007] A digital beam architecture forming method supporting flexible expansion, comprising the following steps:

[0008] S1, obtaining the channel number N, beam bandwidth B, beam number M and digital signal bit width W;

[0009] S2, determining the chip data throughput T, chip hardware resource amount L and chip processing main frequency F;

[0010] S3, calculating the storage resource C and digital operation resource D;

[0011] The storage resource C is calculated by formula (1);

[0012] C=a×C w (1)

[0013] Wherein, a represents the empirical coefficient of storage resource C, C w represents the required resource amount, which is calculated by formula (2);

[0014]

[0015] Wherein, N s represents the number of channels realized by a single chip, M s represents the number of beams realized by a single chip;

[0016] The digital operation resource D is calculated by formula (3);

[0017] D=b×D w (3)

[0018] Wherein, b represents the empirical coefficient of digital operation resource D, D w represents the required resource amount, which is calculated by formula (4);

[0019]

[0020] S4, calculating the channel digital signal Q c and the beam digital signal Q b by formula (5) and formula (6);

[0021] Q c =N S ×2×B×W (5)

[0022] Q b =M S ×2×B×W (6)

[0023] S5, if the chip resource conditions L>(C+D) and T>(Q c +Q b are met at the same time, the obtained Ns and M s are all rounded up, to obtain the required chip number P as formula (7), finally obtaining the digital beam architecture supporting flexible expansion;

[0024] P=(N / N s )×(M / M s ) (7)

[0025] Conversely, repeat S3-S5 until the chip resource condition is met.

[0026] Preferably, a is 1.5.

[0027] Preferably, b is 1.25.

[0028] A digital beam architecture supporting flexible expansion is formed by the method for forming a digital beam architecture supporting flexible expansion disclosed in the present application.

[0029] Compared with the prior art, the present application has the following advantages:

[0030] (1) The method for forming a digital beam architecture supporting flexible expansion decouples the rapid change of market demand and the development of digital processing chips, uses a single digital processing chip as the basic computing power of the digital beam forming system, realizes the simple hardware expansion or reduction of the system architecture through large-scale chip stacking, quickly adapts to different system requirements with high resource utilization, shortens the product market cycle, and ensures the quality reliability and consistency of batch production.

[0031] (2) The method for forming a digital beam architecture supporting flexible expansion breaks the traditional development thinking and design concept in the field of large-scale satellite phased array digital beam forming systems, no longer separately demonstrates and designs digital processing chips for each system, but adapts chip capabilities with system index requirements and actual functions, and then realizes flexible expansion of any digital beam forming system under a unified system architecture.

[0032] (3) The method for forming a digital beam architecture supporting flexible expansion accelerates the architecture design of the system by the system designer, and for large-scale satellite phased array systems, a general system template can be gradually formed, and based on this, the development framework of the entire satellite system can be quickly constructed. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, and are used to explain the present application together with the following specific embodiments, but do not constitute a limitation of the present application. In the drawings:

[0034] Figure 1 Schematic diagram for tree type cascaded beam weighting calculation;

[0035] Figure 2 Schematic diagram for chain type cascaded beam weighting calculation;

[0036] Figure 3 Schematic diagram for channel, beam dimension expansion system structure. DETAILED DESCRIPTION

[0037] The application is not limited to the following specific embodiments, and any equivalent transformation based on the technical solutions of the present application falls within the protection scope of the present application. All components and devices in the present application, if not specifically stated, are all components and devices known in the prior art.

[0038] EMBODIMENT

[0039] The embodiment discloses a digital beam architecture forming method supporting flexible expansion, comprising the following steps:

[0040] S1, obtaining the channel number N, beam bandwidth B, beam number M and digital signal bit width W.

[0041] The embodiment designs the system architecture of the digital beam forming according to the four core indexes of the channel number N of the digital beam forming system = 100, the beam bandwidth B = 2GHz, the beam number M = 64 and the digital signal bit width W = 32 bits. The architecture here mainly refers to the topological connection relationship of the large-scale digital chip.

[0042] S2, determining the chip data throughput T, the chip hardware resource amount L and the chip processing main frequency F.

[0043] The embodiment clearly analyzes the performance indexes of the digital chip. Without the need of re-designing and developing the digital chip in the face of different index requirements, the system architecture is adjusted to flexibly meet various requirements. The digital chip is usually realized by using FPGA or ASIC, and the digital beam forming system mainly focuses on three performance indexes of the chip data throughput T, the chip hardware resource amount L and the chip processing main frequency F.

[0044] The chip data throughput T disclosed in the embodiment is assumed that the data interface number K of the selected system chip is 128 and the data interface rate S is 25Gpbs, so that the chip data throughput T = K x S = 3.2Tbps.

[0045] The chip hardware resource amount L disclosed in the embodiment is that the storage resource in the hardware resource L is about 108Mbit (3000 storage resource minimum blocks, each block is about 36Kbit storage amount), and the digital operation resource is about 6400 multiplier resources.

[0046] The chip processing main frequency F disclosed in the embodiment is 400MHz.

[0047] S3, the storage resource C and the digital operation resource D are calculated;

[0048] The storage resource C is calculated by formula (1) specifically;

[0049] C=a*C w (1)

[0050] Wherein, a represents the experience coefficient of the storage resource C, and the value of the embodiment is 1.5; C w represents the required resource quantity, which is calculated by formula (2);

[0051]

[0052] Wherein, N s represents the number of channels realized by a single chip, and M s represents the number of beams realized by a single chip;

[0053] The digital operation resource D is calculated by formula (3) specifically;

[0054] D=b*D w (3)

[0055] Wherein, b represents the experience coefficient of the digital operation resource D, and the value of the embodiment is 1.25; D w represents the required resource quantity, which is calculated by formula (4);

[0056]

[0057] The algorithm of beam weighting is adopted to realize digital beam forming, and the storage resource C and the digital operation resource D are two core requirements. The required resource quantity is related to three system indexes N, B and M. Generally, a single chip requires all frequency band signals of the sampling system index, that is, the index B is not split, and N and M index requirements are realized by hardware stacking of a large-scale chip. The number of channels N s =10 realized by a single chip is defined, the number of beams M s =8, and then the required number of chips P=(N / N s )×(M / M s )=10×8=80.

[0058] The storage resource C disclosed in the embodiment is mainly used for storing beam weight values, because the storage resource required by the beam weight values usually accounts for more than 80% of the total resource quantity. It is generally considered that the beam weight values are the same as the beam signal bit width, and the required resource quantity C w =2*N s *M s× (2 × B / F) × 1 = 2 × 10 × 8 × (2 × 5) × 1 = 1600. Storage resource C = 1.5 × C w = 1.5 × 1600 = 2400.

[0059] The digital operation resource D disclosed in the embodiment is mainly used for complex multiplication calculation of the digital beam weighting network, and the required resource amount D w = 2 × N s × M s × (2 × B / F) × 3 = 2 × 10 × 8 × (2 × 5) × 3 = 4800. Digital operation resource D = 1.25 × D w = 1.25 × 4800 = 6000.

[0060] S4, calculate the channel digital signal Q c and the beam digital signal Q b by formula (5) and formula (6).

[0061] Q c = N S × 2 × B × W (5)

[0062] Q b = M S × 2 × B × W (6)

[0063] The data amount Q of the digital signal is related to the signal bit width, bandwidth and quantity. For the channel digital signal Q c = N S × 2 × B × W = 10 × 2 × 2 × 32 = 1280 Gbit, for the beam digital signal Q b = M S × 2 × B × W = 8 × 2 × 2 × 32 = 1024 Gbit.

[0064] S5, if the chip resource conditions L > (C + D) and T > (Q c + Q b ) are met at the same time, the N s and M s are all rounded up, and the required chip amount P is obtained as formula (7), and finally the digital beam architecture supporting flexible expansion is obtained;

[0065] P = (N / N s ) × (M / M s ) (7)

[0066] Otherwise, repeat S3-S5 until the chip resource conditions are met.

[0067] The chip resource evaluation of the embodiment can meet the requirements of 2400 36Kbit storage resource blocks and 6000 multiplier operation resource blocks, and T can meet the transmission requirements of the total data amount of the channel digital signals and the beam digital signals, so the subsequent steps are continued to be executed.

[0068] The topology connection relationship between large-scale chips is designed from the two dimensions of channel expansion and beam expansion. The digital beam weighting network is a process of superimposed summation of a group of signal complex weights, as shown in Figure 1 、 2 A single chip receives 10 channel signals, and outputs 8 beam signals after digital beam weighting network operation. The channel received by a single chip is defined as a system subarray channel, and the beam formed by the subarray channel is defined as a system subarray beam. The subarray channel is cascaded by the chips to realize channel dimension expansion until 100 channels of the system index are met, and the subarray beam is stacked by the chips to realize beam dimension expansion until 64 beams of the system index are met. Figure 3 is a cascaded mode, wherein each DBF (digital beam forming) branch contains 2 DBF chips, and each branch increases 1 in the row dimension, thereby realizing 20 channel expansion; each branch increases 1 in the column dimension, thereby realizing 16 beam expansion. It should be noted that the expansion mode shown in the example is not unique, and the skilled person should optimize the expansion mode in combination with system design, such as tree expansion, chain expansion, etc., but no matter which mode, the system is expanded based on a single chip as a basic component unit.

[0069] The preferred embodiments of the present disclosure are described in detail above in combination with the drawings, but the present disclosure is not limited to the specific details in the above-described embodiments, and various simple modifications can be made to the technical solutions of the present disclosure within the technical concept of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

[0070] In addition, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction, and in order to avoid unnecessary repetition, the present disclosure will not further describe various possible combination manners. In addition, the various different embodiments disclosed in the present solution can also be combined in any manner, as long as it does not deviate from the idea of the present disclosure, it should also be considered as the content invented by the present disclosure.

Claims

1. A method for forming a digital beamformation architecture that supports flexible expansion, characterized in that, Includes the following steps: S1, obtain the number of channels N, beam bandwidth B, number of beams M, and digital signal bit width W; S2, specify the chip data throughput T, chip hardware resource quantity L, and chip main processing frequency F; S3, calculates the storage resource C and the digital computing resource D; Specifically, the storage resource C is calculated using equation (1); C=a×C w (1) Where 'a' represents the empirical coefficient of storage resource C, and C w The required amount of resources is calculated using equation (2); C w =2×N s ×M s ×(2×B / F)×1 [F≤B] C w =2×N s ×M s ×(2×F / B) ×1 [F>B] (2) Where, N s M represents the number of channels implemented in a single chip. s This indicates the number of beams implemented by a single chip; Specifically, the digital computing resource D is calculated using equation (3); D=b×D w (3) Where b represents the empirical coefficient of digital computing resource D, D w The required amount of resources is calculated using equation (4); D w =2×N s ×M s ×(2×B / F)×3 [F≤B] D w =2×N s ×M s ×(2×F / B) ×3 [F>B] (4) S4, calculate the channel digital signal Q using equations (5) and (6). c and beam digital signal Q b ; Q c =N S ×2×B×W (5) Q b =M S ×2×B×W (6) S5, if the chip resource conditions L>(C+D) and T>(Q) are satisfied simultaneously... c +Q b ), and obtained N s and M s Rounding up, we get the required number of chips P as shown in equation (7), and finally obtain a digital beam architecture that supports flexible expansion. P=(N / N s )×(M / M s ) (7) Conversely, repeat steps S3-S5 until the chip resource conditions are met.

2. The digital beamforming method supporting flexible expansion as described in claim 1, characterized in that, The value of 'a' is 1.

5.

3. The digital beamforming method supporting flexible expansion as described in claim 1, characterized in that, The value of b is 1.

25.

4. A digital beamforming architecture that supports flexible expansion, characterized in that, It is prepared by the digital beamforming method supporting flexible expansion as described in any one of claims 1-3.

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