Digital radio frequency device and laser frequency stabilization device based on gigabit transceiver

Abstract

The invention discloses a digital radio frequency device based on a gigabit transceiver and a laser frequency stabilization device, and relates to the technical field of laser frequency stabilization. The digital radio frequency device comprises a coding phase module, a phase modulation module, a serial transmitting module and a radio frequency driving module. Wherein the coding phase module is used for generating an initial coding phase based on the clock signal frequency of the gigabit transceiver, the preset number of parallel channels and the target laser frequency shift; the phase modulation module is used for performing phase modulation on the initial coding phase to generate a coding phase and a demodulation signal; the serial transmitting module is used for generating a digital radio frequency signal based on the coding phase and the gigabit transceiver; and the radio frequency driving module is used for performing power amplification and filtering on the digital radio frequency signal to generate a target digital radio frequency signal. The digital radio frequency device can provide a digital radio frequency source which is low in cost, wide in frequency range and high in power stability for the field of space cold atoms and the like.

Description

Technical Field

[0001] The present application relates to the technical field of laser frequency stabilization, and in particular to a digital radio frequency device and a laser frequency stabilization device based on a gigabit transceiver. Background Art

[0002] In the field of space cold atoms, a large number of radio frequency sources are needed. However, the radio frequency sources currently used have many problems such as high price, low indicators, and complex operation. How to make a low-cost radio frequency source with a wide frequency range and high power stability has become a technical problem that needs to be solved in the field of atomic cold space. Summary of the invention

[0003] Based on the above problems, the present application provides a digital RF device based on a gigabit transceiver, which can provide a digital RF source with low cost, wide frequency range and high power stability for the field of space cold atoms, etc.

[0004] The embodiments of the present application disclose the following technical solutions: The first aspect of the present application discloses a digital radio frequency device based on a gigabit transceiver, comprising: A coding phase module, for generating an initial coding phase based on a clock signal frequency of the gigabit transceiver, a preset number of parallel channels, and a target laser shift frequency; A phase modulation module, used for phase modulating the initial coding phase to generate a coding phase and a demodulation signal; the coding phase has a double-sideband; the demodulation signal is a signal with the same frequency as the target sideband; the target sideband is a sideband in the double-sideband; A serial transmission module, configured to generate a digital radio frequency signal based on the coding phase and the gigabit transceiver; The RF driving module is used to amplify and filter the digital RF signal to generate a target digital RF signal.

[0005] In an optional implementation, the coding phase module includes: A first accumulation step length determination submodule, configured to determine a serial phase accumulation step length according to a clock signal frequency of the gigabit transceiver and the target laser shift frequency; A second accumulation step determination submodule, configured to determine a parallel phase accumulation step based on the serial phase accumulation step and the number of parallel channels; A basic phase determination submodule, used to determine the basic phase corresponding to the parallel channel at the current counting moment based on the basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each of the parallel channels has the same basic phase at the same counting moment; The coding phase determination submodule is used to determine, for each of the parallel channels, an initial coding phase of the parallel channel at the current counting moment based on the basic phase of the parallel channel at the current counting moment, the channel coding of the parallel channel and the serial phase accumulation step; the channel coding is a preset digital coding for indicating the arrangement order of the corresponding parallel channel in the plurality of parallel channels.

[0006] In an optional implementation, the first accumulation step size determination submodule includes: A time step determining unit, configured to determine a time step based on a clock signal frequency of the gigabit transceiver; The serial phase accumulation step length determining unit is used to determine the serial phase accumulation step length based on the time step length, the target laser frequency shift and the full phase range.

[0007] In an optional implementation, the phase modulation module includes: A parameter setting submodule, used to set an initial phase corresponding to the digital radio frequency signal as a first initial phase; A function setting submodule is used to set the phase modulation depth, the phase modulation signal frequency and the second initial phase to obtain a phase modulation function; The phase modulation submodule is used to phase modulate the initial coding phase based on the phase modulation function and the first initial phase to generate the coding phase and the demodulated signal.

[0008] In an optional implementation, the function setting submodule includes: a target address determining unit, configured to determine a target address based on the second initial phase and a phase corresponding to the gigabit transceiver; the phase corresponding to the gigabit transceiver being a product of a frequency of the phase modulation signal and time; a target amplitude determination unit, configured to determine a target amplitude based on the target address and a preset first lookup table; the first lookup table indicates a correspondence between an address and an amplitude of a sine wave; A sine wave determination unit is used to determine a sine wave function as the phase modulation function based on the phase modulation depth, the phase modulation signal frequency and the second initial phase, the phase corresponding to the gigabit transceiver and the target amplitude.

[0009] In an optional implementation, the function setting submodule includes: A triangle wave function setting unit is used to determine a triangle wave function as the phase modulation function based on the phase corresponding to the gigabit transceiver and a preset triangle wave formula; the phase corresponding to the gigabit transceiver is the product of the phase modulation signal frequency and time.

[0010] In an optional implementation, the phase modulation submodule includes: a modulation basic phase determining unit, configured to determine the modulation basic phase corresponding to the parallel channel at the current counting moment based on the modulation basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each of the parallel channels has the same modulation basic phase at the same counting moment; a coding modulation phase determining unit, configured to determine, for each of the parallel channels, the coding modulation phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the current counting moment, the channel coding of the parallel channel, the serial phase accumulation step, the phase modulation function and the first initial phase; The coding phase determining unit is used to determine, for each of the parallel channels, the coding phase of the parallel channel at the current counting moment based on the initial coding phase corresponding to the parallel channel at the current counting moment and the coding modulation phase corresponding to the parallel channel at the current counting moment.

[0011] In an optional implementation, the serial transmission module includes: A preprocessing module, configured to perform a parameter zeroing operation on the gigabit transceiver to obtain a target gigabit transceiver; the parameter zeroing operation is configured to clear the pre-stored protocols and parameters in the gigabit transceiver; A digital coding unit, used for splicing the coding phases of the highest bits of the plurality of parallel channels to obtain the digital code; A digital radio frequency transmitting unit is used to generate the digital radio frequency signal based on the target gigabit transceiver and the digital code.

[0012] The second aspect of the present application discloses a laser frequency stabilization device, the device comprising: a laser, a digital radio frequency module, an electro-optical modulator, a frequency stabilization cavity, an error detection module and a servo control module; The laser is used to output a first laser signal; The digital radio frequency module is used to generate the phase of the demodulated signal and the digital radio frequency signal according to the target laser frequency shift; the demodulated signal and the digital radio frequency signal are homologous signals; the digital radio frequency module is the digital radio frequency device disclosed in the first aspect; The electro-optical modulator is used to generate a second laser signal according to the first laser signal and the digital radio frequency signal; The frequency stabilizing cavity is used to output a third laser signal according to the second laser signal; The error detection module is used to generate a digital error signal based on the phase of the third laser signal and the demodulated signal; The servo control module is used to perform servo control on the laser according to the digital error signal, so that the error value corresponding to the re-detected digital error signal is smaller than a set error threshold.

[0013] In an optional implementation, the error detection module includes: A detection signal acquisition unit, used to detect and process the third laser signal through an analog-to-digital converter and a photodetector to obtain a detection signal; An error signal generating unit is used to mix and filter the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain the digital error signal; the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second lookup table; the second lookup table is used to indicate the correspondence between the phase and the digital code value.

[0014] In an optional implementation, the servo control module is specifically used to: According to the digital error signal, the digital lead-lag and the digital proportional differential integral regulator, the laser is servo-controlled so that the error value corresponding to the re-detected digital error signal is smaller than the set error threshold.

[0015] Compared with the prior art, this application has the following beneficial effects: The present application discloses a digital radio frequency device based on a gigabit transceiver, including: a coding phase module, a phase modulation module, a serial transmission module and a radio frequency driver module. Among them, the coding phase module is used to generate an initial coding phase based on the clock signal frequency of the gigabit transceiver, the number of preset parallel channels and the target laser frequency shift; the phase modulation module is used to phase modulate the initial coding phase to generate a coding phase and a demodulation signal; the serial transmission module is used to generate a digital radio frequency signal based on the coding phase and the gigabit transceiver; the radio frequency driver module is used to power amplify and filter the digital radio frequency signal to generate a target digital radio frequency signal. Since the gigabit transceiver can be integrated on an FPGA, it has the advantages of low cost and strong stability; by changing the signal frequency of the gigabit transceiver, the output of the target digital radio frequency signal in the frequency range of 0-5G can be achieved; therefore, the digital radio frequency device in the present application can provide a digital radio frequency source with low cost, wide frequency range and high power stability for the field of space cold atoms, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A schematic diagram of the structure of a digital radio frequency device provided in an embodiment of the present application; Figure 2A A schematic diagram of generating an initial coding phase provided in an embodiment of the present application; Figure 2B A schematic diagram of generating a coding phase provided in an embodiment of the present application; Figure 3 A schematic diagram of the relationship between frequency and power of a digital radio frequency signal provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a laser frequency stabilization device provided in an embodiment of the present application; Figure 5 A schematic diagram of a frequency distribution of a second laser signal provided in an embodiment of the present application; Figure 6 A schematic diagram of a third-order lead-lag frequency response curve provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In the field of space cold atoms, a large number of radio frequency sources are needed. However, the radio frequency sources currently used have many problems such as high price, low performance and complex operation.

[0019] Gigabit transceiver (GTX) is a high-performance, high-reliability, high-speed serial transceiver with broad application prospects in a variety of high-speed serial communication interfaces. Gigabit transceivers are embedded in FPGAs, with line speeds typically ranging from 1Gbps to 12Gbps and effective loads ranging from 0.8Gbps to 10Gbps, which can meet the high-speed, real-time transmission requirements of massive data in modern digital processing and computing technologies.

[0020] The present application proposes a digital radio frequency device based on a gigabit transceiver, which can provide a digital radio frequency source with low cost, wide frequency range, high power stability, high resolution and fast response for the field of space cold atoms, etc.

[0021] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] Figure 1 A schematic diagram of the structure of a digital radio frequency device provided in an embodiment of the present application. Figure 1 As shown, the digital radio frequency device 100 in the present application includes: a coding phase module 101 , a phase modulation module 102 , a serial transmission module 103 and a radio frequency driving module 104 .

[0023] The coding phase module 101 is used to generate an initial coding phase based on the clock signal frequency of the GTX transceiver, the number of preset parallel channels and the target laser shift frequency.

[0024] The phase modulation module 102 is used to phase modulate the initial coding phase to generate coding phase and demodulation signal. The coding phase has a double sideband; the demodulation signal is a signal with the same frequency as the target sideband; the target sideband is a sideband in the double sideband.

[0025] The serial transmission module 103 is used to generate a digital radio frequency signal based on the coding phase and the GTX transceiver.

[0026] The RF driving module 104 is used to amplify and filter the digital RF signal to generate a target digital RF signal.

[0027] In an optional implementation, the encoding phase module 101 includes: A first accumulation step determination submodule, used to determine the serial phase accumulation step according to the clock signal frequency of the GTX transceiver and the target laser shift frequency; A second accumulation step determination submodule, used to determine the parallel phase accumulation step based on the serial phase accumulation step and the number of parallel channels; A basic phase determination submodule is used to determine the basic phase corresponding to the parallel channel at the current counting moment based on the basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same basic phase at the same counting moment; The coding phase determination submodule is used to determine, for each parallel channel, the initial coding phase of the parallel channel at the current counting moment based on the basic phase of the parallel channel at the current counting moment, the channel coding of the parallel channel and the serial phase accumulation step; the channel coding is a preset digital coding for indicating the arrangement order of the corresponding parallel channel in multiple parallel channels.

[0028] In an optional implementation, the first accumulation step size determination submodule includes: A time step determination unit, for determining a time step based on a clock signal frequency of the GTX transceiver; The serial phase accumulation step length determination unit is used to determine the serial phase accumulation step length based on the time step length, the target laser frequency shift and the full phase range.

[0029] Figure 2A A schematic diagram of generating an initial coding phase is provided in an embodiment of the present application. Figure 2A , a process of generating an initial coding phase by coding phase module 101 is described in detail. The process can be summarized into three steps: Step 1: Determine the parallel phase accumulation step size.

[0030] Gigabit transceiver is a high-speed serial transceiver with a maximum sampling rate of more than 10GHz. However, 10GHz is not suitable for the internal logic unit of FPGA. In this application, parallel encoding is configured to the transmission port of GTX through parallel encoding, and parallel-to-serial operation is performed inside GTX to achieve a serial transmission speed of 10G.

[0031] In digital circuits, the clock frequency can be framed by integers through counters. The data transmission clock of GTX can be as high as 10G, and through integer framing, 10 / 2N (N=1, 2, 3...) positive integer framing can be achieved in theory; 10 / 2N corresponds to the frequency of the output signal; 10G is the highest serial transceiver clock frequency supported by GTX, and the frequency division factor is 2N (N is the width of half a cycle, and the length of the positive and negative cycles of the square wave is the same, so the frequency division factor is an integer multiple of two).

[0032] The characteristic of integer framing is that the duty cycle of the output waveform is kept stable at 50%. The disadvantage is that the output frequency is limited and the interval is not fixed. The higher the frequency, the larger the interval. In many application scenarios, the duty cycle is not required to be stable at 50%. Fractional frequency division can be achieved by changing the ratio of 0 and 1.

[0033] It should be emphasized that the clock signal frequency, target laser shift frequency, number of serial channels (also called parallel bit width) and encoding of the serial channels of the gigabit transceiver are pre-set according to usage requirements.

[0034] For example, in the present application, the clock signal frequency of the gigabit transceiver is set to 10G and the number of serial channels is set to 64.

[0035] The commonly used parallel bit width under the 10GHz serial clock is 64, and the corresponding parallel clock (also known as the parallel clock in the phase modulation module) is 156.25MHz. Therefore, the phase counter is 64 parallel channels under the 156.25MHz clock, corresponding to 64-bit parallel encoding. Under the 64-channel parallel, the single accumulation phase of a single-channel counter is the phase step under the parallel clock, and the initial phase is the phase offset of the corresponding encoding of the counter under the serial clock.

[0036] The sinusoidal signal y1(t)=sin(ω1t+φ O ) as an example, the real-time phase of the sinusoidal signal is ω1t+φ O , ω1 is the angular frequency, φ O is the initial phase, t is time, and y1(t) is the expression of the sine function. The real-time phase of a sine signal is linearly related to time, that is, the time domain waveform of a sine signal is linearly related to time. Therefore, a counter can be used to accumulate the phase; that is, the real-time phase of the corresponding sine signal increases by how much in the time length when the counter increases by one number, and then the time domain waveform of the sine signal can be obtained.

[0037] However, the counter can keep increasing, and the accumulation of the counter is infinite. The sine signal is a periodic signal, and its phase will start to accumulate from zero again after accumulating to 2π. Therefore, the integer period part in the phase accumulation can be removed by phase folding, and the fractional period can be matched with the accumulation range of the counter. In this way, the process of resetting the counter after the accumulation exceeds the range and starting to count again is equivalent to the process of phase folding and re-accumulating the phase after the phase accumulation reaches 2π.

[0038] The clock signal frequency of the gigabit transceiver is 10G, so the time step is 1 / 10G; the phase full scale is 2π, then when the target laser shift frequency is △F, the corresponding serial phase accumulation step is equal to 2π×target laser shift frequency×time step, that is, equal to 2π×△F×(1 / 10G); this process is implemented by the first accumulation step determination submodule.

[0039] When the clock speed is much lower, it is necessary to increase the counter accumulation frequency through parallel multiplexing to achieve a phase accumulation frequency equal to the serial transmission frequency.

[0040] The number of parallel channels preset in the present application is 64. After obtaining the serial phase accumulation step, the product of the serial phase accumulation step and the number of parallel channels is used as the parallel phase accumulation step corresponding to the parallel clock in the phase modulation module. That is, the parallel phase accumulation step = serial phase accumulation step × 64; this process is implemented by the second accumulation step determination submodule.

[0041] Step 2: Determine the basic phase of the parallel channel at the Tth counting moment.

[0042] It can be understood that each of the parallel channels is counted at the same time, and at the same counting moment, each of the 64 parallel channels has the same basic phase. When the digital radio frequency device is not started, the basic phase of each parallel channel is 0.

[0043] After the parallel phase accumulation step is obtained and the digital RF device is started, for any counting moment, such as the Tth counting moment, the basic phase corresponding to the parallel channel at the current counting moment (Tth counting moment) can be determined according to the basic phase corresponding to the previous counting moment (T-1th counting moment) and the parallel phase accumulation step.

[0044] Specifically, the basic phase of the parallel channel at the Tth counting moment=the basic phase of the parallel channel at the T-1th counting moment+the parallel phase accumulation step; this process is implemented by the basic phase determination submodule.

[0045] Step 3: Determine the initial encoding phase of the parallel channel at the Tth counting moment.

[0046] For each of the 64 parallel channels, an initial coding phase of the parallel channel at the current counting moment is determined based on the basic phase of the parallel channel at the current counting moment, the channel coding of the parallel channel and the serial phase accumulation step.

[0047] Specifically, the initial coding phase of the parallel channel at the Tth counting moment=the basic phase of the parallel channel at the Tth counting moment+the serial phase accumulation step×the channel coding of the parallel channel.

[0048] Exemplarily, the initial coding phase of the Mth parallel channel at the Tth counting moment=the basic phase of the Mth parallel channel at the Tth counting moment+the serial phase accumulation step×the channel coding of the Mth parallel channel; wherein M is an integer greater than 0 and less than 64.

[0049] When the number of parallel channels is 64, the range of channel coding is 0-63. Each of the 64 parallel channels has a channel coding. The channel coding is a preset digital coding used to indicate the arrangement order of the corresponding parallel channels in multiple parallel channels; this process is implemented by the coding phase determination submodule.

[0050] In an optional implementation, the phase modulation module 102 includes: A parameter setting submodule, used to set an initial phase corresponding to the digital radio frequency signal as a first initial phase; A function setting submodule is used to set the phase modulation depth, the phase modulation signal frequency and the second initial phase to obtain a phase modulation function; The phase modulation submodule is used to perform phase modulation on the initial coding phase based on the phase modulation function and the first initial phase to generate a coding phase and a demodulation signal.

[0051] In an optional implementation, the function setting submodule includes: a target address determination unit, configured to determine a target address based on the second initial phase and a phase corresponding to the GTX transceiver; the phase corresponding to the GTX transceiver being a product of a frequency of the phase modulation signal and time; A target amplitude determination unit, configured to determine a target amplitude based on a target address and a preset first lookup table; the first lookup table indicates a correspondence between an address and an amplitude of a sine wave; The sine wave determination unit is used to determine a sine wave function as a phase modulation function based on the phase modulation depth, the phase modulation signal frequency and the second initial phase, the phase corresponding to the GTX transceiver and the target amplitude.

[0052] In another optional implementation, the function sets the submodule, including: The triangle wave function setting unit is used to determine the triangle wave function as the phase modulation function based on the phase corresponding to the GTX transceiver and the preset triangle wave formula; the phase corresponding to the GTX transceiver is the product of the phase modulation signal frequency and time.

[0053] In an optional implementation, the phase modulation submodule includes: A modulation basic phase determination unit, used to determine the modulation basic phase corresponding to the parallel channel at the current counting moment based on the modulation basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each parallel channel has the same modulation basic phase at the same counting moment; a coding modulation phase determination unit, configured to determine, for each parallel channel, the coding modulation phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the current counting moment, the channel coding of the parallel channel, the serial phase accumulation step, the phase modulation function and the first initial phase; The coding phase determining unit is used to determine the coding phase of each parallel channel at the current counting moment based on the initial coding phase corresponding to the parallel channel at the current counting moment and the coding modulation phase corresponding to the parallel channel at the current counting moment.

[0054] It should be noted that in the present application, the coding phase module 101 outputs the initial coding phase. After the initial coding phase is input into the phase modulation module 102, the phase modulation module 101 may perform phase modulation on the initial coding phase to generate a coding phase. In another case, the phase modulation module 101 may not perform phase modulation on the initial coding phase and directly determine the initial coding phase as the coding phase.

[0055] Based on the phase modulation module 102, the process of generating the modulation phase can be summarized into three steps: Step 1: Determine the first initial phase.

[0056] The expression of phase modulation is: y2(t)=A C ×sin(ω C ×t+m(t)+φ C ). Where y2(t) is the expression of phase modulation, t is time, A C is the carrier amplitude, ω C is the carrier frequency, m(t) is the phase modulation function, φ C is the initial phase of the RF signal.

[0057] The initial phase φ corresponding to the digital RF signal can be set by the submodule parameter setting C Set the value as the first initial phase. C The setting range is [0, 2π].

[0058] The second step is to determine the phase modulation function.

[0059] The expression of the phase modulation function is: m(t)=β m ×sin(ω m ×t+φ m ). Where m(t) is the phase modulation function, t is time, β m is the phase modulation depth, ω m is the phase modulation signal frequency, φ m is the initial phase of the phase modulation signal, that is, the second initial phase.

[0060] The phase modulation function can be obtained by setting the phase modulation depth, the phase modulation signal frequency and the second initial phase.

[0061] In an optional implementation, the phase modulation function may be set as a sine wave function by a target address determination unit, a target amplitude determination unit, and a sine wave determination unit in a function setting submodule, including the following steps: First, a target address is determined by a target address determination unit based on the second initial phase and a phase corresponding to the GTX transceiver.

[0062] The phase corresponding to the GTX transceiver is the product of the phase modulation signal frequency and time, which is ω m ×t, abbreviated as P m .

[0063] The second initial phase φ m The phase P corresponding to the GTX transceiver m The sum of is used as the target address.

[0064] Secondly, the target amplitude is determined by the target amplitude determination unit based on the target address and a preset first lookup table.

[0065] The preset first lookup table indicates the corresponding relationship between the address and the amplitude of the sine wave.

[0066] For example, the sine wave amplitude corresponding to the target address in sin_bram can be searched as the target amplitude. Wherein, sin_bram is a lookup table generated by the bram IP core, and the phase corresponding to the address range of sin_bram is 0-2π; the stored data calculates the target amplitude with the target address as the phase, and the expression is shown in formula (1): addr=mod{(P m +φ m ), 2π}×2 ADDR_WIDTH (1) Among them, addr is the target address, mod{} function is the remainder operation, P m is the phase corresponding to the GTX transceiver, φ m is the second initial phase, ADDR_WIDTH is the address width of the lookup table; through this formula, the binary address corresponding to the periodic phase can be obtained as shown in formula (2): data=2 DATA_WIDTH-1 ×{sin (2π×addr÷2 ADDR_WIDTH )+1}(2) Among them, data is the target amplitude, that is, the storage data of the sinusoidal signal lookup table, ADDR_WIDTH is the address width of the lookup table, and DATA_WIDTH is the data width stored in the lookup table; the functions of other letters refer to the introduction of the previous embodiment and will not be repeated here.

[0067] The phase modulation depth β m , phase modulation signal frequency ω m , the second initial phase φ m , the phase P corresponding to the GTX transceiver m Substitute the target amplitude into m(t)=β m ×sin(ω m ×t+φ m ), the obtained sinusoidal wave function is used as the phase modulation function.

[0068] In an optional implementation manner, the phase modulation function may be set as a triangular wave function by a triangular wave function setting unit in a function setting submodule.

[0069] Specifically, the phase P corresponding to the GTX transceiver can be set by the triangle wave function setting unit. m Substitute into the preset triangular wave function to obtain the triangular wave function.

[0070] The expression of the preset triangular wave function is shown in formula (3): (3) Where Tri(t) is the triangular wave function, P m is the phase corresponding to the GTX transceiver, β m is the phase modulation depth.

[0071] The third step is to perform phase modulation on the coding phase based on the phase modulation function and the first initial phase to generate a modulation phase and a demodulation signal.

[0072] Figure 2B A schematic diagram of generating a coding phase provided in an embodiment of the present application. Figure 2B As shown, the generation process of the coding phase is: (1) Determine the parallel phase accumulation step corresponding to the preset 64 parallel channels in the modulation phase module 102.

[0073] The parallel phase accumulation step corresponding to the parallel clock in the phase modulation module, that is, the parallel phase accumulation step = the serial phase accumulation step × 64. This step can refer to the description of the first step of the process of generating the initial coding phase based on the coding phase module 101 in the above embodiment. It will not be repeated here.

[0074] It should be emphasized that the clock signal frequencies in the coding phase module 101 and the phase modulation module 102 in the present application are set with reference to the clock signal frequency of the same gigabit transceiver; the coding phase module 101 and the phase modulation module 102 count separately, but the counting of the two is synchronized; that is, when the coding phase module 101 reaches the Tth counting moment, the phase modulation module 102 also reaches the Tth counting moment.

[0075] (2) Determine the modulation base phase of the parallel channel at the Tth counting time in the phase modulation module 102.

[0076] The modulation basic phase of the parallel channel at the Tth counting time = the modulation basic phase of the parallel channel at the T-1th counting time + the parallel phase accumulation step.

[0077] In the present application, the basic phase at the current counting moment in the phase modulation module 102 is referred to as the modulation basic phase at the current counting moment.

[0078] The process of calculating the modulation basic phase may refer to the description of the second step of the process of generating the initial coding phase based on the coding phase module 101 in the aforementioned embodiment, which will not be described in detail here.

[0079] (3) Determine the coding modulation phase of each parallel channel at the Tth counting time in the phase modulation module 102.

[0080] For each of the 64 parallel channels, the coded modulation phase of the parallel channel at the current counting moment is determined based on the modulation base phase of the parallel channel at the current counting moment, the channel coding of the parallel channel, the serial phase accumulation step and the modulation function.

[0081] Specifically, the coded modulation phase of the parallel channel at the Tth counting time = the modulation function of the parallel channel at the Tth counting time × (modulation base phase of the parallel channel at the Tth counting time + serial phase accumulation step × channel coding of the parallel channel).

[0082] For example, the coded modulation phase of the Mth parallel channel at the Tth counting time = the modulation function of the Mth parallel channel at the Tth counting time × (modulation base phase of the Mth parallel channel at the Tth counting time + serial phase accumulation step × channel coding of the Mth parallel channel).

[0083] Among them, the modulation function of the parallel channel at the Tth counting moment, with reference to the introduction of the above-mentioned embodiment, can be selected as a sine modulation function or a triangle wave modulation function.

[0084] (4) In the coding phase module 101 , the initial coding phase of each of the preset 64 parallel channels at the Tth counting moment is obtained.

[0085] The generation process of the initial coding phase refers to Figure 2A The description in will not be repeated here.

[0086] (5) Determine the coding phase of each of the preset 64 parallel channels in the phase modulation module 102.

[0087] For each of the 64 parallel channels, the coding phase of the parallel channel at the current counting moment can be determined based on the initial coding phase of the parallel channel at the current counting moment and the coding modulation phase of the parallel channel at the current counting moment.

[0088] Specifically, for each of the 64 parallel channels, the coding phase of the parallel channel at the Tth counting time = the initial coding phase of the parallel channel at the Tth counting time + the coding modulation phase of the parallel channel at the Tth counting time. In this way, the coding phase of each of the 64 parallel channels can be obtained.

[0089] In an optional implementation, the serial transmission module 103 includes: A preprocessing module, used for performing a parameter zeroing operation on the gigabit transceiver to obtain a target gigabit transceiver; the parameter zeroing operation is used for clearing the pre-stored protocols and parameters in the gigabit transceiver; A digital coding unit, used for splicing the coding phases of the highest bits of multiple parallel channels to obtain digital codes; The digital radio frequency transmitting unit is used to generate a digital radio frequency signal based on a target gigabit transceiver and digital coding.

[0090] Gigabit transceivers (GTX) are mainly used in FPGA (field programmable gate array), which uses the programmable resources inside the FPGA for flexible configuration to adapt to different needs, such as Ethernet. There are often some preset parameters and protocols in the gigabit transceiver, including but not limited to differential output swing and on-chip terminal resistance; the preset protocol can be the Aurora protocol; in actual applications, the specific parameters and protocols of the gigabit transceiver may vary according to the specific FPGA model, application requirements and interface standards.

[0091] Before starting the solution in this application, it is necessary to clear the built-in parameters or protocols in the gigabit transceiver, and at the same time, set the bit width of the parallel channel to obtain the target gigabit transceiver. It should be noted that the serial clock speed must be divisible by the parallel clock.

[0092] Then, the phase modulation code 102 transmits the coding phase of the parallel channel output at the current counting moment to the serial transmission module 103. The digital coding unit in the serial transmission module 103 splices the coding phase of the highest bit of the 64 parallel channels to obtain the digital code.

[0093] Finally, based on the target gigabit transceiver and digital coding, a digital RF signal is output.

[0094] Since the digital RF signal is a square wave, it contains many high-frequency harmonics in addition to the carrier wave. Although in many cases, harmonics do not affect the use, if there is a requirement for the harmonic power, it is necessary to use a filter for filtering. When the output frequency range is large, a single filter circuit cannot meet the use requirements, so an RF switch can be added to switch the filter circuit. At the same time, since the power of the digital RF signal output by the serial transmission module is generally small, it cannot meet the driving requirements of most RF devices. Therefore, in this application, after the serial transmission module 103, an RF driver module 104 is matched.

[0095] The digital RF signal output by the serial transmitting module 103 enters the RF driving module 104, undergoes power amplification and filtering, and generates a target digital RF signal.

[0096] Figure 3 A schematic diagram of the relationship between the frequency and power of a digital radio frequency signal provided in an embodiment of the present application. Figure 3 The curve indicating the relationship between the power of the digital RF signal and the frequency is called the output amplitude-frequency characteristic curve. Figure 3 As shown in the figure, the peak power of the RF signal output by GTX is about -3dBm. The power attenuation can be kept within 3dB within 0~1G, but the attenuation is faster from 1G to 5G. If the output frequency changes frequently and there is a certain requirement for power, the GTX output RF can be made flatter within the range of 0~1G through an equalizer. The frequency points greater than 1G can meet the power requirements after multi-stage RF amplification, and the power difference between different frequencies can be compensated by a voltage-controlled attenuator.

[0097] The digital RF device disclosed in the above-mentioned embodiment includes a gigabit transceiver, which is integrated on an FPGA and has the advantages of low cost and strong stability; by changing the signal frequency of the gigabit transceiver, the output of the target digital RF signal with a frequency range of 0-5G can be achieved; up to 16 RF signals can be output, which is enough to meet a large number of RF needs; the frequency and phase adjustment speed in this application is extremely fast, the upper limit of the speed adjustment is the GTX system clock, and it can be output uninterruptedly, which can provide a low-cost, wide frequency range, high power stability, high resolution and fast response digital RF source for the field of space cold atoms, etc. In this application, while outputting the RF signal, behavioral modulation can also be performed to generate double-sideband, which can be used in the PDH frequency stabilization optical path (Pound-Drever-Hall laser frequency stabilization optical path), saving the use of RF devices in the PDH frequency stabilization optical path.

[0098] Figure 4 A schematic diagram of the structure of a laser frequency stabilization device provided in an embodiment of the present application. Figure 4 As shown, the laser frequency stabilization device in the present application includes: a laser 401 , an electro-optic modulator 402 , a frequency stabilization cavity 403 , an error detection module 404 , a servo control module 405 , and a digital radio frequency module 406 . Figure 4 The digital radio frequency module 406 in the embodiment is the digital radio frequency module disclosed in the above embodiment.

[0099] Figure 4 The laser 401 is a controlled object, which is used to output a first laser signal. The laser frequency output by the laser 401 can be adjusted by a current modulation signal.

[0100] The digital radio frequency module 406 is used to generate a demodulation signal and a digital radio frequency signal according to the target laser frequency shift; wherein the demodulation signal and the digital radio frequency signal are homologous signals.

[0101] The electro-optic modulator 402 is used to receive the first laser signal output by the laser 401 and the digital RF signal output by the digital RF module 406, and generate a second laser signal. That is, the phase of the first laser signal output by the laser is modulated, and according to the Bessel function, the modulated laser signal carries multiple sidebands, and the sideband distribution is related to the frequency of the digital RF signal.

[0102] The frequency stabilizing cavity 403 is used to lock the laser wavelength to the characteristic cavity length of the cavity after receiving the second laser signal. That is, when the second laser signal is transmitted to the frequency stabilizing cavity 403, a third laser signal is output.

[0103] After being reflected by the cavity reflection mirror, the third laser signal is detected by the photoelectric detector as cavity reflection light and converted into a detection signal.

[0104] The error detection module 404 receives the detection signal (essentially the third laser signal) and the phase of the demodulated signal output by the digital RF module 406 to generate a digital error signal.

[0105] After receiving the digital error signal, the servo control module 405 generates a current modulation signal and uses the current modulation signal to servo control the laser 401 so that the error value corresponding to the re-detected digital error signal is less than the set error threshold. The specific value of the error threshold is not limited in this application.

[0106] It can be understood that in addition to adopting the servo control mode, that is, using an analog-to-digital converter to collect error signals, performing servo control operations on the collected error signals, obtaining feedback signals, scaling the feedback signals, and adjusting the frequency control of the frequency synthesis module to realize digital RF feedback; it is also possible to use a sweep mode, that is, after the host computer sets the sweep range, sweep compensation, and sweep interval, the digital RF is output according to the set value, and then through the servo control module 405, the synthesis of a single-frequency square wave is realized, thereby modulating the phase.

[0107] Exemplarily, the expression of the first laser signal output by the laser 401 is shown in formula (4): (4) Among them, E in formula (4) 10 is the light intensity of the first laser signal, t is the time, ω is the laser frequency of the first laser signal, E1(t) is the function of the first laser signal changing with time, and i is used to represent the imaginary part, so that the complex number can be expressed as the sum of the real part and the imaginary part.

[0108] The digital RF signal output by the digital RF module 406 has a double sideband. The electro-optic modulator 402 is driven by the digital RF signal with a double sideband to perform phase modulation on the first laser signal, so that the modulated laser signal, i.e., the second laser signal double sideband has a second-order sideband. Among them, the first sideband is used for laser frequency shifting, and the second-order sideband is used for PDH frequency stabilization.

[0109] The expression of the second laser signal after electro-optical modulation is shown in formula (5): (5) Where, E2(t) in formula (5) is the function of the second laser signal changing with time, E 20 is the light intensity of the second laser signal, Ω is the digital RF carrier frequency, which is also the frequency corresponding to the first-order sideband, β is the modulation depth of the first-order sideband, γ is the digital RF sideband frequency, which is also the frequency corresponding to the second-order sideband, and δ is the modulation depth of the second-order sideband. The meanings of the remaining letters refer to the description in formula (4) and will not be repeated here.

[0110] Figure 5 A schematic diagram of a frequency distribution of a second laser signal provided in an embodiment of the present application. Figure 5 As shown, the frequency of the first laser signal before entering the electro-optic modulator is ω, the carrier frequency of the digital RF signal is Ω, the phase modulation frequency is γ, and the frequencies included in the digital RF signal are Ω-γ, Ω, and Ω+γ; the main frequency components of the second laser signal after passing through the electro-optic modulator are: ω-Ω-γ, ω-Ω, ω-Ω+γ, ω, ω+Ω-γ, ω+Ω, and ω+Ω+γ.

[0111] Among them, ω-Ω and ω+Ω are first-order sidebands related to the carrier frequency of the digital RF signal, and ω-Ω-γ, ω-Ω+γ, ω+Ω-γ, and ω+Ω+γ are second-order sidebands related to the sidebands of the digital RF signal. In this application, the frequency component of ω-Ω or ω+Ω is locked to the frequency stabilization cavity to achieve laser frequency shifting, and the corresponding second-order sidebands can replace the sideband modulation in conventional PDH frequency stabilization.

[0112] In an optional implementation, the error detection module 404 in the present application includes: A detection signal acquisition unit, used to detect and process the third laser signal through an analog-to-digital converter and a photodetector to obtain a detection signal; The error signal generating unit is used to mix and filter the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain a digital error signal; the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second lookup table; the second lookup table is used to indicate the correspondence between the phase and the digital code value.

[0113] It should be noted that in the process of determining the digital code value corresponding to the phase of the demodulated signal based on the phase of the demodulated signal and the preset second lookup table, a multiplication operation is also required to scale the digital code value. The multiplication operation combines binary multiplication with binary shift (shifting right by one bit is equal to dividing by 2), so that decimal multiplication can be achieved. The calculation process of the modulation depth disclosed in the aforementioned embodiment of the present application also uses a multiplication operation.

[0114] The digital radio frequency output by the serial transmission module 103 of the present application has a double sideband, which is equivalent to the double sideband generated by modulation in the laser frequency stabilization optical path. Therefore, the demodulated signal should be the same source signal as the phase modulation signal of the digital radio frequency signal.

[0115] Conventionally used mixers and low-pass filters are both analog devices, and the demodulated signal needs to be output separately. The digital radio frequency device used in the present invention can directly generate a homologous digital demodulated signal in the FPGA.

[0116] In the present application, the third laser signal is detected and processed by an analog-to-digital converter and a photodetector to generate a detection signal; the detection signal generated by the photodetector is collected by a high-speed analog-to-digital converter; then, a digital mixer and a digital low-pass filter are used to mix and filter the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulated signal to obtain a digital error signal.

[0117] The digital code value corresponding to the phase of the demodulated signal is determined based on the phase of the demodulated signal and a preset second lookup table; the second lookup table is used to indicate the corresponding relationship between the phase and the digital code value.

[0118] Among them, the digital mixer is implemented using a multiplier, and the multiplier can directly call the IP core of the FPGA.

[0119] The digital low-pass filter can be implemented using a capacitive digital integrator. The expression of the capacitive digital integrator is shown in formula (6): y(n) = y(n-1) + a×in (n); a=2π×F P ÷F S (6) Where y(n) represents the output of the integrator at discrete time n; y(n-1) represents the output of the integrator at the previous discrete time n-1; in(n) represents the input signal at discrete time n; a is the integration coefficient, F S is the sampling rate, F P is the pole frequency.

[0120] In an optional implementation, the servo control module in the present application is specifically used to: perform servo control on the laser according to the digital error signal, digital lead-lag and digital proportional differential integral regulator, so that the error value corresponding to the re-detected digital error signal is less than the set error threshold.

[0121] The error detection module in this application is a digital module that outputs a digital signal; the servo control module is also a digital module. The servo control module in this application includes a digital lead-lag and a digital proportional-integral-derivative controller (digital PID, Proportional-Integral-Derivative). The digital PID includes the fast feedback and slow feedback required for laser frequency stabilization; the digital lead-lag provides bandwidth modulation for the fast feedback of the laser, reduces the high-frequency gain, and improves the phase margin.

[0122] In an optional implementation, the digital lead-lag in the present application is of order 3, and 3 pairs of poles and zeros can be added. Among them, when the system input amplitude is not zero and the input frequency makes the system output zero, this input frequency value is the zero point, and the effect of the zero point on the frequency response curve is leading. When the system input amplitude is not zero and the input frequency makes the system output infinite (system stability is destroyed and oscillation occurs), this frequency value is the pole, and the effect of the pole on the frequency response curve is lagging.

[0123] At each pole, the gain is reduced by -3db and the phase is shifted by -45 degrees. After the pole, the gain decreases by 20db for each decade. The zero point is opposite to the pole; at each zero point, the gain increases by 3db and the phase is shifted by 45 degrees. After the zero point, the gain increases by 20db for each decade.

[0124] In digital lead-lag, the operation of adding poles is digital integration, and the operation of adding zeros is digital differentiation.

[0125] The pole operation formula is the same as that of the capacitive digital integrator and will not be repeated here.

[0126] The zero point operation is shown in formula (7): y(m) = (b+1)×in(m)-b×in(m-1); b= F S ÷(2π×F Z )(7) Where y(m) represents the output of the differentiator at discrete time m; b is the differential coefficient, F S is the sampling rate, F Z is the zero-point frequency, in(m) represents the input signal at discrete time m; in(m-1) represents the input signal at discrete time m-1.

[0127] Figure 6 A schematic diagram of a third-order lead-lag frequency response curve provided in an embodiment of the present application. Figure 6 (a) is a schematic diagram indicating the change of amplitude with frequency, referred to as the "amplitude-frequency response" diagram; Figure 6 (b) is a schematic diagram indicating the change of phase with frequency, referred to as the "phase-frequency response" schematic diagram. In order to prevent the high-frequency gain from being too large but the phase margin from being insufficient, which leads to loop oscillation, a third-order digital lead-lag is introduced into the servo control module to achieve the following: Figure 6 (a) and Figure 6 (b) Effect. Figure 6As shown, the gain is first attenuated at the two middle frequency points, and then the gain is increased at the high frequency; the phase change is not obvious at low frequency, and the phase change due to integration is within an acceptable range. The phase and gain of the intermediate frequency are both worse, but the phase and gain of the high frequency are better.

[0128] It should be noted that the pole and zero positions used in the actual working process are determined according to the loop parameters. One of the advantages of digital lead-lag is that the pole and zero positions and the pole and zero order can be adjusted according to the actual use. Figure 6 It is mainly to illustrate the influence of poles and zeros on loop bandwidth.

[0129] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A digital radio frequency device based on a gigabit transceiver, characterized in that: The device comprises: A coding phase module, for generating an initial coding phase based on a clock signal frequency of the gigabit transceiver, a preset number of parallel channels, and a target laser shift frequency; A phase modulation module, used for phase modulating the initial coding phase to generate a coding phase and a demodulation signal; the coding phase has a double-sideband; the demodulation signal is a signal with the same frequency as the target sideband; the target sideband is a sideband in the double-sideband; A serial transmission module, configured to generate a digital radio frequency signal based on the coding phase and the gigabit transceiver; The RF driving module is used to amplify and filter the digital RF signal to generate a target digital RF signal.

2. The device according to claim 1, characterized in that The encoding phase module comprises: A first accumulation step length determination submodule, configured to determine a serial phase accumulation step length according to a clock signal frequency of the gigabit transceiver and the target laser shift frequency; A second accumulation step determination submodule, configured to determine a parallel phase accumulation step based on the serial phase accumulation step and the number of parallel channels; A basic phase determination submodule, used to determine the basic phase corresponding to the parallel channel at the current counting moment based on the basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each of the parallel channels has the same basic phase at the same counting moment; The coding phase determination submodule is used to determine, for each of the parallel channels, an initial coding phase of the parallel channel at the current counting moment based on the basic phase of the parallel channel at the current counting moment, the channel coding of the parallel channel and the serial phase accumulation step; the channel coding is a preset digital coding for indicating the arrangement order of the corresponding parallel channel in the plurality of parallel channels.

3. The device according to claim 2, characterized in that The first accumulation step size determination submodule includes: A time step determining unit, configured to determine a time step based on a clock signal frequency of the gigabit transceiver; The serial phase accumulation step length determining unit is used to determine the serial phase accumulation step length based on the time step length, the target laser frequency shift and the full phase range.

4. The device according to claim 2, characterized in that The phase modulation module comprises: A parameter setting submodule, used to set an initial phase corresponding to the digital radio frequency signal as a first initial phase; A function setting submodule is used to set the phase modulation depth, the phase modulation signal frequency and the second initial phase to obtain a phase modulation function; The phase modulation submodule is used to phase modulate the initial coding phase based on the phase modulation function and the first initial phase to generate the coding phase and the demodulated signal.

5. The device according to claim 4, characterized in that The function setting submodule includes: a target address determining unit, configured to determine a target address based on the second initial phase and a phase corresponding to the gigabit transceiver; the phase corresponding to the gigabit transceiver being a product of a frequency of the phase modulation signal and time; a target amplitude determination unit, configured to determine a target amplitude based on the target address and a preset first lookup table; the first lookup table indicates a correspondence between an address and an amplitude of a sine wave; A sine wave determination unit is used to determine a sine wave function as the phase modulation function based on the phase modulation depth, the phase modulation signal frequency and the second initial phase, the phase corresponding to the gigabit transceiver and the target amplitude.

6. The device according to claim 4, characterized in that The function setting submodule includes: A triangle wave function setting unit is used to determine a triangle wave function as the phase modulation function based on the phase corresponding to the gigabit transceiver and a preset triangle wave formula; the phase corresponding to the gigabit transceiver is the product of the phase modulation signal frequency and time.

7. The device according to claim 4, characterized in that The phase modulation submodule comprises: a modulation basic phase determining unit, configured to determine the modulation basic phase corresponding to the parallel channel at the current counting moment based on the modulation basic phase corresponding to the parallel channel at the previous counting moment and the parallel phase accumulation step; each of the parallel channels has the same modulation basic phase at the same counting moment; a coding modulation phase determining unit, configured to determine, for each of the parallel channels, the coding modulation phase corresponding to the parallel channel at the current counting moment based on the modulation base phase corresponding to the parallel channel at the current counting moment, the channel coding of the parallel channel, the serial phase accumulation step, the phase modulation function and the first initial phase; The coding phase determining unit is used to determine, for each of the parallel channels, the coding phase of the parallel channel at the current counting moment based on the initial coding phase corresponding to the parallel channel at the current counting moment and the coding modulation phase corresponding to the parallel channel at the current counting moment.

8. The device according to claim 2, characterized in that The serial transmission module comprises: A preprocessing module, configured to perform a parameter zeroing operation on the gigabit transceiver to obtain a target gigabit transceiver; the parameter zeroing operation is configured to clear the pre-stored protocols and parameters in the gigabit transceiver; A digital coding unit, used for splicing the coding phases of the highest bits of the plurality of parallel channels to obtain the digital code; A digital radio frequency transmitting unit is used to generate the digital radio frequency signal based on the target gigabit transceiver and the digital code.

9. A laser frequency stabilization device, characterized in that: The device comprises: a laser, a digital radio frequency module, an electro-optic modulator, a frequency stabilization cavity, an error detection module and a servo control module; The laser is used to output a first laser signal; The digital RF module is used to generate a phase of a demodulated signal and a digital RF signal according to a target laser frequency shift; the demodulated signal and the digital RF signal are homologous signals; the digital RF module is a device according to any one of claims 1 to 8; The electro-optical modulator is used to generate a second laser signal according to the first laser signal and the digital radio frequency signal; The frequency stabilizing cavity is used to output a third laser signal according to the second laser signal; The error detection module is used to generate a digital error signal based on the phase of the third laser signal and the demodulated signal; The servo control module is used to perform servo control on the laser according to the digital error signal, so that the error value corresponding to the re-detected digital error signal is smaller than a set error threshold.

10. The device according to claim 9, characterized in that The error detection module comprises: A detection signal acquisition unit, used to detect and process the third laser signal through an analog-to-digital converter and a photodetector to obtain a detection signal; An error signal generating unit is used to mix and filter the digital code value of the detection signal and the digital code value corresponding to the phase of the demodulation signal to obtain the digital error signal; the digital code value corresponding to the phase of the demodulation signal is determined based on the phase of the demodulation signal and a preset second lookup table; the second lookup table is used to indicate the correspondence between the phase and the digital code value.

11. The device according to claim 9, characterized in that The servo control module is specifically used for: According to the digital error signal, the digital lead-lag and the digital proportional differential integral regulator, the laser is servo-controlled so that the error value corresponding to the re-detected digital error signal is smaller than the set error threshold.

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